Update CEC1302 peripheral library version.
This commit is contained in:
Richard Barry
parent
057b38ad23
commit
da6c95edae
File diff suppressed because one or more lines are too long
@ -89,7 +89,7 @@
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tGomain>0</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
@ -179,7 +179,7 @@
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
@ -245,7 +245,7 @@
|
||||
|
||||
<Group>
|
||||
<GroupName>main_and_config</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
@ -369,7 +369,7 @@
|
||||
|
||||
<Group>
|
||||
<GroupName>main_low_power</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
@ -401,7 +401,7 @@
|
||||
|
||||
<Group>
|
||||
<GroupName>main_full</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
|
||||
@ -1,9 +1,10 @@
|
||||
/*
|
||||
* Default linker script for GCC MEC1322
|
||||
* Default linker script for GCC CEC1302
|
||||
* Based upon linker scripts from GNU ARM Eclipse plug-in
|
||||
*/
|
||||
|
||||
INCLUDE mem.ld
|
||||
__SRAM_segment_end__ = ORIGIN( RAM ) + LENGTH( RAM );
|
||||
|
||||
/*
|
||||
* The '__stack' definition is required by crt0, do not remove it.
|
||||
|
||||
@ -33,43 +33,16 @@
|
||||
.syntax unified
|
||||
.arch armv7e-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
|
||||
.equ ulMainStackSize, 200 * 4
|
||||
.equ Stack_Size, 0x004
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
.extern ulMainStack
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
.extern __SRAM_segment_end__
|
||||
|
||||
.section .isr_vector,"a",%progbits
|
||||
.align 4
|
||||
.globl __isr_vector
|
||||
.global __Vectors
|
||||
.type __Vectors, %object
|
||||
.size __Vectors, .-__Vectors
|
||||
|
||||
__Vectors:
|
||||
.long ulMainStack + ulMainStackSize /* Top of Stack */
|
||||
__isr_vector:
|
||||
.long __SRAM_segment_end__ - 4 /* Top of Stack at top of RAM*/
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
@ -207,9 +180,6 @@ Reset_Handler:
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr sp, =ulMainStack + ulMainStackSize
|
||||
sub sp, sp, #4
|
||||
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
@ -280,10 +250,10 @@ Default_Handler:
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
/* def_irq_handler SVC_Handler */
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
/* def_irq_handler PendSV_Handler */
|
||||
/* def_irq_handler SysTick_Handler */
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
def_irq_handler DEF_IRQHandler
|
||||
|
||||
def_irq_handler NVIC_Handler_I2C0
|
||||
|
||||
@ -55,12 +55,6 @@
|
||||
#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(uint32_t *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))
|
||||
#define CPU_CLOCK_DIVIDER 1
|
||||
|
||||
/* The start up code is configured to use the following array as the stack used
|
||||
by main(), which will then also get used by FreeRTOS interrupt handlers after
|
||||
the scheduler has been started. */
|
||||
#warning If the array size is modified here then ulMainStackSize must also be modified in startup_ARMCM4.S.
|
||||
volatile uint32_t ulMainStack[ 200 ];
|
||||
|
||||
/******************************************************************************/
|
||||
/** system_set_ec_clock
|
||||
* Set CPU speed
|
||||
|
||||
@ -397,7 +397,7 @@
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>14</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\main_full\main_full.c</PathWithFileName>
|
||||
@ -573,7 +573,7 @@
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>28</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\peripheral_library\basic_timer\btimer_api.c</PathWithFileName>
|
||||
|
||||
@ -19,10 +19,10 @@
|
||||
;* OF THESE TERMS.
|
||||
;******************************************************************************
|
||||
; */
|
||||
;/** @file startup_MEC1322.s
|
||||
; *MEC1322 API Test: startup and vector table
|
||||
;/** @file startup_CEC1302.s
|
||||
; *CEC1302 API Test: startup and vector table
|
||||
; */
|
||||
;/** @defgroup startup_MEC1322
|
||||
;/** @defgroup startup_CEC1302
|
||||
; * @{
|
||||
; */
|
||||
|
||||
@ -88,7 +88,7 @@ __Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; MEC1322 External Interrupts
|
||||
; CEC1302 External Interrupts
|
||||
DCD NVIC_Handler_I2C0 ; 40h: 0, I2C/SMBus 0
|
||||
DCD NVIC_Handler_I2C1 ; 44h: 1, I2C/SMBus 1
|
||||
DCD NVIC_Handler_I2C2 ; 48h: 2, I2C/SMBus 2
|
||||
@ -275,7 +275,7 @@ SysTick_Handler PROC
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
; External MEC1322 NVIC Interrupt Inputs
|
||||
; External CEC1302 NVIC Interrupt Inputs
|
||||
EXPORT NVIC_Handler_I2C0 [WEAK]
|
||||
EXPORT NVIC_Handler_I2C1 [WEAK]
|
||||
EXPORT NVIC_Handler_I2C2 [WEAK]
|
||||
|
||||
@ -165,7 +165,7 @@ static void prvSetupHardware( void )
|
||||
extern void system_set_ec_clock( void );
|
||||
extern unsigned long __Vectors[];
|
||||
|
||||
/* Disable M4 write buffer: fix MEC1322 hardware bug. */
|
||||
/* Disable M4 write buffer: fix CEC1302 hardware bug. */
|
||||
mainNVIC_AUX_ACTLR |= 0x07;
|
||||
|
||||
/* Enable alternative NVIC vectors. */
|
||||
|
||||
@ -117,8 +117,13 @@ timers must still be above the tick interrupt priority. */
|
||||
#define tmrMEDIUM_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 0 )
|
||||
#define tmrHIGHER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 )
|
||||
|
||||
/* Hardware register locations. */
|
||||
/* Hardware register locations and bit definitions to enable the btimer
|
||||
interrupts. */
|
||||
#define tmrGIRQ23_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C130 )
|
||||
#define tmrGIRQ23_BIT_TIMER0 ( 1UL << 0UL )
|
||||
#define tmrGIRQ23_BIT_TIMER1 ( 1UL << 1UL )
|
||||
#define tmrGIRQ23_BIT_TIMER2 ( 1UL << 2UL )
|
||||
#define tmrGIRQ23_TIMER_BITS ( tmrGIRQ23_BIT_TIMER0 | tmrGIRQ23_BIT_TIMER1 | tmrGIRQ23_BIT_TIMER2 )
|
||||
|
||||
#define tmrRECORD_NESTING_DEPTH() \
|
||||
ulNestingDepth++; \
|
||||
@ -138,13 +143,12 @@ const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / tmrTIMER_0_FREQUENCY;
|
||||
const uint32_t ulTimer1Count = configCPU_CLOCK_HZ / tmrTIMER_1_FREQUENCY;
|
||||
const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;
|
||||
|
||||
tmrGIRQ23_ENABLE_SET = 0x03;
|
||||
tmrGIRQ23_ENABLE_SET = tmrGIRQ23_TIMER_BITS;
|
||||
|
||||
/* Initialise the three timers as described at the top of this file, and
|
||||
enable their interrupts in the NVIC. */
|
||||
btimer_init( tmrTIMER_CHANNEL_0, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );
|
||||
btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_0 );
|
||||
enable_timer0_irq();
|
||||
NVIC_SetPriority( TIMER0_IRQn, tmrLOWER_PRIORITY ); //0xc0 into 0xe000e431
|
||||
NVIC_ClearPendingIRQ( TIMER0_IRQn );
|
||||
NVIC_EnableIRQ( TIMER0_IRQn );
|
||||
@ -152,7 +156,6 @@ const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;
|
||||
|
||||
btimer_init( tmrTIMER_CHANNEL_1, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer1Count, ulTimer1Count );
|
||||
btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_1 );
|
||||
enable_timer1_irq();
|
||||
NVIC_SetPriority( TIMER1_IRQn, tmrMEDIUM_PRIORITY ); //0xa0 into 0xe000e432
|
||||
NVIC_ClearPendingIRQ( TIMER1_IRQn );
|
||||
NVIC_EnableIRQ( TIMER1_IRQn );
|
||||
@ -160,7 +163,6 @@ const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;
|
||||
|
||||
btimer_init( tmrTIMER_CHANNEL_2, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer2Count, ulTimer2Count );
|
||||
btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_2 );
|
||||
enable_timer2_irq();
|
||||
NVIC_SetPriority( TIMER2_IRQn, tmrHIGHER_PRIORITY );
|
||||
NVIC_ClearPendingIRQ( TIMER2_IRQn );
|
||||
NVIC_EnableIRQ( TIMER2_IRQn );
|
||||
|
||||
@ -76,6 +76,8 @@
|
||||
|
||||
/* Library includes. */
|
||||
#include "common_lib.h"
|
||||
#include "peripheral_library/interrupt/interrupt.h"
|
||||
#include "peripheral_library/basic_timer/btimer.h"
|
||||
|
||||
/* This file contains functions that will override the default implementations
|
||||
in the RTOS port layer. Therefore only build this file if the low power demo
|
||||
@ -170,13 +172,14 @@ void NVIC_Handler_HIB_TMR( void )
|
||||
#if( lpINCLUDE_TEST_TIMER == 1 )
|
||||
|
||||
#define lpGIRQ23_ENABLE_SET ( * ( uint32_t * ) 0x4000C130 )
|
||||
#define tmrGIRQ23_BIT_TIMER0 ( 1UL << 0UL )
|
||||
|
||||
static void prvSetupBasicTimer( void )
|
||||
{
|
||||
const uint8_t ucTimerChannel = 0;
|
||||
const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / 10;
|
||||
|
||||
lpGIRQ23_ENABLE_SET = 0x03;
|
||||
lpGIRQ23_ENABLE_SET = tmrGIRQ23_BIT_TIMER0;
|
||||
|
||||
/* To fully test the low power tick processing it is necessary to sometimes
|
||||
bring the MCU out of its sleep state by a method other than the tick
|
||||
@ -184,7 +187,6 @@ void NVIC_Handler_HIB_TMR( void )
|
||||
purpose. */
|
||||
btimer_init( ucTimerChannel, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );
|
||||
btimer_interrupt_status_get_clr( ucTimerChannel );
|
||||
enable_timer0_irq();
|
||||
NVIC_SetPriority( TIMER0_IRQn, ucTimerChannel );
|
||||
NVIC_ClearPendingIRQ( TIMER0_IRQn );
|
||||
NVIC_EnableIRQ( TIMER0_IRQn );
|
||||
|
||||
@ -23,10 +23,10 @@
|
||||
**********************************************************************************
|
||||
* SMSC version control information (Perforce):
|
||||
*
|
||||
* FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/ARM_REG.h $
|
||||
* FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_PLIB_CLIB/release5/Source/hw_blks/common/include/ARM_REG.h $
|
||||
* REVISION: $Revision: #1 $
|
||||
* DATETIME: $DateTime: 2015/12/23 15:37:58 $
|
||||
* AUTHOR: $Author: akrishnan $
|
||||
* DATETIME: $DateTime: 2016/04/08 10:18:28 $
|
||||
* AUTHOR: $Author: pramans $
|
||||
*
|
||||
* Revision history (latest first):
|
||||
* #xx
|
||||
|
||||
@ -963,7 +963,7 @@ typedef struct { /*!< ACPI_EC0 Structure
|
||||
struct {
|
||||
__I uint8_t OBF : 1; /*!< Output Buffer Full bit */
|
||||
__I uint8_t IBF : 1; /*!< Input Buffer Full bit */
|
||||
__I uint8_t UD1A : 1; /*!< User Defined */
|
||||
__IO uint8_t UD1A : 1; /*!< User Defined */
|
||||
__I uint8_t CMD : 1; /*!< OS2EC Data contains a command byte */
|
||||
__IO uint8_t BURST : 1; /*!< set when the ACPI_EC is in Burst Mode */
|
||||
__IO uint8_t SCI_EVT : 1; /*!< set when an SCI event is pending */
|
||||
@ -975,8 +975,8 @@ typedef struct { /*!< ACPI_EC0 Structure
|
||||
__I uint16_t RESERVED1;
|
||||
|
||||
union {
|
||||
__IO uint32_t OS2EC_DATA; /*!< OS2EC Data EC-Register */
|
||||
__IO uint8_t OS2EC_DATA_BYTE[4]; /*!< OS2EC Data Bytes */
|
||||
__I uint32_t OS2EC_DATA; /*!< OS2EC Data EC-Register */
|
||||
__I uint8_t OS2EC_DATA_BYTE[4]; /*!< OS2EC Data Bytes */
|
||||
};
|
||||
} ACPI_EC0_Type;
|
||||
|
||||
@ -1034,7 +1034,7 @@ typedef struct { /*!< KBC Structure
|
||||
__IO uint8_t UD0 : 1; /*!< User-defined data. */
|
||||
__I uint8_t CMDnDATA : 1; /*!< data register contains data(0) or command(1) */
|
||||
__IO uint8_t UD1 : 1; /*!< User-defined data. */
|
||||
__IO uint8_t AUXOBF : 1; /*!< Auxiliary Output Buffer Full. */
|
||||
__I uint8_t AUXOBF : 1; /*!< Auxiliary Output Buffer Full. */
|
||||
__IO uint8_t UD2 : 2; /*!< User-defined data. */
|
||||
} STATUS_b; /*!< BitSize */
|
||||
};
|
||||
@ -1087,7 +1087,7 @@ typedef struct { /*!< PORT92 Structure
|
||||
__I uint8_t RESERVED1[7];
|
||||
__O uint8_t SETGA20L; /*!< write to set GATEA20 in GATEA20 Control Reg */
|
||||
__I uint8_t RESERVED2[3];
|
||||
__IO uint8_t RSTGA20L; /*!< write to set GATEA20 in GATEA20 Control Reg */
|
||||
__O uint8_t RSTGA20L; /*!< write to set GATEA20 in GATEA20 Control Reg */
|
||||
__I uint8_t RESERVED3[547];
|
||||
__IO uint8_t PORT92_ENABLE; /*!< [0:0] 1= Port92h Register is enabled. */
|
||||
} PORT92_Type;
|
||||
@ -2110,8 +2110,7 @@ typedef struct { /*!< RPM_FAN Structure
|
||||
__IO uint8_t VALID_TACH_COUNT; /*!< max value to indicate fan spin properly */
|
||||
__IO uint16_t DRIVE_FAIL_BAND; /*!< [15:3]counts for Drive Fail circuitry */
|
||||
__IO uint16_t TACH_TARGET; /*!< [12:0] The target tachometer value. */
|
||||
__IO uint8_t TACH_READING; /*!< [15:3]current tachometer reading value. */
|
||||
__I uint8_t RESERVED1;
|
||||
__IO uint16_t TACH_READING; /*!< [15:3]current tachometer reading value. */
|
||||
__IO uint8_t DRIVER_BASE_FREQUENCY; /*!< [1:0]frequency range of the PWM fan driver */
|
||||
|
||||
union {
|
||||
@ -2513,7 +2512,7 @@ typedef struct { /*!< JTAG Structure
|
||||
|
||||
|
||||
/*------------- Public Key Encryption Subsystem (PKE) -----------------------------*/
|
||||
/** @addtogroup MEC1322_PKE Public Key Encryption (PKE)
|
||||
/** @addtogroup CEC1302_PKE Public Key Encryption (PKE)
|
||||
@{
|
||||
*/
|
||||
typedef struct
|
||||
@ -2525,10 +2524,10 @@ typedef struct
|
||||
__I uint32_t VERSION; /*!< Offset: 0x0010 Version */
|
||||
__IO uint32_t LOAD_MICRO_CODE; /*!< Offset: 0x0014 Load Micro Code */
|
||||
} PKE_TypeDef;
|
||||
/*@}*/ /* end of group MEC1322_PKE */
|
||||
/*@}*/ /* end of group CEC1302_PKE */
|
||||
|
||||
/*------------- Random Number Generator Subsystem (TRNG) -----------------------------*/
|
||||
/** @addtogroup MEC1322_TRNG Random Number Generator (TRNG)
|
||||
/** @addtogroup CEC1302_TRNG Random Number Generator (TRNG)
|
||||
@{
|
||||
*/
|
||||
typedef struct
|
||||
@ -2537,10 +2536,10 @@ typedef struct
|
||||
__I uint32_t FIFO_LEVEL; /*!< Offset: 0x0004 FIFO Level */
|
||||
__I uint32_t VERSION; /*!< Offset: 0x0008 Version */
|
||||
} TRNG_TypeDef;
|
||||
/*@}*/ /* end of group MEC1322_TRNG */
|
||||
/*@}*/ /* end of group CEC1302_TRNG */
|
||||
|
||||
/*------------- Hash Subsystem (HASH) -----------------------------*/
|
||||
/** @addtogroup MEC1322_HASH Hash Security (HASH)
|
||||
/** @addtogroup CEC1302_HASH Hash Security (HASH)
|
||||
@{
|
||||
*/
|
||||
typedef struct
|
||||
@ -2555,12 +2554,12 @@ typedef struct
|
||||
__IO uint32_t DATA_SOURCE_ADDR; /*!< Offset: 0x001C Data to hash Address */
|
||||
__IO uint32_t HASH_RESULT_ADDR; /*!< Offset: 0x0020 Hash result address */
|
||||
} HASH_TypeDef;
|
||||
/*@}*/ /* end of group MEC1322_HASH */
|
||||
/*@}*/ /* end of group CEC1302_HASH */
|
||||
|
||||
|
||||
|
||||
/*------------- Advanced Encryption Subsystem (AES) -----------------------------*/
|
||||
/** @addtogroup MEC1322_AES Advanced Encryption Subsys (AES)
|
||||
/** @addtogroup CEC1302_AES Advanced Encryption Subsys (AES)
|
||||
@{
|
||||
*/
|
||||
|
||||
@ -2603,7 +2602,7 @@ typedef struct
|
||||
!< Offset: 0x0158 KeyIn1[95:64]
|
||||
!< Offset: 0x015C KeyIn1[127:96] */
|
||||
} AES_TypeDef;
|
||||
/*@}*/ /* end of group MEC1322_AES */
|
||||
/*@}*/ /* end of group CEC1302_AES */
|
||||
|
||||
/* -------------------- End of section using anonymous unions ------------------- */
|
||||
#if defined(__CC_ARM)
|
||||
@ -3280,114 +3279,6 @@ typedef struct
|
||||
#define ACPI_EC0_EC_STATUS_UD0A_Msk (0x80UL) /*!< ACPI_EC0 EC_STATUS: UD0A (Bitfield-Mask: 0x01) */
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ struct 'ACPI_EC1' Position & Mask ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
|
||||
/* ----------------------------- ACPI_EC1_OS_STATUS ----------------------------- */
|
||||
#define ACPI_EC1_OS_STATUS_OBF_Pos (0UL) /*!< ACPI_EC1 OS_STATUS: OBF (Bit 0) */
|
||||
#define ACPI_EC1_OS_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC1 OS_STATUS: OBF (Bitfield-Mask: 0x01) */
|
||||
#define ACPI_EC1_OS_STATUS_IBF_Pos (1UL) /*!< ACPI_EC1 OS_STATUS: IBF (Bit 1) */
|
||||
#define ACPI_EC1_OS_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC1 OS_STATUS: IBF (Bitfield-Mask: 0x01) */
|
||||
#define ACPI_EC1_OS_STATUS_UD1B_Pos (2UL) /*!< ACPI_EC1 OS_STATUS: UD1B (Bit 2) */
|
||||
#define ACPI_EC1_OS_STATUS_UD1B_Msk (0x4UL) /*!< ACPI_EC1 OS_STATUS: UD1B (Bitfield-Mask: 0x01) */
|
||||
#define ACPI_EC1_OS_STATUS_CMD_Pos (3UL) /*!< ACPI_EC1 OS_STATUS: CMD (Bit 3) */
|
||||
#define ACPI_EC1_OS_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC1 OS_STATUS: CMD (Bitfield-Mask: 0x01) */
|
||||
#define ACPI_EC1_OS_STATUS_BURST_Pos (4UL) /*!< ACPI_EC1 OS_STATUS: BURST (Bit 4) */
|
||||
#define ACPI_EC1_OS_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC1 OS_STATUS: BURST (Bitfield-Mask: 0x01) */
|
||||
#define ACPI_EC1_OS_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC1 OS_STATUS: SCI_EVT (Bit 5) */
|
||||
#define ACPI_EC1_OS_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC1 OS_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */
|
||||
#define ACPI_EC1_OS_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC1 OS_STATUS: SMI_EVT (Bit 6) */
|
||||
#define ACPI_EC1_OS_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC1 OS_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */
|
||||
#define ACPI_EC1_OS_STATUS_UD0B_Pos (7UL) /*!< ACPI_EC1 OS_STATUS: UD0B (Bit 7) */
|
||||
#define ACPI_EC1_OS_STATUS_UD0B_Msk (0x80UL) /*!< ACPI_EC1 OS_STATUS: UD0B (Bitfield-Mask: 0x01) */
|
||||
|
||||
/* ----------------------------- ACPI_EC1_EC_STATUS ----------------------------- */
|
||||
#define ACPI_EC1_EC_STATUS_OBF_Pos (0UL) /*!< ACPI_EC1 EC_STATUS: OBF (Bit 0) */
|
||||
#define ACPI_EC1_EC_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC1 EC_STATUS: OBF (Bitfield-Mask: 0x01) */
|
||||
#define ACPI_EC1_EC_STATUS_IBF_Pos (1UL) /*!< ACPI_EC1 EC_STATUS: IBF (Bit 1) */
|
||||
#define ACPI_EC1_EC_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC1 EC_STATUS: IBF (Bitfield-Mask: 0x01) */
|
||||
#define ACPI_EC1_EC_STATUS_UD1A_Pos (2UL) /*!< ACPI_EC1 EC_STATUS: UD1A (Bit 2) */
|
||||
#define ACPI_EC1_EC_STATUS_UD1A_Msk (0x4UL) /*!< ACPI_EC1 EC_STATUS: UD1A (Bitfield-Mask: 0x01) */
|
||||
#define ACPI_EC1_EC_STATUS_CMD_Pos (3UL) /*!< ACPI_EC1 EC_STATUS: CMD (Bit 3) */
|
||||
#define ACPI_EC1_EC_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC1 EC_STATUS: CMD (Bitfield-Mask: 0x01) */
|
||||
#define ACPI_EC1_EC_STATUS_BURST_Pos (4UL) /*!< ACPI_EC1 EC_STATUS: BURST (Bit 4) */
|
||||
#define ACPI_EC1_EC_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC1 EC_STATUS: BURST (Bitfield-Mask: 0x01) */
|
||||
#define ACPI_EC1_EC_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC1 EC_STATUS: SCI_EVT (Bit 5) */
|
||||
#define ACPI_EC1_EC_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC1 EC_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */
|
||||
#define ACPI_EC1_EC_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC1 EC_STATUS: SMI_EVT (Bit 6) */
|
||||
#define ACPI_EC1_EC_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC1 EC_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */
|
||||
#define ACPI_EC1_EC_STATUS_UD0A_Pos (7UL) /*!< ACPI_EC1 EC_STATUS: UD0A (Bit 7) */
|
||||
#define ACPI_EC1_EC_STATUS_UD0A_Msk (0x80UL) /*!< ACPI_EC1 EC_STATUS: UD0A (Bitfield-Mask: 0x01) */
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ struct 'KBC' Position & Mask ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
|
||||
/* ---------------------------- KBC_RD_PORT64_STATUS ---------------------------- */
|
||||
#define KBC_RD_PORT64_STATUS_OBF_Pos (0UL) /*!< KBC RD_PORT64_STATUS: OBF (Bit 0) */
|
||||
#define KBC_RD_PORT64_STATUS_OBF_Msk (0x1UL) /*!< KBC RD_PORT64_STATUS: OBF (Bitfield-Mask: 0x01) */
|
||||
#define KBC_RD_PORT64_STATUS_IBF_Pos (1UL) /*!< KBC RD_PORT64_STATUS: IBF (Bit 1) */
|
||||
#define KBC_RD_PORT64_STATUS_IBF_Msk (0x2UL) /*!< KBC RD_PORT64_STATUS: IBF (Bitfield-Mask: 0x01) */
|
||||
#define KBC_RD_PORT64_STATUS_UD0_Pos (2UL) /*!< KBC RD_PORT64_STATUS: UD0 (Bit 2) */
|
||||
#define KBC_RD_PORT64_STATUS_UD0_Msk (0x4UL) /*!< KBC RD_PORT64_STATUS: UD0 (Bitfield-Mask: 0x01) */
|
||||
#define KBC_RD_PORT64_STATUS_CMDnDATA_Pos (3UL) /*!< KBC RD_PORT64_STATUS: CMDnDATA (Bit 3) */
|
||||
#define KBC_RD_PORT64_STATUS_CMDnDATA_Msk (0x8UL) /*!< KBC RD_PORT64_STATUS: CMDnDATA (Bitfield-Mask: 0x01) */
|
||||
#define KBC_RD_PORT64_STATUS_UD1_Pos (4UL) /*!< KBC RD_PORT64_STATUS: UD1 (Bit 4) */
|
||||
#define KBC_RD_PORT64_STATUS_UD1_Msk (0x10UL) /*!< KBC RD_PORT64_STATUS: UD1 (Bitfield-Mask: 0x01) */
|
||||
#define KBC_RD_PORT64_STATUS_AUXOBF_Pos (5UL) /*!< KBC RD_PORT64_STATUS: AUXOBF (Bit 5) */
|
||||
#define KBC_RD_PORT64_STATUS_AUXOBF_Msk (0x20UL) /*!< KBC RD_PORT64_STATUS: AUXOBF (Bitfield-Mask: 0x01) */
|
||||
#define KBC_RD_PORT64_STATUS_UD2_Pos (6UL) /*!< KBC RD_PORT64_STATUS: UD2 (Bit 6) */
|
||||
#define KBC_RD_PORT64_STATUS_UD2_Msk (0xc0UL) /*!< KBC RD_PORT64_STATUS: UD2 (Bitfield-Mask: 0x03) */
|
||||
|
||||
/* --------------------------------- KBC_STATUS --------------------------------- */
|
||||
#define KBC_STATUS_OBF_Pos (0UL) /*!< KBC STATUS: OBF (Bit 0) */
|
||||
#define KBC_STATUS_OBF_Msk (0x1UL) /*!< KBC STATUS: OBF (Bitfield-Mask: 0x01) */
|
||||
#define KBC_STATUS_IBF_Pos (1UL) /*!< KBC STATUS: IBF (Bit 1) */
|
||||
#define KBC_STATUS_IBF_Msk (0x2UL) /*!< KBC STATUS: IBF (Bitfield-Mask: 0x01) */
|
||||
#define KBC_STATUS_UD0_Pos (2UL) /*!< KBC STATUS: UD0 (Bit 2) */
|
||||
#define KBC_STATUS_UD0_Msk (0x4UL) /*!< KBC STATUS: UD0 (Bitfield-Mask: 0x01) */
|
||||
#define KBC_STATUS_CMDnDATA_Pos (3UL) /*!< KBC STATUS: CMDnDATA (Bit 3) */
|
||||
#define KBC_STATUS_CMDnDATA_Msk (0x8UL) /*!< KBC STATUS: CMDnDATA (Bitfield-Mask: 0x01) */
|
||||
#define KBC_STATUS_UD1_Pos (4UL) /*!< KBC STATUS: UD1 (Bit 4) */
|
||||
#define KBC_STATUS_UD1_Msk (0x10UL) /*!< KBC STATUS: UD1 (Bitfield-Mask: 0x01) */
|
||||
#define KBC_STATUS_AUXOBF_Pos (5UL) /*!< KBC STATUS: AUXOBF (Bit 5) */
|
||||
#define KBC_STATUS_AUXOBF_Msk (0x20UL) /*!< KBC STATUS: AUXOBF (Bitfield-Mask: 0x01) */
|
||||
#define KBC_STATUS_UD2_Pos (6UL) /*!< KBC STATUS: UD2 (Bit 6) */
|
||||
#define KBC_STATUS_UD2_Msk (0xc0UL) /*!< KBC STATUS: UD2 (Bitfield-Mask: 0x03) */
|
||||
|
||||
/* --------------------------------- KBC_CONTROL -------------------------------- */
|
||||
#define KBC_CONTROL_UD3_Pos (0UL) /*!< KBC CONTROL: UD3 (Bit 0) */
|
||||
#define KBC_CONTROL_UD3_Msk (0x1UL) /*!< KBC CONTROL: UD3 (Bitfield-Mask: 0x01) */
|
||||
#define KBC_CONTROL_SAEN_Pos (1UL) /*!< KBC CONTROL: SAEN (Bit 1) */
|
||||
#define KBC_CONTROL_SAEN_Msk (0x2UL) /*!< KBC CONTROL: SAEN (Bitfield-Mask: 0x01) */
|
||||
#define KBC_CONTROL_PCOBFEN_Pos (2UL) /*!< KBC CONTROL: PCOBFEN (Bit 2) */
|
||||
#define KBC_CONTROL_PCOBFEN_Msk (0x4UL) /*!< KBC CONTROL: PCOBFEN (Bitfield-Mask: 0x01) */
|
||||
#define KBC_CONTROL_UD4_Pos (3UL) /*!< KBC CONTROL: UD4 (Bit 3) */
|
||||
#define KBC_CONTROL_UD4_Msk (0x18UL) /*!< KBC CONTROL: UD4 (Bitfield-Mask: 0x03) */
|
||||
#define KBC_CONTROL_OBFEN_Pos (5UL) /*!< KBC CONTROL: OBFEN (Bit 5) */
|
||||
#define KBC_CONTROL_OBFEN_Msk (0x20UL) /*!< KBC CONTROL: OBFEN (Bitfield-Mask: 0x01) */
|
||||
#define KBC_CONTROL_UD5_Pos (6UL) /*!< KBC CONTROL: UD5 (Bit 6) */
|
||||
#define KBC_CONTROL_UD5_Msk (0x40UL) /*!< KBC CONTROL: UD5 (Bitfield-Mask: 0x01) */
|
||||
#define KBC_CONTROL_AUXH_Pos (7UL) /*!< KBC CONTROL: AUXH (Bit 7) */
|
||||
#define KBC_CONTROL_AUXH_Msk (0x80UL) /*!< KBC CONTROL: AUXH (Bitfield-Mask: 0x01) */
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ struct 'PORT92' Position & Mask ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
|
||||
/* -------------------------------- PORT92_PORT92 ------------------------------- */
|
||||
#define PORT92_PORT92_ALT_CPU_RESET_Pos (0UL) /*!< PORT92 PORT92: ALT_CPU_RESET (Bit 0) */
|
||||
#define PORT92_PORT92_ALT_CPU_RESET_Msk (0x1UL) /*!< PORT92 PORT92: ALT_CPU_RESET (Bitfield-Mask: 0x01) */
|
||||
#define PORT92_PORT92_ALT_GATE_A20_Pos (1UL) /*!< PORT92 PORT92: ALT_GATE_A20 (Bit 1) */
|
||||
#define PORT92_PORT92_ALT_GATE_A20_Msk (0x2UL) /*!< PORT92 PORT92: ALT_GATE_A20 (Bitfield-Mask: 0x01) */
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ struct 'MBX' Position & Mask ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -21,8 +21,8 @@
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #1 $
|
||||
$DateTime: 2015/11/22 06:01:28 $
|
||||
$Author: amohandas $
|
||||
$DateTime: 2016/04/08 10:18:28 $
|
||||
$Author: pramans $
|
||||
Last Change: Updated with unit testing feedbacks
|
||||
******************************************************************************/
|
||||
/** @file btimer.h
|
||||
|
||||
@ -20,9 +20,9 @@
|
||||
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #2 $
|
||||
$DateTime: 2015/11/24 06:27:00 $
|
||||
$Author: amohandas $
|
||||
$Revision: #1 $
|
||||
$DateTime: 2016/04/08 10:18:28 $
|
||||
$Author: pramans $
|
||||
Last Change: Updated for tabs
|
||||
******************************************************************************/
|
||||
/** @file btimer_api.c
|
||||
@ -39,6 +39,7 @@ Last Change: Updated for tabs
|
||||
#include "common_lib.h"
|
||||
#include "btimer.h"
|
||||
#include "..\pcr\pcr.h"
|
||||
//#include "..\interrupt\ecia.h"
|
||||
|
||||
/** Basic Timer Sleep Registers & Bit Positions */
|
||||
static const uint32_t btmr_pcr_id[BTIMER_MAX_INSTANCE] = {
|
||||
|
||||
@ -20,9 +20,9 @@
|
||||
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #2 $
|
||||
$DateTime: 2015/11/24 06:27:00 $
|
||||
$Author: amohandas $
|
||||
$Revision: #1 $
|
||||
$DateTime: 2016/04/08 10:18:28 $
|
||||
$Author: pramans $
|
||||
Last Change: Updated for tabs
|
||||
******************************************************************************/
|
||||
/** @file btimer_perphl.c
|
||||
|
||||
@ -21,12 +21,12 @@
|
||||
* common.h
|
||||
* This is the header file including common headers from various modules
|
||||
**********************************************************************************
|
||||
* $Revision: #1 $ $DateTime: 2015/12/23 15:37:58 $ $ $
|
||||
* $Revision: #1 $ $DateTime: 2016/04/08 10:18:28 $ $ $
|
||||
* Description: added ict module
|
||||
**********************************************************************************
|
||||
* #xx
|
||||
**********************************************************************************
|
||||
* $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common.h $
|
||||
* $File: //depot_pcs/FWEng/Release/projects/CEC1302_PLIB_CLIB/release5/Source/hw_blks/common/include/common.h $
|
||||
*/
|
||||
|
||||
/*********************************************************************************/
|
||||
@ -50,7 +50,6 @@
|
||||
#include "ARM_REG.h"
|
||||
/* Cortex-M4 processor and core peripherals */
|
||||
#include "core_cm4.h"
|
||||
#include "MEC1322.h"
|
||||
|
||||
#include "defs.h"
|
||||
#include "string.h"
|
||||
@ -58,7 +57,7 @@
|
||||
#include "kernel.h"
|
||||
#include "..\system\system.h"
|
||||
#include "..\debug\trace.h"
|
||||
#include "..\interrupt\interrupt.h"
|
||||
#include "..\interrupt\irqhandler.h"
|
||||
#include "..\timer\timer_app.h"
|
||||
|
||||
#include "cec1302_crypto_api.h"
|
||||
|
||||
@ -21,12 +21,12 @@
|
||||
* common.h
|
||||
* This is the header file including common headers from various modules
|
||||
**********************************************************************************
|
||||
* $Revision: #1 $ $DateTime: 2015/12/23 15:37:58 $ $ $
|
||||
* $Revision: #1 $ $DateTime: 2016/04/08 10:18:28 $ $ $
|
||||
* Description: added ict module
|
||||
**********************************************************************************
|
||||
* #xx
|
||||
**********************************************************************************
|
||||
* $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common_lib.h $
|
||||
* $File: //depot_pcs/FWEng/Release/projects/CEC1302_PLIB_CLIB/release5/Source/hw_blks/common/include/common_lib.h $
|
||||
*/
|
||||
|
||||
/*********************************************************************************/
|
||||
@ -49,12 +49,11 @@
|
||||
#include "MCHP_CEC1302.h"
|
||||
/* Cortex-M4 processor and core peripherals */
|
||||
#include "core_cm4.h"
|
||||
#include "MEC1322.h"
|
||||
#include "defs.h"
|
||||
#include "string.h"
|
||||
//_RB_#include "build.h"
|
||||
//_RB_#include "..\system\system.h"
|
||||
//_RB_#include "..\debug\trace.h"
|
||||
//#include "build.h"
|
||||
//#include "..\system\system.h"
|
||||
//#include "..\debug\trace.h"
|
||||
#include <stdbool.h>
|
||||
#endif /*_COMMON_LIB_H_*/
|
||||
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
**********************************************************************************
|
||||
* #xx
|
||||
**********************************************************************************
|
||||
* $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/defs.h $
|
||||
* $File: //depot_pcs/FWEng/Release/projects/CEC1302_PLIB_CLIB/release5/Source/hw_blks/common/include/defs.h $
|
||||
*/
|
||||
|
||||
|
||||
|
||||
@ -21,8 +21,8 @@
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #1 $
|
||||
$DateTime: 2015/12/17 01:09:00 $
|
||||
$Author: snakka $
|
||||
$DateTime: 2016/04/08 10:18:28 $
|
||||
$Author: pramans $
|
||||
Last Change: Updated for peripheral functions prefix p_
|
||||
******************************************************************************/
|
||||
/** @file btimer.h
|
||||
@ -84,9 +84,6 @@ void htimer_reload(uint8_t htimer_id, uint16_t reload_value);
|
||||
*/
|
||||
void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value);
|
||||
|
||||
/*_RB_ Added by RB. */
|
||||
uint16_t p_htimer_preload_get(uint8_t htimer_id);
|
||||
|
||||
/** Sets hibernation timer resolution
|
||||
* @param htimer_id Hibernation Timer ID
|
||||
* @param resolution_mode 0 - resolution of 30.5us per LSB,
|
||||
|
||||
@ -21,8 +21,8 @@
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #1 $
|
||||
$DateTime: 2015/12/17 01:09:00 $
|
||||
$Author: snakka $
|
||||
$DateTime: 2016/04/08 10:18:28 $
|
||||
$Author: pramans $
|
||||
Last Change: Updated for peripheral functions prefix p_
|
||||
******************************************************************************/
|
||||
/** @file btimer_perphl.c
|
||||
|
||||
@ -21,8 +21,8 @@
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #1 $
|
||||
$DateTime: 2015/12/17 01:09:00 $
|
||||
$Author: snakka $
|
||||
$DateTime: 2016/04/08 10:18:28 $
|
||||
$Author: pramans $
|
||||
Last Change: Updated for peripheral functions prefix p_
|
||||
******************************************************************************/
|
||||
/** @file btimer_perphl.c
|
||||
@ -79,12 +79,6 @@ uint16_t p_htimer_count_get(uint8_t htimer_id)
|
||||
return htimer_count;
|
||||
}
|
||||
|
||||
/*_RB_ Added by RB. */
|
||||
uint16_t p_htimer_preload_get(uint8_t htimer_id)
|
||||
{
|
||||
return htmr_inst[htimer_id]->PRELOAD;
|
||||
}
|
||||
|
||||
|
||||
/* end htimer_perphl.c */
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/****************************************************************************
|
||||
* © 2013 Microchip Technology Inc. and its subsidiaries.
|
||||
/*****************************************************************************
|
||||
* © 2015 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
@ -16,220 +16,28 @@
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*/
|
||||
******************************************************************************
|
||||
|
||||
/** @defgroup interrupt interrupt
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #1 $
|
||||
$DateTime: 2016/04/08 10:18:28 $
|
||||
$Author: pramans $
|
||||
Last Change: Corrected several header definations
|
||||
******************************************************************************/
|
||||
/** @file interrupt.h
|
||||
* \brief Interrupt Header File
|
||||
* \author jvasanth
|
||||
*
|
||||
* This file implements the Interrupt Module Header file
|
||||
******************************************************************************/
|
||||
|
||||
/** @defgroup Interrupt
|
||||
* @{
|
||||
*/
|
||||
/** @file interrupt.h
|
||||
\brief This is the header file for interrupt.c
|
||||
This program is designed to allow the other C programs to be able to use this component
|
||||
|
||||
There are entry points for all C wrapper API implementation
|
||||
|
||||
<b>Platform:</b> This is ARC-based component
|
||||
|
||||
<b>Toolset:</b> Metaware IDE(8.5.1)
|
||||
<b>Reference:</b> smsc_reusable_fw_requirement.doc */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMSC version control information (Perforce):
|
||||
*
|
||||
* FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/kernel/skern/source/interrupt/interrupt.h $
|
||||
* REVISION: $Revision: #1 $
|
||||
* DATETIME: $DateTime: 2015/12/23 15:37:58 $
|
||||
* AUTHOR: $Author: akrishnan $
|
||||
*
|
||||
* Revision history (latest first):
|
||||
* #xx
|
||||
***********************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _INTERRUPT_H_
|
||||
#define _INTERRUPT_H_
|
||||
|
||||
|
||||
/* public function prototypes */
|
||||
void interrupt_block_init(void);
|
||||
void null_handler(void);
|
||||
|
||||
/* macro for interrupt control */
|
||||
/* 16-bit timers interrupt control */
|
||||
#define sbit_TIMER0 ( 1UL << 0UL )
|
||||
#define sbit_TIMER1 ( 1UL << 1UL )
|
||||
#define sbit_TIMER2 ( 1UL << 2UL )
|
||||
#define sbit_TIMER3 ( 1UL << 3Ul )
|
||||
|
||||
#define disable_timer0_irq() mCLR_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_ENABLE_SET)
|
||||
#define enable_timer0_irq() mSET_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_ENABLE_SET)
|
||||
#define clear_timer0_source() mCLR_SRC_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_SOURCE)
|
||||
#define get_timer0_source() mGET_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_SOURCE)
|
||||
|
||||
#define disable_timer1_irq() mCLR_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_ENABLE_SET)
|
||||
#define enable_timer1_irq() mSET_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_ENABLE_SET)
|
||||
#define clear_timer1_source() mCLR_SRC_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_SOURCE)
|
||||
#define get_timer1_source() mGET_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_SOURCE)
|
||||
|
||||
#define disable_timer2_irq() mCLR_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_ENABLE_SET)
|
||||
#define enable_timer2_irq() mSET_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_ENABLE_SET)
|
||||
#define clear_timer2_source() mCLR_SRC_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_SOURCE)
|
||||
#define get_timer2_source() mGET_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_SOURCE)
|
||||
|
||||
#define disable_timer3_irq() mCLR_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_ENABLE_SET)
|
||||
#define enable_timer3_irq() mSET_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_ENABLE_SET)
|
||||
#define clear_timer3_source() mCLR_SRC_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_SOURCE)
|
||||
#define get_timer3_source() mGET_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_SOURCE)
|
||||
|
||||
|
||||
/* hibernation timers interrupt control */
|
||||
#define sbit_HTIMER0 ( 1UL << 20 )
|
||||
#define sbit_HTIMER1 b_bit14
|
||||
|
||||
#define disable_htimer0_irq() mCLR_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_ENABLE_SET)
|
||||
#define enable_htimer0_irq() mSET_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_ENABLE_SET)
|
||||
#define clear_htimer0_source() mCLR_SRC_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_SOURCE)
|
||||
#define get_htimer0_source() mGET_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_SOURCE)
|
||||
|
||||
#define disable_htimer1_irq() mCLR_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_ENABLE_SET)
|
||||
#define enable_htimer1_irq() mSET_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_ENABLE_SET)
|
||||
#define clear_htimer1_source() mCLR_SRC_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_SOURCE)
|
||||
#define get_htimer1_source() mGET_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_SOURCE)
|
||||
|
||||
/* RTC interrupt control */
|
||||
#define b_bit18 (1 << 18)
|
||||
#define b_bit19 (1 << 19)
|
||||
#define sbit_RTC_INT b_bit18
|
||||
#define disable_rtc_irq() mCLR_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)
|
||||
#define enable_rtc_irq() mSET_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)
|
||||
#define clear_rtc_irq_source() mCLR_SRC_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)
|
||||
#define get_rtc_irq_source() mGET_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)
|
||||
/* RTC alarm interrupt control */
|
||||
#define sbit_RTC_ALM_INT b_bit19
|
||||
#define disable_rtc_alm_irq() mCLR_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)
|
||||
#define enable_rtc_alm_irq() mSET_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)
|
||||
#define clear_rtc_irq_alm_source() mCLR_SRC_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)
|
||||
#define get_rtc_irq_alm_source() mGET_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)
|
||||
|
||||
/* week timer interrupt control */
|
||||
#define sbit_WKTIMER b_bit7
|
||||
|
||||
#define disable_wktimer_irq() mCLR_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_ENABLE_SET)
|
||||
#define enable_wktimer_irq() mSET_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_ENABLE_SET)
|
||||
#define clear_wktimer_source() mCLR_SRC_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_SOURCE)
|
||||
#define get_wktimer_source() mGET_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_SOURCE)
|
||||
|
||||
|
||||
/* scan matrix interrupt control */
|
||||
#define sbit_SCANNER b_bit16
|
||||
#define disable_scanner_irq() mCLR_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_ENABLE_SET)
|
||||
#define enable_scanner_irq() mSET_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_ENABLE_SET)
|
||||
#define clear_scanner_source() mCLR_SRC_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_SOURCE)
|
||||
#define get_scanner_source() mGET_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_SOURCE)
|
||||
|
||||
|
||||
/* PS2 interrupt control */
|
||||
/* PS2 activity interrupt */
|
||||
#define sbit_PS2_ACT_0 b_bit13
|
||||
#define sbit_PS2_ACT_1 b_bit14
|
||||
#define sbit_PS2_ACT_2 b_bit15
|
||||
/* PS2 wakeup interrupt: detect start bit */
|
||||
#define sbit_PS2_WK_0A b_bit17
|
||||
#define sbit_PS2_WK_1B b_bit20
|
||||
#define sbit_PS2_WK_2 b_bit21
|
||||
|
||||
/* PS2 activity interrupt control */
|
||||
#define disable_ps2_act_0_irq() mCLR_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_ENABLE_SET)
|
||||
#define enable_ps2_act_0_irq() mSET_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_ENABLE_SET)
|
||||
#define clear_ps2_act_0_source() mCLR_SRC_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_SOURCE)
|
||||
#define get_ps2_act_0_source() mGET_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_SOURCE)
|
||||
|
||||
#define disable_ps2_act_1_irq() mCLR_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_ENABLE_SET)
|
||||
#define enable_ps2_act_1_irq() mSET_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_ENABLE_SET)
|
||||
#define clear_ps2_act_1_source() mCLR_SRC_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_SOURCE)
|
||||
#define get_ps2_act_1_source() mGET_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_SOURCE)
|
||||
|
||||
#define disable_ps2_act_2_irq() mCLR_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_ENABLE_SET)
|
||||
#define enable_ps2_act_2_irq() mSET_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_ENABLE_SET)
|
||||
#define clear_ps2_act_2_source() mCLR_SRC_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_SOURCE)
|
||||
#define get_ps2_act_2_source() mGET_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_SOURCE)
|
||||
|
||||
/* PS2 wakeup interrupt control */
|
||||
#define disable_ps2_wk_0_irq() mCLR_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_ENABLE_SET)
|
||||
#define enable_ps2_wk_0_irq() mSET_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_ENABLE_SET)
|
||||
#define clear_ps2_wk_0_source() mCLR_SRC_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_SOURCE)
|
||||
#define get_ps2_wk_0_source() mGET_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_SOURCE)
|
||||
|
||||
#define disable_ps2_wk_1_irq() mCLR_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_ENABLE_SET)
|
||||
#define enable_ps2_wk_1_irq() mSET_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_ENABLE_SET)
|
||||
#define clear_ps2_wk_1_source() mCLR_SRC_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_SOURCE)
|
||||
#define get_ps2_wk_1_source() mGET_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_SOURCE)
|
||||
|
||||
#define disable_ps2_wk_2_irq() mCLR_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_ENABLE_SET)
|
||||
#define enable_ps2_wk_2_irq() mSET_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_ENABLE_SET)
|
||||
#define clear_ps2_wk_2_source() mCLR_SRC_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_SOURCE)
|
||||
#define get_ps2_wk_2_source() mGET_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_SOURCE)
|
||||
|
||||
|
||||
/* ICT interrupt control */
|
||||
/* capture 0~5 interrupt */
|
||||
#define sbit_ICT_CAPTURE0 b_bit17
|
||||
#define sbit_ICT_CAPTURE1 b_bit18
|
||||
#define sbit_ICT_CAPTURE2 b_bit19
|
||||
#define sbit_ICT_CAPTURE3 b_bit20
|
||||
#define sbit_ICT_CAPTURE4 b_bit21
|
||||
#define sbit_ICT_CAPTURE5 b_bit22
|
||||
|
||||
/* capture 0 interrupt control */
|
||||
#define disable_capture0_irq() mCLR_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_ENABLE_SET)
|
||||
#define enable_capture0_irq() mSET_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_ENABLE_SET)
|
||||
#define clear_capture0_source() mCLR_SRC_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_SOURCE)
|
||||
#define get_capture0_source() mGET_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_SOURCE)
|
||||
|
||||
|
||||
/* SMBus interrupt control */
|
||||
|
||||
|
||||
/* GPIO interrupt control */
|
||||
|
||||
|
||||
/* BC link interrupt control */
|
||||
/* bclink A~D interrupt */
|
||||
#define sbit_BCLINK_A_BUSY b_bit0
|
||||
#define sbit_BCLINK_A_ERR b_bit1
|
||||
#define sbit_BCLINK_A_INT b_bit2
|
||||
#define sbit_BCLINK_B_BUSY b_bit3
|
||||
#define sbit_BCLINK_B_ERR b_bit4
|
||||
#define sbit_BCLINK_B_INT b_bit5
|
||||
#define sbit_BCLINK_C_BUSY b_bit6
|
||||
#define sbit_BCLINK_C_ERR b_bit7
|
||||
#define sbit_BCLINK_C_INT b_bit8
|
||||
#define sbit_BCLINK_D_BUSY b_bit9
|
||||
#define sbit_BCLINK_D_ERR b_bit10
|
||||
#define sbit_BCLINK_D_INT b_bit11
|
||||
|
||||
/* bclink B interrupt control */
|
||||
#define disable_bclink_b_busy_irq() mCLR_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_ENABLE_SET)
|
||||
#define enable_bclink_b_busy_irq() mSET_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_ENABLE_SET)
|
||||
#define clear_bclink_b_busy_source() mCLR_SRC_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_SOURCE)
|
||||
#define get_bclink_b_busy_source() mGET_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_SOURCE)
|
||||
|
||||
#define disable_bclink_b_err_irq() mCLR_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_ENABLE_SET)
|
||||
#define enable_bclink_b_err_irq() mSET_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_ENABLE_SET)
|
||||
#define clear_bclink_b_err_source() mCLR_SRC_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_SOURCE)
|
||||
#define get_bclink_b_err_source() mGET_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_SOURCE)
|
||||
|
||||
#define disable_bclink_b_int_irq() mCLR_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_ENABLE_SET)
|
||||
#define enable_bclink_b_int_irq() mSET_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_ENABLE_SET)
|
||||
#define clear_bclink_b_int_source() mCLR_SRC_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_SOURCE)
|
||||
#define get_bclink_b_int_source() mGET_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_SOURCE)
|
||||
|
||||
/* UART interrupt control */
|
||||
#define sbit_UART_INT b_bit0
|
||||
|
||||
#define disable_uart_irq() mCLR_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_ENABLE_SET)
|
||||
#define enable_uart_irq() mSET_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_ENABLE_SET)
|
||||
#define clear_uart_irq_source() mCLR_SRC_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_SOURCE)
|
||||
#define get_uart_irq_source() mGET_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_SOURCE)
|
||||
#ifndef _INTERRUPT_H
|
||||
#define _INTERRUPT_H
|
||||
|
||||
// GIRQ IDs for EC Interrupt Aggregator
|
||||
enum MEC_GIRQ_IDS
|
||||
@ -303,6 +111,7 @@ enum MEC_GIRQ_IDS
|
||||
#define GPIO_0143_IROUTE IROUTE(3,8,57,57)
|
||||
#define GPIO_0144_IROUTE IROUTE(4,8,57,57)
|
||||
#define GPIO_0145_IROUTE IROUTE(5,8,57,57)
|
||||
#define GPIO_0146_IROUTE IROUTE(6,8,57,57)
|
||||
#define GPIO_0147_IROUTE IROUTE(7,8,57,57)
|
||||
//
|
||||
#define GPIO_0150_IROUTE IROUTE(8,8,57,57)
|
||||
@ -320,8 +129,6 @@ enum MEC_GIRQ_IDS
|
||||
#define GPIO_0163_IROUTE IROUTE(19,8,57,57)
|
||||
#define GPIO_0164_IROUTE IROUTE(20,8,57,57)
|
||||
#define GPIO_0165_IROUTE IROUTE(21,8,57,57)
|
||||
#define GPIO_0166_IROUTE IROUTE(22,8,57,57)
|
||||
#define GPIO_0167_IROUTE IROUTE(23,8,57,57)
|
||||
|
||||
//
|
||||
// GIRQ09
|
||||
@ -332,7 +139,7 @@ enum MEC_GIRQ_IDS
|
||||
#define GPIO_0103_IROUTE IROUTE(3,9,58,58)
|
||||
#define GPIO_0104_IROUTE IROUTE(4,9,58,58)
|
||||
#define GPIO_0105_IROUTE IROUTE(5,9,58,58)
|
||||
#define GPIO_0105_IROUTE IROUTE(5,9,58,58)
|
||||
#define GPIO_0106_IROUTE IROUTE(6,9,58,58)
|
||||
#define GPIO_0107_IROUTE IROUTE(7,9,58,58)
|
||||
//
|
||||
#define GPIO_0110_IROUTE IROUTE(8,9,58,58)
|
||||
@ -369,7 +176,7 @@ enum MEC_GIRQ_IDS
|
||||
#define GPIO_0043_IROUTE IROUTE(3,10,59,59)
|
||||
#define GPIO_0044_IROUTE IROUTE(4,10,59,59)
|
||||
#define GPIO_0045_IROUTE IROUTE(5,10,59,59)
|
||||
#define GPIO_0045_IROUTE IROUTE(5,10,59,59)
|
||||
#define GPIO_0046_IROUTE IROUTE(6,10,59,59)
|
||||
#define GPIO_0047_IROUTE IROUTE(7,10,59,59)
|
||||
//
|
||||
#define GPIO_0050_IROUTE IROUTE(8,10,59,59)
|
||||
@ -389,14 +196,6 @@ enum MEC_GIRQ_IDS
|
||||
#define GPIO_0065_IROUTE IROUTE(21,10,59,59)
|
||||
#define GPIO_0066_IROUTE IROUTE(22,10,59,59)
|
||||
#define GPIO_0067_IROUTE IROUTE(23,10,59,59)
|
||||
//
|
||||
#define GPIO_0070_IROUTE IROUTE(24,10,59,59)
|
||||
#define GPIO_0071_IROUTE IROUTE(25,10,59,59)
|
||||
#define GPIO_0072_IROUTE IROUTE(26,10,59,59)
|
||||
#define GPIO_0073_IROUTE IROUTE(27,10,59,59)
|
||||
#define GPIO_0074_IROUTE IROUTE(28,10,59,59)
|
||||
#define GPIO_0075_IROUTE IROUTE(29,10,59,59)
|
||||
#define GPIO_0076_IROUTE IROUTE(30,10,59,59)
|
||||
|
||||
//
|
||||
// GIRQ11
|
||||
@ -443,12 +242,11 @@ enum MEC_GIRQ_IDS
|
||||
#define SMB1_IROUTE IROUTE(1,12,61,1)
|
||||
#define SMB2_IROUTE IROUTE(2,12,61,2)
|
||||
#define SMB3_IROUTE IROUTE(3,12,61,3)
|
||||
// SMB wakes have no direct connection to NVIC, always aggregated
|
||||
#define SMB0_WAKE_IROUTE IROUTE(4,12,61,61)
|
||||
#define SMB1_WAKE_IROUTE IROUTE(5,12,61,61)
|
||||
#define SMB2_WAKE_IROUTE IROUTE(6,12,61,61)
|
||||
#define SMB3_WAKE_IROUTE IROUTE(7,12,61,61)
|
||||
#define SMB4_WAKE_IROUTE IROUTE(8,12,61,61)
|
||||
#define I2C0_0_WAKE_IROUTE IROUTE(4,12,61,61)
|
||||
#define I2C0_1_WAKE_IROUTE IROUTE(5,12,61,61)
|
||||
#define I2C2_0_WAKE_IROUTE IROUTE(6,12,61,61)
|
||||
#define I2C1_0_WAKE_IROUTE IROUTE(7,12,61,61)
|
||||
#define I2C3_0_WAKE_IROUTE IROUTE(8,12,61,61)
|
||||
|
||||
//
|
||||
// GIRQ13
|
||||
@ -519,9 +317,9 @@ enum MEC_GIRQ_IDS
|
||||
#define RPM_STALL_IROUTE IROUTE(23,17,66,41)
|
||||
#define RPM_SPIN_IROUTE IROUTE(24,17,66,42)
|
||||
#define PFR_IROUTE IROUTE(25,17,66,43)
|
||||
#define LED0_IROUTE IROUTE(26,17,66,44)
|
||||
#define LED1_IROUTE IROUTE(27,17,66,45)
|
||||
#define LED2_IROUTE IROUTE(28,17,66,46)
|
||||
#define PWM_WDT_0_IROUTE IROUTE(26,17,66,44)
|
||||
#define PWM_WDT_1_IROUTE IROUTE(27,17,66,45)
|
||||
#define PWM_WDT_2_IROUTE IROUTE(28,17,66,46)
|
||||
#define BCM_ERR_IROUTE IROUTE(29,17,66,47)
|
||||
#define BCM_BUSY_IROUTE IROUTE(30,17,66,48)
|
||||
|
||||
@ -542,8 +340,8 @@ enum MEC_GIRQ_IDS
|
||||
//
|
||||
// GIRQ19, Aggregated only
|
||||
//
|
||||
#define LRESET_IROUTE IROUTE(0,19,68,68)
|
||||
#define VCC_PWRGD_IROUTE IROUTE(1,19,68,68)
|
||||
#define VCC_PWRGD_IROUTE IROUTE(0,19,68,68)
|
||||
#define LRESET_IROUTE IROUTE(1,19,68,68)
|
||||
|
||||
//
|
||||
// GIRQ20, Aggregated only
|
||||
@ -553,6 +351,7 @@ enum MEC_GIRQ_IDS
|
||||
#define GPIO_0202_IROUTE IROUTE(2,20,69,69)
|
||||
#define GPIO_0203_IROUTE IROUTE(3,20,69,69)
|
||||
#define GPIO_0204_IROUTE IROUTE(4,20,69,69)
|
||||
//
|
||||
#define GPIO_0206_IROUTE IROUTE(6,20,69,69)
|
||||
//
|
||||
#define GPIO_0210_IROUTE IROUTE(8,20,69,69)
|
||||
@ -580,14 +379,17 @@ enum MEC_GIRQ_IDS
|
||||
#define BTMR4_IROUTE IROUTE(4,23,72,53)
|
||||
#define BTMR5_IROUTE IROUTE(5,23,72,54)
|
||||
|
||||
|
||||
//
|
||||
// GIRQ08 Bit Positions
|
||||
//
|
||||
#define GIRQ08_GPIO_0140_BITPOS (0)
|
||||
#define GIRQ08_GPIO_0141_BITPOS (1)
|
||||
#define GIRQ08_GPIO_0142_BITPOS (2)
|
||||
#define GIRQ08_GPIO_0143_BITPOS (3)
|
||||
#define GIRQ08_GPIO_0144_BITPOS (4)
|
||||
#define GIRQ08_GPIO_0145_BITPOS (5)
|
||||
//#define GIRQ08_GPIO_0146_BITPOS (6) RESERVED
|
||||
#define GIRQ08_GPIO_0146_BITPOS (6)
|
||||
#define GIRQ08_GPIO_0147_BITPOS (7)
|
||||
//
|
||||
#define GIRQ08_GPIO_0150_BITPOS (8)
|
||||
@ -612,7 +414,9 @@ enum MEC_GIRQ_IDS
|
||||
#define GIRQ08_WAKE_CAPABLE_MASK (0x00FFFFBFul)
|
||||
//
|
||||
|
||||
//
|
||||
// GIRQ09 Bit Positions
|
||||
//
|
||||
#define GIRQ09_GPIO_0100_BITPOS (0)
|
||||
#define GIRQ09_GPIO_0101_BITPOS (1)
|
||||
#define GIRQ09_GPIO_0102_BITPOS (2)
|
||||
@ -634,7 +438,7 @@ enum MEC_GIRQ_IDS
|
||||
#define GIRQ09_GPIO_0120_BITPOS (16)
|
||||
#define GIRQ09_GPIO_0121_BITPOS (17)
|
||||
#define GIRQ09_GPIO_0122_BITPOS (18)
|
||||
//#define GIRQ09_GPIO_0123_BITPOS (19) RESERVED
|
||||
#define GIRQ09_GPIO_0123_BITPOS (19)
|
||||
#define GIRQ09_GPIO_0124_BITPOS (20)
|
||||
#define GIRQ09_GPIO_0125_BITPOS (21)
|
||||
#define GIRQ09_GPIO_0126_BITPOS (22)
|
||||
@ -647,13 +451,14 @@ enum MEC_GIRQ_IDS
|
||||
#define GIRQ09_GPIO_0134_BITPOS (28)
|
||||
#define GIRQ09_GPIO_0135_BITPOS (29)
|
||||
#define GIRQ09_GPIO_0136_BITPOS (30)
|
||||
//#define GIRQ09_GPIO_0137_BITPOS (31) RESERVED
|
||||
//
|
||||
#define GIRQ09_MASK (0x7FF7FFFFul)
|
||||
#define GIRQ09_WAKE_CAPABLE_MASK (0x7FF7FFFFul)
|
||||
//
|
||||
|
||||
//
|
||||
// GIRQ10 Bit Positions
|
||||
//
|
||||
#define GIRQ10_GPIO_0040_BITPOS (0)
|
||||
#define GIRQ10_GPIO_0041_BITPOS (1)
|
||||
#define GIRQ10_GPIO_0042_BITPOS (2)
|
||||
@ -681,15 +486,6 @@ enum MEC_GIRQ_IDS
|
||||
#define GIRQ10_GPIO_0066_BITPOS (22)
|
||||
#define GIRQ10_GPIO_0067_BITPOS (23)
|
||||
//
|
||||
#define GIRQ10_GPIO_0070_BITPOS (24)
|
||||
#define GIRQ10_GPIO_0071_BITPOS (25)
|
||||
#define GIRQ10_GPIO_0072_BITPOS (26)
|
||||
#define GIRQ10_GPIO_0073_BITPOS (27)
|
||||
#define GIRQ10_GPIO_0074_BITPOS (28)
|
||||
#define GIRQ10_GPIO_0075_BITPOS (29)
|
||||
#define GIRQ10_GPIO_0076_BITPOS (30)
|
||||
//#define GIRQ10_GPIO_0077_BITPOS (31) RESERVED
|
||||
//
|
||||
#define GIRQ10_MASK (0x7FFFFFFFul)
|
||||
#define GIRQ10_WAKE_CAPABLE_MASK (0x7FFFFFFFul)
|
||||
//
|
||||
@ -729,7 +525,6 @@ enum MEC_GIRQ_IDS
|
||||
#define GIRQ11_GPIO_0034_BITPOS (28)
|
||||
#define GIRQ11_GPIO_0035_BITPOS (29)
|
||||
#define GIRQ11_GPIO_0036_BITPOS (30)
|
||||
//#define GIRQ11_GPIO_0037_BITPOS (31) RESERVED
|
||||
//
|
||||
#define GIRQ11_MASK (0x7FFFFFFFul)
|
||||
#define GIRQ11_WAKE_CAPABLE_MASK (0x7FFFFFFFul)
|
||||
@ -740,17 +535,19 @@ enum MEC_GIRQ_IDS
|
||||
#define GIRQ12_SMBUS1_BITPOS (1)
|
||||
#define GIRQ12_SMBUS2_BITPOS (2)
|
||||
#define GIRQ12_SMBUS3_BITPOS (3)
|
||||
#define GIRQ12_SMBUS0_WAKE_BITPOS (4)
|
||||
#define GIRQ12_SMBUS1_WAKE_BITPOS (5)
|
||||
#define GIRQ12_SMBUS2_WAKE_BITPOS (6)
|
||||
#define GIRQ12_SMBUS3_WAKE_BITPOS (7)
|
||||
#define GIRQ12_SMBUS4_WAKE_BITPOS (8)
|
||||
// RESERVED bits[31:9]
|
||||
#define GIRQ12_I2C0_0_WAKE_BITPOS (4)
|
||||
#define GIRQ12_I2C0_1_WAKE_BITPOS (5)
|
||||
#define GIRQ12_I2C2_0_WAKE_BITPOS (6)
|
||||
#define GIRQ12_I2C1_0_WAKE_BITPOS (7)
|
||||
#define GIRQ12_I2C3_0_WAKE_BITPOS (8)
|
||||
//
|
||||
#define GIRQ12_MASK (0x01FFul)
|
||||
#define GIRQ12_WAKE_CAPABLE_MASK (0x01F0ul)
|
||||
//
|
||||
|
||||
//
|
||||
// GIRQ13 Bit Positions
|
||||
//
|
||||
#define GIRQ13_DMA0_BITPOS (16)
|
||||
#define GIRQ13_DMA1_BITPOS (17)
|
||||
#define GIRQ13_DMA2_BITPOS (18)
|
||||
@ -768,18 +565,20 @@ enum MEC_GIRQ_IDS
|
||||
#define GIRQ13_WAKE_CAPABLE_MASK (0x00000000ul)
|
||||
//
|
||||
|
||||
//
|
||||
// GIRQ14 Bit Positions
|
||||
//
|
||||
#define GIRQ14_LPC_BITPOS (2)
|
||||
//
|
||||
#define GIRQ14_MASK (0x04ul)
|
||||
#define GIRQ14_WAKE_CAPABLE_MASK (0x00ul)
|
||||
//
|
||||
|
||||
//
|
||||
// GIRQ15 Bit Positions
|
||||
//
|
||||
#define GIRQ15_UART0_BITPOS (0)
|
||||
#define GIRQ15_IMAP_BITPOS (2)
|
||||
#define GIRQ15_KBD_K_BITPOS (3)
|
||||
#define GIRQ15_KBD_M_BITPOS (4)
|
||||
#define GIRQ15_ACPI0_IBF_BITPOS (6)
|
||||
#define GIRQ15_ACPI0_OBF_BITPOS (7)
|
||||
#define GIRQ15_ACPI1_IBF_BITPOS (8)
|
||||
@ -796,14 +595,18 @@ enum MEC_GIRQ_IDS
|
||||
#define GIRQ15_WAKE_CAPABLE_MASK (0x000000ul)
|
||||
//
|
||||
|
||||
//
|
||||
// GIRQ16 Bit Positions
|
||||
//
|
||||
#define GIRQ16_PECI_BITPOS (3)
|
||||
//
|
||||
#define GIRQ16_MASK (0x08ul)
|
||||
#define GIRQ16_WAKE_CAPABLE_MASK (0x00ul)
|
||||
//
|
||||
|
||||
//
|
||||
// GIRQ17 Bit Positions
|
||||
//
|
||||
#define GIRQ17_TACH0_BITPOS (0)
|
||||
#define GIRQ17_TACH1_BITPOS (1)
|
||||
#define GIRQ17_PS2_0_WAKE_BITPOS (2)
|
||||
@ -820,16 +623,17 @@ enum MEC_GIRQ_IDS
|
||||
#define GIRQ17_PS2_1_BITPOS (15)
|
||||
#define GIRQ17_PS2_2_BITPOS (16)
|
||||
#define GIRQ17_PS2_3_BITPOS (17)
|
||||
// RESERVED b[19:18]
|
||||
#define GIRQ17_RTC_BITPOS (18)
|
||||
#define GIRQ17_RTC_ALARM_BITPOS (19)
|
||||
#define GIRQ17_HIBTMR_BITPOS (20)
|
||||
#define GIRQ17_KEY_INT_BITPOS (21)
|
||||
#define GIRQ17_KEY_INT_WAKE_BITPOS (22)
|
||||
#define GIRQ17_RPM_STALL_BITPOS (23)
|
||||
#define GIRQ17_RPM_SPIN_BITPOS (24)
|
||||
#define GIRQ17_VBAT_BITPOS (25)
|
||||
#define GIRQ17_LED0_BITPOS (26)
|
||||
#define GIRQ17_LED1_BITPOS (27)
|
||||
#define GIRQ17_LED2_BITPOS (28)
|
||||
#define GIRQ17_PWM_WDT_0_BITPOS (26)
|
||||
#define GIRQ17_PWM_WDT_1_BITPOS (27)
|
||||
#define GIRQ17_PWM_WDT_2_BITPOS (28)
|
||||
#define GIRQ17_MBC_ERR_BITPOS (29)
|
||||
#define GIRQ17_MBC_BUSY_BITPOS (30)
|
||||
//
|
||||
@ -837,12 +641,14 @@ enum MEC_GIRQ_IDS
|
||||
#define GIRQ17_WAKE_CAPABLE_MASK (0x0230007Cul)
|
||||
//
|
||||
|
||||
//
|
||||
// GIRQ18 Bit Positions
|
||||
//
|
||||
#define GIRQ18_SPI0_TX_BITPOS (0)
|
||||
#define GIRQ18_SPI0_RX_BITPOS (1)
|
||||
#define GIRQ18_SPI1_TX_BITPOS (2)
|
||||
#define GIRQ18_SPI1_RX_BITPOS (3)
|
||||
#define GIRQ18_LED3_BITPOS (4) // NVIC 85
|
||||
#define GIRQ18_PWM_WDT_3_BITPOS (4) // NVIC 85
|
||||
#define GIRQ18_PKE_ERR_BITPOS (5) // NVIC 86
|
||||
#define GIRQ18_PKE_END_BITPOS (6) // NVIC 87
|
||||
#define GIRQ18_TRNG_BITPOS (7) // NVIC 88
|
||||
@ -853,23 +659,26 @@ enum MEC_GIRQ_IDS
|
||||
#define GIRQ18_WAKE_CAPABLE_MASK (0x000ul)
|
||||
//
|
||||
|
||||
//
|
||||
// GIRQ19 Bit Positions
|
||||
#define GIRQ19_LRESET_BITPOS (0)
|
||||
#define GIRQ19_VCC_PWRGD_BITPOS (1)
|
||||
//
|
||||
#define GIRQ19_VCC_PWRGD_BITPOS (0)
|
||||
#define GIRQ19_LRESET_BITPOS (1)
|
||||
//
|
||||
#define GIRQ19_MASK (0x03ul)
|
||||
#define GIRQ19_WAKE_CAPABLE_MASK (0x03ul)
|
||||
//
|
||||
|
||||
//
|
||||
// GIRQ20 Bit Positions
|
||||
//
|
||||
#define GIRQ20_GPIO_0200_BITPOS (0)
|
||||
#define GIRQ20_GPIO_0201_BITPOS (1)
|
||||
#define GIRQ20_GPIO_0202_BITPOS (2)
|
||||
#define GIRQ20_GPIO_0203_BITPOS (3)
|
||||
#define GIRQ20_GPIO_0204_BITPOS (4)
|
||||
//#define GIRQ20_GPIO_0205_BITPOS (5)
|
||||
//
|
||||
#define GIRQ20_GPIO_0206_BITPOS (6)
|
||||
//#define GIRQ20_GPIO_0207_BITPOS (7)
|
||||
//
|
||||
#define GIRQ20_GPIO_0210_BITPOS (8)
|
||||
#define GIRQ20_GPIO_0211_BITPOS (9)
|
||||
@ -880,15 +689,21 @@ enum MEC_GIRQ_IDS
|
||||
#define GIRQ20_WAKE_CAPABLE_MASK (0x0F5Ful)
|
||||
//
|
||||
|
||||
//
|
||||
// GIRQ21 Bit Positions
|
||||
//
|
||||
#define GIRQ21_MASK (0x00ul)
|
||||
#define GIRQ21_WAKE_CAPABLE_MASK (0x00ul)
|
||||
|
||||
//
|
||||
// GIRQ22 Bit Positions
|
||||
//
|
||||
#define GIRQ22_MASK (0x00ul)
|
||||
#define GIRQ22_WAKE_CAPABLE_MASK (0x00ul)
|
||||
|
||||
//
|
||||
// GIRQ23 Bit Positions
|
||||
//
|
||||
#define GIRQ23_TMR0_BITPOS (0)
|
||||
#define GIRQ23_TMR1_BITPOS (1)
|
||||
#define GIRQ23_TMR2_BITPOS (2)
|
||||
@ -900,6 +715,7 @@ enum MEC_GIRQ_IDS
|
||||
#define GIRQ23_WAKE_CAPABLE_MASK (0x000ul)
|
||||
//
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------------- */
|
||||
/* NVIC,ECIA Routing Policy for Direct Mode */
|
||||
/* ------------------------------------------------------------------------------- */
|
||||
@ -1167,8 +983,8 @@ void p_interrupt_nvic_priorities_default_set(void);
|
||||
*/
|
||||
void p_interrupt_nvic_priorities_set(uint8_t new_pri);
|
||||
|
||||
#endif /*_INTERRUPT_H_*/
|
||||
|
||||
#endif // #ifndef _INTERRUPT_H
|
||||
/* end interrupt.h */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
||||
@ -21,8 +21,8 @@
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #1 $
|
||||
$DateTime: 2015/11/24 06:28:28 $
|
||||
$Author: amohandas $
|
||||
$DateTime: 2016/04/08 10:18:28 $
|
||||
$Author: pramans $
|
||||
Last Change: Updated for tabs
|
||||
******************************************************************************/
|
||||
/** @file pcr.h
|
||||
|
||||
@ -21,8 +21,8 @@
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #1 $
|
||||
$DateTime: 2015/11/24 06:28:28 $
|
||||
$Author: amohandas $
|
||||
$DateTime: 2016/04/08 10:18:28 $
|
||||
$Author: pramans $
|
||||
Last Change: Updated for tabs
|
||||
******************************************************************************/
|
||||
/** @file pcr_api.c
|
||||
|
||||
@ -21,8 +21,8 @@
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #1 $
|
||||
$DateTime: 2015/11/24 06:28:28 $
|
||||
$Author: amohandas $
|
||||
$DateTime: 2016/04/08 10:18:28 $
|
||||
$Author: pramans $
|
||||
Last Change: Updated for tabs
|
||||
******************************************************************************/
|
||||
/** @file pcr_perphl.c
|
||||
|
||||
@ -35,10 +35,10 @@
|
||||
/*******************************************************************************
|
||||
* SMSC version control information (Perforce):
|
||||
*
|
||||
* FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/platform.h $
|
||||
* FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_PLIB_CLIB/release5/Source/hw_blks/common/include/platform.h $
|
||||
* REVISION: $Revision: #1 $
|
||||
* DATETIME: $DateTime: 2015/12/23 15:37:58 $
|
||||
* AUTHOR: $Author: akrishnan $
|
||||
* DATETIME: $DateTime: 2016/04/08 10:18:28 $
|
||||
* AUTHOR: $Author: pramans $
|
||||
*
|
||||
* Revision history (latest first):
|
||||
* #xx
|
||||
@ -48,6 +48,12 @@
|
||||
#ifndef _PLATFORM_H_
|
||||
#define _PLATFORM_H_
|
||||
#include <stdint.h>
|
||||
|
||||
/* Enable any one of the below flag which enables either Aggregated or Disaggregated Interrupts */
|
||||
#define DISAGGREGATED_INPT_DEFINED 1
|
||||
//#define AGGREGATED_INPT_DEFINED 1
|
||||
|
||||
|
||||
/* Platform Configuration PreProcessor Conditions */
|
||||
#define TOOLKEIL 1
|
||||
#define TOOLPC 2
|
||||
@ -132,6 +138,10 @@ typedef signed long INT32;
|
||||
|
||||
typedef void VOID;
|
||||
|
||||
typedef volatile unsigned char VUINT8;
|
||||
typedef volatile unsigned short int VUINT16;
|
||||
typedef volatile unsigned long int VUINT32;
|
||||
|
||||
/* union types */
|
||||
typedef union _BITS_8
|
||||
{
|
||||
@ -189,7 +199,7 @@ typedef union _BITS_8
|
||||
#define FUNC_NEVER_RETURNS
|
||||
#define BEGIN_SMALL_DATA_BLOCK(x)
|
||||
#define END_SMALL_DATA_BLOCK()
|
||||
UINT32 soft_norm(UINT32 val);
|
||||
uint32_t soft_norm(uint32_t val);
|
||||
#define NORM(x) soft_norm(x)
|
||||
//
|
||||
#define USE_FUNC_REPLACEMENT 0
|
||||
@ -228,7 +238,7 @@ UINT32 soft_norm(UINT32 val);
|
||||
#define FUNC_NEVER_RETURNS
|
||||
#define BEGIN_SMALL_DATA_BLOCK(x)
|
||||
#define END_SMALL_DATA_BLOCK()
|
||||
UINT32 soft_norm(UINT32 val);
|
||||
uint32_t soft_norm(uint32_t val);
|
||||
#define NORM(x) soft_norm(x)
|
||||
//
|
||||
#define USE_FUNC_REPLACEMENT 0
|
||||
@ -335,7 +345,7 @@ UINT32 soft_norm(UINT32 val);
|
||||
#else
|
||||
/* for ARM MDK */
|
||||
#define FUNC_NEVER_RETURNS
|
||||
UINT32 soft_norm(UINT32 val);
|
||||
uint32_t soft_norm(uint32_t val);
|
||||
#define NORM(x) soft_norm(x)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user