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Remove ACE files that are not necessary for the SmartFusion demo.

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This commit is contained in:
Richard Barry 2011-04-28 14:59:31 +00:00
parent 65ceb00a1f
commit d23df3d0af
5 changed files with 281 additions and 2730 deletions
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1678
Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/drivers/mss_ace/ace_flags.c
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File diff suppressed because it is too large Load Diff

306
Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/drivers/mss_ace/ace_sse.c
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@ -1,306 +0,0 @@
/*******************************************************************************
* (c) Copyright 2009 Actel Corporation. All rights reserved.
*
* SVN $Revision: 2905 $
* SVN $Date: 2010-08-20 14:03:28 +0100 (Fri, 20 Aug 2010) $
*/
#include "mss_ace.h"
#include "mss_ace_configurator.h"
#include "../../drivers_config/mss_ace/ace_handles.h"
#include "../../drivers_config/mss_ace/ace_config.h"
#include "../../CMSIS/a2fxxxm3.h"
#include "../../CMSIS/mss_assert.h"
#include <string.h>
#ifdef __cplusplus
extern "C" {
#endif
#define SSE_START 1uL
#define SSE_STOP 0uL
#define NB_OF_ANALOG_BLOCKS 3u
#define SEE_RAM_WORD_SIZE 512
#define TS_ENABLE_MASK 0x01u
#define PPE_ENABLE_MASK 0x01u
#define ADC_RESET_MASK 0x10u
#define ADC_FIFO_CLR_MASK 0x04u
#define PDMA_DATAOUT_CLR_MASK 0x04u
/*-------------------------------------------------------------------------*//**
*
*/
extern ace_procedure_desc_t g_sse_sequences_desc_table[ACE_NB_OF_SSE_PROCEDURES];
/*-------------------------------------------------------------------------*//**
*
*/
sse_sequence_handle_t
ACE_get_sse_seq_handle
(
const uint8_t * p_sz_sequence_name
)
{
uint16_t seq_idx;
sse_sequence_handle_t handle = INVALID_SSE_SEQ_HANDLE;
for ( seq_idx = 0u; seq_idx < (uint32_t)ACE_NB_OF_SSE_PROCEDURES; ++seq_idx )
{
if ( g_sse_sequences_desc_table[seq_idx].p_sz_proc_name != 0 )
{
int32_t diff;
diff = strncmp( (const char *)p_sz_sequence_name, (const char *)g_sse_sequences_desc_table[seq_idx].p_sz_proc_name, MAX_PROCEDURE_NAME_LENGTH );
if ( 0 == diff )
{
/* channel name found. */
handle = seq_idx;
break;
}
}
}
return handle;
}
/*-------------------------------------------------------------------------*//**
*
*/
static uint32_t volatile * const sse_pc_ctrl_lut[NB_OF_ANALOG_BLOCKS] =
{
&ACE->PC0_CTRL,
&ACE->PC1_CTRL,
&ACE->PC2_CTRL
};
static uint32_t volatile * const sse_pc_lo_lut[NB_OF_ANALOG_BLOCKS] =
{
&ACE->PC0_LO,
&ACE->PC1_LO,
&ACE->PC2_LO
};
static uint32_t volatile * const sse_pc_hi_lut[NB_OF_ANALOG_BLOCKS] =
{
&ACE->PC0_HI,
&ACE->PC1_HI,
&ACE->PC2_HI
};
/*-------------------------------------------------------------------------*//**
*
*/
void ACE_load_sse
(
sse_sequence_handle_t sequence
)
{
ASSERT( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES );
if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )
{
uint16_t i;
uint16_t offset;
const uint16_t * p_ucode;
ASSERT( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS );
if ( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS )
{
/* Stop relevant program counter. */
*sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_STOP;
/* Load microcode into SEE RAM.*/
p_ucode = g_sse_sequences_desc_table[sequence].sse_ucode;
offset = g_sse_sequences_desc_table[sequence].sse_load_offset;
for ( i = 0u; i < g_sse_sequences_desc_table[sequence].sse_ucode_length; ++i )
{
ACE->SSE_RAM_DATA[offset + i] = (uint32_t)*p_ucode;
++p_ucode;
}
}
}
}
/*-------------------------------------------------------------------------*//**
*
*/
void ACE_start_sse
(
sse_sequence_handle_t sequence
)
{
ASSERT( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES );
if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )
{
uint16_t pc;
ASSERT( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS );
ASSERT( g_sse_sequences_desc_table[sequence].sse_load_offset < SEE_RAM_WORD_SIZE );
pc = g_sse_sequences_desc_table[sequence].sse_load_offset;
if ( pc < 256u )
{
*sse_pc_lo_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc;
}
else
{
*sse_pc_hi_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc - 256;
}
*sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_START;
/* Enable Sample Sequencing Engine in case it was not done as part of
* system boot. */
ACE->SSE_TS_CTRL |= TS_ENABLE_MASK;
}
}
/*-------------------------------------------------------------------------*//**
*
*/
void ACE_restart_sse
(
sse_sequence_handle_t sequence
)
{
ASSERT( sequence < ACE_NB_OF_SSE_PROCEDURES );
ASSERT( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS );
ASSERT( g_sse_sequences_desc_table[sequence].sse_load_offset < SEE_RAM_WORD_SIZE );
if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )
{
uint16_t pc;
pc = g_sse_sequences_desc_table[sequence].sse_loop_pc;
if ( pc < 256u )
{
*sse_pc_lo_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc;
}
else
{
*sse_pc_hi_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc - 256;
}
*sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_START;
}
}
/*-------------------------------------------------------------------------*//**
*
*/
void ACE_stop_sse
(
sse_sequence_handle_t sequence
)
{
ASSERT( sequence < ACE_NB_OF_SSE_PROCEDURES );
if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )
{
/* Stop relevant program counter. */
*sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_STOP;
}
}
/*-------------------------------------------------------------------------*//**
*
*/
void ACE_resume_sse
(
sse_sequence_handle_t sequence
)
{
ASSERT( sequence < ACE_NB_OF_SSE_PROCEDURES );
if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )
{
*sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_START;
}
}
/*-------------------------------------------------------------------------*//**
*
*/
void ACE_enable_sse_irq
(
sse_irq_id_t sse_irq_id
)
{
ASSERT( sse_irq_id < NB_OF_SSE_FLAG_IRQS );
ACE->SSE_IRQ_EN |= 1uL << (uint32_t)sse_irq_id;
}
/*-------------------------------------------------------------------------*//**
*
*/
void ACE_disable_sse_irq
(
sse_irq_id_t sse_irq_id
)
{
ASSERT( sse_irq_id < NB_OF_SSE_FLAG_IRQS );
ACE->SSE_IRQ_EN &= (uint32_t)~(1uL << (uint32_t)sse_irq_id);
}
/*-------------------------------------------------------------------------*//**
*
*/
void ACE_clear_sse_irq
(
sse_irq_id_t sse_irq_id
)
{
ASSERT( sse_irq_id < NB_OF_SSE_FLAG_IRQS );
ACE->SSE_IRQ_CLR |= 1uL << (uint32_t)sse_irq_id;
}
/*-------------------------------------------------------------------------*//**
*
*/
void ACE_clear_sample_pipeline(void)
{
uint32_t saved_sse_ctrl;
uint32_t saved_ppe_ctrl;
/* Pause the Sample Sequencing Engine. */
saved_sse_ctrl = ACE->SSE_TS_CTRL;
ACE->SSE_TS_CTRL = ACE->SSE_TS_CTRL & ~((uint32_t)TS_ENABLE_MASK);
/* Pause the Post Processing Engine. */
saved_ppe_ctrl = ACE->PPE_CTRL;
ACE->PPE_CTRL = ACE->PPE_CTRL & ~((uint32_t)PPE_ENABLE_MASK);
/* Reset the ADCs */
ACE->ADC0_MISC_CTRL |= ADC_RESET_MASK;
ACE->ADC1_MISC_CTRL |= ADC_RESET_MASK;
ACE->ADC2_MISC_CTRL |= ADC_RESET_MASK;
/* Clear ADC FIFOs */
ACE->ADC0_FIFO_CTRL |= ADC_FIFO_CLR_MASK;
ACE->ADC1_FIFO_CTRL |= ADC_FIFO_CLR_MASK;
ACE->ADC2_FIFO_CTRL |= ADC_FIFO_CLR_MASK;
/* clear DMA FIFOs */
ACE->PPE_PDMA_CTRL |= PDMA_DATAOUT_CLR_MASK;
/* Unpause the Post Processing Engine. */
ACE->PPE_CTRL = saved_ppe_ctrl;
/* Unpause the Sample Sequencing Engine. */
ACE->SSE_TS_CTRL = saved_sse_ctrl;
}
#ifdef __cplusplus
}
#endif

467
Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/drivers/mss_ace/ace_transform.c
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@ -1,467 +0,0 @@
/*******************************************************************************
* (c) Copyright 2010 Actel Corporation. All rights reserved.
*
* This file contains the implementation of the functions used to dynamically
* control the linear transforms applied by the ACE post processing engine to
* the samples read from the SSE.
*
* SVN $Revision: 2908 $
* SVN $Date: 2010-08-20 16:01:28 +0100 (Fri, 20 Aug 2010) $
*/
#include "mss_ace.h"
#include "mss_ace_configurator.h"
#include "mtd_data.h"
#include "envm_layout.h"
#include "../../CMSIS/a2fxxxm3.h"
#include "../../CMSIS/mss_assert.h"
#include "../../drivers_config/mss_ace/ace_config.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* The ACE_set_linear_transform() is only available when using ACE configuration
* files generated by Libero 9.1 or later.
*/
#ifdef ACE_CFG_DATA_FORMAT_VERSION
/*------------------------------------------------------------------------------
* Masks ans shift values used to derive the ABPS ranges from the analog block
* configuration.
*/
#define ABPS1_CFG_BITS_MASK (uint32_t)0x06
#define ABPS1_CFG_BITS_SHIFT (uint32_t)1
#define ABPS2_CFG_BITS_MASK (uint32_t)0x60
#define ABPS2_CFG_BITS_SHIFT (uint32_t)5
/*------------------------------------------------------------------------------
* One Bit DAC definitions.
*/
#define OBD_CURRENT (uint32_t)1
#define OBD_VOLTAGE (uint32_t)0
#define OBD_MODE_MASK (uint32_t)0x01
#define OBD_CHOPPING_MASK (uint32_t)0x02
/*-------------------------------------------------------------------------*//**
Neutral factor and offset for m*x + c trnasform.
*/
#define NEUTRAL_M_FACTOR 0x4000
#define NEUTRAL_C_OFFSET 0x0000
/*-------------------------------------------------------------------------*//**
Enumearation of the various input channel types. This is used to differentiate
between channel types in order to extract the relevant factory calibration
data(m1 and c1).
*/
typedef enum channel_type
{
ABPS1_CHAN = 0,
ABPS2_CHAN,
CMB_CHAN,
TMB_CHAN,
DIRECT_ADC_INPUT_CHAN,
OBDOUT_CHAN,
FLOATING_CHAN
} cal_channel_type_t;
/*-------------------------------------------------------------------------*//**
This data structure is used to store factory calibration data for a specific
analog input.
*/
typedef struct __channel_calibration_t
{
uint16_t mext;
uint16_t m1;
uint16_t c1;
} channel_calibration_t;
/*-------------------------------------------------------------------------*//**
Local functions
*/
int32_t extend_sign
(
uint16_t x
);
uint32_t adjust_to_24bit_ace_format
(
int64_t signed48
);
uint32_t adjust_to_16bit_ace_format
(
int64_t signed48
);
void get_calibration
(
adc_channel_id_t channel_id,
channel_calibration_t * p_calibration
);
void write_transform_coefficients
(
ace_channel_handle_t channel_handle,
uint32_t m,
uint32_t c
);
/*-------------------------------------------------------------------------*//**
*/
extern const uint8_t g_ace_external_varef_used[ACE_NB_OF_ADC];
extern ace_channel_desc_t g_ace_channel_desc_table[ACE_NB_OF_INPUT_CHANNELS];
extern const ppe_transforms_desc_t g_ace_ppe_transforms_desc_table[ACE_NB_OF_INPUT_CHANNELS];
/*------------------------------------------------------------------------------
* Pointer to the manufacturing test data containing trimming information
* generated during manufacturing.
*/
static const mtd_data_t * const p_mtd_data = (mtd_data_t *)MTD_ADDRESS;
/*-------------------------------------------------------------------------*//**
See "mss_ace.h" for details of how to use this function.
*/
int16_t ACE_get_default_m_factor
(
ace_channel_handle_t channel_handle
)
{
ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );
return g_ace_ppe_transforms_desc_table[channel_handle].m_ppe_offset;
}
/*-------------------------------------------------------------------------*//**
See "mss_ace.h" for details of how to use this function.
*/
int16_t ACE_get_default_c_offset
(
ace_channel_handle_t channel_handle
)
{
ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );
return g_ace_ppe_transforms_desc_table[channel_handle].c_ppe_offset;
}
/*-------------------------------------------------------------------------*//**
See "mss_ace.h" for details of how to use this function.
m = m2 * m1 * mext
c = (m2 * c1 * mext) + (c2 * mext)
*/
void ACE_set_linear_transform
(
ace_channel_handle_t channel_handle,
int16_t m2,
int16_t c2
)
{
adc_channel_id_t channel_id;
uint32_t m;
uint32_t c;
int32_t m32;
int64_t m64;
int32_t c32;
int64_t c64_1;
int64_t c64_2;
uint16_t m1;
uint16_t c1;
uint16_t mext;
channel_calibration_t calibration;
ASSERT( channel_handle < NB_OF_ACE_CHANNEL_HANDLES );
if(channel_handle < NB_OF_ACE_CHANNEL_HANDLES)
{
channel_id = g_ace_channel_desc_table[channel_handle].signal_id;
get_calibration(channel_id, &calibration);
m1 = calibration.m1;
c1 = calibration.c1;
mext = calibration.mext;
/*
* m = m2 * m1 * mext
*/
m32 = extend_sign(m2) * extend_sign(m1);
m64 = (int64_t)m32 * extend_sign(mext);
/* Convert 48-bit result to 32-bit ACE format result. */
m = adjust_to_16bit_ace_format(m64);
/*
* c = (m2 * c1 * mext) + (c2 * mext)
*/
c32 = extend_sign(m2) * extend_sign(c1);
c64_1 = (int64_t)c32 * extend_sign(mext);
c64_2 = ((int64_t)(extend_sign(c2) * extend_sign(mext))) << 14;
c = adjust_to_24bit_ace_format(c64_1 + c64_2);
write_transform_coefficients(channel_handle, m, c);
}
}
/*-------------------------------------------------------------------------*//**
Extend 16-bit signed number to 32-bit signed number.
*/
int32_t extend_sign
(
uint16_t x
)
{
int32_t y;
const uint32_t sign_bit_mask = 0x00008000u;
y = (x ^ sign_bit_mask) - sign_bit_mask;
return y;
}
/*-------------------------------------------------------------------------*//**
Take a 48-bit signed number, adjust it for saturation in the range -8 to
+7.999, translate into 24-bit ACE format.
*/
uint32_t adjust_to_24bit_ace_format
(
int64_t signed48
)
{
int32_t ace24_format;
const int64_t MAX_POSITIVE = 0x00001FFFFFFFFFFFuLL; /* +7.9999 */
const int64_t MIN_NEGATIVE = 0xFFFF200000000000uLL; /* -8 */
/* Check saturation. */
if(signed48 > MAX_POSITIVE)
{
signed48 = MAX_POSITIVE;
}
else if(signed48 < MIN_NEGATIVE)
{
signed48 = MIN_NEGATIVE;
}
/* Adjust to 24-bit ACE format. */
ace24_format = (uint32_t)(signed48 >> 14);
return ace24_format;
}
/*-------------------------------------------------------------------------*//**
Take a 48-bit signed number, adjust it for saturation in the range -8 to
+7.999, translate into 16-bit ACE format.
*/
uint32_t adjust_to_16bit_ace_format
(
int64_t signed48
)
{
int32_t ace24_format;
const int64_t MAX_POSITIVE = 0x00001FFFFFFFFFFFuLL; /* +7.9999 */
const int64_t MIN_NEGATIVE = 0xFFFF200000000000uLL; /* -8 */
/* Check saturation. */
if(signed48 > MAX_POSITIVE)
{
signed48 = MAX_POSITIVE;
}
else if(signed48 < MIN_NEGATIVE)
{
signed48 = MIN_NEGATIVE;
}
/* Adjust to 24-bit ACE format. */
ace24_format = (uint32_t)(signed48 >> 20);
return ace24_format;
}
/*-------------------------------------------------------------------------*//**
*/
void get_calibration
(
adc_channel_id_t channel_id,
channel_calibration_t * p_calibration
)
{
const uint32_t channel_mask = 0x0000000F;
const uint32_t CMB_MUX_SEL_MASK = 0x01;
const uint32_t TMB_MUX_SEL_MASK = 0x01;
const cal_channel_type_t channel_type_lut[16] =
{
FLOATING_CHAN,
ABPS1_CHAN,
ABPS2_CHAN,
CMB_CHAN,
TMB_CHAN,
ABPS1_CHAN,
ABPS2_CHAN,
CMB_CHAN,
TMB_CHAN,
DIRECT_ADC_INPUT_CHAN,
DIRECT_ADC_INPUT_CHAN,
DIRECT_ADC_INPUT_CHAN,
DIRECT_ADC_INPUT_CHAN,
FLOATING_CHAN,
FLOATING_CHAN,
OBDOUT_CHAN
};
cal_channel_type_t channel_type;
uint32_t channel_nb;
uint32_t adc_nb;
uint32_t range;
uint32_t quad_id;
mtd_calibration_mc_t const * p_mc_coeff = 0;
channel_nb = channel_id & channel_mask;
channel_type = channel_type_lut[channel_nb];
adc_nb = ((uint32_t)channel_id & 0x30u) >> 4u;
quad_id = adc_nb * 2;
if ( (channel_nb > 4) && (channel_nb < 9) ) { ++quad_id; }
switch ( channel_type )
{
case ABPS1_CHAN:
range = (ACE->ACB_DATA[quad_id].b8 & ABPS1_CFG_BITS_MASK) >> ABPS1_CFG_BITS_SHIFT;
p_mc_coeff = &p_mtd_data->abps_calibration[quad_id][0][range];
break;
case ABPS2_CHAN:
range = (ACE->ACB_DATA[quad_id].b8 & ABPS2_CFG_BITS_MASK) >> ABPS2_CFG_BITS_SHIFT;
p_mc_coeff = &p_mtd_data->abps_calibration[quad_id][1][range];
break;
case CMB_CHAN:
{
uint32_t cmb_mux_sel = (uint32_t)ACE->ACB_DATA[quad_id].b9 & CMB_MUX_SEL_MASK;
if ( cmb_mux_sel == 0 )
{ /* current monitor */
p_mc_coeff = &p_mtd_data->cm_calibration[quad_id];
}
else
{ /* direct input */
p_mc_coeff = &p_mtd_data->quads_direct_input_cal[quad_id][0];
}
}
break;
case TMB_CHAN:
{
uint32_t tmb_mux_sel = (uint32_t)ACE->ACB_DATA[quad_id].b10 & TMB_MUX_SEL_MASK;
if ( tmb_mux_sel == 0 )
{ /* temperature monitor */
p_mc_coeff = &p_mtd_data->tm_calibration[quad_id];
}
else
{ /* direct input */
p_mc_coeff = &p_mtd_data->quads_direct_input_cal[quad_id][1];
}
}
break;
case DIRECT_ADC_INPUT_CHAN:
{
const uint32_t channel_to_direct_in_lut[16]
= { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 0, 0, 0};
uint32_t direct_in_id;
direct_in_id = channel_to_direct_in_lut[channel_id & channel_mask];
p_mc_coeff = &p_mtd_data->adc_direct_input_cal[adc_nb][direct_in_id];
}
break;
case OBDOUT_CHAN:
{
uint32_t obd_mode = (uint32_t)ACE->ACB_DATA[quad_id].b6 & OBD_MODE_MASK;
uint32_t chopping_option = (uint32_t)ACE->ACB_DATA[quad_id].b6 & OBD_CHOPPING_MASK;
if (obd_mode > 0)
{
obd_mode = 1;
}
if (chopping_option > 0)
{
chopping_option = 1;
}
p_mc_coeff = &p_mtd_data->obd_calibration[adc_nb][obd_mode][chopping_option];
}
break;
case FLOATING_CHAN:
default:
/* Give neutral values is invalid channel. */
p_calibration->m1 = NEUTRAL_M_FACTOR;
p_calibration->c1 = NEUTRAL_C_OFFSET;
break;
}
if (p_mc_coeff != 0)
{
p_calibration->m1 = p_mc_coeff->m;
p_calibration->c1 = p_mc_coeff->c;
}
/*--------------------------------------------------------------------------
Retrieve the value of the mext factor. This depends if external VAREF is
used by the ADC sampling the analog input channel.
*/
if (g_ace_external_varef_used[adc_nb])
{
p_calibration->mext = p_mtd_data->global_settings.varef_m;
}
else
{
p_calibration->mext = NEUTRAL_M_FACTOR;
}
}
/*-------------------------------------------------------------------------*//**
Write new m and c transform factors into the PPE RAM. The m and c factors
should be in 32-bit ACE number format. The factors will be merged with
relevant PE opcode into PPE RAM. The 32-bit factors are shifted right by one
byte giving a 24-bit ACE number which is then merged with an 8-bit PPE opcode
located in the most significant byte of the PPE RAM location.
*/
void write_transform_coefficients
(
ace_channel_handle_t channel_handle,
uint32_t m,
uint32_t c
)
{
uint16_t m_ppe_offset;
uint16_t c_ppe_offset;
const uint32_t PPE_OPCODE_MASK = 0xFF000000u;
m_ppe_offset = g_ace_ppe_transforms_desc_table[channel_handle].m_ppe_offset;
c_ppe_offset = g_ace_ppe_transforms_desc_table[channel_handle].c_ppe_offset;
ACE->PPE_RAM_DATA[m_ppe_offset]
= (ACE->PPE_RAM_DATA[m_ppe_offset] & PPE_OPCODE_MASK) | (m >> 8u);
ACE->PPE_RAM_DATA[c_ppe_offset]
= (ACE->PPE_RAM_DATA[c_ppe_offset] & PPE_OPCODE_MASK) | (c >> 8u);
}
#endif /* ACE_CFG_DATA_FORMAT_VERSION */
#ifdef __cplusplus
}
#endif

126
Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/drivers/mss_ace/mss_ace.c
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@ -1,6 +1,6 @@
/*******************************************************************************
* (c) Copyright 2009 Actel Corporation. All rights reserved.
*
*
* SVN $Revision: 2905 $
* SVN $Date: 2010-08-20 14:03:28 +0100 (Fri, 20 Aug 2010) $
*/
@ -16,7 +16,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#endif
#define START_ADC_CONVERSION 0x80uL
@ -31,8 +31,10 @@ void ace_init_convert(void);
void ACE_init( void )
{
/* Initialize driver's internal data. */
ace_init_flags();
#if (ACE_NB_OF_PPE_FLAGS > 0)
ace_init_flags();
#endif
/* Initialize the data structures used by conversion functions. */
ace_init_convert();
}
@ -70,13 +72,13 @@ uint16_t ACE_get_adc_result
uint32_t data_valid;
ASSERT( adc_id < NB_OF_ANALOG_MODULES );
if ( adc_id < (uint8_t)NB_OF_ANALOG_MODULES )
{
do {
data_valid = *adc_status_reg_lut[adc_id] & ADC_DATAVALID_MASK;
} while ( !data_valid );
result = (uint16_t)(*adc_status_reg_lut[adc_id] & ADC_RESULT_MASK);
}
return result;
@ -88,7 +90,7 @@ uint16_t ACE_get_adc_result
#define SDD_ENABLE_MASK 0x20uL
#define SDD_REG_SEL_MASK 0x40uL
#define DAC0_SYNC_EN_MASK 0x10uL
#define DAC1_SYNC_EN_MASK 0x20uL
#define DAC2_SYNC_EN_MASK 0x40uL
@ -149,7 +151,7 @@ void ACE_configure_sdd
)
{
ASSERT( sdd_id < NB_OF_SDD );
if ( sdd_id < NB_OF_SDD )
{
const uint8_t sdd_2_quad_lut[NB_OF_SDD] = {0u, 2u, 4u};
@ -157,16 +159,16 @@ void ACE_configure_sdd
uint8_t obd_mode_idx = 1u;
uint8_t chopping_mode_idx = 0u;
uint32_t saved_pc2_ctrl;
quad_id = sdd_2_quad_lut[sdd_id];
/* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */
saved_pc2_ctrl = ACE->PC2_CTRL;
ACE->PC2_CTRL = 0u;
/* Select between voltage/current and RTZ modes.*/
ACE->ACB_DATA[quad_id].b6 = mode;
/* Load manufacturing generated trim value. */
if ( (mode & OBD_MODE_MASK) > 0u )
{
@ -178,17 +180,17 @@ void ACE_configure_sdd
}
ACE->ACB_DATA[quad_id].b4
= p_mtd_data->odb_trimming[sdd_id][obd_mode_idx][chopping_mode_idx];
/* Restore SSE PC2 operations since no ACB accesses should take place
* beyond this point. */
ACE->PC2_CTRL = saved_pc2_ctrl;
/* Set SDD resolution. */
*dac_ctrl_reg_lut[sdd_id] = (uint32_t)resolution;
/* Update SDD value through SSE_DACn_BYTES01. */
*dac_ctrl_reg_lut[sdd_id] |= SDD_REG_SEL_MASK;
/* Synchronous or individual SDD update. */
if ( INDIVIDUAL_UPDATE == sync_update )
{
@ -210,7 +212,7 @@ void ACE_enable_sdd
)
{
ASSERT( sdd_id < NB_OF_SDD );
if ( sdd_id < NB_OF_SDD )
{
*dac_ctrl_reg_lut[sdd_id] |= SDD_ENABLE_MASK;
@ -226,7 +228,7 @@ void ACE_disable_sdd
)
{
ASSERT( sdd_id < NB_OF_SDD );
if ( sdd_id < NB_OF_SDD )
{
*dac_ctrl_reg_lut[sdd_id] &= ~SDD_ENABLE_MASK;
@ -243,7 +245,7 @@ void ACE_set_sdd_value
)
{
ASSERT( sdd_id < NB_OF_SDD );
if ( sdd_id < NB_OF_SDD )
{
*dac_byte2_reg_lut[sdd_id] = sdd_value >> 16;
@ -262,9 +264,9 @@ void ACE_set_sdd_value_sync
)
{
uint32_t dac_sync_ctrl;
dac_sync_ctrl = ACE->DAC_SYNC_CTRL;
if ( SDD_NO_UPDATE != sdd0_value )
{
ACE->DAC0_BYTE2 = sdd0_value >> 16;
@ -286,7 +288,7 @@ void ACE_set_sdd_value_sync
ACE->SSE_DAC2_BYTES01 = sdd2_value;
dac_sync_ctrl |= DAC2_SYNC_UPDATE;
}
ACE->DAC_SYNC_CTRL = dac_sync_ctrl;
}
@ -357,23 +359,23 @@ void ACE_set_comp_reference
{
uint8_t scb_id;
uint32_t odd;
odd = (uint32_t)comp_id & 0x01uL;
ASSERT( comp_id < NB_OF_COMPARATORS );
ASSERT( reference < NB_OF_COMP_REF );
ASSERT( odd ); /* Only Temperature block comparators have configurable reference input. */
if ( (comp_id < NB_OF_COMPARATORS) && (reference < NB_OF_COMP_REF) && (odd) )
{
uint32_t saved_pc2_ctrl;
scb_id = comp_id_2_scb_lut[comp_id];
/* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */
saved_pc2_ctrl = ACE->PC2_CTRL;
ACE->PC2_CTRL = 0u;
if ( ADC_IN_COMP_REF == reference )
{
ACE->ACB_DATA[scb_id].b10 &= (uint8_t)~B10_COMP_VREF_SW_MASK;
@ -384,7 +386,7 @@ void ACE_set_comp_reference
ACE->ACB_DATA[scb_id].b10 &= (uint8_t)~B10_COMP_VREF_SW_MASK;
ACE->ACB_DATA[scb_id].b11 = (ACE->ACB_DATA[scb_id].b11 & (uint8_t)~B11_DAC_MUXSEL_MASK) + (uint8_t)reference;
}
/* Restore SSE PC2 operations since no ACB accesses should take place
* beyond this point. */
ACE->PC2_CTRL = saved_pc2_ctrl;
@ -401,22 +403,22 @@ void ACE_set_comp_hysteresis
)
{
uint8_t scb_id;
ASSERT( comp_id < NB_OF_COMPARATORS );
ASSERT( hysteresis < NB_OF_HYSTERESIS );
if ( (comp_id < NB_OF_COMPARATORS) && (hysteresis < NB_OF_HYSTERESIS) )
{
uint32_t odd;
uint32_t saved_pc2_ctrl;
scb_id = comp_id_2_scb_lut[comp_id];
odd = (uint32_t)comp_id & 0x01uL;
/* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */
saved_pc2_ctrl = ACE->PC2_CTRL;
ACE->PC2_CTRL = 0u;
if ( odd )
{
/* Temperature monitor block comparator. */
@ -427,7 +429,7 @@ void ACE_set_comp_hysteresis
/* Current monitor block comparator. */
ACE->ACB_DATA[scb_id].b9 = (ACE->ACB_DATA[scb_id].b9 & HYSTERESIS_MASK) | (uint8_t)((uint8_t)hysteresis << HYSTERESIS_SHIFT);
}
/* Restore SSE PC2 operations since no ACB accesses should take place
* beyond this point. */
ACE->PC2_CTRL = saved_pc2_ctrl;
@ -435,7 +437,7 @@ void ACE_set_comp_hysteresis
}
/*-------------------------------------------------------------------------*//**
*/
void ACE_enable_comp
(
@ -443,21 +445,21 @@ void ACE_enable_comp
)
{
uint8_t scb_id;
ASSERT( comp_id < NB_OF_COMPARATORS );
if ( comp_id < NB_OF_COMPARATORS )
{
uint32_t odd;
uint32_t saved_pc2_ctrl;
scb_id = comp_id_2_scb_lut[comp_id];
odd = (uint32_t)comp_id & 0x01uL;
/* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */
saved_pc2_ctrl = ACE->PC2_CTRL;
ACE->PC2_CTRL = 0u;
if ( odd )
{
/* Temperature monitor block comparator. */
@ -468,7 +470,7 @@ void ACE_enable_comp
/* Current monitor block comparator. */
ACE->ACB_DATA[scb_id].b9 |= COMPARATOR_ENABLE_MASK;
}
/* Restore SSE PC2 operations since no ACB accesses should take place
* beyond this point. */
ACE->PC2_CTRL = saved_pc2_ctrl;
@ -484,21 +486,21 @@ void ACE_disable_comp
)
{
uint8_t scb_id;
ASSERT( comp_id < NB_OF_COMPARATORS );
if ( comp_id < NB_OF_COMPARATORS )
{
uint32_t odd;
uint32_t saved_pc2_ctrl;
scb_id = comp_id_2_scb_lut[comp_id];
odd = (uint32_t)comp_id & 0x01uL;
/* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */
saved_pc2_ctrl = ACE->PC2_CTRL;
ACE->PC2_CTRL = 0u;
if ( odd )
{
/* Temperature monitor block comparator. */
@ -509,7 +511,7 @@ void ACE_disable_comp
/* Current monitor block comparator. */
ACE->ACB_DATA[scb_id].b9 &= (uint8_t)~COMPARATOR_ENABLE_MASK;
}
/* Restore SSE PC2 operations since no ACB accesses should take place
* beyond this point. */
ACE->PC2_CTRL = saved_pc2_ctrl;
@ -539,7 +541,7 @@ void ACE_enable_comp_rise_irq
)
{
ASSERT( comp_id < NB_OF_COMPARATORS );
ACE->COMP_IRQ_EN |= (FIRST_RISE_IRQ_MASK << (uint32_t)comp_id);
}
@ -552,7 +554,7 @@ void ACE_disable_comp_rise_irq
)
{
ASSERT( comp_id < NB_OF_COMPARATORS );
ACE->COMP_IRQ_EN &= ~(FIRST_RISE_IRQ_MASK << (uint32_t)comp_id);
}
@ -565,7 +567,7 @@ void ACE_clear_comp_rise_irq
)
{
ASSERT( comp_id < NB_OF_COMPARATORS );
ACE->COMP_IRQ_CLR |= (FIRST_RISE_IRQ_MASK << (uint32_t)comp_id);
}
@ -578,7 +580,7 @@ void ACE_enable_comp_fall_irq
)
{
ASSERT( comp_id < NB_OF_COMPARATORS );
ACE->COMP_IRQ_EN |= (FIRST_FALL_IRQ_MASK << (uint32_t)comp_id);
}
@ -591,7 +593,7 @@ void ACE_disable_comp_fall_irq
)
{
ASSERT( comp_id < NB_OF_COMPARATORS );
ACE->COMP_IRQ_EN &= ~(FIRST_FALL_IRQ_MASK << (uint32_t)comp_id);
}
@ -604,7 +606,7 @@ void ACE_clear_comp_fall_irq
)
{
ASSERT( comp_id < NB_OF_COMPARATORS );
ACE->COMP_IRQ_CLR |= (FIRST_FALL_IRQ_MASK << (uint32_t)comp_id);
}
@ -643,9 +645,9 @@ ACE_get_first_channel
)
{
ace_channel_handle_t channel_handle;
channel_handle = (ace_channel_handle_t)0;
return channel_handle;
}
@ -659,12 +661,12 @@ ACE_get_next_channel
)
{
++channel_handle;
if ( channel_handle >= NB_OF_ACE_CHANNEL_HANDLES )
{
channel_handle = (ace_channel_handle_t)0;
}
return channel_handle;
}
@ -679,7 +681,7 @@ ACE_get_channel_handle
{
uint16_t channel_idx;
ace_channel_handle_t channel_handle = INVALID_CHANNEL_HANDLE;
for ( channel_idx = 0u; channel_idx < (uint16_t)ACE_NB_OF_INPUT_CHANNELS; ++channel_idx )
{
if ( g_ace_channel_desc_table[channel_idx].p_sz_channel_name != 0 )
@ -708,7 +710,7 @@ ACE_get_input_channel_handle
{
uint16_t channel_idx;
ace_channel_handle_t channel_handle = INVALID_CHANNEL_HANDLE;
for ( channel_idx = 0u; channel_idx < (uint16_t)ACE_NB_OF_INPUT_CHANNELS; ++channel_idx )
{
if ( g_ace_channel_desc_table[channel_idx].signal_id == channel_id )
@ -732,10 +734,10 @@ ACE_get_ppe_sample
{
uint16_t sample;
uint16_t ppe_offset;
ppe_offset = g_ace_channel_desc_table[channel_handle].signal_ppe_offset;
sample = (uint16_t)(ACE->PPE_RAM_DATA[ppe_offset] >> 16u);
return sample;
}

434
Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/drivers/mss_ace/mss_ace.h
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