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Start creating the K60 demo directory structure.

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This commit is contained in:
Richard Barry 2011-07-08 08:57:54 +00:00
parent 248123342b
commit d0e8c36aa2
30 changed files with 4586 additions and 0 deletions
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160
Demo/CORTEX_Kinetis_K60_Tower_IAR/FreeRTOSConfig.h Normal file
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/*
FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.
FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:
Atollic AB - Atollic provides professional embedded systems development
tools for C/C++ development, code analysis and test automation.
See http://www.atollic.com
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ ( 75000000UL )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 90 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 60 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 0
#define configGENERATE_RUN_TIME_STATS 0
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 10
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
/* Use the system definition, if there is one */
#ifdef __NVIC_PRIO_BITS
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 4 /* 15 priority levels */
#endif
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* The lowest priority. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Priority 5, or 160 as only the top three bits are implemented. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler SysTick_Handler
/* MAC address configuration. */
#define configMAC_ADDR0 0x00
#define configMAC_ADDR1 0x12
#define configMAC_ADDR2 0x13
#define configMAC_ADDR3 0x10
#define configMAC_ADDR4 0x15
#define configMAC_ADDR5 0x11
/* IP address configuration. */
#define configIP_ADDR0 192
#define configIP_ADDR1 168
#define configIP_ADDR2 0
#define configIP_ADDR3 200
/* Netmask configuration. */
#define configNET_MASK0 255
#define configNET_MASK1 255
#define configNET_MASK2 255
#define configNET_MASK3 0
#endif /* FREERTOS_CONFIG_H */

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Demo/CORTEX_Kinetis_K60_Tower_IAR/Freescale_Code/common/512KB_Pflash.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x00080000;
define symbol __ICFEDIT_region_RAM_start__ = 0x1FFF0410;
define symbol __ICFEDIT_region_RAM_end__ = 0x20000000;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define symbol __region_RAM2_start__ = 0x20000000;
define symbol __region_RAM2_end__ = 0x20010000;
define exported symbol __VECTOR_TABLE = 0x00000000;
define exported symbol __VECTOR_RAM = 0x1fff0000;
define exported symbol __BOOT_STACK_ADDRESS = __region_RAM2_end__ - 8; //0x2000FFF8;
define symbol __code_start__ = 0x00000410;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize manually { readwrite };
initialize manually { section .data};
initialize manually { section .textrw };
do not initialize { section .noinit };
define block CodeRelocate { section .textrw_init };
define block CodeRelocateRam { section .textrw };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place at address mem:__code_start__ { readonly section .noinit };
place in ROM_region { readonly, block CodeRelocate};
place in RAM_region { readwrite, block CodeRelocateRam,
block CSTACK, block HEAP };

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/*
* File: assert.h
* Purpose: Provide macro for software assertions
*
* Notes: assert_failed() defined in assert.c
*/
#ifndef _ASSERT_H_
#define _ASSERT_H_
/********************************************************************/
void assert_failed(char *, int);
#ifdef DEBUG_PRINT
#define ASSERT(expr) \
if (!(expr)) \
assert_failed(__FILE__, __LINE__)
#else
#define ASSERT(expr)
#endif
/********************************************************************/
#endif /* _ASSERT_H_ */

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/*
* File: common.h
* Purpose: File to be included by all project files
*
* Notes:
*/
#ifndef _COMMON_H_
#define _COMMON_H_
/********************************************************************/
/*
* Debug prints ON (#define) or OFF (#undef)
*/
#define DEBUG
#define DEBUG_PRINT
/*
* Include the generic CPU header file
*/
#include "arm_cm4.h"
/*
* Include the platform specific header file
*/
#if (defined(TWR_K40X256))
#include "k40_tower.h"
#elif (defined(TWR_K53N512))
#include "k53_tower.h"
#elif (defined(TWR_K60N512))
#include "k60_tower.h"
#else
#error "No valid platform defined"
#endif
/*
* Include the cpu specific header file
*/
#if (defined(CPU_MK40N512VMD100))
#include <freescale/MK40N512VMD100.h>
#elif (defined(CPU_MK53N512VMD100))
#include <freescale/MK53N512CMD100.h>
#elif (defined(CPU_MK60N512VMD100))
#include <freescale/MK60N512VMD100.h>
#else
#error "No valid CPU defined"
#endif
/*
* Include any toolchain specfic header files
*/
#if (defined(CW))
#include "cw.h"
#elif (defined(IAR))
#include "iar.h"
#else
#warning "No toolchain specific header included"
#endif
/*
* Include common utilities
*/
#include "assert.h"
#include "io.h"
#include "startup.h"
#include "stdlib.h"
#if (defined(IAR))
#include "intrinsics.h"
#endif
/********************************************************************/
#endif /* _COMMON_H_ */

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/*
* File: iar.h
* Purpose: Define constants used by IAR toolchain
*
* Notes:
*
*/
#ifndef _IAR_H_
#define _IAR_H_
/********************************************************************/
/********************************************************************/
#endif /* _IAR_H_ */

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/*
* File: io.h
* Purpose: Serial Input/Output routines
*
*/
#ifndef _IO_H
#define _IO_H
/********************************************************************/
char
in_char(void);
void
out_char(char);
int
char_present(void);
int
printf(const char *, ... );
int
sprintf(char *, const char *, ... );
/********************************************************************/
#endif

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/*
* File: queue.h
* Purpose: Implement a first in, first out linked list
*
* Notes:
*/
#ifndef _QUEUE_H_
#define _QUEUE_H_
/********************************************************************/
/*
* Individual queue node
*/
typedef struct NODE
{
struct NODE *next;
} QNODE;
/*
* Queue Struture - linked list of qentry items
*/
typedef struct
{
QNODE *head;
QNODE *tail;
} QUEUE;
/*
* Functions provided by queue.c
*/
void
queue_init(QUEUE *);
int
queue_isempty(QUEUE *);
void
queue_add(QUEUE *, QNODE *);
QNODE*
queue_remove(QUEUE *);
QNODE*
queue_peek(QUEUE *);
void
queue_move(QUEUE *, QUEUE *);
/********************************************************************/
#endif /* _QUEUE_H_ */

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/*
* File: startup.c
* Purpose: Generic Kinetis startup code
*
* Notes:
*/
#include "common.h"
#if (defined(IAR))
#pragma section = ".data"
#pragma section = ".data_init"
#pragma section = ".bss"
#pragma section = "CodeRelocate"
#pragma section = "CodeRelocateRam"
#endif
/********************************************************************/
void
common_startup(void)
{
#if (defined(CW))
extern char __START_BSS[];
extern char __END_BSS[];
extern uint32 __DATA_ROM[];
extern uint32 __DATA_RAM[];
extern char __DATA_END[];
#endif
/* Declare a counter we'll use in all of the copy loops */
uint32 n;
/* Declare pointers for various data sections. These pointers
* are initialized using values pulled in from the linker file
*/
uint8 * data_ram, * data_rom, * data_rom_end;
uint8 * bss_start, * bss_end;
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
extern uint32 __VECTOR_TABLE[];
extern uint32 __VECTOR_RAM[];
/* Copy the vector table to RAM */
if (__VECTOR_RAM != __VECTOR_TABLE)
{
for (n = 0; n < 0x410; n++)
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
}
/* Point the VTOR to the new copy of the vector table */
write_vtor((uint32)__VECTOR_RAM);
/* Get the addresses for the .data section (initialized data section) */
#if (defined(CW))
data_ram = (uint8 *)__DATA_RAM;
data_rom = (uint8 *)__DATA_ROM;
data_rom_end = (uint8 *)__DATA_END; /* This is actually a RAM address in CodeWarrior */
n = data_rom_end - data_ram;
#elif (defined(IAR))
data_ram = __section_begin(".data");
data_rom = __section_begin(".data_init");
data_rom_end = __section_end(".data_init");
n = data_rom_end - data_rom;
#endif
/* Copy initialized data from ROM to RAM */
while (n--)
*data_ram++ = *data_rom++;
/* Get the addresses for the .bss section (zero-initialized data) */
#if (defined(CW))
bss_start = (uint8 *)__START_BSS;
bss_end = (uint8 *)__END_BSS;
#elif (defined(IAR))
bss_start = __section_begin(".bss");
bss_end = __section_end(".bss");
#endif
/* Clear the zero-initialized data section */
n = bss_end - bss_start;
while(n--)
*bss_start++ = 0;
/* Get addresses for any code sections that need to be copied from ROM to RAM.
* The IAR tools have a predefined keyword that can be used to mark individual
* functions for execution from RAM. Add "__ramfunc" before the return type in
* the function prototype for any routines you need to execute from RAM instead
* of ROM. ex: __ramfunc void foo(void);
*/
#if (defined(IAR))
uint8* code_relocate_ram = __section_begin("CodeRelocateRam");
uint8* code_relocate = __section_begin("CodeRelocate");
uint8* code_relocate_end = __section_end("CodeRelocate");
/* Copy functions from ROM to RAM */
n = code_relocate_end - code_relocate;
while (n--)
*code_relocate_ram++ = *code_relocate++;
#endif
}
/********************************************************************/

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/*
* File: startup.h
* Purpose: Determine cause of Reset and which processor is running
*
* Notes:
*/
#ifndef _STARTUP_H_
#define _STARTUP_H_
/********************************************************************/
void common_startup(void);
/********************************************************************/
#endif /* _STARTUP_H_ */

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/*
* File: arm_cm4.c
* Purpose: Generic high-level routines for ARM Cortex M4 processors
*
* Notes:
*/
#include "common.h"
/***********************************************************************/
/*
* Configures the ARM system control register for STOP (deep sleep) mode
* and then executes the WFI instruction to enter the mode.
*
* Parameters:
* none
*
* Note: Might want to change this later to allow for passing in a parameter
* to optionally set the sleep on exit bit.
*/
void stop (void)
{
/* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */
SCB_SCR |= SCB_SCR_SLEEPDEEP_MASK;
/* WFI instruction will start entry into STOP mode */
asm("WFI");
}
/***********************************************************************/
/*
* Configures the ARM system control register for WAIT (sleep) mode
* and then executes the WFI instruction to enter the mode.
*
* Parameters:
* none
*
* Note: Might want to change this later to allow for passing in a parameter
* to optionally set the sleep on exit bit.
*/
void wait (void)
{
/* Clear the SLEEPDEEP bit to make sure we go into WAIT (sleep) mode instead
* of deep sleep.
*/
SCB_SCR &= ~SCB_SCR_SLEEPDEEP_MASK;
/* WFI instruction will start entry into WAIT mode */
asm("WFI");
}
/***********************************************************************/
/*
* Change the value of the vector table offset register to the specified value.
*
* Parameters:
* vtor new value to write to the VTOR
*/
void write_vtor (int vtor)
{
/* Write the VTOR with the new value */
SCB_VTOR = vtor;
}
/***********************************************************************/
/*
* Initialize the NVIC to enable the specified IRQ.
*
* NOTE: The function only initializes the NVIC to enable a single IRQ.
* Interrupts will also need to be enabled in the ARM core. This can be
* done using the EnableInterrupts macro.
*
* Parameters:
* irq irq number to be enabled (the irq number NOT the vector number)
*/
void enable_irq (int irq)
{
int div;
/* Make sure that the IRQ is an allowable number. Right now up to 91 is
* used.
*/
if (irq > 91)
printf("\nERR! Invalid IRQ value passed to enable irq function!\n");
/* Determine which of the NVICISERs corresponds to the irq */
div = irq/32;
switch (div)
{
case 0x0:
NVICICPR0 = 1 << (irq%32);
NVICISER0 = 1 << (irq%32);
break;
case 0x1:
NVICICPR1 = 1 << (irq%32);
NVICISER1 = 1 << (irq%32);
break;
case 0x2:
NVICICPR2 = 1 << (irq%32);
NVICISER2 = 1 << (irq%32);
break;
}
}
/***********************************************************************/
/*
* Initialize the NVIC to disable the specified IRQ.
*
* NOTE: The function only initializes the NVIC to disable a single IRQ.
* If you want to disable all interrupts, then use the DisableInterrupts
* macro instead.
*
* Parameters:
* irq irq number to be disabled (the irq number NOT the vector number)
*/
void disable_irq (int irq)
{
int div;
/* Make sure that the IRQ is an allowable number. Right now up to 91 is
* used.
*/
if (irq > 91)
printf("\nERR! Invalid IRQ value passed to disable irq function!\n");
/* Determine which of the NVICICERs corresponds to the irq */
div = irq/32;
switch (div)
{
case 0x0:
NVICICER0 = 1 << (irq%32);
break;
case 0x1:
NVICICER1 = 1 << (irq%32);
break;
case 0x2:
NVICICER2 = 1 << (irq%32);
break;
}
}
/***********************************************************************/
/*
* Initialize the NVIC to set specified IRQ priority.
*
* NOTE: The function only initializes the NVIC to set a single IRQ priority.
* Interrupts will also need to be enabled in the ARM core. This can be
* done using the EnableInterrupts macro.
*
* Parameters:
* irq irq number to be enabled (the irq number NOT the vector number)
* prio irq priority. 0-15 levels. 0 max priority
*/
void set_irq_priority (int irq, int prio)
{
/*irq priority pointer*/
uint8 *prio_reg;
/* Make sure that the IRQ is an allowable number. Right now up to 91 is
* used.
*/
if (irq > 91)
printf("\nERR! Invalid IRQ value passed to priority irq function!\n");
if (prio > 15)
printf("\nERR! Invalid priority value passed to priority irq function!\n");
/* Determine which of the NVICIPx corresponds to the irq */
prio_reg = (uint8 *)(((uint32)&NVICIP0) + irq);
/* Assign priority to IRQ */
*prio_reg = ( (prio&0xF) << (8 - ARM_INTERRUPT_LEVEL_BITS) );
}
/***********************************************************************/

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/*
* File: arm_cm4.h
* Purpose: Definitions common to all ARM Cortex M4 processors
*
* Notes:
*/
#ifndef _CPU_ARM_CM4_H
#define _CPU_ARM_CM4_H
#include "common.h"
/*ARM Cortex M4 implementation for interrupt priority shift*/
#define ARM_INTERRUPT_LEVEL_BITS 4
/***********************************************************************/
// function prototypes for arm_cm4.c
void stop (void);
void wait (void);
void write_vtor (int);
void enable_irq (int);
void disable_irq (int);
void set_irq_priority (int, int);
/***********************************************************************/
/*!< Macro to enable all interrupts. */
#define EnableInterrupts asm(" CPSIE i");
/*!< Macro to disable all interrupts. */
#define DisableInterrupts asm(" CPSID i");
/***********************************************************************/
/*
* Misc. Defines
*/
#ifdef FALSE
#undef FALSE
#endif
#define FALSE (0)
#ifdef TRUE
#undef TRUE
#endif
#define TRUE (1)
#ifdef NULL
#undef NULL
#endif
#define NULL (0)
#ifdef ON
#undef ON
#endif
#define ON (1)
#ifdef OFF
#undef OFF
#endif
#define OFF (0)
/***********************************************************************/
/*
* The basic data types
*/
typedef unsigned char uint8; /* 8 bits */
typedef unsigned short int uint16; /* 16 bits */
typedef unsigned long int uint32; /* 32 bits */
typedef char int8; /* 8 bits */
typedef short int int16; /* 16 bits */
typedef int int32; /* 32 bits */
typedef volatile int8 vint8; /* 8 bits */
typedef volatile int16 vint16; /* 16 bits */
typedef volatile int32 vint32; /* 32 bits */
typedef volatile uint8 vuint8; /* 8 bits */
typedef volatile uint16 vuint16; /* 16 bits */
typedef volatile uint32 vuint32; /* 32 bits */
// function prototype for main function
void main(void);
/***********************************************************************/
#endif /* _CPU_ARM_CM4_H */

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/*
* File: crt0.s
* Purpose: Lowest level routines for Kinetis.
*
* Notes:
*
*/
; AREA Crt0, CODE, READONLY ; name this block of code
SECTION .noinit : CODE
EXPORT __startup
__startup
MOV r0,#0 ; Initialize the GPRs
MOV r1,#0
MOV r2,#0
MOV r3,#0
MOV r4,#0
MOV r5,#0
MOV r6,#0
MOV r7,#0
MOV r8,#0
MOV r9,#0
MOV r10,#0
MOV r11,#0
MOV r12,#0
CPSIE i ; Unmask interrupts
import start
BL start ; call the C code
__done
B __done
END

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/*
* File: dma_channels.h
* Purpose: DMA request macros for use on Kinetis processors.
* This file gives default DMA channel assignments
* for all of the possible Kinetis module DMA requests.
*
*
* Notes: There are more DMA requests than DMA channels, so
* care should be taken to make sure that DMA channel
* assignments are unique for the modules that are
* being used at any time.
*/
#ifndef _DMA_CHANNELS_H
#define _DMA_CHANNELS_H
/********************************************************************/
/* NOTE: There are more DMA requests than DMA channels, so
* care should be taken to make sure that DMA channel
* assignments are unique for the modules that are
* being used at any time.
*
* It is recommended that you read the appropriate DMAMUX_CHCFGn
* register before updating it to verify it is 0x0. If the
* DMAMUX_CHCFGn register is not zero, then that indicates the
* selected DMA channel might already be in use by another peripheral
* (a more specific test would be to look for DMAMUX_CHCFGn[ENBL] set).
* The module's DMA configuration routine can return an error
* when this situation is detected.
*/
/* Default DMA channel assignments and module request macros */
/* UARTs */
#define DMA_UART0RX_CH 0
#define DMA_UART0TX_CH 1
#define DMA_UART1RX_CH 2
#define DMA_UART1TX_CH 3
#define DMA_UART2RX_CH 10
#define DMA_UART2TX_CH 11
#define DMA_UART3RX_CH 12
#define DMA_UART3TX_CH 13
#define DMA_UART4RX_CH 6
#define DMA_UART4TX_CH 7
#define DMA_UART5RX_CH 8
#define DMA_UART5TX_CH 9
/* SSI/SAI */
#define DMA_SSI0RX_CH 4
#define DMA_SSI0TX_CH 5
/* DSPIs */
#define DMA_DSPI0RX_CH 6
#define DMA_DSPI0TX_CH 7
#define DMA_DSPI1RX_CH 8
#define DMA_DSPI1TX_CH 9
#define DMA_DSPI2RX_CH 14
#define DMA_DSPI2TX_CH 15
/* I2Cs */
#define DMA_I2C0_CH 7
#define DMA_I2C1_CH 2
/* FTMs */
#define DMA_FTM0CH0_CH 5
#define DMA_FTM0CH1_CH 6
#define DMA_FTM0CH2_CH 3
#define DMA_FTM0CH3_CH 4
#define DMA_FTM0CH4_CH 12
#define DMA_FTM0CH5_CH 13
#define DMA_FTM0CH6_CH 14
#define DMA_FTM0CH7_CH 15
#define DMA_FTM1CH0_CH 10
#define DMA_FTM1CH1_CH 11
#define DMA_FTM2CH0_CH 0
#define DMA_FTM2CH1_CH 1
/* Ethernet timers */
#define DMA_ENETTMR0_CH 4
#define DMA_ENETTMR1_CH 8
#define DMA_ENETTMR2_CH 0
#define DMA_ENETTMR3_CH 15
/* ADCs */
#define DMA_ADC0_CH 12
#define DMA_ADC1_CH 3
/* HSCMPs */
#define DMA_HSCMP0_CH 13
#define DMA_HSCMP1_CH 2
#define DMA_HSCMP2_CH 9
/* 12-bit DAC */
#define DMA_12bDAC0_CH 14
/* CMT */
#define DMA_CMT_CH 5
/* PDB */
#define DMA_PDB_CH 10
/* GPIO Ports */
#define DMA_GPIOPORTA_CH 15
#define DMA_GPIOPORTB_CH 0
#define DMA_GPIOPORTC_CH 1
#define DMA_GPIOPORTD_CH 11
#define DMA_GPIOPORTE_CH 8
/********************************************************************/
#endif /* _DMA_CHANNELS_H */

57
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/*
* File: k60_tower.h
* Purpose: Definitions for the Kinetis K60 tower card
*
* Notes:
*/
#ifndef __K60_TOWER_H__
#define __K60_TOWER_H__
#include "mcg.h"
/********************************************************************/
/* Global defines to use for all boards */
#define DEBUG_PRINT
/* Defines specific to the K60 tower board */
/* Define for the CPU on the K60 board */
#define CPU_MK60N512VMD100
/*
* System Bus Clock Info
*/
#define K60_CLK 1
#define REF_CLK XTAL8 /* value isn't used, but we still need something defined */
#define CORE_CLK_MHZ PLL96 /* 96MHz is only freq tested for a clock input*/
/*
* Serial Port Info
*/
/*
* Select the serial port that is being used below. Only one of the
* options should be uncommented at any time.
*/
//#define SERIAL_CARD // use this option for serial port on TWR-SER
#define OSJTAG // use this option for serial port over the OS-JTAG circuit
#if (defined(SERIAL_CARD))
#define TERM_PORT UART3_BASE_PTR
#define TERMINAL_BAUD 115200
#undef HW_FLOW_CONTROL
#elif (defined(OSJTAG))
#define TERM_PORT UART5_BASE_PTR
#define TERMINAL_BAUD 115200
#undef HW_FLOW_CONTROL
#else
#error "No valid serial port defined"
#endif
#endif /* __K60_TOWER_H__ */

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/********************************************************************************/
/* FILENAME RegisterFile.h */
/* The current release of the documentation and header files does not include
* the system register file or the VBAT register file. This header file
* adds support for accessing both register files.
*
* Once the manual is updated to include the register files, this file
* will become obsolete.
*/
/********************************************************************************/
/* Register File - Peripheral instance base addresses */
/* Peripheral System Register File base pointer */
#define RFSYS_DATA_BASE_PTR ((RFDATA_MemMapPtr)0x40041000u)
/* Peripheral VBAT Register File base pointer */
#define RFVBAT_DATA_BASE_PTR ((RFDATA_MemMapPtr)0x4003E000u)
typedef struct RFDATA_MemMap {
uint32_t RFDATA [32]; /*!< Register file n, array offset: 0x0, array step: 0x4 */
} volatile *RFDATA_MemMapPtr;
/* ----------------------------------------------------------------------------
-- Register file - Register accessor macros
---------------------------------------------------------------------------- */
/* Register file - Register accessors */
#define RFSYS_DATA_REG(base,index) ((base)->RFDATA[index])
#define RFVBAT_DATA_REG(base,index) ((base)->RFDATA[index])
#define RFSYS_DATA0 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,0 )
#define RFSYS_DATA1 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,1 )
#define RFSYS_DATA2 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,2 )
#define RFSYS_DATA3 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,3 )
#define RFSYS_DATA4 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,4 )
#define RFSYS_DATA5 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,5 )
#define RFSYS_DATA6 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,6 )
#define RFSYS_DATA7 RFSYS_DATA_REG(RFSYS_DATA_BASE_PTR,7 )
#define RFVBAT_DATA0 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,0 )
#define RFVBAT_DATA1 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,1 )
#define RFVBAT_DATA2 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,2 )
#define RFVBAT_DATA3 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,3 )
#define RFVBAT_DATA4 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,4 )
#define RFVBAT_DATA5 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,5 )
#define RFVBAT_DATA6 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,6 )
#define RFVBAT_DATA7 RFVBAT_DATA_REG(RFVBAT_DATA_BASE_PTR,7 )
/* LL Bit Fields */
#define RF_DATA_LL_MASK 0x000000FFu
#define RF_DATA_LL_SHIFT 0
#define RF_DATA_LL(x) (((x)<<RF_DATA_LL_SHIFT)&RF_DATA_LL_MASK)
/* LH Bit Fields */
#define RF_DATA_LH_MASK 0x0000FF00u
#define RF_DATA_LH_SHIFT 8
#define RF_DATA_LH(x) (((x)<<RF_DATA_LH_SHIFT)&RF_DATA_LH_MASK)
/* HL Bit Fields */
#define RF_DATA_HL_MASK 0x00FF0000u
#define RF_DATA_HL_SHIFT 16
#define RF_DATA_HL(x) (((x)<<RF_DATA_HL_SHIFT)&RF_DATA_HL_MASK)
/* HH Bit Fields */
#define RF_DATA_HH_MASK 0xFF000000u
#define RF_DATA_HH_SHIFT 24
#define RF_DATA_HH(x) (((x)<<RF_DATA_HH_SHIFT)&RF_DATA_HH_MASK)
/*! \} */ /* end of group Register_File_Register_Accessor_Macros */

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/*
* File: start.c
* Purpose: Kinetis start up routines.
*
* Notes:
*/
#include "start.h"
#include "common.h"
#include "wdog.h"
#include "sysinit.h"
/********************************************************************/
/*!
* \brief Kinetis Start
* \return None
*
* This function calls all of the needed starup routines and then
* branches to the main process.
*/
void start(void)
{
/* Disable the watchdog timer */
wdog_disable();
/* Copy any vector or data sections that need to be in RAM */
common_startup();
/* Perform processor initialization */
sysinit();
printf("\n\n");
/* Determine the last cause(s) of reset */
if (MC_SRSH & MC_SRSH_SW_MASK)
printf("Software Reset\n");
if (MC_SRSH & MC_SRSH_LOCKUP_MASK)
printf("Core Lockup Event Reset\n");
if (MC_SRSH & MC_SRSH_JTAG_MASK)
printf("JTAG Reset\n");
if (MC_SRSL & MC_SRSL_POR_MASK)
printf("Power-on Reset\n");
if (MC_SRSL & MC_SRSL_PIN_MASK)
printf("External Pin Reset\n");
if (MC_SRSL & MC_SRSL_COP_MASK)
printf("Watchdog(COP) Reset\n");
if (MC_SRSL & MC_SRSL_LOC_MASK)
printf("Loss of Clock Reset\n");
if (MC_SRSL & MC_SRSL_LVD_MASK)
printf("Low-voltage Detect Reset\n");
if (MC_SRSL & MC_SRSL_WAKEUP_MASK)
printf("LLWU Reset\n");
/* Determine specific Kinetis device and revision */
cpu_identify();
/* Jump to main process */
main();
/* No actions to perform after this so wait forever */
while(1);
}
/********************************************************************/
/*!
* \brief Kinetis Identify
* \return None
*
* This is primarly a reporting function that displays information
* about the specific CPU to the default terminal including:
* - Kinetis family
* - package
* - die revision
* - P-flash size
* - Ram size
*/
void cpu_identify (void)
{
/* Determine the Kinetis family */
switch((SIM_SDID & SIM_SDID_FAMID(0x7))>>SIM_SDID_FAMID_SHIFT)
{
case 0x0:
printf("\nK10-");
break;
case 0x1:
printf("\nK20-");
break;
case 0x2:
printf("\nK30-");
break;
case 0x3:
printf("\nK40-");
break;
case 0x4:
printf("\nK60-");
break;
case 0x5:
printf("\nK70-");
break;
case 0x6:
printf("\nK50-");
break;
case 0x7:
printf("\nK53-");
break;
default:
printf("\nUnrecognized Kinetis family device.\n");
break;
}
/* Determine the package size */
switch((SIM_SDID & SIM_SDID_PINID(0xF))>>SIM_SDID_PINID_SHIFT)
{
case 0x2:
printf("32pin ");
break;
case 0x4:
printf("48pin ");
break;
case 0x5:
printf("64pin ");
break;
case 0x6:
printf("80pin ");
break;
case 0x7:
printf("81pin ");
break;
case 0x8:
printf("100pin ");
break;
case 0x9:
printf("104pin ");
break;
case 0xA:
printf("144pin ");
break;
case 0xC:
printf("196pin ");
break;
case 0xE:
printf("256pin ");
break;
default:
printf("\nUnrecognized Kinetis package code. ");
break;
}
/* Determine the revision ID */
printf("Silicon rev %d \n", (SIM_SDID & SIM_SDID_REVID(0xF))>>SIM_SDID_REVID_SHIFT);
/* Determine the flash revision */
flash_identify();
/* Determine the P-flash size */
switch((SIM_FCFG1 & SIM_FCFG1_FSIZE(0xFF))>>SIM_FCFG1_FSIZE_SHIFT)
{
case 0x0:
printf("12 kBytes of P-flash ");
break;
case 0x1:
printf("16 kBytes of P-flash ");
break;
case 0x2:
printf("32 kBytes of P-flash ");
break;
case 0x3:
printf("48 kBytes of P-flash ");
break;
case 0x4:
printf("64 kBytes of P-flash ");
break;
case 0x5:
printf("96 kBytes of P-flash ");
break;
case 0x6:
printf("128 kBytes of P-flash ");
break;
case 0x7:
printf("192 kBytes of P-flash ");
break;
case 0x8:
printf("256 kBytes of P-flash ");
break;
case 0x9:
printf("320 kBytes of P-flash ");
break;
case 0xA:
printf("384 kBytes of P-flash ");
break;
case 0xB:
printf("448 kBytes of P-flash ");
break;
case 0xC:
printf("512 kBytes of P-flash ");
break;
case 0xFF:
printf("Full size P-flash ");
break;
default:
printf("ERR!! Undefined P-flash size\n");
break;
}
/* Determine the RAM size */
switch((SIM_SOPT1 & SIM_SOPT1_RAMSIZE(0xF))>>SIM_SOPT1_RAMSIZE_SHIFT)
{
case 0x5:
printf(" 32 kBytes of RAM\n\n");
break;
case 0x7:
printf(" 64 kBytes of RAM\n\n");
break;
case 0x8:
printf(" 96 kBytes of RAM\n\n");
break;
case 0x9:
printf(" 128 kBytes of RAM\n\n");
break;
default:
printf(" ERR!! Undefined RAM size\n\n");
break;
}
}
/********************************************************************/
/*!
* \brief flash Identify
* \return None
*
* This is primarly a reporting function that displays information
* about the specific flash parameters and flash version ID for
* the current device. These parameters are obtained using a special
* flash command call "read resource." The first four bytes returned
* are the flash parameter revision, and the second four bytes are
* the flash version ID.
*/
void flash_identify (void)
{
/* Get the flash parameter version */
/* Write the flash FCCOB registers with the values for a read resource command */
FTFL_FCCOB0 = 0x03;
FTFL_FCCOB1 = 0x00;
FTFL_FCCOB2 = 0x00;
FTFL_FCCOB3 = 0x00;
FTFL_FCCOB8 = 0x01;
/* All required FCCOBx registers are written, so launch the command */
FTFL_FSTAT = FTFL_FSTAT_CCIF_MASK;
/* Wait for the command to complete */
while(!(FTFL_FSTAT & FTFL_FSTAT_CCIF_MASK));
printf("Flash parameter version %d.%d.%d.%d\n",FTFL_FCCOB4,FTFL_FCCOB5,FTFL_FCCOB6,FTFL_FCCOB7);
/* Get the flash version ID */
/* Write the flash FCCOB registers with the values for a read resource command */
FTFL_FCCOB0 = 0x03;
FTFL_FCCOB1 = 0x00;
FTFL_FCCOB2 = 0x00;
FTFL_FCCOB3 = 0x04;
FTFL_FCCOB8 = 0x01;
/* All required FCCOBx registers are written, so launch the command */
FTFL_FSTAT = FTFL_FSTAT_CCIF_MASK;
/* Wait for the command to complete */
while(!(FTFL_FSTAT & FTFL_FSTAT_CCIF_MASK));
printf("Flash version ID %d.%d.%d.%d\n",FTFL_FCCOB4,FTFL_FCCOB5,FTFL_FCCOB6,FTFL_FCCOB7);
}
/********************************************************************/

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/*
* File: start.h
* Purpose: Kinetis start up routines.
*
* Notes:
*/
// Function prototypes
void _start(void);
void cpu_identify(void);
void flash_identify(void);

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/*
* File: sysinit.c
* Purpose: Kinetis Configuration
* Initializes processor to a default state
*
* Notes:
*
*/
#include "common.h"
#include "sysinit.h"
#include "uart.h"
/********************************************************************/
/* Actual system clock frequency */
int core_clk_khz;
int core_clk_mhz;
int periph_clk_khz;
/********************************************************************/
void sysinit (void)
{
/*
* Enable all of the port clocks. These have to be enabled to configure
* pin muxing options, so most code will need all of these on anyway.
*/
SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK
| SIM_SCGC5_PORTB_MASK
| SIM_SCGC5_PORTC_MASK
| SIM_SCGC5_PORTD_MASK
| SIM_SCGC5_PORTE_MASK );
/* Ramp up the system clock */
core_clk_mhz = pll_init(CORE_CLK_MHZ, REF_CLK);
/*
* Use the value obtained from the pll_init function to define variables
* for the core clock in kHz and also the peripheral clock. These
* variables can be used by other functions that need awareness of the
* system frequency.
*/
core_clk_khz = core_clk_mhz * 1000;
periph_clk_khz = core_clk_khz / (((SIM_CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> 24)+ 1);
/* For debugging purposes, enable the trace clock and/or FB_CLK so that
* we'll be able to monitor clocks and know the PLL is at the frequency
* that we expect.
*/
trace_clk_init();
fb_clk_init();
/* Enable the pins for the selected UART */
if (TERM_PORT == UART0_BASE_PTR)
{
/* Enable the UART0_TXD function on PTD6 */
PORTD_PCR6 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
/* Enable the UART0_RXD function on PTD7 */
PORTD_PCR7 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
}
if (TERM_PORT == UART1_BASE_PTR)
{
/* Enable the UART1_TXD function on PTC4 */
PORTC_PCR4 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
/* Enable the UART1_RXD function on PTC3 */
PORTC_PCR3 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
}
if (TERM_PORT == UART2_BASE_PTR)
{
/* Enable the UART2_TXD function on PTD3 */
PORTD_PCR3 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
/* Enable the UART2_RXD function on PTD2 */
PORTD_PCR2 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
}
if (TERM_PORT == UART3_BASE_PTR)
{
/* Enable the UART3_TXD function on PTC17 */
PORTC_PCR17 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
/* Enable the UART3_RXD function on PTC16 */
PORTC_PCR16 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
}
if (TERM_PORT == UART4_BASE_PTR)
{
/* Enable the UART3_TXD function on PTC17 */
PORTE_PCR24 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
/* Enable the UART3_RXD function on PTC16 */
PORTE_PCR25 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
}
if (TERM_PORT == UART5_BASE_PTR)
{
/* Enable the UART3_TXD function on PTC17 */
PORTE_PCR8 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
/* Enable the UART3_RXD function on PTC16 */
PORTE_PCR9 = PORT_PCR_MUX(0x3); // UART is alt3 function for this pin
}
/* UART0 and UART1 are clocked from the core clock, but all other UARTs are
* clocked from the peripheral clock. So we have to determine which clock
* to send to the uart_init function.
*/
if ((TERM_PORT == UART0_BASE_PTR) | (TERM_PORT == UART1_BASE_PTR))
uart_init (TERM_PORT, core_clk_khz, TERMINAL_BAUD);
else
uart_init (TERM_PORT, periph_clk_khz, TERMINAL_BAUD);
}
/********************************************************************/
void trace_clk_init(void)
{
/* Set the trace clock to the core clock frequency */
SIM_SOPT2 |= SIM_SOPT2_TRACECLKSEL_MASK;
/* Enable the TRACE_CLKOUT pin function on PTA6 (alt7 function) */
PORTA_PCR6 = ( PORT_PCR_MUX(0x7));
}
/********************************************************************/
void fb_clk_init(void)
{
/* Enable the clock to the FlexBus module */
SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;
/* Enable the FB_CLKOUT function on PTC3 (alt5 function) */
PORTC_PCR3 = ( PORT_PCR_MUX(0x5));
}
/********************************************************************/

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/*
* File: sysinit.h
* Purpose: Kinetis Configuration
* Initializes processor to a default state
*
* Notes:
*
*/
/********************************************************************/
// function prototypes
void sysinit (void);
void trace_clk_init(void);
void fb_clk_init(void);
void enable_abort_button(void);
/********************************************************************/

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/******************************************************************************
* File: vectors.c
*
* Purpose: Configure interrupt vector table for Kinetis.
******************************************************************************/
#include "vectors.h"
#include "common.h"
extern void SVC_Handler( void );
extern void PendSV_Handler( void );
extern void SysTick_Handler( void );
/******************************************************************************
* Vector Table
******************************************************************************/
typedef void (*vector_entry)(void);
#if defined(IAR)
#pragma location = ".intvec"
const vector_entry __vector_table[] = //@ ".intvec" =
#elif defined(CW)
#pragma define_section vectortable ".vectortable" ".vectortable" ".vectortable" far_abs R
#define VECTOR __declspec(vectortable)
const VECTOR vector_entry __vector_table[] = //@ ".intvec" =
#endif
{
VECTOR_000, /* Initial SP */
VECTOR_001, /* Initial PC */
VECTOR_002,
VECTOR_003,
VECTOR_004,
VECTOR_005,
VECTOR_006,
VECTOR_007,
VECTOR_008,
VECTOR_009,
VECTOR_010,
SVC_Handler,
VECTOR_012,
VECTOR_013,
PendSV_Handler,
SysTick_Handler,
VECTOR_016,
VECTOR_017,
VECTOR_018,
VECTOR_019,
VECTOR_020,
VECTOR_021,
VECTOR_022,
VECTOR_023,
VECTOR_024,
VECTOR_025,
VECTOR_026,
VECTOR_027,
VECTOR_028,
VECTOR_029,
VECTOR_030,
VECTOR_031,
VECTOR_032,
VECTOR_033,
VECTOR_034,
VECTOR_035,
VECTOR_036,
VECTOR_037,
VECTOR_038,
VECTOR_039,
VECTOR_040,
VECTOR_041,
VECTOR_042,
VECTOR_043,
VECTOR_044,
VECTOR_045,
VECTOR_046,
VECTOR_047,
VECTOR_048,
VECTOR_049,
VECTOR_050,
VECTOR_051,
VECTOR_052,
VECTOR_053,
VECTOR_054,
VECTOR_055,
VECTOR_056,
VECTOR_057,
VECTOR_058,
VECTOR_059,
VECTOR_060,
VECTOR_061,
VECTOR_062,
VECTOR_063,
VECTOR_064,
VECTOR_065,
VECTOR_066,
VECTOR_067,
VECTOR_068,
VECTOR_069,
VECTOR_070,
VECTOR_071,
VECTOR_072,
VECTOR_073,
VECTOR_074,
VECTOR_075,
VECTOR_076,
VECTOR_077,
VECTOR_078,
VECTOR_079,
VECTOR_080,
VECTOR_081,
VECTOR_082,
VECTOR_083,
VECTOR_084,
VECTOR_085,
VECTOR_086,
VECTOR_087,
VECTOR_088,
VECTOR_089,
VECTOR_090,
VECTOR_091,
VECTOR_092,
VECTOR_093,
VECTOR_094,
VECTOR_095,
VECTOR_096,
VECTOR_097,
VECTOR_098,
VECTOR_099,
VECTOR_100,
VECTOR_101,
VECTOR_102,
VECTOR_103, /* Port A */
VECTOR_104,
VECTOR_105, /* Port C */
VECTOR_106,
VECTOR_107, /* Port E */
VECTOR_108,
VECTOR_109,
VECTOR_110,
VECTOR_111,
VECTOR_112,
VECTOR_113,
VECTOR_114,
VECTOR_115,
VECTOR_116,
VECTOR_117,
VECTOR_118,
VECTOR_119,
VECTOR_120,
VECTOR_121,
VECTOR_122,
VECTOR_123,
VECTOR_124,
VECTOR_125,
VECTOR_126,
VECTOR_127,
VECTOR_128,
VECTOR_129,
VECTOR_130,
VECTOR_131,
VECTOR_132,
VECTOR_133,
VECTOR_134,
VECTOR_135,
VECTOR_136,
VECTOR_137,
VECTOR_138,
VECTOR_139,
VECTOR_140,
VECTOR_141,
VECTOR_142,
VECTOR_143,
VECTOR_144,
VECTOR_145,
VECTOR_146,
VECTOR_147,
VECTOR_148,
VECTOR_149,
VECTOR_150,
VECTOR_151,
VECTOR_152,
VECTOR_153,
VECTOR_154,
VECTOR_155,
VECTOR_156,
VECTOR_157,
VECTOR_158,
VECTOR_159,
VECTOR_160,
VECTOR_161,
VECTOR_162,
VECTOR_163,
VECTOR_164,
VECTOR_165,
VECTOR_166,
VECTOR_167,
VECTOR_168,
VECTOR_169,
VECTOR_170,
VECTOR_171,
VECTOR_172,
VECTOR_173,
VECTOR_174,
VECTOR_175,
VECTOR_176,
VECTOR_177,
VECTOR_178,
VECTOR_179,
VECTOR_180,
VECTOR_181,
VECTOR_182,
VECTOR_183,
VECTOR_184,
VECTOR_185,
VECTOR_186,
VECTOR_187,
VECTOR_188,
VECTOR_189,
VECTOR_190,
VECTOR_191,
VECTOR_192,
VECTOR_193,
VECTOR_194,
VECTOR_195,
VECTOR_196,
VECTOR_197,
VECTOR_198,
VECTOR_199,
VECTOR_200,
VECTOR_201,
VECTOR_202,
VECTOR_203,
VECTOR_204,
VECTOR_205,
VECTOR_206,
VECTOR_207,
VECTOR_208,
VECTOR_209,
VECTOR_210,
VECTOR_211,
VECTOR_212,
VECTOR_213,
VECTOR_214,
VECTOR_215,
VECTOR_216,
VECTOR_217,
VECTOR_218,
VECTOR_219,
VECTOR_220,
VECTOR_221,
VECTOR_222,
VECTOR_223,
VECTOR_224,
VECTOR_225,
VECTOR_226,
VECTOR_227,
VECTOR_228,
VECTOR_229,
VECTOR_230,
VECTOR_231,
VECTOR_232,
VECTOR_233,
VECTOR_234,
VECTOR_235,
VECTOR_236,
VECTOR_237,
VECTOR_238,
VECTOR_239,
VECTOR_240,
VECTOR_241,
VECTOR_242,
VECTOR_243,
VECTOR_244,
VECTOR_245,
VECTOR_246,
VECTOR_247,
VECTOR_248,
VECTOR_249,
VECTOR_250,
VECTOR_251,
VECTOR_252,
VECTOR_253,
VECTOR_254,
VECTOR_255,
CONFIG_1,
CONFIG_2,
CONFIG_3,
CONFIG_4,
};
// VECTOR_TABLE end
/******************************************************************************
* default_isr(void)
*
* Default ISR definition.
*
* In: n/a
* Out: n/a
******************************************************************************/
//#if (defined(CW))
//__declspec(interrupt)
//#endif
void default_isr(void)
{
#define VECTORNUM (*(volatile uint8_t*)(0xE000ED04))
printf("\n****default_isr entered on vector %d*****\r\n\n",VECTORNUM);
return;
}
/******************************************************************************/
/* End of "vectors.c" */

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/******************************************************************************
* File: vectors.h
*
* Purpose: Provide custom interrupt service routines for Kinetis.
*
* NOTE: This vector table is a superset table, so interrupt sources might be
* listed that are not available on the specific Kinetis device you are
* using.
******************************************************************************/
#ifndef __VECTORS_H
#define __VECTORS_H 1
// function prototype for default_isr in vectors.c
void default_isr(void);
void abort_isr(void);
void hard_fault_handler_c(unsigned int * hardfault_args);
/* Interrupt Vector Table Function Pointers */
typedef void pointer(void);
extern void __startup(void);
extern unsigned long __BOOT_STACK_ADDRESS[];
extern void __iar_program_start(void);
// Address Vector IRQ Source module Source description
#define VECTOR_000 (pointer*)__BOOT_STACK_ADDRESS // ARM core Initial Supervisor SP
#define VECTOR_001 __startup // 0x0000_0004 1 - ARM core Initial Program Counter
#define VECTOR_002 default_isr // 0x0000_0008 2 - ARM core Non-maskable Interrupt (NMI)
#define VECTOR_003 default_isr // 0x0000_000C 3 - ARM core Hard Fault
#define VECTOR_004 default_isr // 0x0000_0010 4 -
#define VECTOR_005 default_isr // 0x0000_0014 5 - ARM core Bus Fault
#define VECTOR_006 default_isr // 0x0000_0018 6 - ARM core Usage Fault
#define VECTOR_007 default_isr // 0x0000_001C 7 -
#define VECTOR_008 default_isr // 0x0000_0020 8 -
#define VECTOR_009 default_isr // 0x0000_0024 9 -
#define VECTOR_010 default_isr // 0x0000_0028 10 -
#define VECTOR_011 default_isr // 0x0000_002C 11 - ARM core Supervisor call (SVCall)
#define VECTOR_012 default_isr // 0x0000_0030 12 - ARM core Debug Monitor
#define VECTOR_013 default_isr // 0x0000_0034 13 -
#define VECTOR_014 default_isr // 0x0000_0038 14 - ARM core Pendable request for system service (PendableSrvReq)
#define VECTOR_015 default_isr // 0x0000_003C 15 - ARM core System tick timer (SysTick)
#define VECTOR_016 default_isr // 0x0000_0040 16 0 DMA DMA Channel 0 transfer complete
#define VECTOR_017 default_isr // 0x0000_0044 17 1 DMA DMA Channel 1 transfer complete
#define VECTOR_018 default_isr // 0x0000_0048 18 2 DMA DMA Channel 2 transfer complete
#define VECTOR_019 default_isr // 0x0000_004C 19 3 DMA DMA Channel 3 transfer complete
#define VECTOR_020 default_isr // 0x0000_0050 20 4 DMA DMA Channel 4 transfer complete
#define VECTOR_021 default_isr // 0x0000_0054 21 5 DMA DMA Channel 5 transfer complete
#define VECTOR_022 default_isr // 0x0000_0058 22 6 DMA DMA Channel 6 transfer complete
#define VECTOR_023 default_isr // 0x0000_005C 23 7 DMA DMA Channel 7 transfer complete
#define VECTOR_024 default_isr // 0x0000_0060 24 8 DMA DMA Channel 8 transfer complete
#define VECTOR_025 default_isr // 0x0000_0064 25 9 DMA DMA Channel 9 transfer complete
#define VECTOR_026 default_isr // 0x0000_0068 26 10 DMA DMA Channel 10 transfer complete
#define VECTOR_027 default_isr // 0x0000_006C 27 11 DMA DMA Channel 11 transfer complete
#define VECTOR_028 default_isr // 0x0000_0070 28 12 DMA DMA Channel 12 transfer complete
#define VECTOR_029 default_isr // 0x0000_0074 29 13 DMA DMA Channel 13 transfer complete
#define VECTOR_030 default_isr // 0x0000_0078 30 14 DMA DMA Channel 14 transfer complete
#define VECTOR_031 default_isr // 0x0000_007C 31 15 DMA DMA Channel 15 transfer complete
#define VECTOR_032 default_isr // 0x0000_0080 32 16 DMA DMA Error Interrupt Channels 0-15
#define VECTOR_033 default_isr // 0x0000_0084 33 17 MCM Normal interrupt
#define VECTOR_034 default_isr // 0x0000_0088 34 18 Flash memory Command Complete
#define VECTOR_035 default_isr // 0x0000_008C 35 19 Flash memory Read Collision
#define VECTOR_036 default_isr // 0x0000_0090 36 20 Mode Controller Low Voltage Detect,Low Voltage Warning, Low Leakage Wakeup
#define VECTOR_037 default_isr // 0x0000_0094 37 21 LLWU
#define VECTOR_038 default_isr // 0x0000_0098 38 22 WDOG
#define VECTOR_039 default_isr // 0x0000_009C 39 23 RNGB
#define VECTOR_040 default_isr // 0x0000_00A0 40 24 I2C0
#define VECTOR_041 default_isr // 0x0000_00A4 41 25 I2C1
#define VECTOR_042 default_isr // 0x0000_00A8 42 26 SPI0 Single interrupt vector for all sources
#define VECTOR_043 default_isr // 0x0000_00AC 43 27 SPI1 Single interrupt vector for all sources
#define VECTOR_044 default_isr // 0x0000_00B0 44 28 SPI2 Single interrupt vector for all sources
#define VECTOR_045 default_isr // 0x0000_00B4 45 29 CAN0 OR'ed Message buffer (0-15)
#define VECTOR_046 default_isr // 0x0000_00B8 46 30 CAN0 Bus Off
#define VECTOR_047 default_isr // 0x0000_00BC 47 31 CAN0 Error
#define VECTOR_048 default_isr // 0x0000_00C0 48 32 CAN0 Transmit Warning
#define VECTOR_049 default_isr // 0x0000_00C4 49 33 CAN0 Receive Warning
#define VECTOR_050 default_isr // 0x0000_00C8 50 34 CAN0 Wake Up
#define VECTOR_051 default_isr // 0x0000_00CC 51 35 CAN0 Individual Matching Elements Update (IMEU)
#define VECTOR_052 default_isr // 0x0000_00D0 52 36 CAN0 Lost receive
#define VECTOR_053 default_isr // 0x0000_00D4 53 37 CAN1 OR'ed Message buffer (0-15)
#define VECTOR_054 default_isr // 0x0000_00D8 54 38 CAN1 Bus off
#define VECTOR_055 default_isr // 0x0000_00DC 55 39 CAN1 Error
#define VECTOR_056 default_isr // 0x0000_00E0 56 40 CAN1 Transmit Warning
#define VECTOR_057 default_isr // 0x0000_00E4 57 41 CAN1 Receive Warning
#define VECTOR_058 default_isr // 0x0000_00E8 58 42 CAN1 Wake Up
#define VECTOR_059 default_isr // 0x0000_00EC 59 43 CAN1 Individual Matching Elements Update (IMEU)
#define VECTOR_060 default_isr // 0x0000_00F0 60 44 CAN1 Lost receive
#define VECTOR_061 default_isr // 0x0000_00F4 61 45 UART0 Single interrupt vector for UART status sources
#define VECTOR_062 default_isr // 0x0000_00F8 62 46 UART0 Single interrupt vector for UART error sources
#define VECTOR_063 default_isr // 0x0000_00FC 63 47 UART1 Single interrupt vector for UART status sources
#define VECTOR_064 default_isr // 0x0000_0100 64 48 UART1 Single interrupt vector for UART error sources
#define VECTOR_065 default_isr // 0x0000_0104 65 49 UART2 Single interrupt vector for UART status sources
#define VECTOR_066 default_isr // 0x0000_0108 66 50 UART2 Single interrupt vector for UART error sources
#define VECTOR_067 default_isr // 0x0000_010C 67 51 UART3 Single interrupt vector for UART status sources
#define VECTOR_068 default_isr // 0x0000_0110 68 52 UART3 Single interrupt vector for UART error sources
#define VECTOR_069 default_isr // 0x0000_0114 69 53 UART4 Single interrupt vector for UART status sources
#define VECTOR_070 default_isr // 0x0000_0118 70 54 UART4 Single interrupt vector for UART error sources
#define VECTOR_071 default_isr // 0x0000_011C 71 55 UART5 Single interrupt vector for UART status sources
#define VECTOR_072 default_isr // 0x0000_0120 72 56 UART5 Single interrupt vector for UART error sources
#define VECTOR_073 default_isr // 0x0000_0124 73 57 ADC0
#define VECTOR_074 default_isr // 0x0000_0128 74 58 ADC1
#define VECTOR_075 default_isr // 0x0000_012C 75 59 CMP0 High-speed comparator
#define VECTOR_076 default_isr // 0x0000_0130 76 60 CMP1
#define VECTOR_077 default_isr // 0x0000_0134 77 61 CMP2
#define VECTOR_078 default_isr // 0x0000_0138 78 62 FTM0 Single interrupt vector for all sources
#define VECTOR_079 default_isr // 0x0000_013C 79 63 FTM1 Single interrupt vector for all sources
#define VECTOR_080 default_isr // 0x0000_0140 80 64 FTM2 Single interrupt vector for all sources
#define VECTOR_081 default_isr // 0x0000_0144 81 65 CMT
#define VECTOR_082 default_isr // 0x0000_0148 82 66 RTC Timer interrupt
#define VECTOR_083 default_isr // 0x0000_014C 83 67
#define VECTOR_084 default_isr // 0x0000_0150 84 68 PIT Channel 0
#define VECTOR_085 default_isr // 0x0000_0154 85 69 PIT Channel 1
#define VECTOR_086 default_isr // 0x0000_0158 86 70 PIT Channel 2
#define VECTOR_087 default_isr // 0x0000_015C 87 71 PIT Channel 3
#define VECTOR_088 default_isr // 0x0000_0160 88 72 PDB
#define VECTOR_089 default_isr // 0x0000_0164 89 73 USB OTG
#define VECTOR_090 default_isr // 0x0000_0168 90 74 USB Charger Detect
#define VECTOR_091 default_isr // 0x0000_016C 91 75 ENET IEEE 1588 Timer interrupt
#define VECTOR_092 default_isr // 0x0000_0170 92 76 ENET Transmit interrupt
#define VECTOR_093 default_isr // 0x0000_0174 93 77 ENET Receive interrupt
#define VECTOR_094 default_isr // 0x0000_0178 94 78 ENET Error and miscellaneous interrupt
#define VECTOR_095 default_isr // 0x0000_017C 95 79 I2S
#define VECTOR_096 default_isr // 0x0000_0180 96 80 SDHC
#define VECTOR_097 default_isr // 0x0000_0184 97 81 DAC0
#define VECTOR_098 default_isr // 0x0000_0188 98 82 DAC1
#define VECTOR_099 default_isr // 0x0000_018C 99 83 TSI Single interrupt vector for all sources
#define VECTOR_100 default_isr // 0x0000_0190 100 84 MCG
#define VECTOR_101 default_isr // 0x0000_0194 101 85 Low Power Timer
#define VECTOR_102 default_isr // 0x0000_0198 102 86 Segment LCD Single interrupt vector for all sources
#define VECTOR_103 default_isr // 0x0000_019C 103 87 Port control module Pin Detect (Port A)
#define VECTOR_104 default_isr // 0x0000_01A0 104 88 Port control module Pin Detect (Port B)
#define VECTOR_105 default_isr // 0x0000_01A4 105 89 Port control module Pin Detect (Port C)
#define VECTOR_106 default_isr // 0x0000_01A8 106 90 Port control module Pin Detect (Port D)
#define VECTOR_107 default_isr // 0x0000_01AC 107 91 Port control module Pin Detect (Port E)
#define VECTOR_108 default_isr // 0x0000_01B0 108 92
#define VECTOR_109 default_isr // 0x0000_01B4 109 93
#define VECTOR_110 default_isr // 0x0000_01B8 110 94
#define VECTOR_111 default_isr // 0x0000_01BC 111 95
#define VECTOR_112 default_isr // 0x0000_01C0 112 96
#define VECTOR_113 default_isr // 0x0000_01C4 113 97
#define VECTOR_114 default_isr // 0x0000_01C8 114 98
#define VECTOR_115 default_isr // 0x0000_01CC 115 99
#define VECTOR_116 default_isr // 0x0000_01D0 116 100
#define VECTOR_117 default_isr // 0x0000_01D4 117 101
#define VECTOR_118 default_isr // 0x0000_01D8 118 102
#define VECTOR_119 default_isr // 0x0000_01DC 119 103
#define VECTOR_120 default_isr //
#define VECTOR_121 default_isr //
#define VECTOR_122 default_isr //
#define VECTOR_123 default_isr //
#define VECTOR_124 default_isr //
#define VECTOR_125 default_isr //
#define VECTOR_126 default_isr //
#define VECTOR_127 default_isr //
#define VECTOR_128 default_isr //
#define VECTOR_129 default_isr //
#define VECTOR_130 default_isr //
#define VECTOR_131 default_isr //
#define VECTOR_132 default_isr //
#define VECTOR_133 default_isr //
#define VECTOR_134 default_isr //
#define VECTOR_135 default_isr //
#define VECTOR_136 default_isr //
#define VECTOR_137 default_isr //
#define VECTOR_138 default_isr //
#define VECTOR_139 default_isr //
#define VECTOR_140 default_isr //
#define VECTOR_141 default_isr //
#define VECTOR_142 default_isr //
#define VECTOR_143 default_isr //
#define VECTOR_144 default_isr //
#define VECTOR_145 default_isr //
#define VECTOR_146 default_isr //
#define VECTOR_147 default_isr //
#define VECTOR_148 default_isr //
#define VECTOR_149 default_isr //
#define VECTOR_150 default_isr //
#define VECTOR_151 default_isr //
#define VECTOR_152 default_isr //
#define VECTOR_153 default_isr //
#define VECTOR_154 default_isr //
#define VECTOR_155 default_isr //
#define VECTOR_156 default_isr //
#define VECTOR_157 default_isr //
#define VECTOR_158 default_isr //
#define VECTOR_159 default_isr //
#define VECTOR_160 default_isr //
#define VECTOR_161 default_isr //
#define VECTOR_162 default_isr //
#define VECTOR_163 default_isr //
#define VECTOR_164 default_isr //
#define VECTOR_165 default_isr //
#define VECTOR_166 default_isr //
#define VECTOR_167 default_isr //
#define VECTOR_168 default_isr //
#define VECTOR_169 default_isr //
#define VECTOR_170 default_isr //
#define VECTOR_171 default_isr //
#define VECTOR_172 default_isr //
#define VECTOR_173 default_isr //
#define VECTOR_174 default_isr //
#define VECTOR_175 default_isr //
#define VECTOR_176 default_isr //
#define VECTOR_177 default_isr //
#define VECTOR_178 default_isr //
#define VECTOR_179 default_isr //
#define VECTOR_180 default_isr //
#define VECTOR_181 default_isr //
#define VECTOR_182 default_isr //
#define VECTOR_183 default_isr //
#define VECTOR_184 default_isr //
#define VECTOR_185 default_isr //
#define VECTOR_186 default_isr //
#define VECTOR_187 default_isr //
#define VECTOR_188 default_isr //
#define VECTOR_189 default_isr //
#define VECTOR_190 default_isr //
#define VECTOR_191 default_isr //
#define VECTOR_192 default_isr //
#define VECTOR_193 default_isr //
#define VECTOR_194 default_isr //
#define VECTOR_195 default_isr //
#define VECTOR_196 default_isr //
#define VECTOR_197 default_isr //
#define VECTOR_198 default_isr //
#define VECTOR_199 default_isr //
#define VECTOR_200 default_isr //
#define VECTOR_201 default_isr //
#define VECTOR_202 default_isr //
#define VECTOR_203 default_isr //
#define VECTOR_204 default_isr //
#define VECTOR_205 default_isr //
#define VECTOR_206 default_isr //
#define VECTOR_207 default_isr //
#define VECTOR_208 default_isr //
#define VECTOR_209 default_isr //
#define VECTOR_210 default_isr //
#define VECTOR_211 default_isr //
#define VECTOR_212 default_isr //
#define VECTOR_213 default_isr //
#define VECTOR_214 default_isr //
#define VECTOR_215 default_isr //
#define VECTOR_216 default_isr //
#define VECTOR_217 default_isr //
#define VECTOR_218 default_isr //
#define VECTOR_219 default_isr //
#define VECTOR_220 default_isr //
#define VECTOR_221 default_isr //
#define VECTOR_222 default_isr //
#define VECTOR_223 default_isr //
#define VECTOR_224 default_isr //
#define VECTOR_225 default_isr //
#define VECTOR_226 default_isr //
#define VECTOR_227 default_isr //
#define VECTOR_228 default_isr //
#define VECTOR_229 default_isr //
#define VECTOR_230 default_isr //
#define VECTOR_231 default_isr //
#define VECTOR_232 default_isr //
#define VECTOR_233 default_isr //
#define VECTOR_234 default_isr //
#define VECTOR_235 default_isr //
#define VECTOR_236 default_isr //
#define VECTOR_237 default_isr //
#define VECTOR_238 default_isr //
#define VECTOR_239 default_isr //
#define VECTOR_240 default_isr //
#define VECTOR_241 default_isr //
#define VECTOR_242 default_isr //
#define VECTOR_243 default_isr //
#define VECTOR_244 default_isr //
#define VECTOR_245 default_isr //
#define VECTOR_246 default_isr //
#define VECTOR_247 default_isr //
#define VECTOR_248 default_isr //
#define VECTOR_249 default_isr //
#define VECTOR_250 default_isr //
#define VECTOR_251 default_isr //
#define VECTOR_252 default_isr //
#define VECTOR_253 default_isr //
#define VECTOR_254 default_isr //
#define VECTOR_255 default_isr //
#define CONFIG_1 (pointer*)0xffffffff
#define CONFIG_2 (pointer*)0xffffffff
#define CONFIG_3 (pointer*)0xffffffff
#define CONFIG_4 (pointer*)0xfffffffe
#endif /*__VECTORS_H*/
/* End of "vectors.h" */

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/*
* File: mcg.c
* Purpose: Driver for enabling the PLL in 1 of 4 options
*
* Notes:
* Assumes the MCG mode is in the default FEI mode out of reset
* One of 4 clocking oprions can be selected.
* One of 16 crystal values can be used
*/
#include "common.h"
#include "mcg.h"
extern int core_clk_khz;
extern int core_clk_mhz;
extern int periph_clk_khz;
unsigned char pll_init(unsigned char clk_option, unsigned char crystal_val)
{
unsigned char pll_freq;
if (clk_option > 3) {return 0;} //return 0 if one of the available options is not selected
if (crystal_val > 15) {return 1;} // return 1 if one of the available crystal options is not available
//This assumes that the MCG is in default FEI mode out of reset.
// First move to FBE mode
#if (defined(K60_CLK) || defined(K53_CLK) || defined(ASB817))
MCG_C2 = 0;
#else
// Enable external oscillator, RANGE=2, HGO=1, EREFS=1, LP=0, IRCS=0
MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;
#endif
// after initialization of oscillator release latched state of oscillator and GPIO
SIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;
LLWU_CS |= LLWU_CS_ACKISO_MASK;
// Select external oscilator and Reference Divider and clear IREFS to start ext osc
// CLKS=2, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
/* if we aren't using an osc input we don't need to wait for the osc to init */
#if (!defined(K60_CLK) && !defined(K53_CLK) && !defined(ASB817))
while (!(MCG_S & MCG_S_OSCINIT_MASK)){}; // wait for oscillator to initialize
#endif
while (MCG_S & MCG_S_IREFST_MASK){}; // wait for Reference clock Status bit to clear
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}; // Wait for clock status bits to show clock source is ext ref clk
// Now in FBE
#if (defined(K60_CLK) || defined(K53_CLK))
MCG_C5 = MCG_C5_PRDIV(0x18);
#else
// Configure PLL Ref Divider, PLLCLKEN=0, PLLSTEN=0, PRDIV=5
// The crystal frequency is used to select the PRDIV value. Only even frequency crystals are supported
// that will produce a 2MHz reference clock to the PLL.
MCG_C5 = MCG_C5_PRDIV(crystal_val); // Set PLL ref divider to match the crystal used
#endif
// Ensure MCG_C6 is at the reset default of 0. LOLIE disabled, PLL disabled, clk monitor disabled, PLL VCO divider is clear
MCG_C6 = 0x0;
// Select the PLL VCO divider and system clock dividers depending on clocking option
switch (clk_option) {
case 0:
// Set system options dividers
//MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2
set_sys_dividers(0,0,0,1);
// Set the VCO divider and enable the PLL for 50MHz, LOLIE=0, PLLS=1, CME=0, VDIV=1
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(1); //VDIV = 1 (x25)
pll_freq = 50;
break;
case 1:
// Set system options dividers
//MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
set_sys_dividers(0,1,1,3);
// Set the VCO divider and enable the PLL for 100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(26); //VDIV = 26 (x50)
pll_freq = 100;
break;
case 2:
// Set system options dividers
//MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
set_sys_dividers(0,1,1,3);
// Set the VCO divider and enable the PLL for 96MHz, LOLIE=0, PLLS=1, CME=0, VDIV=24
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(24); //VDIV = 24 (x48)
pll_freq = 96;
break;
case 3:
// Set system options dividers
//MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2
set_sys_dividers(0,0,0,1);
// Set the VCO divider and enable the PLL for 48MHz, LOLIE=0, PLLS=1, CME=0, VDIV=0
MCG_C6 = MCG_C6_PLLS_MASK; //VDIV = 0 (x24)
pll_freq = 48;
break;
}
while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
// Now running PBE Mode
// Transition into PEE by setting CLKS to 0
// CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
MCG_C1 &= ~MCG_C1_CLKS_MASK;
// Wait for clock status bits to update
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};
// Now running PEE Mode
return pll_freq;
} //pll_init
/*
* This routine must be placed in RAM. It is a workaround for errata e2448.
* Flash prefetch must be disabled when the flash clock divider is changed.
* This cannot be performed while executing out of flash.
* There must be a short delay after the clock dividers are changed before prefetch
* can be re-enabled.
*/
#if (defined(IAR))
__ramfunc void set_sys_dividers(uint32 outdiv1, uint32 outdiv2, uint32 outdiv3, uint32 outdiv4)
#elif (defined(CW))
__relocate_code__
void set_sys_dividers(uint32 outdiv1, uint32 outdiv2, uint32 outdiv3, uint32 outdiv4)
#endif
{
uint32 temp_reg;
uint8 i;
temp_reg = FMC_PFAPR; // store present value of FMC_PFAPR
// set M0PFD through M7PFD to 1 to disable prefetch
FMC_PFAPR |= FMC_PFAPR_M7PFD_MASK | FMC_PFAPR_M6PFD_MASK | FMC_PFAPR_M5PFD_MASK
| FMC_PFAPR_M4PFD_MASK | FMC_PFAPR_M3PFD_MASK | FMC_PFAPR_M2PFD_MASK
| FMC_PFAPR_M1PFD_MASK | FMC_PFAPR_M0PFD_MASK;
// set clock dividers to desired value
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2)
| SIM_CLKDIV1_OUTDIV3(outdiv3) | SIM_CLKDIV1_OUTDIV4(outdiv4);
// wait for dividers to change
for (i = 0 ; i < outdiv4 ; i++)
{}
FMC_PFAPR = temp_reg; // re-store original value of FMC_PFAPR
return;
} // set_sys_dividers
/********************************************************************/
void mcg_pee_2_blpi(void)
{
uint8 temp_reg;
// Transition from PEE to BLPI: PEE -> PBE -> FBE -> FBI -> BLPI
// Step 1: PEE -> PBE
MCG_C1 |= MCG_C1_CLKS(2); // System clock from external reference OSC, not PLL.
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}; // Wait for clock status to update.
// Step 2: PBE -> FBE
MCG_C6 &= ~MCG_C6_PLLS_MASK; // Clear PLLS to select FLL, still running system from ext OSC.
while (MCG_S & MCG_S_PLLST_MASK){}; // Wait for PLL status flag to reflect FLL selected.
// Step 3: FBE -> FBI
MCG_C2 &= ~MCG_C2_LP_MASK; // FLL remains active in bypassed modes.
MCG_C2 |= MCG_C2_IRCS_MASK; // Select fast (1MHz) internal reference
temp_reg = MCG_C1;
temp_reg &= ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK);
temp_reg |= (MCG_C1_CLKS(1) | MCG_C1_IREFS_MASK); // Select internal reference (fast IREF clock @ 1MHz) as MCG clock source.
MCG_C1 = temp_reg;
while (MCG_S & MCG_S_IREFST_MASK){}; // Wait for Reference Status bit to update.
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x1){}; // Wait for clock status bits to update
// Step 4: FBI -> BLPI
MCG_C1 |= MCG_C1_IREFSTEN_MASK; // Keep internal reference clock running in STOP modes.
MCG_C2 |= MCG_C2_LP_MASK; // FLL remains disabled in bypassed modes.
while (!(MCG_S & MCG_S_IREFST_MASK)){}; // Wait for Reference Status bit to update.
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x1){}; // Wait for clock status bits to update.
} // end MCG PEE to BLPI
/********************************************************************/
void mcg_blpi_2_pee(void)
{
uint8 temp_reg;
// Transition from BLPI to PEE: BLPI -> FBI -> FEI -> FBE -> PBE -> PEE
// Step 1: BLPI -> FBI
MCG_C2 &= ~MCG_C2_LP_MASK; // FLL remains active in bypassed modes.
while (!(MCG_S & MCG_S_IREFST_MASK)){}; // Wait for Reference Status bit to update.
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x1){}; // Wait for clock status bits to update
// Step 2: FBI -> FEI
MCG_C2 &= ~MCG_C2_LP_MASK; // FLL remains active in bypassed modes.
temp_reg = MCG_C2; // assign temporary variable of MCG_C2 contents
temp_reg &= ~MCG_C2_RANGE_MASK; // set RANGE field location to zero
temp_reg |= (0x2 << 0x4); // OR in new values
MCG_C2 = temp_reg; // store new value in MCG_C2
MCG_C4 = 0x0E; // Low-range DCO output (~10MHz bus). FCTRIM=%0111.
MCG_C1 = 0x04; // Select internal clock as MCG source, FRDIV=%000, internal reference selected.
while (!(MCG_S & MCG_S_IREFST_MASK)){}; // Wait for Reference Status bit to update
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x0){}; // Wait for clock status bits to update
// Handle FEI to PEE transitions using standard clock initialization routine.
core_clk_mhz = pll_init(CORE_CLK_MHZ, REF_CLK);
/* Use the value obtained from the pll_init function to define variables
* for the core clock in kHz and also the peripheral clock. These
* variables can be used by other functions that need awareness of the
* system frequency.
*/
core_clk_khz = core_clk_mhz * 1000;
periph_clk_khz = core_clk_khz / (((SIM_CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> 24)+ 1);
} // end MCG BLPI to PEE
/********************************************************************/
void mcg_pbe_2_pee(void)
{
MCG_C1 &= ~MCG_C1_CLKS_MASK; // select PLL as MCG_OUT
// Wait for clock status bits to update
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};
switch (CORE_CLK_MHZ) {
case PLL50:
core_clk_khz = 50000;
break;
case PLL100:
core_clk_khz = 100000;
break;
case PLL96:
core_clk_khz = 96000;
break;
case PLL48:
core_clk_khz = 48000;
break;
}
}

61
Demo/CORTEX_Kinetis_K60_Tower_IAR/Freescale_Code/drivers/mcg/mcg.h Normal file
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/*
* File: pll_init.h
* Purpose: pll_driver specific declarations
*
* Notes:
*/
#ifndef __MCG_H__
#define __MCG_H__
/********************************************************************/
/* For some reason CW needs to have cw.h explicitly included here for
* the code relocation of set_sys_dividers() to work correctly even
* though common.h should pull in cw.h.
*/
#if (defined(CW))
#include "cw.h"
#endif
unsigned char pll_init(unsigned char, unsigned char);
void mcg_pee_2_blpi(void);
void mcg_blpi_2_pee(void);
void mcg_pbe_2_pee(void);
#if (defined(IAR))
__ramfunc void set_sys_dividers(uint32 outdiv1, uint32 outdiv2, uint32 outdiv3, uint32 outdiv4);
#elif (defined(CW))
__relocate_code__
void set_sys_dividers(uint32 outdiv1, uint32 outdiv2, uint32 outdiv3, uint32 outdiv4);
#endif
enum clk_option
{
PLL50,
PLL100,
PLL96,
PLL48
};
enum crystal_val
{
XTAL2,
XTAL4,
XTAL6,
XTAL8,
XTAL10,
XTAL12,
XTAL14,
XTAL16,
XTAL18,
XTAL20,
XTAL22,
XTAL24,
XTAL26,
XTAL28,
XTAL30,
XTAL32
};
/********************************************************************/
#endif /* __MCG_H__ */

129
Demo/CORTEX_Kinetis_K60_Tower_IAR/Freescale_Code/drivers/uart/uart.c Normal file
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/*
* File: uart.c
* Purpose: Provide common UART routines for serial IO
*
* Notes:
*
*/
#include "common.h"
#include "uart.h"
/********************************************************************/
/*
* Initialize the UART for 8N1 operation, interrupts disabled, and
* no hardware flow-control
*
* NOTE: Since the UARTs are pinned out in multiple locations on most
* Kinetis devices, this driver does not enable UART pin functions.
* The desired pins should be enabled before calling this init function.
*
* Parameters:
* uartch UART channel to initialize
* sysclk UART module Clock in kHz(used to calculate baud)
* baud UART baud rate
*/
void uart_init (UART_MemMapPtr uartch, int sysclk, int baud)
{
register uint16 sbr, brfa;
uint8 temp;
/* Enable the clock to the selected UART */
if(uartch == UART0_BASE_PTR)
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
else
if (uartch == UART1_BASE_PTR)
SIM_SCGC4 |= SIM_SCGC4_UART1_MASK;
else
if (uartch == UART2_BASE_PTR)
SIM_SCGC4 |= SIM_SCGC4_UART2_MASK;
else
if(uartch == UART3_BASE_PTR)
SIM_SCGC4 |= SIM_SCGC4_UART3_MASK;
else
if(uartch == UART4_BASE_PTR)
SIM_SCGC1 |= SIM_SCGC1_UART4_MASK;
else
SIM_SCGC1 |= SIM_SCGC1_UART5_MASK;
/* Make sure that the transmitter and receiver are disabled while we
* change settings.
*/
UART_C2_REG(uartch) &= ~(UART_C2_TE_MASK
| UART_C2_RE_MASK );
/* Configure the UART for 8-bit mode, no parity */
UART_C1_REG(uartch) = 0; /* We need all default settings, so entire register is cleared */
/* Calculate baud settings */
sbr = (uint16)((sysclk*1000)/(baud * 16));
/* Save off the current value of the UARTx_BDH except for the SBR field */
temp = UART_BDH_REG(uartch) & ~(UART_BDH_SBR(0x1F));
UART_BDH_REG(uartch) = temp | UART_BDH_SBR(((sbr & 0x1F00) >> 8));
UART_BDL_REG(uartch) = (uint8)(sbr & UART_BDL_SBR_MASK);
/* Determine if a fractional divider is needed to get closer to the baud rate */
brfa = (((sysclk*32000)/(baud * 16)) - (sbr * 32));
/* Save off the current value of the UARTx_C4 register except for the BRFA field */
temp = UART_C4_REG(uartch) & ~(UART_C4_BRFA(0x1F));
UART_C4_REG(uartch) = temp | UART_C4_BRFA(brfa);
/* Enable receiver and transmitter */
UART_C2_REG(uartch) |= (UART_C2_TE_MASK
| UART_C2_RE_MASK );
}
/********************************************************************/
/*
* Wait for a character to be received on the specified UART
*
* Parameters:
* channel UART channel to read from
*
* Return Values:
* the received character
*/
char uart_getchar (UART_MemMapPtr channel)
{
/* Wait until character has been received */
while (!(UART_S1_REG(channel) & UART_S1_RDRF_MASK));
/* Return the 8-bit data from the receiver */
return UART_D_REG(channel);
}
/********************************************************************/
/*
* Wait for space in the UART Tx FIFO and then send a character
*
* Parameters:
* channel UART channel to send to
* ch character to send
*/
void uart_putchar (UART_MemMapPtr channel, char ch)
{
/* Wait until space is available in the FIFO */
while(!(UART_S1_REG(channel) & UART_S1_TDRE_MASK));
/* Send the character */
UART_D_REG(channel) = (uint8)ch;
}
/********************************************************************/
/*
* Check to see if a character has been received
*
* Parameters:
* channel UART channel to check for a character
*
* Return values:
* 0 No character received
* 1 Character has been received
*/
int uart_getchar_present (UART_MemMapPtr channel)
{
return (UART_S1_REG(channel) & UART_S1_RDRF_MASK);
}
/********************************************************************/

20
Demo/CORTEX_Kinetis_K60_Tower_IAR/Freescale_Code/drivers/uart/uart.h Normal file
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/*
* File: uart.h
* Purpose: Provide common ColdFire UART routines for polled serial IO
*
* Notes:
*/
#ifndef __UART_H__
#define __UART_H__
/********************************************************************/
void uart_init (UART_MemMapPtr, int, int);
char uart_getchar (UART_MemMapPtr);
void uart_putchar (UART_MemMapPtr, char);
int uart_getchar_present (UART_MemMapPtr);
/********************************************************************/
#endif /* __UART_H__ */

59
Demo/CORTEX_Kinetis_K60_Tower_IAR/Freescale_Code/drivers/wdog/wdog.c Normal file
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/*
* File: wdog.c
* Purpose: Provide common watchdog module routines
*
* Notes: Need to add more functionality. Right now it
* is just a disable routine since we know almost
* all projects will need that.
*
*/
#include "common.h"
#include "wdog.h"
/********************************************************************/
/*
* Watchdog timer disable routine
*
* Parameters:
* none
*/
void wdog_disable(void)
{
/* First unlock the watchdog so that we can write to registers */
wdog_unlock();
/* Clear the WDOGEN bit to disable the watchdog */
WDOG_STCTRLH &= ~WDOG_STCTRLH_WDOGEN_MASK;
}
/********************************************************************/
/*
* Watchdog timer unlock routine. Writing 0xC520 followed by 0xD928
* will unlock the write once registers in the WDOG so they are writable
* within the WCT period.
*
* Parameters:
* none
*/
void wdog_unlock(void)
{
/* NOTE: DO NOT SINGLE STEP THROUGH THIS FUNCTION!!! */
/* There are timing requirements for the execution of the unlock. If
* you single step through the code you will cause the CPU to reset.
*/
/* This sequence must execute within 20 clock cycles, so disable
* interrupts will keep the code atomic and ensure the timing.
*/
DisableInterrupts;
/* Write 0xC520 to the unlock register */
WDOG_UNLOCK = 0xC520;
/* Followed by 0xD928 to complete the unlock */
WDOG_UNLOCK = 0xD928;
/* Re-enable interrupts now that we are done */
EnableInterrupts;
}
/********************************************************************/

18
Demo/CORTEX_Kinetis_K60_Tower_IAR/Freescale_Code/drivers/wdog/wdog.h Normal file
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/*
* File: wdog.h
* Purpose: Provide common watchdog module routines
*
* Notes:
*/
#ifndef __WDOG_H__
#define __WDOG_H__
/********************************************************************/
// function prototypes
void wdog_disable(void);
void wdog_unlock(void);
/********************************************************************/
#endif /* __WDOG_H__ */

896
Demo/CORTEX_Kinetis_K60_Tower_IAR/RTOSDemo.ewd Normal file
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@ -0,0 +1,896 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<project>
<fileVersion>2</fileVersion>
<configuration>
<name>RTOSDemo</name>
<toolchain>
<name>ARM</name>
</toolchain>
<debug>1</debug>
<settings>
<name>C-SPY</name>
<archiveVersion>2</archiveVersion>
<data>
<version>22</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CInput</name>
<state>1</state>
</option>
<option>
<name>CEndian</name>
<state>1</state>
</option>
<option>
<name>CProcessor</name>
<state>1</state>
</option>
<option>
<name>OCVariant</name>
<state>0</state>
</option>
<option>
<name>MacOverride</name>
<state>0</state>
</option>
<option>
<name>MacFile</name>
<state></state>
</option>
<option>
<name>MemOverride</name>
<state>0</state>
</option>
<option>
<name>MemFile</name>
<state>$TOOLKIT_DIR$\CONFIG\debugger\Freescale\iok60xxxx.ddf</state>
</option>
<option>
<name>RunToEnable</name>
<state>1</state>
</option>
<option>
<name>RunToName</name>
<state>main</state>
</option>
<option>
<name>CExtraOptionsCheck</name>
<state>0</state>
</option>
<option>
<name>CExtraOptions</name>
<state></state>
</option>
<option>
<name>CFpuProcessor</name>
<state>1</state>
</option>
<option>
<name>OCDDFArgumentProducer</name>
<state></state>
</option>
<option>
<name>OCDownloadSuppressDownload</name>
<state>0</state>
</option>
<option>
<name>OCDownloadVerifyAll</name>
<state>1</state>
</option>
<option>
<name>OCProductVersion</name>
<state>5.50.0.51907</state>
</option>
<option>
<name>OCDynDriverList</name>
<state>JLINK_ID</state>
</option>
<option>
<name>OCLastSavedByProductVersion</name>
<state>6.21.1.52845</state>
</option>
<option>
<name>OCDownloadAttachToProgram</name>
<state>0</state>
</option>
<option>
<name>UseFlashLoader</name>
<state>1</state>
</option>
<option>
<name>CLowLevel</name>
<state>1</state>
</option>
<option>
<name>OCBE8Slave</name>
<state>1</state>
</option>
<option>
<name>MacFile2</name>
<state></state>
</option>
<option>
<name>CDevice</name>
<state>1</state>
</option>
<option>
<name>FlashLoadersV3</name>
<state>$TOOLKIT_DIR$\config\flashloader\Freescale\FlashK60Xxxx.board</state>
</option>
<option>
<name>OCImagesSuppressCheck1</name>
<state>0</state>
</option>
<option>
<name>OCImagesPath1</name>
<state></state>
</option>
<option>
<name>OCImagesSuppressCheck2</name>
<state>0</state>
</option>
<option>
<name>OCImagesPath2</name>
<state></state>
</option>
<option>
<name>OCImagesSuppressCheck3</name>
<state>0</state>
</option>
<option>
<name>OCImagesPath3</name>
<state></state>
</option>
<option>
<name>OverrideDefFlashBoard</name>
<state>0</state>
</option>
<option>
<name>OCImagesOffset1</name>
<state></state>
</option>
<option>
<name>OCImagesOffset2</name>
<state></state>
</option>
<option>
<name>OCImagesOffset3</name>
<state></state>
</option>
<option>
<name>OCImagesUse1</name>
<state>0</state>
</option>
<option>
<name>OCImagesUse2</name>
<state>0</state>
</option>
<option>
<name>OCImagesUse3</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>ARMSIM_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OCSimDriverInfo</name>
<state>1</state>
</option>
<option>
<name>OCSimEnablePSP</name>
<state>0</state>
</option>
<option>
<name>OCSimPspOverrideConfig</name>
<state>0</state>
</option>
<option>
<name>OCSimPspConfigFile</name>
<state></state>
</option>
</data>
</settings>
<settings>
<name>ANGEL_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CCAngelHeartbeat</name>
<state>1</state>
</option>
<option>
<name>CAngelCommunication</name>
<state>1</state>
</option>
<option>
<name>CAngelCommBaud</name>
<version>0</version>
<state>3</state>
</option>
<option>
<name>CAngelCommPort</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>ANGELTCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>DoAngelLogfile</name>
<state>0</state>
</option>
<option>
<name>AngelLogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>GDBSERVER_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>TCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>DoLogfile</name>
<state>0</state>
</option>
<option>
<name>LogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCJTagBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJTagDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJTagUpdateBreakpoints</name>
<state>_call_main</state>
</option>
</data>
</settings>
<settings>
<name>IARROM_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CRomLogFileCheck</name>
<state>0</state>
</option>
<option>
<name>CRomLogFileEditB</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
<option>
<name>CRomCommPort</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CRomCommBaud</name>
<version>0</version>
<state>7</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>JLINK_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>13</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>JLinkSpeed</name>
<state>32</state>
</option>
<option>
<name>CCJLinkDoLogfile</name>
<state>0</state>
</option>
<option>
<name>CCJLinkLogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCJLinkHWResetDelay</name>
<state>0</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>JLinkInitialSpeed</name>
<state>32</state>
</option>
<option>
<name>CCDoJlinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCScanChainNonARMDevices</name>
<state>0</state>
</option>
<option>
<name>CCJLinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCJLinkIRLength</name>
<state>0</state>
</option>
<option>
<name>CCJLinkCommRadio</name>
<state>0</state>
</option>
<option>
<name>CCJLinkTCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>CCJLinkSpeedRadioV2</name>
<state>0</state>
</option>
<option>
<name>CCUSBDevice</name>
<version>1</version>
<state>1</state>
</option>
<option>
<name>CCRDICatchReset</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchUndef</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchSWI</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchData</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchPrefetch</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchIRQ</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchFIQ</name>
<state>0</state>
</option>
<option>
<name>CCJLinkBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJLinkDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJLinkUpdateBreakpoints</name>
<state>_call_main</state>
</option>
<option>
<name>CCJLinkInterfaceRadio</name>
<state>0</state>
</option>
<option>
<name>OCJLinkAttachSlave</name>
<state>1</state>
</option>
<option>
<name>CCJLinkResetList</name>
<version>5</version>
<state>7</state>
</option>
<option>
<name>CCJLinkInterfaceCmdLine</name>
<state>0</state>
</option>
<option>
<name>CCCatchCORERESET</name>
<state>0</state>
</option>
<option>
<name>CCCatchMMERR</name>
<state>0</state>
</option>
<option>
<name>CCCatchNOCPERR</name>
<state>0</state>
</option>
<option>
<name>CCCatchCHRERR</name>
<state>0</state>
</option>
<option>
<name>CCCatchSTATERR</name>
<state>0</state>
</option>
<option>
<name>CCCatchBUSERR</name>
<state>0</state>
</option>
<option>
<name>CCCatchINTERR</name>
<state>0</state>
</option>
<option>
<name>CCCatchHARDERR</name>
<state>0</state>
</option>
<option>
<name>CCCatchDummy</name>
<state>0</state>
</option>
<option>
<name>OCJLinkScriptFile</name>
<state>1</state>
</option>
<option>
<name>CCJLinkUsbSerialNo</name>
<state></state>
</option>
<option>
<name>CCTcpIpAlt</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCJLinkTcpIpSerialNo</name>
<state></state>
</option>
<option>
<name>CCCpuClockEdit</name>
<state>72.0</state>
</option>
<option>
<name>CCSwoClockAuto</name>
<state>0</state>
</option>
<option>
<name>CCSwoClockEdit</name>
<state>2000</state>
</option>
</data>
</settings>
<settings>
<name>LMIFTDI_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>2</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>LmiftdiSpeed</name>
<state>500</state>
</option>
<option>
<name>CCLmiftdiDoLogfile</name>
<state>0</state>
</option>
<option>
<name>CCLmiftdiLogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCLmiFtdiInterfaceRadio</name>
<state>0</state>
</option>
<option>
<name>CCLmiFtdiInterfaceCmdLine</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>MACRAIGOR_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>3</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>jtag</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>EmuSpeed</name>
<state>1</state>
</option>
<option>
<name>TCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>DoLogfile</name>
<state>0</state>
</option>
<option>
<name>LogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
<option>
<name>DoEmuMultiTarget</name>
<state>0</state>
</option>
<option>
<name>EmuMultiTarget</name>
<state>0@ARM7TDMI</state>
</option>
<option>
<name>EmuHWReset</name>
<state>0</state>
</option>
<option>
<name>CEmuCommBaud</name>
<version>0</version>
<state>4</state>
</option>
<option>
<name>CEmuCommPort</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>jtago</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>UnusedAddr</name>
<state>0x00800000</state>
</option>
<option>
<name>CCMacraigorHWResetDelay</name>
<state></state>
</option>
<option>
<name>CCJTagBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJTagDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJTagUpdateBreakpoints</name>
<state>_call_main</state>
</option>
<option>
<name>CCMacraigorInterfaceRadio</name>
<state>0</state>
</option>
<option>
<name>CCMacraigorInterfaceCmdLine</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>PEMICRO_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>OCPEMicroAttachSlave</name>
<state>1</state>
</option>
<option>
<name>CCPEMicroInterfaceList</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCPEMicroResetDelay</name>
<state></state>
</option>
<option>
<name>CCPEMicroJtagSpeed</name>
<state>1000</state>
</option>
<option>
<name>CCJPEMicroShowSettings</name>
<state>0</state>
</option>
<option>
<name>DoLogfile</name>
<state>0</state>
</option>
<option>
<name>LogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCPEMicroUSBDevice</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCPEMicroSerialPort</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCJPEMicroTCPIPAutoScanNetwork</name>
<state>1</state>
</option>
<option>
<name>CCPEMicroTCPIP</name>
<state>10.0.0.1</state>
</option>
<option>
<name>CCPEMicroCommCmdLineProducer</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>RDI_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>2</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CRDIDriverDll</name>
<state>###Uninitialized###</state>
</option>
<option>
<name>CRDILogFileCheck</name>
<state>0</state>
</option>
<option>
<name>CRDILogFileEdit</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCRDIHWReset</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchReset</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchUndef</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchSWI</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchData</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchPrefetch</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchIRQ</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchFIQ</name>
<state>0</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>STLINK_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>2</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>CCSTLinkInterfaceRadio</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkInterfaceCmdLine</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkResetList</name>
<version>1</version>
<state>0</state>
</option>
<option>
<name>CCCpuClockEdit</name>
<state>72.0</state>
</option>
<option>
<name>CCSwoClockAuto</name>
<state>0</state>
</option>
<option>
<name>CCSwoClockEdit</name>
<state>2000</state>
</option>
</data>
</settings>
<settings>
<name>THIRDPARTY_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CThirdPartyDriverDll</name>
<state>###Uninitialized###</state>
</option>
<option>
<name>CThirdPartyLogFileCheck</name>
<state>0</state>
</option>
<option>
<name>CThirdPartyLogFileEditB</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>XDS100_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>OCXDS100AttachSlave</name>
<state>1</state>
</option>
</data>
</settings>
<debuggerPlugins>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
</debuggerPlugins>
</configuration>
</project>

989
Demo/CORTEX_Kinetis_K60_Tower_IAR/RTOSDemo.ewp Normal file
View File

@ -0,0 +1,989 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<project>
<fileVersion>2</fileVersion>
<configuration>
<name>RTOSDemo</name>
<toolchain>
<name>ARM</name>
</toolchain>
<debug>1</debug>
<settings>
<name>General</name>
<archiveVersion>3</archiveVersion>
<data>
<version>21</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>ExePath</name>
<state>RTOSDemo\Exe</state>
</option>
<option>
<name>ObjPath</name>
<state>RTOSDemo\Obj</state>
</option>
<option>
<name>ListPath</name>
<state>RTOSDemo\List</state>
</option>
<option>
<name>Variant</name>
<version>19</version>
<state>38</state>
</option>
<option>
<name>GEndianMode</name>
<state>0</state>
</option>
<option>
<name>Input variant</name>
<version>3</version>
<state>1</state>
</option>
<option>
<name>Input description</name>
<state>Full formatting.</state>
</option>
<option>
<name>Output variant</name>
<version>2</version>
<state>1</state>
</option>
<option>
<name>Output description</name>
<state>Full formatting.</state>
</option>
<option>
<name>GOutputBinary</name>
<state>0</state>
</option>
<option>
<name>FPU</name>
<version>2</version>
<state>0</state>
</option>
<option>
<name>OGCoreOrChip</name>
<state>1</state>
</option>
<option>
<name>GRuntimeLibSelect</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>GRuntimeLibSelectSlave</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>RTDescription</name>
<state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
</option>
<option>
<name>OGProductVersion</name>
<state>5.41.0.51757</state>
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>6.21.1.52845</state>
</option>
<option>
<name>GeneralEnableMisra</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraVerbose</name>
<state>0</state>
</option>
<option>
<name>OGChipSelectEditMenu</name>
<state>K60Xxxx Freescale K60Xxxx</state>
</option>
<option>
<name>GenLowLevelInterface</name>
<state>1</state>
</option>
<option>
<name>GEndianModeBE</name>
<state>1</state>
</option>
<option>
<name>OGBufferedTerminalOutput</name>
<state>0</state>
</option>
<option>
<name>GenStdoutInterface</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraRules98</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>GeneralMisraVer</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraRules04</name>
<version>0</version>
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
</option>
<option>
<name>RTConfigPath2</name>
<state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
</option>
<option>
<name>GFPUCoreSlave</name>
<version>19</version>
<state>38</state>
</option>
<option>
<name>GBECoreSlave</name>
<version>19</version>
<state>38</state>
</option>
<option>
<name>OGUseCmsis</name>
<state>1</state>
</option>
<option>
<name>OGUseCmsisDspLib</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>ICCARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>28</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CCDefines</name>
<state>IAR</state>
<state>TWR_K60N512</state>
</option>
<option>
<name>CCPreprocFile</name>
<state>0</state>
</option>
<option>
<name>CCPreprocComments</name>
<state>0</state>
</option>
<option>
<name>CCPreprocLine</name>
<state>0</state>
</option>
<option>
<name>CCListCFile</name>
<state>0</state>
</option>
<option>
<name>CCListCMnemonics</name>
<state>0</state>
</option>
<option>
<name>CCListCMessages</name>
<state>0</state>
</option>
<option>
<name>CCListAssFile</name>
<state>0</state>
</option>
<option>
<name>CCListAssSource</name>
<state>0</state>
</option>
<option>
<name>CCEnableRemarks</name>
<state>0</state>
</option>
<option>
<name>CCDiagSuppress</name>
<state>Pa082</state>
</option>
<option>
<name>CCDiagRemark</name>
<state></state>
</option>
<option>
<name>CCDiagWarning</name>
<state></state>
</option>
<option>
<name>CCDiagError</name>
<state></state>
</option>
<option>
<name>CCObjPrefix</name>
<state>1</state>
</option>
<option>
<name>CCAllowList</name>
<version>1</version>
<state>0000000</state>
</option>
<option>
<name>CCDebugInfo</name>
<state>1</state>
</option>
<option>
<name>IEndianMode</name>
<state>1</state>
</option>
<option>
<name>IProcessor</name>
<state>1</state>
</option>
<option>
<name>IExtraOptionsCheck</name>
<state>0</state>
</option>
<option>
<name>IExtraOptions</name>
<state></state>
</option>
<option>
<name>CCLangConformance</name>
<state>0</state>
</option>
<option>
<name>CCSignedPlainChar</name>
<state>1</state>
</option>
<option>
<name>CCRequirePrototypes</name>
<state>0</state>
</option>
<option>
<name>CCMultibyteSupport</name>
<state>0</state>
</option>
<option>
<name>CCDiagWarnAreErr</name>
<state>0</state>
</option>
<option>
<name>CCCompilerRuntimeInfo</name>
<state>0</state>
</option>
<option>
<name>IFpuProcessor</name>
<state>1</state>
</option>
<option>
<name>OutputFile</name>
<state>$FILE_BNAME$.o</state>
</option>
<option>
<name>CCLibConfigHeader</name>
<state>1</state>
</option>
<option>
<name>PreInclude</name>
<state></state>
</option>
<option>
<name>CompilerMisraOverride</name>
<state>0</state>
</option>
<option>
<name>CCIncludePath2</name>
<state>$PROJ_DIR$</state>
<state>$PROJ_DIR$\..\..\Source\include</state>
<state>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3</state>
<state>$PROJ_DIR$\..\Common\include</state>
<state>$PROJ_DIR$\Freescale_Code\common</state>
<state>$PROJ_DIR$\Freescale_Code\cpu</state>
<state>$PROJ_DIR$\Freescale_Code\drivers\uart</state>
<state>$PROJ_DIR$\Freescale_Code\drivers\mcg</state>
<state>$PROJ_DIR$\Freescale_Code\drivers\wdog</state>
<state>$PROJ_DIR$\Freescale_Code\drivers\adc16</state>
</option>
<option>
<name>CCStdIncCheck</name>
<state>0</state>
</option>
<option>
<name>CCCodeSection</name>
<state>.text</state>
</option>
<option>
<name>IInterwork2</name>
<state>0</state>
</option>
<option>
<name>IProcessorMode2</name>
<state>1</state>
</option>
<option>
<name>CCOptLevel</name>
<state>1</state>
</option>
<option>
<name>CCOptStrategy</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCOptLevelSlave</name>
<state>1</state>
</option>
<option>
<name>CompilerMisraRules98</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>CompilerMisraRules04</name>
<version>0</version>
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
</option>
<option>
<name>CCPosIndRopi</name>
<state>0</state>
</option>
<option>
<name>CCPosIndRwpi</name>
<state>0</state>
</option>
<option>
<name>CCPosIndNoDynInit</name>
<state>0</state>
</option>
<option>
<name>IccLang</name>
<state>0</state>
</option>
<option>
<name>IccCDialect</name>
<state>1</state>
</option>
<option>
<name>IccAllowVLA</name>
<state>0</state>
</option>
<option>
<name>IccCppDialect</name>
<state>1</state>
</option>
<option>
<name>IccExceptions</name>
<state>1</state>
</option>
<option>
<name>IccRTTI</name>
<state>1</state>
</option>
<option>
<name>IccStaticDestr</name>
<state>1</state>
</option>
<option>
<name>IccCppInlineSemantics</name>
<state>1</state>
</option>
<option>
<name>IccCmsis</name>
<state>1</state>
</option>
<option>
<name>IccFloatSemantics</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>AARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>8</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>AObjPrefix</name>
<state>1</state>
</option>
<option>
<name>AEndian</name>
<state>1</state>
</option>
<option>
<name>ACaseSensitivity</name>
<state>1</state>
</option>
<option>
<name>MacroChars</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>AWarnEnable</name>
<state>0</state>
</option>
<option>
<name>AWarnWhat</name>
<state>0</state>
</option>
<option>
<name>AWarnOne</name>
<state></state>
</option>
<option>
<name>AWarnRange1</name>
<state></state>
</option>
<option>
<name>AWarnRange2</name>
<state></state>
</option>
<option>
<name>ADebug</name>
<state>1</state>
</option>
<option>
<name>AltRegisterNames</name>
<state>0</state>
</option>
<option>
<name>ADefines</name>
<state></state>
</option>
<option>
<name>AList</name>
<state>1</state>
</option>
<option>
<name>AListHeader</name>
<state>1</state>
</option>
<option>
<name>AListing</name>
<state>1</state>
</option>
<option>
<name>Includes</name>
<state>0</state>
</option>
<option>
<name>MacDefs</name>
<state>0</state>
</option>
<option>
<name>MacExps</name>
<state>1</state>
</option>
<option>
<name>MacExec</name>
<state>0</state>
</option>
<option>
<name>OnlyAssed</name>
<state>0</state>
</option>
<option>
<name>MultiLine</name>
<state>0</state>
</option>
<option>
<name>PageLengthCheck</name>
<state>0</state>
</option>
<option>
<name>PageLength</name>
<state>80</state>
</option>
<option>
<name>TabSpacing</name>
<state>8</state>
</option>
<option>
<name>AXRef</name>
<state>0</state>
</option>
<option>
<name>AXRefDefines</name>
<state>0</state>
</option>
<option>
<name>AXRefInternal</name>
<state>0</state>
</option>
<option>
<name>AXRefDual</name>
<state>0</state>
</option>
<option>
<name>AProcessor</name>
<state>1</state>
</option>
<option>
<name>AFpuProcessor</name>
<state>1</state>
</option>
<option>
<name>AOutputFile</name>
<state>$FILE_BNAME$.o</state>
</option>
<option>
<name>AMultibyteSupport</name>
<state>0</state>
</option>
<option>
<name>ALimitErrorsCheck</name>
<state>0</state>
</option>
<option>
<name>ALimitErrorsEdit</name>
<state>100</state>
</option>
<option>
<name>AIgnoreStdInclude</name>
<state>0</state>
</option>
<option>
<name>AUserIncludes</name>
<state>$PROJ_DIR$</state>
</option>
<option>
<name>AExtraOptionsCheckV2</name>
<state>0</state>
</option>
<option>
<name>AExtraOptionsV2</name>
<state></state>
</option>
</data>
</settings>
<settings>
<name>OBJCOPY</name>
<archiveVersion>0</archiveVersion>
<data>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OOCOutputFormat</name>
<version>2</version>
<state>0</state>
</option>
<option>
<name>OCOutputOverride</name>
<state>0</state>
</option>
<option>
<name>OOCOutputFile</name>
<state>RTOSDemo.srec</state>
</option>
<option>
<name>OOCCommandLineProducer</name>
<state>1</state>
</option>
<option>
<name>OOCObjCopyEnable</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>CUSTOM</name>
<archiveVersion>3</archiveVersion>
<data>
<extensions></extensions>
<cmdline></cmdline>
</data>
</settings>
<settings>
<name>BICOMP</name>
<archiveVersion>0</archiveVersion>
<data/>
</settings>
<settings>
<name>BUILDACTION</name>
<archiveVersion>1</archiveVersion>
<data>
<prebuild></prebuild>
<postbuild></postbuild>
</data>
</settings>
<settings>
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>13</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>IlinkLibIOConfig</name>
<state>1</state>
</option>
<option>
<name>XLinkMisraHandler</name>
<state>0</state>
</option>
<option>
<name>IlinkInputFileSlave</name>
<state>0</state>
</option>
<option>
<name>IlinkOutputFile</name>
<state>$PROJ_FNAME$.out</state>
</option>
<option>
<name>IlinkDebugInfoEnable</name>
<state>1</state>
</option>
<option>
<name>IlinkKeepSymbols</name>
<state></state>
</option>
<option>
<name>IlinkRawBinaryFile</name>
<state></state>
</option>
<option>
<name>IlinkRawBinarySymbol</name>
<state></state>
</option>
<option>
<name>IlinkRawBinarySegment</name>
<state></state>
</option>
<option>
<name>IlinkRawBinaryAlign</name>
<state></state>
</option>
<option>
<name>IlinkDefines</name>
<state></state>
</option>
<option>
<name>IlinkConfigDefines</name>
<state></state>
</option>
<option>
<name>IlinkMapFile</name>
<state>1</state>
</option>
<option>
<name>IlinkLogFile</name>
<state>0</state>
</option>
<option>
<name>IlinkLogInitialization</name>
<state>0</state>
</option>
<option>
<name>IlinkLogModule</name>
<state>0</state>
</option>
<option>
<name>IlinkLogSection</name>
<state>0</state>
</option>
<option>
<name>IlinkLogVeneer</name>
<state>0</state>
</option>
<option>
<name>IlinkIcfOverride</name>
<state>1</state>
</option>
<option>
<name>IlinkIcfFile</name>
<state>$PROJ_DIR$\Freescale_Code\common\512KB_Pflash.icf</state>
</option>
<option>
<name>IlinkIcfFileSlave</name>
<state></state>
</option>
<option>
<name>IlinkEnableRemarks</name>
<state>0</state>
</option>
<option>
<name>IlinkSuppressDiags</name>
<state>Lp012</state>
</option>
<option>
<name>IlinkTreatAsRem</name>
<state></state>
</option>
<option>
<name>IlinkTreatAsWarn</name>
<state></state>
</option>
<option>
<name>IlinkTreatAsErr</name>
<state></state>
</option>
<option>
<name>IlinkWarningsAreErrors</name>
<state>0</state>
</option>
<option>
<name>IlinkUseExtraOptions</name>
<state>0</state>
</option>
<option>
<name>IlinkExtraOptions</name>
<state></state>
</option>
<option>
<name>IlinkLowLevelInterfaceSlave</name>
<state>1</state>
</option>
<option>
<name>IlinkAutoLibEnable</name>
<state>1</state>
</option>
<option>
<name>IlinkAdditionalLibs</name>
<state></state>
</option>
<option>
<name>IlinkOverrideProgramEntryLabel</name>
<state>0</state>
</option>
<option>
<name>IlinkProgramEntryLabelSelect</name>
<state>0</state>
</option>
<option>
<name>IlinkProgramEntryLabel</name>
<state>__iar_program_start</state>
</option>
<option>
<name>DoFill</name>
<state>0</state>
</option>
<option>
<name>FillerByte</name>
<state>0xFF</state>
</option>
<option>
<name>FillerStart</name>
<state>0x0</state>
</option>
<option>
<name>FillerEnd</name>
<state>0x0</state>
</option>
<option>
<name>CrcSize</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>CrcAlign</name>
<state>1</state>
</option>
<option>
<name>CrcAlgo</name>
<state>1</state>
</option>
<option>
<name>CrcPoly</name>
<state>0x11021</state>
</option>
<option>
<name>CrcCompl</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CrcBitOrder</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CrcInitialValue</name>
<state>0x0</state>
</option>
<option>
<name>DoCrc</name>
<state>0</state>
</option>
<option>
<name>IlinkBE8Slave</name>
<state>1</state>
</option>
<option>
<name>IlinkBufferedTerminalOutput</name>
<state>1</state>
</option>
<option>
<name>IlinkStdoutInterfaceSlave</name>
<state>1</state>
</option>
<option>
<name>CrcFullSize</name>
<state>0</state>
</option>
<option>
<name>IlinkIElfToolPostProcess</name>
<state>0</state>
</option>
<option>
<name>IlinkLogAutoLibSelect</name>
<state>0</state>
</option>
<option>
<name>IlinkLogRedirSymbols</name>
<state>0</state>
</option>
<option>
<name>IlinkLogUnusedFragments</name>
<state>0</state>
</option>
<option>
<name>IlinkCrcReverseByteOrder</name>
<state>0</state>
</option>
<option>
<name>IlinkCrcUseAsInput</name>
<state>1</state>
</option>
<option>
<name>IlinkOptInline</name>
<state>0</state>
</option>
<option>
<name>IlinkOptExceptionsAllow</name>
<state>1</state>
</option>
<option>
<name>IlinkOptExceptionsForce</name>
<state>0</state>
</option>
<option>
<name>IlinkCmsis</name>
<state>1</state>
</option>
<option>
<name>IlinkOptMergeDuplSections</name>
<state>0</state>
</option>
<option>
<name>IlinkOptUseVfe</name>
<state>1</state>
</option>
<option>
<name>IlinkOptForceVfe</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>IARCHIVE</name>
<archiveVersion>0</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>IarchiveInputs</name>
<state></state>
</option>
<option>
<name>IarchiveOverride</name>
<state>0</state>
</option>
<option>
<name>IarchiveOutput</name>
<state>###Unitialized###</state>
</option>
</data>
</settings>
<settings>
<name>BILINK</name>
<archiveVersion>0</archiveVersion>
<data/>
</settings>
</configuration>
<group>
<name>FreeRTOS_Source</name>
<group>
<name>portable</name>
<file>
<name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>
</file>
</group>
<file>
<name>$PROJ_DIR$\..\..\Source\list.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\queue.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\tasks.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\Source\timers.c</name>
</file>
</group>
<group>
<name>Freescale_Code</name>
<group>
<name>common</name>
<file>
<name>$PROJ_DIR$\Freescale_Code\common\startup.c</name>
</file>
</group>
<group>
<name>cpu</name>
<file>
<name>$PROJ_DIR$\Freescale_Code\cpu\arm_cm4.c</name>
</file>
<file>
<name>$PROJ_DIR$\Freescale_Code\cpu\crt0.s</name>
</file>
<file>
<name>$PROJ_DIR$\Freescale_Code\cpu\start.c</name>
</file>
<file>
<name>$PROJ_DIR$\Freescale_Code\cpu\sysinit.c</name>
</file>
<file>
<name>$PROJ_DIR$\Freescale_Code\cpu\vectors.c</name>
</file>
</group>
<group>
<name>drivers</name>
<group>
<name>mcg</name>
<file>
<name>$PROJ_DIR$\Freescale_Code\drivers\mcg\mcg.c</name>
</file>
</group>
<group>
<name>uart</name>
<file>
<name>$PROJ_DIR$\Freescale_Code\drivers\uart\uart.c</name>
</file>
</group>
<group>
<name>wdog</name>
<file>
<name>$PROJ_DIR$\Freescale_Code\drivers\wdog\wdog.c</name>
</file>
</group>
</group>
</group>
<file>
<name>$PROJ_DIR$\main_blinky.c</name>
</file>
</project>

50
Demo/CORTEX_Kinetis_K60_Tower_IAR/RTOSDemo.eww Normal file
View File

@ -0,0 +1,50 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\RTOSDemo.ewp</path>
</project>
<batchBuild>
<batchDefinition>
<name>All</name>
<member>
<project>gpio_k40_tower</project>
<configuration>FLASH_128KB_PFLASH</configuration>
</member>
<member>
<project>gpio_k40_tower</project>
<configuration>FLASH_64KB_PFLASH_64KB_DFLASH</configuration>
</member>
<member>
<project>gpio_k40_tower</project>
<configuration>RAM_128KB</configuration>
</member>
<member>
<project>RTOSDemo</project>
<configuration>FLASH_128KB_PFLASH</configuration>
</member>
<member>
<project>RTOSDemo</project>
<configuration>FLASH_64KB_PFLASH_64KB_DFLASH</configuration>
</member>
<member>
<project>RTOSDemo</project>
<configuration>RAM_128KB</configuration>
</member>
<member>
<project>gpio_k53_tower</project>
<configuration>FLASH_128KB_PFLASH</configuration>
</member>
<member>
<project>gpio_k53_tower</project>
<configuration>FLASH_64KB_PFLASH_64KB_DFLASH</configuration>
</member>
<member>
<project>gpio_k53_tower</project>
<configuration>RAM_128KB</configuration>
</member>
</batchDefinition>
</batchBuild>
</workspace>