RISC-V: add float-point and C906 MTIMER support
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@ -0,0 +1,205 @@
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/*
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* FreeRTOS Kernel V10.4.0
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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* 1 tab == 4 spaces!
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*/
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
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*
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* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
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* is common to all currently supported RISC-V chips. There is only one
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* portASM.S file because the same file is built for all RISC-V target chips.
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*
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* + Header files called freertos_risc_v_chip_specific_extensions.h contain the
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* code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
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* chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
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* as there are multiple RISC-V chip implementations.
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*
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* !!!NOTE!!!
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* TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
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* HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
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* compiler's!) include path. For example, if the chip in use includes a core
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* local interrupter (CLINT) and does not include any chip specific register
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* extensions then add the path below to the assembler's include path:
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
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*
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*/
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#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
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#define __FREERTOS_RISC_V_EXTENSIONS_H__
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#define portasmHANDLE_INTERRUPT Default_IRQHandler
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#define portasmHAS_SIFIVE_CLINT 1
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#define portasmHAS_MTIME 1
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#define portasmADDITIONAL_CONTEXT_SIZE 32 /* Must be even number on 32-bit cores. */
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.macro portasmSAVE_ADDITIONAL_REGISTERS
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/* save float registers */
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addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE)
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#if __riscv_flen == 64
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fsd f31, 32 * portWORD_SIZE( sp )
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fsd f30, 31 * portWORD_SIZE( sp )
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fsd f29, 30 * portWORD_SIZE( sp )
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fsd f28, 29 * portWORD_SIZE( sp )
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fsd f27, 28 * portWORD_SIZE( sp )
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fsd f26, 27 * portWORD_SIZE( sp )
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fsd f25, 26 * portWORD_SIZE( sp )
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fsd f24, 25 * portWORD_SIZE( sp )
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fsd f23, 24 * portWORD_SIZE( sp )
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fsd f22, 23 * portWORD_SIZE( sp )
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fsd f21, 22 * portWORD_SIZE( sp )
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fsd f20, 21 * portWORD_SIZE( sp )
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fsd f19, 20 * portWORD_SIZE( sp )
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fsd f18, 19 * portWORD_SIZE( sp )
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fsd f17, 18 * portWORD_SIZE( sp )
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fsd f16, 17 * portWORD_SIZE( sp )
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fsd f15, 16 * portWORD_SIZE( sp )
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fsd f14, 15 * portWORD_SIZE( sp )
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fsd f13, 14 * portWORD_SIZE( sp )
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fsd f12, 13 * portWORD_SIZE( sp )
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fsd f11, 12 * portWORD_SIZE( sp )
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fsd f10, 11 * portWORD_SIZE( sp )
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fsd f9, 10 * portWORD_SIZE( sp )
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fsd f8, 9 * portWORD_SIZE( sp )
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fsd f7, 8 * portWORD_SIZE( sp )
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fsd f6, 7 * portWORD_SIZE( sp )
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fsd f5, 6 * portWORD_SIZE( sp )
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fsd f4, 5 * portWORD_SIZE( sp )
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fsd f3, 4 * portWORD_SIZE( sp )
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fsd f2, 3 * portWORD_SIZE( sp )
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fsd f1, 2 * portWORD_SIZE( sp )
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fsd f0, 1 * portWORD_SIZE( sp )
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#elif __riscv_flen == 32
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fsw f31, 32 * portWORD_SIZE( sp )
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fsw f30, 31 * portWORD_SIZE( sp )
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fsw f29, 30 * portWORD_SIZE( sp )
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fsw f28, 29 * portWORD_SIZE( sp )
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fsw f27, 28 * portWORD_SIZE( sp )
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fsw f26, 27 * portWORD_SIZE( sp )
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fsw f25, 26 * portWORD_SIZE( sp )
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fsw f24, 25 * portWORD_SIZE( sp )
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fsw f23, 24 * portWORD_SIZE( sp )
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fsw f22, 23 * portWORD_SIZE( sp )
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fsw f21, 22 * portWORD_SIZE( sp )
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fsw f20, 21 * portWORD_SIZE( sp )
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fsw f19, 20 * portWORD_SIZE( sp )
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fsw f18, 19 * portWORD_SIZE( sp )
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fsw f17, 18 * portWORD_SIZE( sp )
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fsw f16, 17 * portWORD_SIZE( sp )
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fsw f15, 16 * portWORD_SIZE( sp )
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fsw f14, 15 * portWORD_SIZE( sp )
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fsw f13, 14 * portWORD_SIZE( sp )
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fsw f12, 13 * portWORD_SIZE( sp )
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fsw f11, 12 * portWORD_SIZE( sp )
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fsw f10, 11 * portWORD_SIZE( sp )
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fsw f9, 10 * portWORD_SIZE( sp )
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fsw f8, 9 * portWORD_SIZE( sp )
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fsw f7, 8 * portWORD_SIZE( sp )
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fsw f6, 7 * portWORD_SIZE( sp )
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fsw f5, 6 * portWORD_SIZE( sp )
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fsw f4, 5 * portWORD_SIZE( sp )
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fsw f3, 4 * portWORD_SIZE( sp )
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fsw f2, 3 * portWORD_SIZE( sp )
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fsw f1, 2 * portWORD_SIZE( sp )
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fsw f0, 1 * portWORD_SIZE( sp )
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#endif
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.endm
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.macro portasmRESTORE_ADDITIONAL_REGISTERS
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/* load float registers */
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#if __riscv_flen == 64
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fld f31, 32 * portWORD_SIZE( sp )
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fld f30, 31 * portWORD_SIZE( sp )
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fld f29, 30 * portWORD_SIZE( sp )
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fld f28, 29 * portWORD_SIZE( sp )
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fld f27, 28 * portWORD_SIZE( sp )
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fld f26, 27 * portWORD_SIZE( sp )
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fld f25, 26 * portWORD_SIZE( sp )
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fld f24, 25 * portWORD_SIZE( sp )
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fld f23, 24 * portWORD_SIZE( sp )
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fld f22, 23 * portWORD_SIZE( sp )
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fld f21, 22 * portWORD_SIZE( sp )
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fld f20, 21 * portWORD_SIZE( sp )
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fld f19, 20 * portWORD_SIZE( sp )
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fld f18, 19 * portWORD_SIZE( sp )
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fld f17, 18 * portWORD_SIZE( sp )
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fld f16, 17 * portWORD_SIZE( sp )
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fld f15, 16 * portWORD_SIZE( sp )
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fld f14, 15 * portWORD_SIZE( sp )
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fld f13, 14 * portWORD_SIZE( sp )
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fld f12, 13 * portWORD_SIZE( sp )
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fld f11, 12 * portWORD_SIZE( sp )
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fld f10, 11 * portWORD_SIZE( sp )
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fld f9, 10 * portWORD_SIZE( sp )
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fld f8, 9 * portWORD_SIZE( sp )
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fld f7, 8 * portWORD_SIZE( sp )
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fld f6, 7 * portWORD_SIZE( sp )
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fld f5, 6 * portWORD_SIZE( sp )
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fld f4, 5 * portWORD_SIZE( sp )
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fld f3, 4 * portWORD_SIZE( sp )
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fld f2, 3 * portWORD_SIZE( sp )
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fld f1, 2 * portWORD_SIZE( sp )
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fld f0, 1 * portWORD_SIZE( sp )
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#elif __riscv_flen == 32
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flw f31, 32 * portWORD_SIZE( sp )
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flw f30, 31 * portWORD_SIZE( sp )
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flw f29, 30 * portWORD_SIZE( sp )
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flw f28, 29 * portWORD_SIZE( sp )
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flw f27, 28 * portWORD_SIZE( sp )
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flw f26, 27 * portWORD_SIZE( sp )
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flw f25, 26 * portWORD_SIZE( sp )
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flw f24, 25 * portWORD_SIZE( sp )
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flw f23, 24 * portWORD_SIZE( sp )
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flw f22, 23 * portWORD_SIZE( sp )
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flw f21, 22 * portWORD_SIZE( sp )
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flw f20, 21 * portWORD_SIZE( sp )
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flw f19, 20 * portWORD_SIZE( sp )
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flw f18, 19 * portWORD_SIZE( sp )
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flw f17, 18 * portWORD_SIZE( sp )
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flw f16, 17 * portWORD_SIZE( sp )
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flw f15, 16 * portWORD_SIZE( sp )
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flw f14, 15 * portWORD_SIZE( sp )
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flw f13, 14 * portWORD_SIZE( sp )
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flw f12, 13 * portWORD_SIZE( sp )
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flw f11, 12 * portWORD_SIZE( sp )
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flw f10, 11 * portWORD_SIZE( sp )
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flw f9, 10 * portWORD_SIZE( sp )
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flw f8, 9 * portWORD_SIZE( sp )
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flw f7, 8 * portWORD_SIZE( sp )
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flw f6, 7 * portWORD_SIZE( sp )
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flw f5, 6 * portWORD_SIZE( sp )
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flw f4, 5 * portWORD_SIZE( sp )
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flw f3, 4 * portWORD_SIZE( sp )
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flw f2, 3 * portWORD_SIZE( sp )
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flw f1, 2 * portWORD_SIZE( sp )
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flw f0, 1 * portWORD_SIZE( sp )
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#endif
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addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE)
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.endm
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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@ -50,6 +50,10 @@
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#warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#endif
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#ifndef configCPU_THEAD_C906
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#warning configCPU_THEAD_C906 must be defined in FreeRTOSConfig.h. If the target chip is T-Head C906 then set configCPU_THEAD_C906 to 1. Otherwise set configCPU_THEAD_C906 to 0.
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#endif
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/* Let the user override the pre-loading of the initial RA. */
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#ifdef configTASK_RETURN_ADDRESS
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#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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@ -123,18 +127,20 @@ size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS;
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/*-----------------------------------------------------------*/
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#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
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#if( configMTIME_BASE_ADDRESS != 0 || configCPU_THEAD_C906 != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
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void vPortSetupTimerInterrupt( void )
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{
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uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
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volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte type so high 32-bit word is 4 bytes up. */
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volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS );
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volatile uint32_t ulHartId;
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volatile uint32_t ulHartId;
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__asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) );
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pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
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#if ( configCPU_THEAD_C906 != 0 )
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{
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uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
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volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte type so high 32-bit word is 4 bytes up. */
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volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS );
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do
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{
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ulCurrentTimeHigh = *pulTimeHigh;
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ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
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ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */
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ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
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}
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#else
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{
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// C906 Manual
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__asm volatile("csrr %0, 0xc01" : "=r"(ullNextTime));
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}
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#endif
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ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
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*pullMachineTimerCompareRegister = ullNextTime;
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@ -151,7 +165,7 @@ size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS;
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ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
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}
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#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */
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#endif /* ( configMTIME_BASE_ADDRESS != 0 || configCPU_THEAD_C906 != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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* configure whichever clock is to be used to generate the tick interrupt. */
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vPortSetupTimerInterrupt();
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#if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
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#if( ( configMTIME_BASE_ADDRESS != 0 || configCPU_THEAD_C906 != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
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{
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/* Enable mtime and external interrupts. 1<<7 for timer interrupt,
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* 1<<11 for external interrupt. _RB_ What happens here when mtime is
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* not present as with pulpino? */
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__asm volatile( "csrs mie, %0" :: "r"(0x880) );
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}
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#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
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#endif /* ( configMTIME_BASE_ADDRESS != 0 || configCPU_THEAD_C906 != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
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xPortStartFirstTask();
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@ -180,8 +180,8 @@ extern size_t xCriticalNesting;
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* from the CLINT address. */
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#define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
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#define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
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#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
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#error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS ) || !defined( configCPU_THEAD_C906 )
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#error configMTIME_BASE_ADDRESS, configMTIMECMP_BASE_ADDRESS and configCPU_THEAD_C906 must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#endif
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#ifdef __cplusplus
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@ -21,3 +21,12 @@
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
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*
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*/
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My Addition Notes:
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+ chip_specific_extensions/Thead_common
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- modified from portable/ThirdParty/Community-Supported-Ports/GCC/RISC-V/chip_specific_extensions/THEAD_RV32
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-
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+ port.c
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- modify configMTIME_BASE_ADDRESS related logic
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+ C906 has MTIMER but count is in CSR
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