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Added a build configuration for the Wonder Gecko starter kit to the existing Giant Gecko Simplicity Studio project.

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Fix some lint warnings that were generated by some of the new core functionality.
This commit is contained in:
Richard Barry 2016-01-31 20:22:00 +00:00
parent 802af0150c
commit c4dd17eeb5
78 changed files with 28742 additions and 168 deletions
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217
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/.cproject
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49
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/.project
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@ -70,7 +70,7 @@
</matcher>
</filter>
<filter>
<id>1453621082417</id>
<id>1454263538723</id>
<name>Source/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -79,7 +79,7 @@
</matcher>
</filter>
<filter>
<id>1453621082420</id>
<id>1454263538726</id>
<name>Source/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -88,7 +88,7 @@
</matcher>
</filter>
<filter>
<id>1453621082425</id>
<id>1454263538748</id>
<name>Source/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -97,7 +97,7 @@
</matcher>
</filter>
<filter>
<id>1453621082429</id>
<id>1454263538751</id>
<name>Source/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -106,7 +106,7 @@
</matcher>
</filter>
<filter>
<id>1453621082433</id>
<id>1454263538755</id>
<name>Source/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -115,7 +115,7 @@
</matcher>
</filter>
<filter>
<id>1453621082437</id>
<id>1454263538759</id>
<name>Source/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -124,7 +124,7 @@
</matcher>
</filter>
<filter>
<id>1453621082441</id>
<id>1454263538763</id>
<name>Source/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -133,7 +133,7 @@
</matcher>
</filter>
<filter>
<id>1453621082445</id>
<id>1454263538766</id>
<name>Source/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -142,16 +142,7 @@
</matcher>
</filter>
<filter>
<id>1453621082449</id>
<name>Source/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-death.c</arguments>
</matcher>
</filter>
<filter>
<id>1453621082455</id>
<id>1454263538770</id>
<name>Source/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -160,16 +151,7 @@
</matcher>
</filter>
<filter>
<id>1453621082460</id>
<name>Source/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-IntSemTest.c</arguments>
</matcher>
</filter>
<filter>
<id>1453621082465</id>
<id>1454263538774</id>
<name>Source/Full_Demo/Standard_Demo_Tasks</name>
<type>5</type>
<matcher>
@ -178,7 +160,7 @@
</matcher>
</filter>
<filter>
<id>0</id>
<id>1454264510429</id>
<name>Source/FreeRTOS_Source/portable/GCC</name>
<type>9</type>
<matcher>
@ -186,6 +168,15 @@
<arguments>1.0-name-matches-false-false-ARM_CM3</arguments>
</matcher>
</filter>
<filter>
<id>1454264510433</id>
<name>Source/FreeRTOS_Source/portable/GCC</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-ARM_CM4F</arguments>
</matcher>
</filter>
<filter>
<id>0</id>
<name>Source/FreeRTOS_Source/portable/MemMang</name>

8
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/FreeRTOSConfig.h
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@ -134,9 +134,9 @@ the comments at the top of main.c for more information. */
#define configSUPPORT_STATIC_ALLOCATION ( 1 )
#define configCPU_CLOCK_HZ (( unsigned long ) 14000000)
#define configMAX_PRIORITIES ( 6 )
#define configMINIMAL_STACK_SIZE (( unsigned short ) 140)
#define configTOTAL_HEAP_SIZE (( size_t )(40000))
#define configMAX_TASK_NAME_LEN ( 10 )
#define configMINIMAL_STACK_SIZE (( unsigned short ) 130)
#define configTOTAL_HEAP_SIZE (( size_t )(25000))
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY ( 0 )
#define configUSE_16_BIT_TICKS ( 0 )
#define configIDLE_SHOULD_YIELD ( 0 )
@ -145,7 +145,7 @@ the comments at the top of main.c for more information. */
#define configUSE_COUNTING_SEMAPHORES ( 1 )
#define configUSE_ALTERNATIVE_API ( 0 )/* Deprecated! */
#define configQUEUE_REGISTRY_SIZE ( 10 )
#define configUSE_QUEUE_SETS ( 0 )
#define configUSE_QUEUE_SETS ( 0 )
/* Run time stats gathering related definitions. */
#define configGENERATE_RUN_TIME_STATS ( 0 )

21
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/Full_Demo/main_full.c
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@ -128,11 +128,9 @@
#include "blocktim.h"
#include "GenQTest.h"
#include "recmutex.h"
#include "death.h"
#include "TimerDemo.h"
#include "EventGroupsDemo.h"
#include "TaskNotify.h"
#include "IntSemTest.h"
#include "StaticAllocation.h"
/* Priorities for the demo application tasks. */
@ -227,7 +225,6 @@ void main_full( void )
vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
vStartEventGroupTasks();
vStartTaskNotifyTask();
vStartInterruptSemaphoreTasks();
vStartStaticallyAllocatedTasks();
/* Create the register check tasks, as described at the top of this file */
@ -238,11 +235,6 @@ void main_full( void )
the top of this file. */
xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* The set of tasks created by the following function call have to be
created last as they keep account of the number of tasks they expect to see
running. */
vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
/* Start the scheduler. */
vTaskStartScheduler();
@ -313,11 +305,6 @@ unsigned long ulErrorFound = pdFALSE;
ulErrorFound = 1UL << 6UL;
}
if( xIsCreateTaskStillRunning() != pdTRUE )
{
ulErrorFound = 1UL << 7UL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFound = 1UL << 8UL;
@ -328,11 +315,6 @@ unsigned long ulErrorFound = pdFALSE;
ulErrorFound = 1UL << 9UL;
}
if( xAreInterruptSemaphoreTasksStillRunning() != pdPASS )
{
ulErrorFound = 1UL << 11UL;
}
if( xAreEventGroupTasksStillRunning() != pdPASS )
{
ulErrorFound = 1UL << 12UL;
@ -424,9 +406,6 @@ void vFullDemoTickHook( void )
/* Call the periodic event group from ISR demo. */
vPeriodicEventGroupsProcessing();
/* Call the code that uses a mutex from an ISR. */
vInterruptSemaphorePeriodicTest();
/* Call the code that 'gives' a task notification from an ISR. */
xNotifyTaskFromISR();
}

2
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/Low_Power_Demo/low_power_tick_management.c
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@ -67,6 +67,8 @@
1 tab == 4 spaces!
*/
#warning Not functioning correctly above -O1 optimisation level.
/* Standard includes. */
#include "limits.h"

1802
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/CMSIS/Include/core_cm4.h Normal file
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341
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/CMSIS/efm32wg/startup_gcc_efm32wg.s Normal file
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@ -0,0 +1,341 @@
/* @file startup_efm32wg.S
* @brief startup file for Silicon Labs EFM32WG devices.
* For use with GCC for ARM Embedded Processors
* @version 4.0.0
* Date: 12 June 2014
*
*/
/* Copyright (c) 2011 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv7-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00000400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000C00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long Default_Handler /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long DMA_IRQHandler /* 0 - DMA */
.long GPIO_EVEN_IRQHandler /* 1 - GPIO_EVEN */
.long TIMER0_IRQHandler /* 2 - TIMER0 */
.long USART0_RX_IRQHandler /* 3 - USART0_RX */
.long USART0_TX_IRQHandler /* 4 - USART0_TX */
.long USB_IRQHandler /* 5 - USB */
.long ACMP0_IRQHandler /* 6 - ACMP0 */
.long ADC0_IRQHandler /* 7 - ADC0 */
.long DAC0_IRQHandler /* 8 - DAC0 */
.long I2C0_IRQHandler /* 9 - I2C0 */
.long I2C1_IRQHandler /* 10 - I2C1 */
.long GPIO_ODD_IRQHandler /* 11 - GPIO_ODD */
.long TIMER1_IRQHandler /* 12 - TIMER1 */
.long TIMER2_IRQHandler /* 13 - TIMER2 */
.long TIMER3_IRQHandler /* 14 - TIMER3 */
.long USART1_RX_IRQHandler /* 15 - USART1_RX */
.long USART1_TX_IRQHandler /* 16 - USART1_TX */
.long LESENSE_IRQHandler /* 17 - LESENSE */
.long USART2_RX_IRQHandler /* 18 - USART2_RX */
.long USART2_TX_IRQHandler /* 19 - USART2_TX */
.long UART0_RX_IRQHandler /* 20 - UART0_RX */
.long UART0_TX_IRQHandler /* 21 - UART0_TX */
.long UART1_RX_IRQHandler /* 22 - UART1_RX */
.long UART1_TX_IRQHandler /* 23 - UART1_TX */
.long LEUART0_IRQHandler /* 24 - LEUART0 */
.long LEUART1_IRQHandler /* 25 - LEUART1 */
.long LETIMER0_IRQHandler /* 26 - LETIMER0 */
.long PCNT0_IRQHandler /* 27 - PCNT0 */
.long PCNT1_IRQHandler /* 28 - PCNT1 */
.long PCNT2_IRQHandler /* 29 - PCNT2 */
.long RTC_IRQHandler /* 30 - RTC */
.long BURTC_IRQHandler /* 31 - BURTC */
.long CMU_IRQHandler /* 32 - CMU */
.long VCMP_IRQHandler /* 33 - VCMP */
.long LCD_IRQHandler /* 34 - LCD */
.long MSC_IRQHandler /* 35 - MSC */
.long AES_IRQHandler /* 36 - AES */
.long EBI_IRQHandler /* 37 - EBI */
.long EMU_IRQHandler /* 38 - EMU */
.long FPUEH_IRQHandler /* 39 - FPUEH */
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
#ifndef __NO_SYSTEM_INIT
ldr r0, =SystemInit
blx r0
#endif
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
HardFault_Handler:
b .
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler DMA_IRQHandler
def_irq_handler GPIO_EVEN_IRQHandler
def_irq_handler TIMER0_IRQHandler
def_irq_handler USART0_RX_IRQHandler
def_irq_handler USART0_TX_IRQHandler
def_irq_handler USB_IRQHandler
def_irq_handler ACMP0_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler DAC0_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler GPIO_ODD_IRQHandler
def_irq_handler TIMER1_IRQHandler
def_irq_handler TIMER2_IRQHandler
def_irq_handler TIMER3_IRQHandler
def_irq_handler USART1_RX_IRQHandler
def_irq_handler USART1_TX_IRQHandler
def_irq_handler LESENSE_IRQHandler
def_irq_handler USART2_RX_IRQHandler
def_irq_handler USART2_TX_IRQHandler
def_irq_handler UART0_RX_IRQHandler
def_irq_handler UART0_TX_IRQHandler
def_irq_handler UART1_RX_IRQHandler
def_irq_handler UART1_TX_IRQHandler
def_irq_handler LEUART0_IRQHandler
def_irq_handler LEUART1_IRQHandler
def_irq_handler LETIMER0_IRQHandler
def_irq_handler PCNT0_IRQHandler
def_irq_handler PCNT1_IRQHandler
def_irq_handler PCNT2_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler BURTC_IRQHandler
def_irq_handler CMU_IRQHandler
def_irq_handler VCMP_IRQHandler
def_irq_handler LCD_IRQHandler
def_irq_handler MSC_IRQHandler
def_irq_handler AES_IRQHandler
def_irq_handler EBI_IRQHandler
def_irq_handler EMU_IRQHandler
def_irq_handler FPUEH_IRQHandler
.end

388
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/CMSIS/efm32wg/system_efm32wg.c Normal file
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@ -0,0 +1,388 @@
/***************************************************************************//**
* @file system_efm32wg.c
* @brief CMSIS Cortex-M4 System Layer for EFM32WG devices.
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#include <stdint.h>
#include "em_device.h"
/*******************************************************************************
****************************** DEFINES ************************************
******************************************************************************/
/** LFRCO frequency, tuned to below frequency during manufacturing. */
#define EFM32_LFRCO_FREQ (32768UL)
#define EFM32_ULFRCO_FREQ (1000UL)
/*******************************************************************************
************************** LOCAL VARIABLES ********************************
******************************************************************************/
/* System oscillator frequencies. These frequencies are normally constant */
/* for a target, but they are made configurable in order to allow run-time */
/* handling of different boards. The crystal oscillator clocks can be set */
/* compile time to a non-default value by defining respective EFM32_nFXO_FREQ */
/* values according to board design. By defining the EFM32_nFXO_FREQ to 0, */
/* one indicates that the oscillator is not present, in order to save some */
/* SW footprint. */
#ifndef EFM32_HFXO_FREQ
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#define EFM32_HFXO_FREQ (48000000UL)
#else
#define EFM32_HFXO_FREQ (32000000UL)
#endif
#endif
/* Do not define variable if HF crystal oscillator not present */
#if (EFM32_HFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System HFXO clock. */
static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
#ifndef EFM32_LFXO_FREQ
#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
#endif
/* Do not define variable if LF crystal oscillator not present */
#if (EFM32_LFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System LFXO clock. */
static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
/* Inline function to get the chip's Production Revision. */
__STATIC_INLINE uint8_t GetProdRev(void)
{
return ((DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK)
>> _DEVINFO_PART_PROD_REV_SHIFT);
}
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
/**
* @brief
* System System Clock Frequency (Core Clock).
*
* @details
* Required CMSIS global variable that must be kept up-to-date.
*/
uint32_t SystemCoreClock;
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
/***************************************************************************//**
* @brief
* Get the current core clock frequency.
*
* @details
* Calculate and get the current core clock frequency based on the current
* configuration. Assuming that the SystemCoreClock global variable is
* maintained, the core clock frequency is stored in that variable as well.
* This function will however calculate the core clock based on actual HW
* configuration. It will also update the SystemCoreClock global variable.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* The current core clock frequency in Hz.
******************************************************************************/
uint32_t SystemCoreClockGet(void)
{
uint32_t ret;
ret = SystemHFClockGet();
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
/* Leopard/Giant/Wonder Gecko has an additional divider */
ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));
#endif
ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
/* Keep CMSIS variable up-to-date just in case */
SystemCoreClock = ret;
return ret;
}
/***************************************************************************//**
* @brief
* Get the current HFCLK frequency.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* The current HFCLK frequency in Hz.
******************************************************************************/
uint32_t SystemHFClockGet(void)
{
uint32_t ret;
switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
{
case CMU_STATUS_LFXOSEL:
#if (EFM32_LFXO_FREQ > 0)
ret = SystemLFXOClock;
#else
/* We should not get here, since core should not be clocked. May */
/* be caused by a misconfiguration though. */
ret = 0;
#endif
break;
case CMU_STATUS_LFRCOSEL:
ret = EFM32_LFRCO_FREQ;
break;
case CMU_STATUS_HFXOSEL:
#if (EFM32_HFXO_FREQ > 0)
ret = SystemHFXOClock;
#else
/* We should not get here, since core should not be clocked. May */
/* be caused by a misconfiguration though. */
ret = 0;
#endif
break;
default: /* CMU_STATUS_HFRCOSEL */
switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
{
case CMU_HFRCOCTRL_BAND_28MHZ:
ret = 28000000;
break;
case CMU_HFRCOCTRL_BAND_21MHZ:
ret = 21000000;
break;
case CMU_HFRCOCTRL_BAND_14MHZ:
ret = 14000000;
break;
case CMU_HFRCOCTRL_BAND_11MHZ:
ret = 11000000;
break;
case CMU_HFRCOCTRL_BAND_7MHZ:
if ( GetProdRev() >= 19 )
ret = 6600000;
else
ret = 7000000;
break;
case CMU_HFRCOCTRL_BAND_1MHZ:
if ( GetProdRev() >= 19 )
ret = 1200000;
else
ret = 1000000;
break;
default:
ret = 0;
break;
}
break;
}
return ret;
}
/**************************************************************************//**
* @brief
* Get high frequency crystal oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* HFXO frequency in Hz.
*****************************************************************************/
uint32_t SystemHFXOClockGet(void)
{
/* External crystal oscillator present? */
#if (EFM32_HFXO_FREQ > 0)
return SystemHFXOClock;
#else
return 0;
#endif
}
/**************************************************************************//**
* @brief
* Set high frequency crystal oscillator clock frequency for target system.
*
* @note
* This function is mainly provided for being able to handle target systems
* with different HF crystal oscillator frequencies run-time. If used, it
* should probably only be used once during system startup.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @param[in] freq
* HFXO frequency in Hz used for target.
*****************************************************************************/
void SystemHFXOClockSet(uint32_t freq)
{
/* External crystal oscillator present? */
#if (EFM32_HFXO_FREQ > 0)
SystemHFXOClock = freq;
/* Update core clock frequency if HFXO is used to clock core */
if (CMU->STATUS & CMU_STATUS_HFXOSEL)
{
/* The function will update the global variable */
SystemCoreClockGet();
}
#else
(void)freq; /* Unused parameter */
#endif
}
/**************************************************************************//**
* @brief
* Initialize the system.
*
* @details
* Do required generic HW system init.
*
* @note
* This function is invoked during system init, before the main() routine
* and any data has been initialized. For this reason, it cannot do any
* initialization of variables etc.
*****************************************************************************/
void SystemInit(void)
{
/* Set floating point coprosessor access mode. */
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
}
/**************************************************************************//**
* @brief
* Get low frequency RC oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* LFRCO frequency in Hz.
*****************************************************************************/
uint32_t SystemLFRCOClockGet(void)
{
/* Currently we assume that this frequency is properly tuned during */
/* manufacturing and is not changed after reset. If future requirements */
/* for re-tuning by user, we can add support for that. */
return EFM32_LFRCO_FREQ;
}
/**************************************************************************//**
* @brief
* Get ultra low frequency RC oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* ULFRCO frequency in Hz.
*****************************************************************************/
uint32_t SystemULFRCOClockGet(void)
{
/* The ULFRCO frequency is not tuned, and can be very inaccurate */
return EFM32_ULFRCO_FREQ;
}
/**************************************************************************//**
* @brief
* Get low frequency crystal oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* LFXO frequency in Hz.
*****************************************************************************/
uint32_t SystemLFXOClockGet(void)
{
/* External crystal oscillator present? */
#if (EFM32_LFXO_FREQ > 0)
return SystemLFXOClock;
#else
return 0;
#endif
}
/**************************************************************************//**
* @brief
* Set low frequency crystal oscillator clock frequency for target system.
*
* @note
* This function is mainly provided for being able to handle target systems
* with different HF crystal oscillator frequencies run-time. If used, it
* should probably only be used once during system startup.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @param[in] freq
* LFXO frequency in Hz used for target.
*****************************************************************************/
void SystemLFXOClockSet(uint32_t freq)
{
/* External crystal oscillator present? */
#if (EFM32_LFXO_FREQ > 0)
SystemLFXOClock = freq;
/* Update core clock frequency if LFXO is used to clock core */
if (CMU->STATUS & CMU_STATUS_LFXOSEL)
{
/* The function will update the global variable */
SystemCoreClockGet();
}
#else
(void)freq; /* Unused parameter */
#endif
}

486
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Include/efm32wg990f256.h Normal file
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/**************************************************************************//**
* @file efm32wg990f256.h
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFM32WG990F256
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#ifndef __SILICON_LABS_EFM32WG990F256_H__
#define __SILICON_LABS_EFM32WG990F256_H__
#ifdef __cplusplus
extern "C" {
#endif
/**************************************************************************//**
* @addtogroup Parts
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG990F256 EFM32WG990F256
* @{
*****************************************************************************/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M4 Processor Exceptions Numbers *******************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** EFM32WG Peripheral Interrupt Numbers *********************************************/
DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */
ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */
ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */
DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */
I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */
I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */
GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */
TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */
TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */
TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */
USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */
USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */
LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */
USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */
USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */
UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */
UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */
UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */
UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */
LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */
LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */
LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */
PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */
PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */
RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */
BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */
CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */
VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */
LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */
MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */
AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */
EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */
EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */
FPUEH_IRQn = 39, /*!< 16+39 EFM32 FPUEH Interrupt */
} IRQn_Type;
/**************************************************************************//**
* @defgroup EFM32WG990F256_Core EFM32WG990F256 Core
* @{
* @brief Processor and Core Peripheral Section
*****************************************************************************/
#define __MPU_PRESENT 1 /**< Presence of MPU */
#define __FPU_PRESENT 1 /**< Presence of FPU */
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
/** @} End of group EFM32WG990F256_Core */
/**************************************************************************//**
* @defgroup EFM32WG990F256_Part EFM32WG990F256 Part
* @{
******************************************************************************/
/** Part family */
#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
/* If part number is not defined as compiler option, define it */
#if !defined(EFM32WG990F256)
#define EFM32WG990F256 1 /**< Wonder Gecko Part */
#endif
/** Configure part number */
#define PART_NUMBER "EFM32WG990F256" /**< Part Number */
/** Memory Base addresses and limits */
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
/** Bit banding area */
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
/** Flash and SRAM limits for EFM32WG990F256 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
/** AF channels connect the different on-chip peripherals with the af-mux */
#define AFCHAN_MAX 163
#define AFCHANLOC_MAX 7
/** Analog AF channels */
#define AFACHAN_MAX 53
/* Part number capabilities */
#define USART_PRESENT /**< USART is available in this part */
#define USART_COUNT 3 /**< 3 USARTs available */
#define UART_PRESENT /**< UART is available in this part */
#define UART_COUNT 2 /**< 2 UARTs available */
#define TIMER_PRESENT /**< TIMER is available in this part */
#define TIMER_COUNT 4 /**< 4 TIMERs available */
#define ACMP_PRESENT /**< ACMP is available in this part */
#define ACMP_COUNT 2 /**< 2 ACMPs available */
#define LEUART_PRESENT /**< LEUART is available in this part */
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
#define LETIMER_PRESENT /**< LETIMER is available in this part */
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
#define PCNT_PRESENT /**< PCNT is available in this part */
#define PCNT_COUNT 3 /**< 3 PCNTs available */
#define I2C_PRESENT /**< I2C is available in this part */
#define I2C_COUNT 2 /**< 2 I2Cs available */
#define ADC_PRESENT /**< ADC is available in this part */
#define ADC_COUNT 1 /**< 1 ADCs available */
#define DAC_PRESENT /**< DAC is available in this part */
#define DAC_COUNT 1 /**< 1 DACs available */
#define DMA_PRESENT
#define DMA_COUNT 1
#define AES_PRESENT
#define AES_COUNT 1
#define USBC_PRESENT
#define USBC_COUNT 1
#define USB_PRESENT
#define USB_COUNT 1
#define LE_PRESENT
#define LE_COUNT 1
#define MSC_PRESENT
#define MSC_COUNT 1
#define EMU_PRESENT
#define EMU_COUNT 1
#define RMU_PRESENT
#define RMU_COUNT 1
#define CMU_PRESENT
#define CMU_COUNT 1
#define LESENSE_PRESENT
#define LESENSE_COUNT 1
#define EBI_PRESENT
#define EBI_COUNT 1
#define FPUEH_PRESENT
#define FPUEH_COUNT 1
#define RTC_PRESENT
#define RTC_COUNT 1
#define GPIO_PRESENT
#define GPIO_COUNT 1
#define VCMP_PRESENT
#define VCMP_COUNT 1
#define PRS_PRESENT
#define PRS_COUNT 1
#define OPAMP_PRESENT
#define OPAMP_COUNT 1
#define BU_PRESENT
#define BU_COUNT 1
#define LCD_PRESENT
#define LCD_COUNT 1
#define BURTC_PRESENT
#define BURTC_COUNT 1
#define HFXTAL_PRESENT
#define HFXTAL_COUNT 1
#define LFXTAL_PRESENT
#define LFXTAL_COUNT 1
#define WDOG_PRESENT
#define WDOG_COUNT 1
#define DBG_PRESENT
#define DBG_COUNT 1
#define ETM_PRESENT
#define ETM_COUNT 1
#define BOOTLOADER_PRESENT
#define BOOTLOADER_COUNT 1
#define ANALOG_PRESENT
#define ANALOG_COUNT 1
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_efm32wg.h" /* System Header */
/** @} End of group EFM32WG990F256_Part */
/**************************************************************************//**
* @defgroup EFM32WG990F256_Peripheral_TypeDefs EFM32WG990F256 Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
*****************************************************************************/
#include "efm32wg_dma_ch.h"
#include "efm32wg_dma.h"
#include "efm32wg_aes.h"
#include "efm32wg_usb_hc.h"
#include "efm32wg_usb_diep.h"
#include "efm32wg_usb_doep.h"
#include "efm32wg_usb.h"
#include "efm32wg_msc.h"
#include "efm32wg_emu.h"
#include "efm32wg_rmu.h"
#include "efm32wg_cmu.h"
#include "efm32wg_lesense_st.h"
#include "efm32wg_lesense_buf.h"
#include "efm32wg_lesense_ch.h"
#include "efm32wg_lesense.h"
#include "efm32wg_ebi.h"
#include "efm32wg_fpueh.h"
#include "efm32wg_usart.h"
#include "efm32wg_timer_cc.h"
#include "efm32wg_timer.h"
#include "efm32wg_acmp.h"
#include "efm32wg_leuart.h"
#include "efm32wg_rtc.h"
#include "efm32wg_letimer.h"
#include "efm32wg_pcnt.h"
#include "efm32wg_i2c.h"
#include "efm32wg_gpio_p.h"
#include "efm32wg_gpio.h"
#include "efm32wg_vcmp.h"
#include "efm32wg_prs_ch.h"
#include "efm32wg_prs.h"
#include "efm32wg_adc.h"
#include "efm32wg_dac.h"
#include "efm32wg_lcd.h"
#include "efm32wg_burtc_ret.h"
#include "efm32wg_burtc.h"
#include "efm32wg_wdog.h"
#include "efm32wg_etm.h"
#include "efm32wg_dma_descriptor.h"
#include "efm32wg_devinfo.h"
#include "efm32wg_romtable.h"
#include "efm32wg_calibrate.h"
/** @} End of group EFM32WG990F256_Peripheral_TypeDefs */
/**************************************************************************//**
* @defgroup EFM32WG990F256_Peripheral_Base EFM32WG990F256 Peripheral Memory Map
* @{
*****************************************************************************/
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
#define AES_BASE (0x400E0000UL) /**< AES base address */
#define USB_BASE (0x400C4000UL) /**< USB base address */
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
#define EBI_BASE (0x40008000UL) /**< EBI base address */
#define FPUEH_BASE (0x400C1C00UL) /**< FPUEH base address */
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
#define RTC_BASE (0x40080000UL) /**< RTC base address */
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
/** @} End of group EFM32WG990F256_Peripheral_Base */
/**************************************************************************//**
* @defgroup EFM32WG990F256_Peripheral_Declaration EFM32WG990F256 Peripheral Declarations
* @{
*****************************************************************************/
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
/** @} End of group EFM32WG990F256_Peripheral_Declaration */
/**************************************************************************//**
* @defgroup EFM32WG990F256_BitFields EFM32WG990F256 Bit Fields
* @{
*****************************************************************************/
#include "efm32wg_prs_signals.h"
#include "efm32wg_dmareq.h"
#include "efm32wg_dmactrl.h"
#include "efm32wg_uart.h"
/**************************************************************************//**
* @defgroup EFM32WG990F256_UNLOCK EFM32WG990F256 Unlock Codes
* @{
*****************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
/** @} End of group EFM32WG990F256_UNLOCK */
/** @} End of group EFM32WG990F256_BitFields */
/**************************************************************************//**
* @defgroup EFM32WG990F256_Alternate_Function EFM32WG990F256 Alternate Function
* @{
*****************************************************************************/
#include "efm32wg_af_ports.h"
#include "efm32wg_af_pins.h"
/** @} End of group EFM32WG990F256_Alternate_Function */
/**************************************************************************//**
* @brief Set the value of a bit field within a register.
*
* @param REG
* The register to update
* @param MASK
* The mask for the bit field to update
* @param VALUE
* The value to write to the bit field
* @param OFFSET
* The number of bits that the field is offset within the register.
* 0 (zero) means LSB.
*****************************************************************************/
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
/** @} End of group EFM32WG990F256 */
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
#endif /* __SILICON_LABS_EFM32WG990F256_H__ */

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FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Include/efm32wg_acmp.h Normal file
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/**************************************************************************//**
* @file efm32wg_acmp.h
* @brief EFM32WG_ACMP register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_ACMP
* @{
* @brief EFM32WG_ACMP Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t INPUTSEL; /**< Input Selection Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t ROUTE; /**< I/O Routing Register */
} ACMP_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_ACMP_BitFields
* @{
*****************************************************************************/
/* Bit fields for ACMP CTRL */
#define _ACMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for ACMP_CTRL */
#define _ACMP_CTRL_MASK 0xCF03077FUL /**< Mask for ACMP_CTRL */
#define ACMP_CTRL_EN (0x1UL << 0) /**< Analog Comparator Enable */
#define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */
#define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */
#define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_MUXEN (0x1UL << 1) /**< Input Mux Enable */
#define _ACMP_CTRL_MUXEN_SHIFT 1 /**< Shift value for ACMP_MUXEN */
#define _ACMP_CTRL_MUXEN_MASK 0x2UL /**< Bit mask for ACMP_MUXEN */
#define _ACMP_CTRL_MUXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_MUXEN_DEFAULT (_ACMP_CTRL_MUXEN_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */
#define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */
#define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */
#define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
#define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */
#define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */
#define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /**< Shifted mode LOW for ACMP_CTRL */
#define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /**< Shifted mode HIGH for ACMP_CTRL */
#define ACMP_CTRL_GPIOINV (0x1UL << 3) /**< Comparator GPIO Output Invert */
#define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */
#define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */
#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */
#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */
#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /**< Shifted mode NOTINV for ACMP_CTRL */
#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /**< Shifted mode INV for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_SHIFT 4 /**< Shift value for ACMP_HYSTSEL */
#define _ACMP_CTRL_HYSTSEL_MASK 0x70UL /**< Bit mask for ACMP_HYSTSEL */
#define _ACMP_CTRL_HYSTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_DEFAULT (_ACMP_CTRL_HYSTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST0 (_ACMP_CTRL_HYSTSEL_HYST0 << 4) /**< Shifted mode HYST0 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST1 (_ACMP_CTRL_HYSTSEL_HYST1 << 4) /**< Shifted mode HYST1 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST2 (_ACMP_CTRL_HYSTSEL_HYST2 << 4) /**< Shifted mode HYST2 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST3 (_ACMP_CTRL_HYSTSEL_HYST3 << 4) /**< Shifted mode HYST3 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST4 (_ACMP_CTRL_HYSTSEL_HYST4 << 4) /**< Shifted mode HYST4 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST5 (_ACMP_CTRL_HYSTSEL_HYST5 << 4) /**< Shifted mode HYST5 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST6 (_ACMP_CTRL_HYSTSEL_HYST6 << 4) /**< Shifted mode HYST6 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST7 (_ACMP_CTRL_HYSTSEL_HYST7 << 4) /**< Shifted mode HYST7 for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for ACMP_WARMTIME */
#define _ACMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for ACMP_WARMTIME */
#define _ACMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_DEFAULT (_ACMP_CTRL_WARMTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_4CYCLES (_ACMP_CTRL_WARMTIME_4CYCLES << 8) /**< Shifted mode 4CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_8CYCLES (_ACMP_CTRL_WARMTIME_8CYCLES << 8) /**< Shifted mode 8CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_16CYCLES (_ACMP_CTRL_WARMTIME_16CYCLES << 8) /**< Shifted mode 16CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_32CYCLES (_ACMP_CTRL_WARMTIME_32CYCLES << 8) /**< Shifted mode 32CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_64CYCLES (_ACMP_CTRL_WARMTIME_64CYCLES << 8) /**< Shifted mode 64CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_128CYCLES (_ACMP_CTRL_WARMTIME_128CYCLES << 8) /**< Shifted mode 128CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_256CYCLES (_ACMP_CTRL_WARMTIME_256CYCLES << 8) /**< Shifted mode 256CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_512CYCLES (_ACMP_CTRL_WARMTIME_512CYCLES << 8) /**< Shifted mode 512CYCLES for ACMP_CTRL */
#define ACMP_CTRL_IRISE (0x1UL << 16) /**< Rising Edge Interrupt Sense */
#define _ACMP_CTRL_IRISE_SHIFT 16 /**< Shift value for ACMP_IRISE */
#define _ACMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for ACMP_IRISE */
#define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
#define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */
#define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */
#define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 16) /**< Shifted mode DISABLED for ACMP_CTRL */
#define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 16) /**< Shifted mode ENABLED for ACMP_CTRL */
#define ACMP_CTRL_IFALL (0x1UL << 17) /**< Falling Edge Interrupt Sense */
#define _ACMP_CTRL_IFALL_SHIFT 17 /**< Shift value for ACMP_IFALL */
#define _ACMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for ACMP_IFALL */
#define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
#define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */
#define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */
#define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 17) /**< Shifted mode DISABLED for ACMP_CTRL */
#define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 17) /**< Shifted mode ENABLED for ACMP_CTRL */
#define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */
#define _ACMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for ACMP_BIASPROG */
#define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_HALFBIAS (0x1UL << 30) /**< Half Bias Current */
#define _ACMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for ACMP_HALFBIAS */
#define _ACMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for ACMP_HALFBIAS */
#define _ACMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_HALFBIAS_DEFAULT (_ACMP_CTRL_HALFBIAS_DEFAULT << 30) /**< Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_FULLBIAS (0x1UL << 31) /**< Full Bias Current */
#define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */
#define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */
#define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */
/* Bit fields for ACMP INPUTSEL */
#define _ACMP_INPUTSEL_RESETVALUE 0x00010080UL /**< Default value for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_MASK 0x31013FF7UL /**< Mask for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */
#define _ACMP_INPUTSEL_POSSEL_MASK 0x7UL /**< Bit mask for ACMP_POSSEL */
#define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH0 0x00000000UL /**< Mode CH0 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH1 0x00000001UL /**< Mode CH1 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH2 0x00000002UL /**< Mode CH2 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH3 0x00000003UL /**< Mode CH3 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH4 0x00000004UL /**< Mode CH4 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH5 0x00000005UL /**< Mode CH5 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH6 0x00000006UL /**< Mode CH6 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH7 0x00000007UL /**< Mode CH7 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH0 (_ACMP_INPUTSEL_POSSEL_CH0 << 0) /**< Shifted mode CH0 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH1 (_ACMP_INPUTSEL_POSSEL_CH1 << 0) /**< Shifted mode CH1 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH2 (_ACMP_INPUTSEL_POSSEL_CH2 << 0) /**< Shifted mode CH2 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH3 (_ACMP_INPUTSEL_POSSEL_CH3 << 0) /**< Shifted mode CH3 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH4 (_ACMP_INPUTSEL_POSSEL_CH4 << 0) /**< Shifted mode CH4 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH5 (_ACMP_INPUTSEL_POSSEL_CH5 << 0) /**< Shifted mode CH5 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH6 (_ACMP_INPUTSEL_POSSEL_CH6 << 0) /**< Shifted mode CH6 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH7 (_ACMP_INPUTSEL_POSSEL_CH7 << 0) /**< Shifted mode CH7 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_SHIFT 4 /**< Shift value for ACMP_NEGSEL */
#define _ACMP_INPUTSEL_NEGSEL_MASK 0xF0UL /**< Bit mask for ACMP_NEGSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH0 0x00000000UL /**< Mode CH0 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH1 0x00000001UL /**< Mode CH1 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH2 0x00000002UL /**< Mode CH2 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH3 0x00000003UL /**< Mode CH3 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH4 0x00000004UL /**< Mode CH4 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH5 0x00000005UL /**< Mode CH5 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH6 0x00000006UL /**< Mode CH6 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH7 0x00000007UL /**< Mode CH7 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000008UL /**< Mode DEFAULT for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_1V25 0x00000008UL /**< Mode 1V25 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_2V5 0x00000009UL /**< Mode 2V5 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_VDD 0x0000000AUL /**< Mode VDD for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CAPSENSE 0x0000000BUL /**< Mode CAPSENSE for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_DAC0CH0 0x0000000CUL /**< Mode DAC0CH0 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_DAC0CH1 0x0000000DUL /**< Mode DAC0CH1 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH0 (_ACMP_INPUTSEL_NEGSEL_CH0 << 4) /**< Shifted mode CH0 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH1 (_ACMP_INPUTSEL_NEGSEL_CH1 << 4) /**< Shifted mode CH1 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH2 (_ACMP_INPUTSEL_NEGSEL_CH2 << 4) /**< Shifted mode CH2 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH3 (_ACMP_INPUTSEL_NEGSEL_CH3 << 4) /**< Shifted mode CH3 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH4 (_ACMP_INPUTSEL_NEGSEL_CH4 << 4) /**< Shifted mode CH4 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH5 (_ACMP_INPUTSEL_NEGSEL_CH5 << 4) /**< Shifted mode CH5 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH6 (_ACMP_INPUTSEL_NEGSEL_CH6 << 4) /**< Shifted mode CH6 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH7 (_ACMP_INPUTSEL_NEGSEL_CH7 << 4) /**< Shifted mode CH7 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_1V25 (_ACMP_INPUTSEL_NEGSEL_1V25 << 4) /**< Shifted mode 1V25 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_2V5 (_ACMP_INPUTSEL_NEGSEL_2V5 << 4) /**< Shifted mode 2V5 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 4) /**< Shifted mode VDD for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CAPSENSE (_ACMP_INPUTSEL_NEGSEL_CAPSENSE << 4) /**< Shifted mode CAPSENSE for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_DAC0CH0 (_ACMP_INPUTSEL_NEGSEL_DAC0CH0 << 4) /**< Shifted mode DAC0CH0 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_DAC0CH1 (_ACMP_INPUTSEL_NEGSEL_DAC0CH1 << 4) /**< Shifted mode DAC0CH1 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_VDDLEVEL_SHIFT 8 /**< Shift value for ACMP_VDDLEVEL */
#define _ACMP_INPUTSEL_VDDLEVEL_MASK 0x3F00UL /**< Bit mask for ACMP_VDDLEVEL */
#define _ACMP_INPUTSEL_VDDLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_VDDLEVEL_DEFAULT (_ACMP_INPUTSEL_VDDLEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_LPREF (0x1UL << 16) /**< Low Power Reference Mode */
#define _ACMP_INPUTSEL_LPREF_SHIFT 16 /**< Shift value for ACMP_LPREF */
#define _ACMP_INPUTSEL_LPREF_MASK 0x10000UL /**< Bit mask for ACMP_LPREF */
#define _ACMP_INPUTSEL_LPREF_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_LPREF_DEFAULT (_ACMP_INPUTSEL_LPREF_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_CSRESEN (0x1UL << 24) /**< Capacitive Sense Mode Internal Resistor Enable */
#define _ACMP_INPUTSEL_CSRESEN_SHIFT 24 /**< Shift value for ACMP_CSRESEN */
#define _ACMP_INPUTSEL_CSRESEN_MASK 0x1000000UL /**< Bit mask for ACMP_CSRESEN */
#define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */
#define _ACMP_INPUTSEL_CSRESSEL_MASK 0x30000000UL /**< Bit mask for ACMP_CSRESSEL */
#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTSEL */
/* Bit fields for ACMP STATUS */
#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */
#define _ACMP_STATUS_MASK 0x00000003UL /**< Mask for ACMP_STATUS */
#define ACMP_STATUS_ACMPACT (0x1UL << 0) /**< Analog Comparator Active */
#define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */
#define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */
#define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
#define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */
#define ACMP_STATUS_ACMPOUT (0x1UL << 1) /**< Analog Comparator Output */
#define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */
#define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */
#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */
/* Bit fields for ACMP IEN */
#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */
#define _ACMP_IEN_MASK 0x00000003UL /**< Mask for ACMP_IEN */
#define ACMP_IEN_EDGE (0x1UL << 0) /**< Edge Trigger Interrupt Enable */
#define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
#define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
#define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
#define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */
#define ACMP_IEN_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Enable */
#define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
#define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
#define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
#define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */
/* Bit fields for ACMP IF */
#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */
#define _ACMP_IF_MASK 0x00000003UL /**< Mask for ACMP_IF */
#define ACMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */
#define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
#define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
#define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
#define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */
#define ACMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */
#define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
#define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
#define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
#define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */
/* Bit fields for ACMP IFS */
#define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */
#define _ACMP_IFS_MASK 0x00000003UL /**< Mask for ACMP_IFS */
#define ACMP_IFS_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Set */
#define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
#define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
#define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */
#define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFS */
#define ACMP_IFS_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Set */
#define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
#define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
#define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */
#define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFS */
/* Bit fields for ACMP IFC */
#define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */
#define _ACMP_IFC_MASK 0x00000003UL /**< Mask for ACMP_IFC */
#define ACMP_IFC_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Clear */
#define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
#define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
#define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */
#define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFC */
#define ACMP_IFC_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Clear */
#define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
#define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
#define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */
#define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFC */
/* Bit fields for ACMP ROUTE */
#define _ACMP_ROUTE_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTE */
#define _ACMP_ROUTE_MASK 0x00000701UL /**< Mask for ACMP_ROUTE */
#define ACMP_ROUTE_ACMPPEN (0x1UL << 0) /**< ACMP Output Pin Enable */
#define _ACMP_ROUTE_ACMPPEN_SHIFT 0 /**< Shift value for ACMP_ACMPPEN */
#define _ACMP_ROUTE_ACMPPEN_MASK 0x1UL /**< Bit mask for ACMP_ACMPPEN */
#define _ACMP_ROUTE_ACMPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTE */
#define ACMP_ROUTE_ACMPPEN_DEFAULT (_ACMP_ROUTE_ACMPPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTE */
#define _ACMP_ROUTE_LOCATION_SHIFT 8 /**< Shift value for ACMP_LOCATION */
#define _ACMP_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for ACMP_LOCATION */
#define _ACMP_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTE */
#define _ACMP_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTE */
#define _ACMP_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTE */
#define _ACMP_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTE */
#define ACMP_ROUTE_LOCATION_LOC0 (_ACMP_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for ACMP_ROUTE */
#define ACMP_ROUTE_LOCATION_DEFAULT (_ACMP_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_ROUTE */
#define ACMP_ROUTE_LOCATION_LOC1 (_ACMP_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for ACMP_ROUTE */
#define ACMP_ROUTE_LOCATION_LOC2 (_ACMP_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for ACMP_ROUTE */
/** @} End of group EFM32WG_ACMP */

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/**************************************************************************//**
* @file efm32wg_adc.h
* @brief EFM32WG_ADC register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_ADC
* @{
* @brief EFM32WG_ADC Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t CMD; /**< Command Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t SINGLECTRL; /**< Single Sample Control Register */
__IO uint32_t SCANCTRL; /**< Scan Control Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
__I uint32_t SINGLEDATA; /**< Single Conversion Result Data */
__I uint32_t SCANDATA; /**< Scan Conversion Result Data */
__I uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */
__I uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */
__IO uint32_t CAL; /**< Calibration Register */
uint32_t RESERVED0[1]; /**< Reserved for future use **/
__IO uint32_t BIASPROG; /**< Bias Programming Register */
} ADC_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_ADC_BitFields
* @{
*****************************************************************************/
/* Bit fields for ADC CTRL */
#define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */
#define _ADC_CTRL_MASK 0x0F7F7F3BUL /**< Mask for ADC_CTRL */
#define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */
#define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */
#define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
#define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */
#define _ADC_CTRL_WARMUPMODE_FASTBG 0x00000001UL /**< Mode FASTBG for ADC_CTRL */
#define _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM 0x00000002UL /**< Mode KEEPSCANREFWARM for ADC_CTRL */
#define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */
#define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */
#define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */
#define ADC_CTRL_WARMUPMODE_FASTBG (_ADC_CTRL_WARMUPMODE_FASTBG << 0) /**< Shifted mode FASTBG for ADC_CTRL */
#define ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM (_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM << 0) /**< Shifted mode KEEPSCANREFWARM for ADC_CTRL */
#define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */
#define ADC_CTRL_TAILGATE (0x1UL << 3) /**< Conversion Tailgating */
#define _ADC_CTRL_TAILGATE_SHIFT 3 /**< Shift value for ADC_TAILGATE */
#define _ADC_CTRL_TAILGATE_MASK 0x8UL /**< Bit mask for ADC_TAILGATE */
#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
#define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */
#define _ADC_CTRL_LPFMODE_SHIFT 4 /**< Shift value for ADC_LPFMODE */
#define _ADC_CTRL_LPFMODE_MASK 0x30UL /**< Bit mask for ADC_LPFMODE */
#define _ADC_CTRL_LPFMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
#define _ADC_CTRL_LPFMODE_BYPASS 0x00000000UL /**< Mode BYPASS for ADC_CTRL */
#define _ADC_CTRL_LPFMODE_DECAP 0x00000001UL /**< Mode DECAP for ADC_CTRL */
#define _ADC_CTRL_LPFMODE_RCFILT 0x00000002UL /**< Mode RCFILT for ADC_CTRL */
#define ADC_CTRL_LPFMODE_DEFAULT (_ADC_CTRL_LPFMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */
#define ADC_CTRL_LPFMODE_BYPASS (_ADC_CTRL_LPFMODE_BYPASS << 4) /**< Shifted mode BYPASS for ADC_CTRL */
#define ADC_CTRL_LPFMODE_DECAP (_ADC_CTRL_LPFMODE_DECAP << 4) /**< Shifted mode DECAP for ADC_CTRL */
#define ADC_CTRL_LPFMODE_RCFILT (_ADC_CTRL_LPFMODE_RCFILT << 4) /**< Shifted mode RCFILT for ADC_CTRL */
#define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */
#define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */
#define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
#define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */
#define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */
#define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */
#define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */
#define _ADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for ADC_TIMEBASE */
#define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */
#define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */
#define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */
#define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */
#define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
#define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */
#define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */
#define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */
#define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */
#define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */
#define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */
#define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */
#define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */
#define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */
#define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */
#define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */
#define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */
#define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */
#define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */
#define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */
#define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */
#define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */
#define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */
#define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */
#define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */
#define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */
#define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */
#define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */
#define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */
#define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */
/* Bit fields for ADC CMD */
#define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */
#define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */
#define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Conversion Start */
#define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */
#define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */
#define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
#define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */
#define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Conversion Stop */
#define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */
#define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */
#define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
#define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */
#define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */
#define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */
#define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */
#define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
#define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */
#define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */
#define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */
#define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */
#define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
#define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */
/* Bit fields for ADC STATUS */
#define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */
#define _ADC_STATUS_MASK 0x07031303UL /**< Mask for ADC_STATUS */
#define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Conversion Active */
#define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */
#define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */
#define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
#define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */
#define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */
#define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */
#define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */
#define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
#define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */
#define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Reference Warmed Up */
#define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */
#define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */
#define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
#define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */
#define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */
#define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */
#define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */
#define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
#define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */
#define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */
#define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */
#define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */
#define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
#define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */
#define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Sample Data Valid */
#define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */
#define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */
#define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
#define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */
#define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */
#define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */
#define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */
#define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
#define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */
#define _ADC_STATUS_SCANDATASRC_SHIFT 24 /**< Shift value for ADC_SCANDATASRC */
#define _ADC_STATUS_SCANDATASRC_MASK 0x7000000UL /**< Bit mask for ADC_SCANDATASRC */
#define _ADC_STATUS_SCANDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
#define _ADC_STATUS_SCANDATASRC_CH0 0x00000000UL /**< Mode CH0 for ADC_STATUS */
#define _ADC_STATUS_SCANDATASRC_CH1 0x00000001UL /**< Mode CH1 for ADC_STATUS */
#define _ADC_STATUS_SCANDATASRC_CH2 0x00000002UL /**< Mode CH2 for ADC_STATUS */
#define _ADC_STATUS_SCANDATASRC_CH3 0x00000003UL /**< Mode CH3 for ADC_STATUS */
#define _ADC_STATUS_SCANDATASRC_CH4 0x00000004UL /**< Mode CH4 for ADC_STATUS */
#define _ADC_STATUS_SCANDATASRC_CH5 0x00000005UL /**< Mode CH5 for ADC_STATUS */
#define _ADC_STATUS_SCANDATASRC_CH6 0x00000006UL /**< Mode CH6 for ADC_STATUS */
#define _ADC_STATUS_SCANDATASRC_CH7 0x00000007UL /**< Mode CH7 for ADC_STATUS */
#define ADC_STATUS_SCANDATASRC_DEFAULT (_ADC_STATUS_SCANDATASRC_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_STATUS */
#define ADC_STATUS_SCANDATASRC_CH0 (_ADC_STATUS_SCANDATASRC_CH0 << 24) /**< Shifted mode CH0 for ADC_STATUS */
#define ADC_STATUS_SCANDATASRC_CH1 (_ADC_STATUS_SCANDATASRC_CH1 << 24) /**< Shifted mode CH1 for ADC_STATUS */
#define ADC_STATUS_SCANDATASRC_CH2 (_ADC_STATUS_SCANDATASRC_CH2 << 24) /**< Shifted mode CH2 for ADC_STATUS */
#define ADC_STATUS_SCANDATASRC_CH3 (_ADC_STATUS_SCANDATASRC_CH3 << 24) /**< Shifted mode CH3 for ADC_STATUS */
#define ADC_STATUS_SCANDATASRC_CH4 (_ADC_STATUS_SCANDATASRC_CH4 << 24) /**< Shifted mode CH4 for ADC_STATUS */
#define ADC_STATUS_SCANDATASRC_CH5 (_ADC_STATUS_SCANDATASRC_CH5 << 24) /**< Shifted mode CH5 for ADC_STATUS */
#define ADC_STATUS_SCANDATASRC_CH6 (_ADC_STATUS_SCANDATASRC_CH6 << 24) /**< Shifted mode CH6 for ADC_STATUS */
#define ADC_STATUS_SCANDATASRC_CH7 (_ADC_STATUS_SCANDATASRC_CH7 << 24) /**< Shifted mode CH7 for ADC_STATUS */
/* Bit fields for ADC SINGLECTRL */
#define _ADC_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_MASK 0xF1F70F37UL /**< Mask for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Sample Repetitive Mode */
#define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
#define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
#define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Sample Differential Mode */
#define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
#define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
#define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Sample Result Adjustment */
#define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
#define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
#define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_RES_SHIFT 4 /**< Shift value for ADC_RES */
#define _ADC_SINGLECTRL_RES_MASK 0x30UL /**< Bit mask for ADC_RES */
#define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 4) /**< Shifted mode 12BIT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 4) /**< Shifted mode 8BIT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 4) /**< Shifted mode 6BIT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 4) /**< Shifted mode OVS for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_SHIFT 8 /**< Shift value for ADC_INPUTSEL */
#define _ADC_SINGLECTRL_INPUTSEL_MASK 0xF00UL /**< Bit mask for ADC_INPUTSEL */
#define _ADC_SINGLECTRL_INPUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL /**< Mode CH0 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH0CH1 0x00000000UL /**< Mode CH0CH1 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL /**< Mode CH1 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH2CH3 0x00000001UL /**< Mode CH2CH3 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL /**< Mode CH2 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH4CH5 0x00000002UL /**< Mode CH4CH5 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH6CH7 0x00000003UL /**< Mode CH6CH7 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH3 0x00000003UL /**< Mode CH3 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL /**< Mode CH4 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_DIFF0 0x00000004UL /**< Mode DIFF0 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH5 0x00000005UL /**< Mode CH5 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH6 0x00000006UL /**< Mode CH6 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_CH7 0x00000007UL /**< Mode CH7 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_TEMP 0x00000008UL /**< Mode TEMP for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_VDDDIV3 0x00000009UL /**< Mode VDDDIV3 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_VDD 0x0000000AUL /**< Mode VDD for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_VSS 0x0000000BUL /**< Mode VSS for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_VREFDIV2 0x0000000CUL /**< Mode VREFDIV2 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 0x0000000DUL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 0x0000000EUL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_DEFAULT (_ADC_SINGLECTRL_INPUTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8) /**< Shifted mode CH0 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH0CH1 (_ADC_SINGLECTRL_INPUTSEL_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8) /**< Shifted mode CH1 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH2CH3 (_ADC_SINGLECTRL_INPUTSEL_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8) /**< Shifted mode CH2 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH4CH5 (_ADC_SINGLECTRL_INPUTSEL_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH6CH7 (_ADC_SINGLECTRL_INPUTSEL_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH3 (_ADC_SINGLECTRL_INPUTSEL_CH3 << 8) /**< Shifted mode CH3 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8) /**< Shifted mode CH4 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_DIFF0 (_ADC_SINGLECTRL_INPUTSEL_DIFF0 << 8) /**< Shifted mode DIFF0 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH5 (_ADC_SINGLECTRL_INPUTSEL_CH5 << 8) /**< Shifted mode CH5 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH6 (_ADC_SINGLECTRL_INPUTSEL_CH6 << 8) /**< Shifted mode CH6 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_CH7 (_ADC_SINGLECTRL_INPUTSEL_CH7 << 8) /**< Shifted mode CH7 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_TEMP (_ADC_SINGLECTRL_INPUTSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_VDDDIV3 (_ADC_SINGLECTRL_INPUTSEL_VDDDIV3 << 8) /**< Shifted mode VDDDIV3 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_VDD (_ADC_SINGLECTRL_INPUTSEL_VDD << 8) /**< Shifted mode VDD for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_VSS (_ADC_SINGLECTRL_INPUTSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_VREFDIV2 (_ADC_SINGLECTRL_INPUTSEL_VREFDIV2 << 8) /**< Shifted mode VREFDIV2 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_REF_SHIFT 16 /**< Shift value for ADC_REF */
#define _ADC_SINGLECTRL_REF_MASK 0x70000UL /**< Bit mask for ADC_REF */
#define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 16) /**< Shifted mode 1V25 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 16) /**< Shifted mode 2V5 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 16) /**< Shifted mode VDD for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_REF_5VDIFF (_ADC_SINGLECTRL_REF_5VDIFF << 16) /**< Shifted mode 5VDIFF for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 16) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 16) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 16) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_AT_SHIFT 20 /**< Shift value for ADC_AT */
#define _ADC_SINGLECTRL_AT_MASK 0xF00000UL /**< Bit mask for ADC_AT */
#define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_AT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_AT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_AT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_AT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_AT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_AT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_AT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 20) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 20) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 20) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 20) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 20) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 20) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 20) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 20) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 20) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_PRSEN (0x1UL << 24) /**< Single Sample PRS Trigger Enable */
#define _ADC_SINGLECTRL_PRSEN_SHIFT 24 /**< Shift value for ADC_PRSEN */
#define _ADC_SINGLECTRL_PRSEN_MASK 0x1000000UL /**< Bit mask for ADC_PRSEN */
#define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_PRSSEL_SHIFT 28 /**< Shift value for ADC_PRSSEL */
#define _ADC_SINGLECTRL_PRSSEL_MASK 0xF0000000UL /**< Bit mask for ADC_PRSSEL */
#define _ADC_SINGLECTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_PRSSEL_DEFAULT (_ADC_SINGLECTRL_PRSSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_PRSSEL_PRSCH0 (_ADC_SINGLECTRL_PRSSEL_PRSCH0 << 28) /**< Shifted mode PRSCH0 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_PRSSEL_PRSCH1 (_ADC_SINGLECTRL_PRSSEL_PRSCH1 << 28) /**< Shifted mode PRSCH1 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_PRSSEL_PRSCH2 (_ADC_SINGLECTRL_PRSSEL_PRSCH2 << 28) /**< Shifted mode PRSCH2 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_PRSSEL_PRSCH3 (_ADC_SINGLECTRL_PRSSEL_PRSCH3 << 28) /**< Shifted mode PRSCH3 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_PRSSEL_PRSCH4 (_ADC_SINGLECTRL_PRSSEL_PRSCH4 << 28) /**< Shifted mode PRSCH4 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_PRSSEL_PRSCH5 (_ADC_SINGLECTRL_PRSSEL_PRSCH5 << 28) /**< Shifted mode PRSCH5 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_PRSSEL_PRSCH6 (_ADC_SINGLECTRL_PRSSEL_PRSCH6 << 28) /**< Shifted mode PRSCH6 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_PRSSEL_PRSCH7 (_ADC_SINGLECTRL_PRSSEL_PRSCH7 << 28) /**< Shifted mode PRSCH7 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_PRSSEL_PRSCH8 (_ADC_SINGLECTRL_PRSSEL_PRSCH8 << 28) /**< Shifted mode PRSCH8 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_PRSSEL_PRSCH9 (_ADC_SINGLECTRL_PRSSEL_PRSCH9 << 28) /**< Shifted mode PRSCH9 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_PRSSEL_PRSCH10 (_ADC_SINGLECTRL_PRSSEL_PRSCH10 << 28) /**< Shifted mode PRSCH10 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_PRSSEL_PRSCH11 (_ADC_SINGLECTRL_PRSSEL_PRSCH11 << 28) /**< Shifted mode PRSCH11 for ADC_SINGLECTRL */
/* Bit fields for ADC SCANCTRL */
#define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */
#define _ADC_SCANCTRL_MASK 0xF1F7FF37UL /**< Mask for ADC_SCANCTRL */
#define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */
#define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
#define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
#define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
#define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
#define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */
#define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
#define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
#define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
#define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
#define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */
#define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
#define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
#define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
#define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */
#define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */
#define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
#define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */
#define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */
#define _ADC_SCANCTRL_RES_SHIFT 4 /**< Shift value for ADC_RES */
#define _ADC_SCANCTRL_RES_MASK 0x30UL /**< Bit mask for ADC_RES */
#define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
#define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */
#define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */
#define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */
#define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */
#define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
#define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 4) /**< Shifted mode 12BIT for ADC_SCANCTRL */
#define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 4) /**< Shifted mode 8BIT for ADC_SCANCTRL */
#define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 4) /**< Shifted mode 6BIT for ADC_SCANCTRL */
#define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 4) /**< Shifted mode OVS for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_SHIFT 8 /**< Shift value for ADC_INPUTMASK */
#define _ADC_SCANCTRL_INPUTMASK_MASK 0xFF00UL /**< Bit mask for ADC_INPUTMASK */
#define _ADC_SCANCTRL_INPUTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL /**< Mode CH0 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH0CH1 0x00000001UL /**< Mode CH0CH1 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL /**< Mode CH1 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH2CH3 0x00000002UL /**< Mode CH2CH3 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL /**< Mode CH2 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH4CH5 0x00000004UL /**< Mode CH4CH5 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH6CH7 0x00000008UL /**< Mode CH6CH7 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH3 0x00000008UL /**< Mode CH3 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH4 0x00000010UL /**< Mode CH4 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH5 0x00000020UL /**< Mode CH5 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH6 0x00000040UL /**< Mode CH6 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_INPUTMASK_CH7 0x00000080UL /**< Mode CH7 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_DEFAULT (_ADC_SCANCTRL_INPUTMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8) /**< Shifted mode CH0 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH0CH1 (_ADC_SCANCTRL_INPUTMASK_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8) /**< Shifted mode CH1 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH2CH3 (_ADC_SCANCTRL_INPUTMASK_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8) /**< Shifted mode CH2 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH4CH5 (_ADC_SCANCTRL_INPUTMASK_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH6CH7 (_ADC_SCANCTRL_INPUTMASK_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH3 (_ADC_SCANCTRL_INPUTMASK_CH3 << 8) /**< Shifted mode CH3 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH4 (_ADC_SCANCTRL_INPUTMASK_CH4 << 8) /**< Shifted mode CH4 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH5 (_ADC_SCANCTRL_INPUTMASK_CH5 << 8) /**< Shifted mode CH5 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH6 (_ADC_SCANCTRL_INPUTMASK_CH6 << 8) /**< Shifted mode CH6 for ADC_SCANCTRL */
#define ADC_SCANCTRL_INPUTMASK_CH7 (_ADC_SCANCTRL_INPUTMASK_CH7 << 8) /**< Shifted mode CH7 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_REF_SHIFT 16 /**< Shift value for ADC_REF */
#define _ADC_SCANCTRL_REF_MASK 0x70000UL /**< Bit mask for ADC_REF */
#define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
#define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */
#define _ADC_SCANCTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SCANCTRL */
#define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */
#define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */
#define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */
#define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
#define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 16) /**< Shifted mode 1V25 for ADC_SCANCTRL */
#define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 16) /**< Shifted mode 2V5 for ADC_SCANCTRL */
#define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 16) /**< Shifted mode VDD for ADC_SCANCTRL */
#define ADC_SCANCTRL_REF_5VDIFF (_ADC_SCANCTRL_REF_5VDIFF << 16) /**< Shifted mode 5VDIFF for ADC_SCANCTRL */
#define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 16) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */
#define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 16) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */
#define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 16) /**< Shifted mode 2XVDD for ADC_SCANCTRL */
#define _ADC_SCANCTRL_AT_SHIFT 20 /**< Shift value for ADC_AT */
#define _ADC_SCANCTRL_AT_MASK 0xF00000UL /**< Bit mask for ADC_AT */
#define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
#define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */
#define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */
#define _ADC_SCANCTRL_AT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SCANCTRL */
#define _ADC_SCANCTRL_AT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SCANCTRL */
#define _ADC_SCANCTRL_AT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SCANCTRL */
#define _ADC_SCANCTRL_AT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SCANCTRL */
#define _ADC_SCANCTRL_AT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SCANCTRL */
#define _ADC_SCANCTRL_AT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SCANCTRL */
#define _ADC_SCANCTRL_AT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SCANCTRL */
#define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
#define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 20) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */
#define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 20) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */
#define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 20) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */
#define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 20) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */
#define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 20) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */
#define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 20) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */
#define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 20) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */
#define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 20) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */
#define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 20) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */
#define ADC_SCANCTRL_PRSEN (0x1UL << 24) /**< Scan Sequence PRS Trigger Enable */
#define _ADC_SCANCTRL_PRSEN_SHIFT 24 /**< Shift value for ADC_PRSEN */
#define _ADC_SCANCTRL_PRSEN_MASK 0x1000000UL /**< Bit mask for ADC_PRSEN */
#define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
#define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
#define _ADC_SCANCTRL_PRSSEL_SHIFT 28 /**< Shift value for ADC_PRSSEL */
#define _ADC_SCANCTRL_PRSSEL_MASK 0xF0000000UL /**< Bit mask for ADC_PRSSEL */
#define _ADC_SCANCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
#define _ADC_SCANCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SCANCTRL */
#define _ADC_SCANCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SCANCTRL */
#define ADC_SCANCTRL_PRSSEL_DEFAULT (_ADC_SCANCTRL_PRSSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
#define ADC_SCANCTRL_PRSSEL_PRSCH0 (_ADC_SCANCTRL_PRSSEL_PRSCH0 << 28) /**< Shifted mode PRSCH0 for ADC_SCANCTRL */
#define ADC_SCANCTRL_PRSSEL_PRSCH1 (_ADC_SCANCTRL_PRSSEL_PRSCH1 << 28) /**< Shifted mode PRSCH1 for ADC_SCANCTRL */
#define ADC_SCANCTRL_PRSSEL_PRSCH2 (_ADC_SCANCTRL_PRSSEL_PRSCH2 << 28) /**< Shifted mode PRSCH2 for ADC_SCANCTRL */
#define ADC_SCANCTRL_PRSSEL_PRSCH3 (_ADC_SCANCTRL_PRSSEL_PRSCH3 << 28) /**< Shifted mode PRSCH3 for ADC_SCANCTRL */
#define ADC_SCANCTRL_PRSSEL_PRSCH4 (_ADC_SCANCTRL_PRSSEL_PRSCH4 << 28) /**< Shifted mode PRSCH4 for ADC_SCANCTRL */
#define ADC_SCANCTRL_PRSSEL_PRSCH5 (_ADC_SCANCTRL_PRSSEL_PRSCH5 << 28) /**< Shifted mode PRSCH5 for ADC_SCANCTRL */
#define ADC_SCANCTRL_PRSSEL_PRSCH6 (_ADC_SCANCTRL_PRSSEL_PRSCH6 << 28) /**< Shifted mode PRSCH6 for ADC_SCANCTRL */
#define ADC_SCANCTRL_PRSSEL_PRSCH7 (_ADC_SCANCTRL_PRSSEL_PRSCH7 << 28) /**< Shifted mode PRSCH7 for ADC_SCANCTRL */
#define ADC_SCANCTRL_PRSSEL_PRSCH8 (_ADC_SCANCTRL_PRSSEL_PRSCH8 << 28) /**< Shifted mode PRSCH8 for ADC_SCANCTRL */
#define ADC_SCANCTRL_PRSSEL_PRSCH9 (_ADC_SCANCTRL_PRSSEL_PRSCH9 << 28) /**< Shifted mode PRSCH9 for ADC_SCANCTRL */
#define ADC_SCANCTRL_PRSSEL_PRSCH10 (_ADC_SCANCTRL_PRSSEL_PRSCH10 << 28) /**< Shifted mode PRSCH10 for ADC_SCANCTRL */
#define ADC_SCANCTRL_PRSSEL_PRSCH11 (_ADC_SCANCTRL_PRSSEL_PRSCH11 << 28) /**< Shifted mode PRSCH11 for ADC_SCANCTRL */
/* Bit fields for ADC IEN */
#define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */
#define _ADC_IEN_MASK 0x00000303UL /**< Mask for ADC_IEN */
#define ADC_IEN_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Enable */
#define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
#define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
#define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
#define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */
#define ADC_IEN_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Enable */
#define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
#define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
#define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
#define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */
#define ADC_IEN_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Enable */
#define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
#define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
#define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
#define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */
#define ADC_IEN_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Enable */
#define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
#define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
#define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
#define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */
/* Bit fields for ADC IF */
#define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */
#define _ADC_IF_MASK 0x00000303UL /**< Mask for ADC_IF */
#define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */
#define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
#define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
#define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
#define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */
#define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */
#define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
#define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
#define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
#define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */
#define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag */
#define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
#define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
#define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
#define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */
#define ADC_IF_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag */
#define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
#define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
#define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
#define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */
/* Bit fields for ADC IFS */
#define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */
#define _ADC_IFS_MASK 0x00000303UL /**< Mask for ADC_IFS */
#define ADC_IFS_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag Set */
#define _ADC_IFS_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
#define _ADC_IFS_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
#define _ADC_IFS_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
#define ADC_IFS_SINGLE_DEFAULT (_ADC_IFS_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IFS */
#define ADC_IFS_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag Set */
#define _ADC_IFS_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
#define _ADC_IFS_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
#define _ADC_IFS_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
#define ADC_IFS_SCAN_DEFAULT (_ADC_IFS_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IFS */
#define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag Set */
#define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
#define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
#define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
#define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */
#define ADC_IFS_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag Set */
#define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
#define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
#define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
#define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */
/* Bit fields for ADC IFC */
#define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */
#define _ADC_IFC_MASK 0x00000303UL /**< Mask for ADC_IFC */
#define ADC_IFC_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag Clear */
#define _ADC_IFC_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
#define _ADC_IFC_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
#define _ADC_IFC_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
#define ADC_IFC_SINGLE_DEFAULT (_ADC_IFC_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IFC */
#define ADC_IFC_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag Clear */
#define _ADC_IFC_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
#define _ADC_IFC_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
#define _ADC_IFC_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
#define ADC_IFC_SCAN_DEFAULT (_ADC_IFC_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IFC */
#define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag Clear */
#define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
#define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
#define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
#define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */
#define ADC_IFC_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag Clear */
#define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
#define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
#define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
#define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */
/* Bit fields for ADC SINGLEDATA */
#define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */
#define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */
#define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
#define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
#define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */
#define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */
/* Bit fields for ADC SCANDATA */
#define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */
#define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */
#define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
#define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
#define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */
#define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */
/* Bit fields for ADC SINGLEDATAP */
#define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */
#define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */
#define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
#define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
#define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */
#define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */
/* Bit fields for ADC SCANDATAP */
#define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */
#define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */
#define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
#define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
#define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */
#define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */
/* Bit fields for ADC CAL */
#define _ADC_CAL_RESETVALUE 0x3F003F00UL /**< Default value for ADC_CAL */
#define _ADC_CAL_MASK 0x7F7F7F7FUL /**< Mask for ADC_CAL */
#define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */
#define _ADC_CAL_SINGLEOFFSET_MASK 0x7FUL /**< Bit mask for ADC_SINGLEOFFSET */
#define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
#define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */
#define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */
#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */
#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */
#define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */
#define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */
#define _ADC_CAL_SCANOFFSET_MASK 0x7F0000UL /**< Bit mask for ADC_SCANOFFSET */
#define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
#define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */
#define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */
#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */
#define _ADC_CAL_SCANGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */
#define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */
/* Bit fields for ADC BIASPROG */
#define _ADC_BIASPROG_RESETVALUE 0x00000747UL /**< Default value for ADC_BIASPROG */
#define _ADC_BIASPROG_MASK 0x00000F4FUL /**< Mask for ADC_BIASPROG */
#define _ADC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for ADC_BIASPROG */
#define _ADC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for ADC_BIASPROG */
#define _ADC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */
#define ADC_BIASPROG_BIASPROG_DEFAULT (_ADC_BIASPROG_BIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */
#define ADC_BIASPROG_HALFBIAS (0x1UL << 6) /**< Half Bias Current */
#define _ADC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for ADC_HALFBIAS */
#define _ADC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for ADC_HALFBIAS */
#define _ADC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_BIASPROG */
#define ADC_BIASPROG_HALFBIAS_DEFAULT (_ADC_BIASPROG_HALFBIAS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_BIASPROG */
#define _ADC_BIASPROG_COMPBIAS_SHIFT 8 /**< Shift value for ADC_COMPBIAS */
#define _ADC_BIASPROG_COMPBIAS_MASK 0xF00UL /**< Bit mask for ADC_COMPBIAS */
#define _ADC_BIASPROG_COMPBIAS_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */
#define ADC_BIASPROG_COMPBIAS_DEFAULT (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */
/** @} End of group EFM32WG_ADC */

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/**************************************************************************//**
* @file efm32wg_aes.h
* @brief EFM32WG_AES register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_AES
* @{
* @brief EFM32WG_AES Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t CMD; /**< Command Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t DATA; /**< DATA Register */
__IO uint32_t XORDATA; /**< XORDATA Register */
uint32_t RESERVED0[3]; /**< Reserved for future use **/
__IO uint32_t KEYLA; /**< KEY Low Register */
__IO uint32_t KEYLB; /**< KEY Low Register */
__IO uint32_t KEYLC; /**< KEY Low Register */
__IO uint32_t KEYLD; /**< KEY Low Register */
__IO uint32_t KEYHA; /**< KEY High Register */
__IO uint32_t KEYHB; /**< KEY High Register */
__IO uint32_t KEYHC; /**< KEY High Register */
__IO uint32_t KEYHD; /**< KEY High Register */
} AES_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_AES_BitFields
* @{
*****************************************************************************/
/* Bit fields for AES CTRL */
#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */
#define _AES_CTRL_MASK 0x00000077UL /**< Mask for AES_CTRL */
#define AES_CTRL_DECRYPT (0x1UL << 0) /**< Decryption/Encryption Mode */
#define _AES_CTRL_DECRYPT_SHIFT 0 /**< Shift value for AES_DECRYPT */
#define _AES_CTRL_DECRYPT_MASK 0x1UL /**< Bit mask for AES_DECRYPT */
#define _AES_CTRL_DECRYPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_DECRYPT_DEFAULT (_AES_CTRL_DECRYPT_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_AES256 (0x1UL << 1) /**< AES-256 Mode */
#define _AES_CTRL_AES256_SHIFT 1 /**< Shift value for AES_AES256 */
#define _AES_CTRL_AES256_MASK 0x2UL /**< Bit mask for AES_AES256 */
#define _AES_CTRL_AES256_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_AES256_DEFAULT (_AES_CTRL_AES256_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_KEYBUFEN (0x1UL << 2) /**< Key Buffer Enable */
#define _AES_CTRL_KEYBUFEN_SHIFT 2 /**< Shift value for AES_KEYBUFEN */
#define _AES_CTRL_KEYBUFEN_MASK 0x4UL /**< Bit mask for AES_KEYBUFEN */
#define _AES_CTRL_KEYBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_KEYBUFEN_DEFAULT (_AES_CTRL_KEYBUFEN_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_DATASTART (0x1UL << 4) /**< AES_DATA Write Start */
#define _AES_CTRL_DATASTART_SHIFT 4 /**< Shift value for AES_DATASTART */
#define _AES_CTRL_DATASTART_MASK 0x10UL /**< Bit mask for AES_DATASTART */
#define _AES_CTRL_DATASTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_DATASTART_DEFAULT (_AES_CTRL_DATASTART_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_XORSTART (0x1UL << 5) /**< AES_XORDATA Write Start */
#define _AES_CTRL_XORSTART_SHIFT 5 /**< Shift value for AES_XORSTART */
#define _AES_CTRL_XORSTART_MASK 0x20UL /**< Bit mask for AES_XORSTART */
#define _AES_CTRL_XORSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_XORSTART_DEFAULT (_AES_CTRL_XORSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_BYTEORDER (0x1UL << 6) /**< Configure byte order in data and key registers */
#define _AES_CTRL_BYTEORDER_SHIFT 6 /**< Shift value for AES_BYTEORDER */
#define _AES_CTRL_BYTEORDER_MASK 0x40UL /**< Bit mask for AES_BYTEORDER */
#define _AES_CTRL_BYTEORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_BYTEORDER_DEFAULT (_AES_CTRL_BYTEORDER_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_CTRL */
/* Bit fields for AES CMD */
#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */
#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */
#define AES_CMD_START (0x1UL << 0) /**< Encryption/Decryption Start */
#define _AES_CMD_START_SHIFT 0 /**< Shift value for AES_START */
#define _AES_CMD_START_MASK 0x1UL /**< Bit mask for AES_START */
#define _AES_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
#define AES_CMD_START_DEFAULT (_AES_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */
#define AES_CMD_STOP (0x1UL << 1) /**< Encryption/Decryption Stop */
#define _AES_CMD_STOP_SHIFT 1 /**< Shift value for AES_STOP */
#define _AES_CMD_STOP_MASK 0x2UL /**< Bit mask for AES_STOP */
#define _AES_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
#define AES_CMD_STOP_DEFAULT (_AES_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */
/* Bit fields for AES STATUS */
#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */
#define _AES_STATUS_MASK 0x00000001UL /**< Mask for AES_STATUS */
#define AES_STATUS_RUNNING (0x1UL << 0) /**< AES Running */
#define _AES_STATUS_RUNNING_SHIFT 0 /**< Shift value for AES_RUNNING */
#define _AES_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for AES_RUNNING */
#define _AES_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
#define AES_STATUS_RUNNING_DEFAULT (_AES_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */
/* Bit fields for AES IEN */
#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */
#define _AES_IEN_MASK 0x00000001UL /**< Mask for AES_IEN */
#define AES_IEN_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Enable */
#define _AES_IEN_DONE_SHIFT 0 /**< Shift value for AES_DONE */
#define _AES_IEN_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
#define _AES_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
#define AES_IEN_DONE_DEFAULT (_AES_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */
/* Bit fields for AES IF */
#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */
#define _AES_IF_MASK 0x00000001UL /**< Mask for AES_IF */
#define AES_IF_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag */
#define _AES_IF_DONE_SHIFT 0 /**< Shift value for AES_DONE */
#define _AES_IF_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
#define _AES_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
#define AES_IF_DONE_DEFAULT (_AES_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */
/* Bit fields for AES IFS */
#define _AES_IFS_RESETVALUE 0x00000000UL /**< Default value for AES_IFS */
#define _AES_IFS_MASK 0x00000001UL /**< Mask for AES_IFS */
#define AES_IFS_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Set */
#define _AES_IFS_DONE_SHIFT 0 /**< Shift value for AES_DONE */
#define _AES_IFS_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
#define _AES_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFS */
#define AES_IFS_DONE_DEFAULT (_AES_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFS */
/* Bit fields for AES IFC */
#define _AES_IFC_RESETVALUE 0x00000000UL /**< Default value for AES_IFC */
#define _AES_IFC_MASK 0x00000001UL /**< Mask for AES_IFC */
#define AES_IFC_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Clear */
#define _AES_IFC_DONE_SHIFT 0 /**< Shift value for AES_DONE */
#define _AES_IFC_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
#define _AES_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */
#define AES_IFC_DONE_DEFAULT (_AES_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFC */
/* Bit fields for AES DATA */
#define _AES_DATA_RESETVALUE 0x00000000UL /**< Default value for AES_DATA */
#define _AES_DATA_MASK 0xFFFFFFFFUL /**< Mask for AES_DATA */
#define _AES_DATA_DATA_SHIFT 0 /**< Shift value for AES_DATA */
#define _AES_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_DATA */
#define _AES_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_DATA */
#define AES_DATA_DATA_DEFAULT (_AES_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_DATA */
/* Bit fields for AES XORDATA */
#define _AES_XORDATA_RESETVALUE 0x00000000UL /**< Default value for AES_XORDATA */
#define _AES_XORDATA_MASK 0xFFFFFFFFUL /**< Mask for AES_XORDATA */
#define _AES_XORDATA_XORDATA_SHIFT 0 /**< Shift value for AES_XORDATA */
#define _AES_XORDATA_XORDATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_XORDATA */
#define _AES_XORDATA_XORDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_XORDATA */
#define AES_XORDATA_XORDATA_DEFAULT (_AES_XORDATA_XORDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_XORDATA */
/* Bit fields for AES KEYLA */
#define _AES_KEYLA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLA */
#define _AES_KEYLA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLA */
#define _AES_KEYLA_KEYLA_SHIFT 0 /**< Shift value for AES_KEYLA */
#define _AES_KEYLA_KEYLA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLA */
#define _AES_KEYLA_KEYLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLA */
#define AES_KEYLA_KEYLA_DEFAULT (_AES_KEYLA_KEYLA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLA */
/* Bit fields for AES KEYLB */
#define _AES_KEYLB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLB */
#define _AES_KEYLB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLB */
#define _AES_KEYLB_KEYLB_SHIFT 0 /**< Shift value for AES_KEYLB */
#define _AES_KEYLB_KEYLB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLB */
#define _AES_KEYLB_KEYLB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLB */
#define AES_KEYLB_KEYLB_DEFAULT (_AES_KEYLB_KEYLB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLB */
/* Bit fields for AES KEYLC */
#define _AES_KEYLC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLC */
#define _AES_KEYLC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLC */
#define _AES_KEYLC_KEYLC_SHIFT 0 /**< Shift value for AES_KEYLC */
#define _AES_KEYLC_KEYLC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLC */
#define _AES_KEYLC_KEYLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLC */
#define AES_KEYLC_KEYLC_DEFAULT (_AES_KEYLC_KEYLC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLC */
/* Bit fields for AES KEYLD */
#define _AES_KEYLD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLD */
#define _AES_KEYLD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLD */
#define _AES_KEYLD_KEYLD_SHIFT 0 /**< Shift value for AES_KEYLD */
#define _AES_KEYLD_KEYLD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLD */
#define _AES_KEYLD_KEYLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLD */
#define AES_KEYLD_KEYLD_DEFAULT (_AES_KEYLD_KEYLD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLD */
/* Bit fields for AES KEYHA */
#define _AES_KEYHA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHA */
#define _AES_KEYHA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHA */
#define _AES_KEYHA_KEYHA_SHIFT 0 /**< Shift value for AES_KEYHA */
#define _AES_KEYHA_KEYHA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHA */
#define _AES_KEYHA_KEYHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHA */
#define AES_KEYHA_KEYHA_DEFAULT (_AES_KEYHA_KEYHA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHA */
/* Bit fields for AES KEYHB */
#define _AES_KEYHB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHB */
#define _AES_KEYHB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHB */
#define _AES_KEYHB_KEYHB_SHIFT 0 /**< Shift value for AES_KEYHB */
#define _AES_KEYHB_KEYHB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHB */
#define _AES_KEYHB_KEYHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHB */
#define AES_KEYHB_KEYHB_DEFAULT (_AES_KEYHB_KEYHB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHB */
/* Bit fields for AES KEYHC */
#define _AES_KEYHC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHC */
#define _AES_KEYHC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHC */
#define _AES_KEYHC_KEYHC_SHIFT 0 /**< Shift value for AES_KEYHC */
#define _AES_KEYHC_KEYHC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHC */
#define _AES_KEYHC_KEYHC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHC */
#define AES_KEYHC_KEYHC_DEFAULT (_AES_KEYHC_KEYHC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHC */
/* Bit fields for AES KEYHD */
#define _AES_KEYHD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHD */
#define _AES_KEYHD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHD */
#define _AES_KEYHD_KEYHD_SHIFT 0 /**< Shift value for AES_KEYHD */
#define _AES_KEYHD_KEYHD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHD */
#define _AES_KEYHD_KEYHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHD */
#define AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHD */
/** @} End of group EFM32WG_AES */

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/**************************************************************************//**
* @file efm32wg_af_pins.h
* @brief EFM32WG_AF_PINS register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_AF_Pins
* @{
*****************************************************************************/
/** AF pin number for location number i */
#define AF_USB_VBUSEN_PIN(i) ((i) == 0 ? 5 : -1)
#define AF_USB_DMPU_PIN(i) ((i) == 0 ? 2 : -1)
#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : -1)
#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : -1)
#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1)
#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1)
#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1)
#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1)
#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1)
#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1)
#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1)
#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1)
#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1)
#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1)
#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1)
#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1)
#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1)
#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1)
#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1)
#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1)
#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1)
#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1)
#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1)
#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1)
#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1)
#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1)
#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 8 : (i) == 2 ? 8 : -1)
#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 9 : -1)
#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 10 : -1)
#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 11 : -1)
#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 12 : (i) == 2 ? 12 : -1)
#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 13 : (i) == 2 ? 13 : -1)
#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 14 : (i) == 2 ? 14 : -1)
#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 15 : (i) == 2 ? 15 : -1)
#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 15 : (i) == 2 ? 15 : -1)
#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1)
#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1)
#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1)
#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1)
#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 9 : -1)
#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 10 : -1)
#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 11 : -1)
#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 12 : (i) == 2 ? 12 : -1)
#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 11 : -1)
#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 4 : -1)
#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 5 : -1)
#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1)
#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1)
#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1)
#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1)
#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 12 : (i) == 2 ? 12 : -1)
#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 13 : (i) == 2 ? 13 : -1)
#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 14 : (i) == 2 ? 14 : -1)
#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 9 : -1)
#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 10 : -1)
#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1)
#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1)
#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1)
#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 9 : (i) == 2 ? 9 : -1)
#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 10 : (i) == 2 ? 10 : -1)
#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1)
#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1)
#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1)
#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 8 : (i) == 2 ? 8 : -1)
#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1)
#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1)
#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1)
#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1)
#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1)
#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1)
#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 8 : (i) == 2 ? 8 : -1)
#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 9 : -1)
#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 10 : -1)
#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 11 : -1)
#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : -1)
#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : -1)
#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1)
#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 14 : -1)
#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1)
#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1)
#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : -1)
#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : -1)
#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : -1)
#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : -1)
#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : -1)
#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : -1)
#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : -1)
#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : -1)
#define AF_UART0_CLK_PIN(i) (-1)
#define AF_UART0_CS_PIN(i) (-1)
#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : -1)
#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : -1)
#define AF_UART1_CLK_PIN(i) (-1)
#define AF_UART1_CS_PIN(i) (-1)
#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 0 : -1)
#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 1 : -1)
#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1)
#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 13 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1)
#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 4 : -1)
#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 15 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1)
#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : -1)
#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1)
#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : -1)
#define AF_TIMER1_CDTI0_PIN(i) (-1)
#define AF_TIMER1_CDTI1_PIN(i) (-1)
#define AF_TIMER1_CDTI2_PIN(i) (-1)
#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : -1)
#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : -1)
#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : -1)
#define AF_TIMER2_CDTI0_PIN(i) (-1)
#define AF_TIMER2_CDTI1_PIN(i) (-1)
#define AF_TIMER2_CDTI2_PIN(i) (-1)
#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : -1)
#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : -1)
#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : -1)
#define AF_TIMER3_CDTI0_PIN(i) (-1)
#define AF_TIMER3_CDTI1_PIN(i) (-1)
#define AF_TIMER3_CDTI2_PIN(i) (-1)
#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1)
#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : -1)
#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : -1)
#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : -1)
#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : -1)
#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : -1)
#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : -1)
#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : -1)
#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : -1)
#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1)
#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : -1)
#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : -1)
#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : -1)
#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : -1)
#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1)
#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1)
#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : -1)
#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : -1)
#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : -1)
#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : -1)
#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : -1)
#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : -1)
#define AF_DBG_SWO_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1)
#define AF_DBG_SWDIO_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : -1)
#define AF_DBG_SWCLK_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : -1)
#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : -1)
#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1)
#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1)
#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1)
#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : -1)
/** @} End of group EFM32WG_AF_Pins */

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/**************************************************************************//**
* @file efm32wg_af_ports.h
* @brief EFM32WG_AF_PORTS register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_AF_Ports
* @{
*****************************************************************************/
/** AF port number for location number i */
#define AF_USB_VBUSEN_PORT(i) ((i) == 0 ? 5 : -1)
#define AF_USB_DMPU_PORT(i) ((i) == 0 ? 3 : -1)
#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1)
#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : -1)
#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1)
#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1)
#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1)
#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1)
#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1)
#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1)
#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1)
#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1)
#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1)
#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1)
#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1)
#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1)
#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1)
#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1)
#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1)
#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1)
#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1)
#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1)
#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1)
#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1)
#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1)
#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1)
#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1)
#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1)
#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1)
#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1)
#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1)
#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1)
#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : -1)
#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : -1)
#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1)
#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1)
#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1)
#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1)
#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : -1)
#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : -1)
#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : -1)
#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : -1)
#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : -1)
#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : -1)
#define AF_UART0_CLK_PORT(i) (-1)
#define AF_UART0_CS_PORT(i) (-1)
#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : -1)
#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : -1)
#define AF_UART1_CLK_PORT(i) (-1)
#define AF_UART1_CS_PORT(i) (-1)
#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 5 : -1)
#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1)
#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1)
#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1)
#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1)
#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1)
#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : -1)
#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : -1)
#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : -1)
#define AF_TIMER1_CDTI0_PORT(i) (-1)
#define AF_TIMER1_CDTI1_PORT(i) (-1)
#define AF_TIMER1_CDTI2_PORT(i) (-1)
#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : -1)
#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : -1)
#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : -1)
#define AF_TIMER2_CDTI0_PORT(i) (-1)
#define AF_TIMER2_CDTI1_PORT(i) (-1)
#define AF_TIMER2_CDTI2_PORT(i) (-1)
#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : -1)
#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : -1)
#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : -1)
#define AF_TIMER3_CDTI0_PORT(i) (-1)
#define AF_TIMER3_CDTI1_PORT(i) (-1)
#define AF_TIMER3_CDTI2_PORT(i) (-1)
#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : -1)
#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : -1)
#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : -1)
#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : -1)
#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : -1)
#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : -1)
#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : -1)
#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : -1)
#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1)
#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1)
#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : -1)
#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : -1)
#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : -1)
#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : -1)
#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1)
#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1)
#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1)
#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1)
#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : -1)
#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : -1)
#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : -1)
#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : -1)
#define AF_DBG_SWO_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1)
#define AF_DBG_SWDIO_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : -1)
#define AF_DBG_SWCLK_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : -1)
#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1)
#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1)
#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : -1)
#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : -1)
#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : -1)
/** @} End of group EFM32WG_AF_Ports */

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/**************************************************************************//**
* @file efm32wg_burtc.h
* @brief EFM32WG_BURTC register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_BURTC
* @{
* @brief EFM32WG_BURTC Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t LPMODE; /**< Low power mode configuration */
__I uint32_t CNT; /**< Counter Value Register */
__IO uint32_t COMP0; /**< Counter Compare Value */
__I uint32_t TIMESTAMP; /**< Backup mode timestamp */
__IO uint32_t LFXOFDET; /**< LFXO */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t CMD; /**< Command Register */
__IO uint32_t POWERDOWN; /**< Retention RAM power-down Register */
__IO uint32_t LOCK; /**< Configuration Lock Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t FREEZE; /**< Freeze Register */
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
uint32_t RESERVED0[48]; /**< Reserved registers */
BURTC_RET_TypeDef RET[128]; /**< RetentionReg */
} BURTC_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_BURTC_BitFields
* @{
*****************************************************************************/
/* Bit fields for BURTC CTRL */
#define _BURTC_CTRL_RESETVALUE 0x00000008UL /**< Default value for BURTC_CTRL */
#define _BURTC_CTRL_MASK 0x000077FFUL /**< Mask for BURTC_CTRL */
#define _BURTC_CTRL_MODE_SHIFT 0 /**< Shift value for BURTC_MODE */
#define _BURTC_CTRL_MODE_MASK 0x3UL /**< Bit mask for BURTC_MODE */
#define _BURTC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
#define _BURTC_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CTRL */
#define _BURTC_CTRL_MODE_EM2EN 0x00000001UL /**< Mode EM2EN for BURTC_CTRL */
#define _BURTC_CTRL_MODE_EM3EN 0x00000002UL /**< Mode EM3EN for BURTC_CTRL */
#define _BURTC_CTRL_MODE_EM4EN 0x00000003UL /**< Mode EM4EN for BURTC_CTRL */
#define BURTC_CTRL_MODE_DEFAULT (_BURTC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_MODE_DISABLE (_BURTC_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_CTRL */
#define BURTC_CTRL_MODE_EM2EN (_BURTC_CTRL_MODE_EM2EN << 0) /**< Shifted mode EM2EN for BURTC_CTRL */
#define BURTC_CTRL_MODE_EM3EN (_BURTC_CTRL_MODE_EM3EN << 0) /**< Shifted mode EM3EN for BURTC_CTRL */
#define BURTC_CTRL_MODE_EM4EN (_BURTC_CTRL_MODE_EM4EN << 0) /**< Shifted mode EM4EN for BURTC_CTRL */
#define BURTC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */
#define _BURTC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for BURTC_DEBUGRUN */
#define _BURTC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for BURTC_DEBUGRUN */
#define _BURTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_DEBUGRUN_DEFAULT (_BURTC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_RSTEN (0x1UL << 3) /**< Enable BURTC reset */
#define _BURTC_CTRL_RSTEN_SHIFT 3 /**< Shift value for BURTC_RSTEN */
#define _BURTC_CTRL_RSTEN_MASK 0x8UL /**< Bit mask for BURTC_RSTEN */
#define _BURTC_CTRL_RSTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_RSTEN_DEFAULT (_BURTC_CTRL_RSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_COMP0TOP (0x1UL << 4) /**< Compare clear enable */
#define _BURTC_CTRL_COMP0TOP_SHIFT 4 /**< Shift value for BURTC_COMP0TOP */
#define _BURTC_CTRL_COMP0TOP_MASK 0x10UL /**< Bit mask for BURTC_COMP0TOP */
#define _BURTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_COMP0TOP_DEFAULT (_BURTC_CTRL_COMP0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_SHIFT 5 /**< Shift value for BURTC_LPCOMP */
#define _BURTC_CTRL_LPCOMP_MASK 0xE0UL /**< Bit mask for BURTC_LPCOMP */
#define _BURTC_CTRL_LPCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN0LSB 0x00000000UL /**< Mode IGN0LSB for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN1LSB 0x00000001UL /**< Mode IGN1LSB for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN2LSB 0x00000002UL /**< Mode IGN2LSB for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN3LSB 0x00000003UL /**< Mode IGN3LSB for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN4LSB 0x00000004UL /**< Mode IGN4LSB for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN5LSB 0x00000005UL /**< Mode IGN5LSB for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN6LSB 0x00000006UL /**< Mode IGN6LSB for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN7LSB 0x00000007UL /**< Mode IGN7LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_DEFAULT (_BURTC_CTRL_LPCOMP_DEFAULT << 5) /**< Shifted mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN0LSB (_BURTC_CTRL_LPCOMP_IGN0LSB << 5) /**< Shifted mode IGN0LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN1LSB (_BURTC_CTRL_LPCOMP_IGN1LSB << 5) /**< Shifted mode IGN1LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN2LSB (_BURTC_CTRL_LPCOMP_IGN2LSB << 5) /**< Shifted mode IGN2LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN3LSB (_BURTC_CTRL_LPCOMP_IGN3LSB << 5) /**< Shifted mode IGN3LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN4LSB (_BURTC_CTRL_LPCOMP_IGN4LSB << 5) /**< Shifted mode IGN4LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN5LSB (_BURTC_CTRL_LPCOMP_IGN5LSB << 5) /**< Shifted mode IGN5LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN6LSB (_BURTC_CTRL_LPCOMP_IGN6LSB << 5) /**< Shifted mode IGN6LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN7LSB (_BURTC_CTRL_LPCOMP_IGN7LSB << 5) /**< Shifted mode IGN7LSB for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_SHIFT 8 /**< Shift value for BURTC_PRESC */
#define _BURTC_CTRL_PRESC_MASK 0x700UL /**< Bit mask for BURTC_PRESC */
#define _BURTC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DEFAULT (_BURTC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV1 (_BURTC_CTRL_PRESC_DIV1 << 8) /**< Shifted mode DIV1 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV2 (_BURTC_CTRL_PRESC_DIV2 << 8) /**< Shifted mode DIV2 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV4 (_BURTC_CTRL_PRESC_DIV4 << 8) /**< Shifted mode DIV4 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV8 (_BURTC_CTRL_PRESC_DIV8 << 8) /**< Shifted mode DIV8 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV16 (_BURTC_CTRL_PRESC_DIV16 << 8) /**< Shifted mode DIV16 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV32 (_BURTC_CTRL_PRESC_DIV32 << 8) /**< Shifted mode DIV32 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV64 (_BURTC_CTRL_PRESC_DIV64 << 8) /**< Shifted mode DIV64 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV128 (_BURTC_CTRL_PRESC_DIV128 << 8) /**< Shifted mode DIV128 for BURTC_CTRL */
#define _BURTC_CTRL_CLKSEL_SHIFT 12 /**< Shift value for BURTC_CLKSEL */
#define _BURTC_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for BURTC_CLKSEL */
#define _BURTC_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
#define _BURTC_CTRL_CLKSEL_NONE 0x00000000UL /**< Mode NONE for BURTC_CTRL */
#define _BURTC_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for BURTC_CTRL */
#define _BURTC_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for BURTC_CTRL */
#define _BURTC_CTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for BURTC_CTRL */
#define BURTC_CTRL_CLKSEL_DEFAULT (_BURTC_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_CLKSEL_NONE (_BURTC_CTRL_CLKSEL_NONE << 12) /**< Shifted mode NONE for BURTC_CTRL */
#define BURTC_CTRL_CLKSEL_LFRCO (_BURTC_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for BURTC_CTRL */
#define BURTC_CTRL_CLKSEL_LFXO (_BURTC_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for BURTC_CTRL */
#define BURTC_CTRL_CLKSEL_ULFRCO (_BURTC_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for BURTC_CTRL */
#define BURTC_CTRL_BUMODETSEN (0x1UL << 14) /**< Backup mode timestamp enable */
#define _BURTC_CTRL_BUMODETSEN_SHIFT 14 /**< Shift value for BURTC_BUMODETSEN */
#define _BURTC_CTRL_BUMODETSEN_MASK 0x4000UL /**< Bit mask for BURTC_BUMODETSEN */
#define _BURTC_CTRL_BUMODETSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_BUMODETSEN_DEFAULT (_BURTC_CTRL_BUMODETSEN_DEFAULT << 14) /**< Shifted mode DEFAULT for BURTC_CTRL */
/* Bit fields for BURTC LPMODE */
#define _BURTC_LPMODE_RESETVALUE 0x00000000UL /**< Default value for BURTC_LPMODE */
#define _BURTC_LPMODE_MASK 0x00000003UL /**< Mask for BURTC_LPMODE */
#define _BURTC_LPMODE_LPMODE_SHIFT 0 /**< Shift value for BURTC_LPMODE */
#define _BURTC_LPMODE_LPMODE_MASK 0x3UL /**< Bit mask for BURTC_LPMODE */
#define _BURTC_LPMODE_LPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LPMODE */
#define _BURTC_LPMODE_LPMODE_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_LPMODE */
#define _BURTC_LPMODE_LPMODE_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_LPMODE */
#define _BURTC_LPMODE_LPMODE_BUEN 0x00000002UL /**< Mode BUEN for BURTC_LPMODE */
#define BURTC_LPMODE_LPMODE_DEFAULT (_BURTC_LPMODE_LPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LPMODE */
#define BURTC_LPMODE_LPMODE_DISABLE (_BURTC_LPMODE_LPMODE_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_LPMODE */
#define BURTC_LPMODE_LPMODE_ENABLE (_BURTC_LPMODE_LPMODE_ENABLE << 0) /**< Shifted mode ENABLE for BURTC_LPMODE */
#define BURTC_LPMODE_LPMODE_BUEN (_BURTC_LPMODE_LPMODE_BUEN << 0) /**< Shifted mode BUEN for BURTC_LPMODE */
/* Bit fields for BURTC CNT */
#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */
#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */
#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */
#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */
#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */
#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */
/* Bit fields for BURTC COMP0 */
#define _BURTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP0 */
#define _BURTC_COMP0_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP0 */
#define _BURTC_COMP0_COMP0_SHIFT 0 /**< Shift value for BURTC_COMP0 */
#define _BURTC_COMP0_COMP0_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP0 */
#define _BURTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP0 */
#define BURTC_COMP0_COMP0_DEFAULT (_BURTC_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP0 */
/* Bit fields for BURTC TIMESTAMP */
#define _BURTC_TIMESTAMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_TIMESTAMP */
#define _BURTC_TIMESTAMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_TIMESTAMP */
#define _BURTC_TIMESTAMP_TIMESTAMP_SHIFT 0 /**< Shift value for BURTC_TIMESTAMP */
#define _BURTC_TIMESTAMP_TIMESTAMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_TIMESTAMP */
#define _BURTC_TIMESTAMP_TIMESTAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_TIMESTAMP */
#define BURTC_TIMESTAMP_TIMESTAMP_DEFAULT (_BURTC_TIMESTAMP_TIMESTAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_TIMESTAMP */
/* Bit fields for BURTC LFXOFDET */
#define _BURTC_LFXOFDET_RESETVALUE 0x00000000UL /**< Default value for BURTC_LFXOFDET */
#define _BURTC_LFXOFDET_MASK 0x000001F3UL /**< Mask for BURTC_LFXOFDET */
#define _BURTC_LFXOFDET_OSC_SHIFT 0 /**< Shift value for BURTC_OSC */
#define _BURTC_LFXOFDET_OSC_MASK 0x3UL /**< Bit mask for BURTC_OSC */
#define _BURTC_LFXOFDET_OSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LFXOFDET */
#define _BURTC_LFXOFDET_OSC_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_LFXOFDET */
#define _BURTC_LFXOFDET_OSC_LFRCO 0x00000001UL /**< Mode LFRCO for BURTC_LFXOFDET */
#define _BURTC_LFXOFDET_OSC_ULFRCO 0x00000002UL /**< Mode ULFRCO for BURTC_LFXOFDET */
#define BURTC_LFXOFDET_OSC_DEFAULT (_BURTC_LFXOFDET_OSC_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LFXOFDET */
#define BURTC_LFXOFDET_OSC_DISABLE (_BURTC_LFXOFDET_OSC_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_LFXOFDET */
#define BURTC_LFXOFDET_OSC_LFRCO (_BURTC_LFXOFDET_OSC_LFRCO << 0) /**< Shifted mode LFRCO for BURTC_LFXOFDET */
#define BURTC_LFXOFDET_OSC_ULFRCO (_BURTC_LFXOFDET_OSC_ULFRCO << 0) /**< Shifted mode ULFRCO for BURTC_LFXOFDET */
#define _BURTC_LFXOFDET_TOP_SHIFT 4 /**< Shift value for BURTC_TOP */
#define _BURTC_LFXOFDET_TOP_MASK 0x1F0UL /**< Bit mask for BURTC_TOP */
#define _BURTC_LFXOFDET_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LFXOFDET */
#define BURTC_LFXOFDET_TOP_DEFAULT (_BURTC_LFXOFDET_TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_LFXOFDET */
/* Bit fields for BURTC STATUS */
#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */
#define _BURTC_STATUS_MASK 0x00000007UL /**< Mask for BURTC_STATUS */
#define BURTC_STATUS_LPMODEACT (0x1UL << 0) /**< Low power mode active */
#define _BURTC_STATUS_LPMODEACT_SHIFT 0 /**< Shift value for BURTC_LPMODEACT */
#define _BURTC_STATUS_LPMODEACT_MASK 0x1UL /**< Bit mask for BURTC_LPMODEACT */
#define _BURTC_STATUS_LPMODEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */
#define BURTC_STATUS_LPMODEACT_DEFAULT (_BURTC_STATUS_LPMODEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */
#define BURTC_STATUS_BUMODETS (0x1UL << 1) /**< Timestamp for backup mode entry stored. */
#define _BURTC_STATUS_BUMODETS_SHIFT 1 /**< Shift value for BURTC_BUMODETS */
#define _BURTC_STATUS_BUMODETS_MASK 0x2UL /**< Bit mask for BURTC_BUMODETS */
#define _BURTC_STATUS_BUMODETS_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */
#define BURTC_STATUS_BUMODETS_DEFAULT (_BURTC_STATUS_BUMODETS_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */
#define BURTC_STATUS_RAMWERR (0x1UL << 2) /**< RAM write error. */
#define _BURTC_STATUS_RAMWERR_SHIFT 2 /**< Shift value for BURTC_RAMWERR */
#define _BURTC_STATUS_RAMWERR_MASK 0x4UL /**< Bit mask for BURTC_RAMWERR */
#define _BURTC_STATUS_RAMWERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */
#define BURTC_STATUS_RAMWERR_DEFAULT (_BURTC_STATUS_RAMWERR_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_STATUS */
/* Bit fields for BURTC CMD */
#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */
#define _BURTC_CMD_MASK 0x00000001UL /**< Mask for BURTC_CMD */
#define BURTC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear BURTC_STATUS register. */
#define _BURTC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for BURTC_CLRSTATUS */
#define _BURTC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for BURTC_CLRSTATUS */
#define _BURTC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */
#define BURTC_CMD_CLRSTATUS_DEFAULT (_BURTC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */
/* Bit fields for BURTC POWERDOWN */
#define _BURTC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for BURTC_POWERDOWN */
#define _BURTC_POWERDOWN_MASK 0x00000001UL /**< Mask for BURTC_POWERDOWN */
#define BURTC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM power-down */
#define _BURTC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for BURTC_RAM */
#define _BURTC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for BURTC_RAM */
#define _BURTC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_POWERDOWN */
#define BURTC_POWERDOWN_RAM_DEFAULT (_BURTC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_POWERDOWN */
/* Bit fields for BURTC LOCK */
#define _BURTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for BURTC_LOCK */
#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */
#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */
#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_LOCK (_BURTC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_UNLOCKED (_BURTC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_LOCKED (_BURTC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */
/* Bit fields for BURTC IF */
#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */
#define _BURTC_IF_MASK 0x00000007UL /**< Mask for BURTC_IF */
#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */
#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */
#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */
#define BURTC_IF_COMP0 (0x1UL << 1) /**< Compare match Interrupt Flag */
#define _BURTC_IF_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */
#define _BURTC_IF_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */
#define _BURTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */
#define BURTC_IF_COMP0_DEFAULT (_BURTC_IF_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */
#define BURTC_IF_LFXOFAIL (0x1UL << 2) /**< LFXO failure Interrupt Flag */
#define _BURTC_IF_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */
#define _BURTC_IF_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */
#define _BURTC_IF_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */
#define BURTC_IF_LFXOFAIL_DEFAULT (_BURTC_IF_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IF */
/* Bit fields for BURTC IFS */
#define _BURTC_IFS_RESETVALUE 0x00000000UL /**< Default value for BURTC_IFS */
#define _BURTC_IFS_MASK 0x00000007UL /**< Mask for BURTC_IFS */
#define BURTC_IFS_OF (0x1UL << 0) /**< Set Overflow Interrupt Flag */
#define _BURTC_IFS_OF_SHIFT 0 /**< Shift value for BURTC_OF */
#define _BURTC_IFS_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
#define _BURTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFS */
#define BURTC_IFS_OF_DEFAULT (_BURTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IFS */
#define BURTC_IFS_COMP0 (0x1UL << 1) /**< Set compare match Interrupt Flag */
#define _BURTC_IFS_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */
#define _BURTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */
#define _BURTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFS */
#define BURTC_IFS_COMP0_DEFAULT (_BURTC_IFS_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IFS */
#define BURTC_IFS_LFXOFAIL (0x1UL << 2) /**< Set LFXO fail Interrupt Flag */
#define _BURTC_IFS_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */
#define _BURTC_IFS_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */
#define _BURTC_IFS_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFS */
#define BURTC_IFS_LFXOFAIL_DEFAULT (_BURTC_IFS_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IFS */
/* Bit fields for BURTC IFC */
#define _BURTC_IFC_RESETVALUE 0x00000000UL /**< Default value for BURTC_IFC */
#define _BURTC_IFC_MASK 0x00000007UL /**< Mask for BURTC_IFC */
#define BURTC_IFC_OF (0x1UL << 0) /**< Clear Overflow Interrupt Flag */
#define _BURTC_IFC_OF_SHIFT 0 /**< Shift value for BURTC_OF */
#define _BURTC_IFC_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
#define _BURTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFC */
#define BURTC_IFC_OF_DEFAULT (_BURTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IFC */
#define BURTC_IFC_COMP0 (0x1UL << 1) /**< Clear compare match Interrupt Flag */
#define _BURTC_IFC_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */
#define _BURTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */
#define _BURTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFC */
#define BURTC_IFC_COMP0_DEFAULT (_BURTC_IFC_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IFC */
#define BURTC_IFC_LFXOFAIL (0x1UL << 2) /**< Clear LFXO failure Interrupt Flag */
#define _BURTC_IFC_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */
#define _BURTC_IFC_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */
#define _BURTC_IFC_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFC */
#define BURTC_IFC_LFXOFAIL_DEFAULT (_BURTC_IFC_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IFC */
/* Bit fields for BURTC IEN */
#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */
#define _BURTC_IEN_MASK 0x00000007UL /**< Mask for BURTC_IEN */
#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */
#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */
#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */
#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */
#define BURTC_IEN_COMP0 (0x1UL << 1) /**< Compare match Interrupt Enable */
#define _BURTC_IEN_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */
#define _BURTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */
#define _BURTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */
#define BURTC_IEN_COMP0_DEFAULT (_BURTC_IEN_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */
#define BURTC_IEN_LFXOFAIL (0x1UL << 2) /**< LFXO failure Interrupt Enable */
#define _BURTC_IEN_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */
#define _BURTC_IEN_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */
#define _BURTC_IEN_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */
#define BURTC_IEN_LFXOFAIL_DEFAULT (_BURTC_IEN_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IEN */
/* Bit fields for BURTC FREEZE */
#define _BURTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for BURTC_FREEZE */
#define _BURTC_FREEZE_MASK 0x00000001UL /**< Mask for BURTC_FREEZE */
#define BURTC_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
#define _BURTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for BURTC_REGFREEZE */
#define _BURTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for BURTC_REGFREEZE */
#define _BURTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_FREEZE */
#define _BURTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for BURTC_FREEZE */
#define _BURTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for BURTC_FREEZE */
#define BURTC_FREEZE_REGFREEZE_DEFAULT (_BURTC_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_FREEZE */
#define BURTC_FREEZE_REGFREEZE_UPDATE (_BURTC_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for BURTC_FREEZE */
#define BURTC_FREEZE_REGFREEZE_FREEZE (_BURTC_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for BURTC_FREEZE */
/* Bit fields for BURTC SYNCBUSY */
#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */
#define _BURTC_SYNCBUSY_MASK 0x00000003UL /**< Mask for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_LPMODE (0x1UL << 0) /**< LPMODE Register Busy */
#define _BURTC_SYNCBUSY_LPMODE_SHIFT 0 /**< Shift value for BURTC_LPMODE */
#define _BURTC_SYNCBUSY_LPMODE_MASK 0x1UL /**< Bit mask for BURTC_LPMODE */
#define _BURTC_SYNCBUSY_LPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_LPMODE_DEFAULT (_BURTC_SYNCBUSY_LPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_COMP0 (0x1UL << 1) /**< COMP0 Register Busy */
#define _BURTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */
#define _BURTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */
#define _BURTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_COMP0_DEFAULT (_BURTC_SYNCBUSY_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
/* Bit fields for BURTC RET_REG */
#define _BURTC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURTC_RET_REG */
#define _BURTC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURTC_RET_REG */
#define _BURTC_RET_REG_REG_SHIFT 0 /**< Shift value for REG */
#define _BURTC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for REG */
#define _BURTC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_RET_REG */
#define BURTC_RET_REG_REG_DEFAULT (_BURTC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_RET_REG */
/** @} End of group EFM32WG_BURTC */

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/**************************************************************************//**
* @file efm32wg_burtc_ret.h
* @brief EFM32WG_BURTC_RET register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @brief BURTC_RET EFM32WG BURTC RET
*****************************************************************************/
typedef struct
{
__IO uint32_t REG; /**< Retention Register */
} BURTC_RET_TypeDef;

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/**************************************************************************//**
* @file efm32wg_calibrate.h
* @brief EFM32WG_CALIBRATE register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_CALIBRATE
* @{
*****************************************************************************/
#define CALIBRATE_MAX_REGISTERS 50 /**< Max number of address/value pairs for calibration */
typedef struct
{
__I uint32_t ADDRESS; /**< Address of calibration register */
__I uint32_t VALUE; /**< Default value for calibration register */
} CALIBRATE_TypeDef; /** @} */

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/**************************************************************************//**
* @file efm32wg_dac.h
* @brief EFM32WG_DAC register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_DAC
* @{
* @brief EFM32WG_DAC Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t CH0CTRL; /**< Channel 0 Control Register */
__IO uint32_t CH1CTRL; /**< Channel 1 Control Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t CH0DATA; /**< Channel 0 Data Register */
__IO uint32_t CH1DATA; /**< Channel 1 Data Register */
__IO uint32_t COMBDATA; /**< Combined Data Register */
__IO uint32_t CAL; /**< Calibration Register */
__IO uint32_t BIASPROG; /**< Bias Programming Register */
uint32_t RESERVED0[8]; /**< Reserved for future use **/
__IO uint32_t OPACTRL; /**< Operational Amplifier Control Register */
__IO uint32_t OPAOFFSET; /**< Operational Amplifier Offset Register */
__IO uint32_t OPA0MUX; /**< Operational Amplifier Mux Configuration Register */
__IO uint32_t OPA1MUX; /**< Operational Amplifier Mux Configuration Register */
__IO uint32_t OPA2MUX; /**< Operational Amplifier Mux Configuration Register */
} DAC_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_DAC_BitFields
* @{
*****************************************************************************/
/* Bit fields for DAC CTRL */
#define _DAC_CTRL_RESETVALUE 0x00000010UL /**< Default value for DAC_CTRL */
#define _DAC_CTRL_MASK 0x003703FFUL /**< Mask for DAC_CTRL */
#define DAC_CTRL_DIFF (0x1UL << 0) /**< Differential Mode */
#define _DAC_CTRL_DIFF_SHIFT 0 /**< Shift value for DAC_DIFF */
#define _DAC_CTRL_DIFF_MASK 0x1UL /**< Bit mask for DAC_DIFF */
#define _DAC_CTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
#define DAC_CTRL_DIFF_DEFAULT (_DAC_CTRL_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CTRL */
#define DAC_CTRL_SINEMODE (0x1UL << 1) /**< Sine Mode */
#define _DAC_CTRL_SINEMODE_SHIFT 1 /**< Shift value for DAC_SINEMODE */
#define _DAC_CTRL_SINEMODE_MASK 0x2UL /**< Bit mask for DAC_SINEMODE */
#define _DAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
#define DAC_CTRL_SINEMODE_DEFAULT (_DAC_CTRL_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CTRL */
#define _DAC_CTRL_CONVMODE_SHIFT 2 /**< Shift value for DAC_CONVMODE */
#define _DAC_CTRL_CONVMODE_MASK 0xCUL /**< Bit mask for DAC_CONVMODE */
#define _DAC_CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
#define _DAC_CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for DAC_CTRL */
#define _DAC_CTRL_CONVMODE_SAMPLEHOLD 0x00000001UL /**< Mode SAMPLEHOLD for DAC_CTRL */
#define _DAC_CTRL_CONVMODE_SAMPLEOFF 0x00000002UL /**< Mode SAMPLEOFF for DAC_CTRL */
#define DAC_CTRL_CONVMODE_DEFAULT (_DAC_CTRL_CONVMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_CTRL */
#define DAC_CTRL_CONVMODE_CONTINUOUS (_DAC_CTRL_CONVMODE_CONTINUOUS << 2) /**< Shifted mode CONTINUOUS for DAC_CTRL */
#define DAC_CTRL_CONVMODE_SAMPLEHOLD (_DAC_CTRL_CONVMODE_SAMPLEHOLD << 2) /**< Shifted mode SAMPLEHOLD for DAC_CTRL */
#define DAC_CTRL_CONVMODE_SAMPLEOFF (_DAC_CTRL_CONVMODE_SAMPLEOFF << 2) /**< Shifted mode SAMPLEOFF for DAC_CTRL */
#define _DAC_CTRL_OUTMODE_SHIFT 4 /**< Shift value for DAC_OUTMODE */
#define _DAC_CTRL_OUTMODE_MASK 0x30UL /**< Bit mask for DAC_OUTMODE */
#define _DAC_CTRL_OUTMODE_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_CTRL */
#define _DAC_CTRL_OUTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_CTRL */
#define _DAC_CTRL_OUTMODE_PIN 0x00000001UL /**< Mode PIN for DAC_CTRL */
#define _DAC_CTRL_OUTMODE_ADC 0x00000002UL /**< Mode ADC for DAC_CTRL */
#define _DAC_CTRL_OUTMODE_PINADC 0x00000003UL /**< Mode PINADC for DAC_CTRL */
#define DAC_CTRL_OUTMODE_DISABLE (_DAC_CTRL_OUTMODE_DISABLE << 4) /**< Shifted mode DISABLE for DAC_CTRL */
#define DAC_CTRL_OUTMODE_DEFAULT (_DAC_CTRL_OUTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CTRL */
#define DAC_CTRL_OUTMODE_PIN (_DAC_CTRL_OUTMODE_PIN << 4) /**< Shifted mode PIN for DAC_CTRL */
#define DAC_CTRL_OUTMODE_ADC (_DAC_CTRL_OUTMODE_ADC << 4) /**< Shifted mode ADC for DAC_CTRL */
#define DAC_CTRL_OUTMODE_PINADC (_DAC_CTRL_OUTMODE_PINADC << 4) /**< Shifted mode PINADC for DAC_CTRL */
#define DAC_CTRL_OUTENPRS (0x1UL << 6) /**< PRS Controlled Output Enable */
#define _DAC_CTRL_OUTENPRS_SHIFT 6 /**< Shift value for DAC_OUTENPRS */
#define _DAC_CTRL_OUTENPRS_MASK 0x40UL /**< Bit mask for DAC_OUTENPRS */
#define _DAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
#define DAC_CTRL_OUTENPRS_DEFAULT (_DAC_CTRL_OUTENPRS_DEFAULT << 6) /**< Shifted mode DEFAULT for DAC_CTRL */
#define DAC_CTRL_CH0PRESCRST (0x1UL << 7) /**< Channel 0 Start Reset Prescaler */
#define _DAC_CTRL_CH0PRESCRST_SHIFT 7 /**< Shift value for DAC_CH0PRESCRST */
#define _DAC_CTRL_CH0PRESCRST_MASK 0x80UL /**< Bit mask for DAC_CH0PRESCRST */
#define _DAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
#define DAC_CTRL_CH0PRESCRST_DEFAULT (_DAC_CTRL_CH0PRESCRST_DEFAULT << 7) /**< Shifted mode DEFAULT for DAC_CTRL */
#define _DAC_CTRL_REFSEL_SHIFT 8 /**< Shift value for DAC_REFSEL */
#define _DAC_CTRL_REFSEL_MASK 0x300UL /**< Bit mask for DAC_REFSEL */
#define _DAC_CTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
#define _DAC_CTRL_REFSEL_1V25 0x00000000UL /**< Mode 1V25 for DAC_CTRL */
#define _DAC_CTRL_REFSEL_2V5 0x00000001UL /**< Mode 2V5 for DAC_CTRL */
#define _DAC_CTRL_REFSEL_VDD 0x00000002UL /**< Mode VDD for DAC_CTRL */
#define DAC_CTRL_REFSEL_DEFAULT (_DAC_CTRL_REFSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_CTRL */
#define DAC_CTRL_REFSEL_1V25 (_DAC_CTRL_REFSEL_1V25 << 8) /**< Shifted mode 1V25 for DAC_CTRL */
#define DAC_CTRL_REFSEL_2V5 (_DAC_CTRL_REFSEL_2V5 << 8) /**< Shifted mode 2V5 for DAC_CTRL */
#define DAC_CTRL_REFSEL_VDD (_DAC_CTRL_REFSEL_VDD << 8) /**< Shifted mode VDD for DAC_CTRL */
#define _DAC_CTRL_PRESC_SHIFT 16 /**< Shift value for DAC_PRESC */
#define _DAC_CTRL_PRESC_MASK 0x70000UL /**< Bit mask for DAC_PRESC */
#define _DAC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
#define _DAC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for DAC_CTRL */
#define DAC_CTRL_PRESC_DEFAULT (_DAC_CTRL_PRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_CTRL */
#define DAC_CTRL_PRESC_NODIVISION (_DAC_CTRL_PRESC_NODIVISION << 16) /**< Shifted mode NODIVISION for DAC_CTRL */
#define _DAC_CTRL_REFRSEL_SHIFT 20 /**< Shift value for DAC_REFRSEL */
#define _DAC_CTRL_REFRSEL_MASK 0x300000UL /**< Bit mask for DAC_REFRSEL */
#define _DAC_CTRL_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
#define _DAC_CTRL_REFRSEL_8CYCLES 0x00000000UL /**< Mode 8CYCLES for DAC_CTRL */
#define _DAC_CTRL_REFRSEL_16CYCLES 0x00000001UL /**< Mode 16CYCLES for DAC_CTRL */
#define _DAC_CTRL_REFRSEL_32CYCLES 0x00000002UL /**< Mode 32CYCLES for DAC_CTRL */
#define _DAC_CTRL_REFRSEL_64CYCLES 0x00000003UL /**< Mode 64CYCLES for DAC_CTRL */
#define DAC_CTRL_REFRSEL_DEFAULT (_DAC_CTRL_REFRSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for DAC_CTRL */
#define DAC_CTRL_REFRSEL_8CYCLES (_DAC_CTRL_REFRSEL_8CYCLES << 20) /**< Shifted mode 8CYCLES for DAC_CTRL */
#define DAC_CTRL_REFRSEL_16CYCLES (_DAC_CTRL_REFRSEL_16CYCLES << 20) /**< Shifted mode 16CYCLES for DAC_CTRL */
#define DAC_CTRL_REFRSEL_32CYCLES (_DAC_CTRL_REFRSEL_32CYCLES << 20) /**< Shifted mode 32CYCLES for DAC_CTRL */
#define DAC_CTRL_REFRSEL_64CYCLES (_DAC_CTRL_REFRSEL_64CYCLES << 20) /**< Shifted mode 64CYCLES for DAC_CTRL */
/* Bit fields for DAC STATUS */
#define _DAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DAC_STATUS */
#define _DAC_STATUS_MASK 0x00000003UL /**< Mask for DAC_STATUS */
#define DAC_STATUS_CH0DV (0x1UL << 0) /**< Channel 0 Data Valid */
#define _DAC_STATUS_CH0DV_SHIFT 0 /**< Shift value for DAC_CH0DV */
#define _DAC_STATUS_CH0DV_MASK 0x1UL /**< Bit mask for DAC_CH0DV */
#define _DAC_STATUS_CH0DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_STATUS */
#define DAC_STATUS_CH0DV_DEFAULT (_DAC_STATUS_CH0DV_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_STATUS */
#define DAC_STATUS_CH1DV (0x1UL << 1) /**< Channel 1 Data Valid */
#define _DAC_STATUS_CH1DV_SHIFT 1 /**< Shift value for DAC_CH1DV */
#define _DAC_STATUS_CH1DV_MASK 0x2UL /**< Bit mask for DAC_CH1DV */
#define _DAC_STATUS_CH1DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_STATUS */
#define DAC_STATUS_CH1DV_DEFAULT (_DAC_STATUS_CH1DV_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_STATUS */
/* Bit fields for DAC CH0CTRL */
#define _DAC_CH0CTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_CH0CTRL */
#define _DAC_CH0CTRL_MASK 0x000000F7UL /**< Mask for DAC_CH0CTRL */
#define DAC_CH0CTRL_EN (0x1UL << 0) /**< Channel 0 Enable */
#define _DAC_CH0CTRL_EN_SHIFT 0 /**< Shift value for DAC_EN */
#define _DAC_CH0CTRL_EN_MASK 0x1UL /**< Bit mask for DAC_EN */
#define _DAC_CH0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
#define DAC_CH0CTRL_EN_DEFAULT (_DAC_CH0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
#define DAC_CH0CTRL_REFREN (0x1UL << 1) /**< Channel 0 Automatic Refresh Enable */
#define _DAC_CH0CTRL_REFREN_SHIFT 1 /**< Shift value for DAC_REFREN */
#define _DAC_CH0CTRL_REFREN_MASK 0x2UL /**< Bit mask for DAC_REFREN */
#define _DAC_CH0CTRL_REFREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
#define DAC_CH0CTRL_REFREN_DEFAULT (_DAC_CH0CTRL_REFREN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
#define DAC_CH0CTRL_PRSEN (0x1UL << 2) /**< Channel 0 PRS Trigger Enable */
#define _DAC_CH0CTRL_PRSEN_SHIFT 2 /**< Shift value for DAC_PRSEN */
#define _DAC_CH0CTRL_PRSEN_MASK 0x4UL /**< Bit mask for DAC_PRSEN */
#define _DAC_CH0CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
#define DAC_CH0CTRL_PRSEN_DEFAULT (_DAC_CH0CTRL_PRSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
#define _DAC_CH0CTRL_PRSSEL_SHIFT 4 /**< Shift value for DAC_PRSSEL */
#define _DAC_CH0CTRL_PRSSEL_MASK 0xF0UL /**< Bit mask for DAC_PRSSEL */
#define _DAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
#define _DAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for DAC_CH0CTRL */
#define _DAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for DAC_CH0CTRL */
#define _DAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for DAC_CH0CTRL */
#define _DAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for DAC_CH0CTRL */
#define _DAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for DAC_CH0CTRL */
#define _DAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for DAC_CH0CTRL */
#define _DAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for DAC_CH0CTRL */
#define _DAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for DAC_CH0CTRL */
#define _DAC_CH0CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for DAC_CH0CTRL */
#define _DAC_CH0CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for DAC_CH0CTRL */
#define _DAC_CH0CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for DAC_CH0CTRL */
#define _DAC_CH0CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for DAC_CH0CTRL */
#define DAC_CH0CTRL_PRSSEL_DEFAULT (_DAC_CH0CTRL_PRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
#define DAC_CH0CTRL_PRSSEL_PRSCH0 (_DAC_CH0CTRL_PRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for DAC_CH0CTRL */
#define DAC_CH0CTRL_PRSSEL_PRSCH1 (_DAC_CH0CTRL_PRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for DAC_CH0CTRL */
#define DAC_CH0CTRL_PRSSEL_PRSCH2 (_DAC_CH0CTRL_PRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for DAC_CH0CTRL */
#define DAC_CH0CTRL_PRSSEL_PRSCH3 (_DAC_CH0CTRL_PRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for DAC_CH0CTRL */
#define DAC_CH0CTRL_PRSSEL_PRSCH4 (_DAC_CH0CTRL_PRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for DAC_CH0CTRL */
#define DAC_CH0CTRL_PRSSEL_PRSCH5 (_DAC_CH0CTRL_PRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for DAC_CH0CTRL */
#define DAC_CH0CTRL_PRSSEL_PRSCH6 (_DAC_CH0CTRL_PRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for DAC_CH0CTRL */
#define DAC_CH0CTRL_PRSSEL_PRSCH7 (_DAC_CH0CTRL_PRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for DAC_CH0CTRL */
#define DAC_CH0CTRL_PRSSEL_PRSCH8 (_DAC_CH0CTRL_PRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for DAC_CH0CTRL */
#define DAC_CH0CTRL_PRSSEL_PRSCH9 (_DAC_CH0CTRL_PRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for DAC_CH0CTRL */
#define DAC_CH0CTRL_PRSSEL_PRSCH10 (_DAC_CH0CTRL_PRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for DAC_CH0CTRL */
#define DAC_CH0CTRL_PRSSEL_PRSCH11 (_DAC_CH0CTRL_PRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for DAC_CH0CTRL */
/* Bit fields for DAC CH1CTRL */
#define _DAC_CH1CTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_CH1CTRL */
#define _DAC_CH1CTRL_MASK 0x000000F7UL /**< Mask for DAC_CH1CTRL */
#define DAC_CH1CTRL_EN (0x1UL << 0) /**< Channel 1 Enable */
#define _DAC_CH1CTRL_EN_SHIFT 0 /**< Shift value for DAC_EN */
#define _DAC_CH1CTRL_EN_MASK 0x1UL /**< Bit mask for DAC_EN */
#define _DAC_CH1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
#define DAC_CH1CTRL_EN_DEFAULT (_DAC_CH1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
#define DAC_CH1CTRL_REFREN (0x1UL << 1) /**< Channel 1 Automatic Refresh Enable */
#define _DAC_CH1CTRL_REFREN_SHIFT 1 /**< Shift value for DAC_REFREN */
#define _DAC_CH1CTRL_REFREN_MASK 0x2UL /**< Bit mask for DAC_REFREN */
#define _DAC_CH1CTRL_REFREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
#define DAC_CH1CTRL_REFREN_DEFAULT (_DAC_CH1CTRL_REFREN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
#define DAC_CH1CTRL_PRSEN (0x1UL << 2) /**< Channel 1 PRS Trigger Enable */
#define _DAC_CH1CTRL_PRSEN_SHIFT 2 /**< Shift value for DAC_PRSEN */
#define _DAC_CH1CTRL_PRSEN_MASK 0x4UL /**< Bit mask for DAC_PRSEN */
#define _DAC_CH1CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
#define DAC_CH1CTRL_PRSEN_DEFAULT (_DAC_CH1CTRL_PRSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
#define _DAC_CH1CTRL_PRSSEL_SHIFT 4 /**< Shift value for DAC_PRSSEL */
#define _DAC_CH1CTRL_PRSSEL_MASK 0xF0UL /**< Bit mask for DAC_PRSSEL */
#define _DAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
#define _DAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for DAC_CH1CTRL */
#define _DAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for DAC_CH1CTRL */
#define _DAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for DAC_CH1CTRL */
#define _DAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for DAC_CH1CTRL */
#define _DAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for DAC_CH1CTRL */
#define _DAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for DAC_CH1CTRL */
#define _DAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for DAC_CH1CTRL */
#define _DAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for DAC_CH1CTRL */
#define _DAC_CH1CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for DAC_CH1CTRL */
#define _DAC_CH1CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for DAC_CH1CTRL */
#define _DAC_CH1CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for DAC_CH1CTRL */
#define _DAC_CH1CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for DAC_CH1CTRL */
#define DAC_CH1CTRL_PRSSEL_DEFAULT (_DAC_CH1CTRL_PRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
#define DAC_CH1CTRL_PRSSEL_PRSCH0 (_DAC_CH1CTRL_PRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for DAC_CH1CTRL */
#define DAC_CH1CTRL_PRSSEL_PRSCH1 (_DAC_CH1CTRL_PRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for DAC_CH1CTRL */
#define DAC_CH1CTRL_PRSSEL_PRSCH2 (_DAC_CH1CTRL_PRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for DAC_CH1CTRL */
#define DAC_CH1CTRL_PRSSEL_PRSCH3 (_DAC_CH1CTRL_PRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for DAC_CH1CTRL */
#define DAC_CH1CTRL_PRSSEL_PRSCH4 (_DAC_CH1CTRL_PRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for DAC_CH1CTRL */
#define DAC_CH1CTRL_PRSSEL_PRSCH5 (_DAC_CH1CTRL_PRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for DAC_CH1CTRL */
#define DAC_CH1CTRL_PRSSEL_PRSCH6 (_DAC_CH1CTRL_PRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for DAC_CH1CTRL */
#define DAC_CH1CTRL_PRSSEL_PRSCH7 (_DAC_CH1CTRL_PRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for DAC_CH1CTRL */
#define DAC_CH1CTRL_PRSSEL_PRSCH8 (_DAC_CH1CTRL_PRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for DAC_CH1CTRL */
#define DAC_CH1CTRL_PRSSEL_PRSCH9 (_DAC_CH1CTRL_PRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for DAC_CH1CTRL */
#define DAC_CH1CTRL_PRSSEL_PRSCH10 (_DAC_CH1CTRL_PRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for DAC_CH1CTRL */
#define DAC_CH1CTRL_PRSSEL_PRSCH11 (_DAC_CH1CTRL_PRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for DAC_CH1CTRL */
/* Bit fields for DAC IEN */
#define _DAC_IEN_RESETVALUE 0x00000000UL /**< Default value for DAC_IEN */
#define _DAC_IEN_MASK 0x00000033UL /**< Mask for DAC_IEN */
#define DAC_IEN_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Enable */
#define _DAC_IEN_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
#define _DAC_IEN_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
#define _DAC_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
#define DAC_IEN_CH0_DEFAULT (_DAC_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IEN */
#define DAC_IEN_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Enable */
#define _DAC_IEN_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
#define _DAC_IEN_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
#define _DAC_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
#define DAC_IEN_CH1_DEFAULT (_DAC_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IEN */
#define DAC_IEN_CH0UF (0x1UL << 4) /**< Channel 0 Conversion Data Underflow Interrupt Enable */
#define _DAC_IEN_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
#define _DAC_IEN_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
#define _DAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
#define DAC_IEN_CH0UF_DEFAULT (_DAC_IEN_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IEN */
#define DAC_IEN_CH1UF (0x1UL << 5) /**< Channel 1 Conversion Data Underflow Interrupt Enable */
#define _DAC_IEN_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
#define _DAC_IEN_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
#define _DAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
#define DAC_IEN_CH1UF_DEFAULT (_DAC_IEN_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IEN */
/* Bit fields for DAC IF */
#define _DAC_IF_RESETVALUE 0x00000000UL /**< Default value for DAC_IF */
#define _DAC_IF_MASK 0x00000033UL /**< Mask for DAC_IF */
#define DAC_IF_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Flag */
#define _DAC_IF_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
#define _DAC_IF_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
#define _DAC_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
#define DAC_IF_CH0_DEFAULT (_DAC_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IF */
#define DAC_IF_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Flag */
#define _DAC_IF_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
#define _DAC_IF_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
#define _DAC_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
#define DAC_IF_CH1_DEFAULT (_DAC_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IF */
#define DAC_IF_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag */
#define _DAC_IF_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
#define _DAC_IF_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
#define _DAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
#define DAC_IF_CH0UF_DEFAULT (_DAC_IF_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IF */
#define DAC_IF_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag */
#define _DAC_IF_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
#define _DAC_IF_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
#define _DAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
#define DAC_IF_CH1UF_DEFAULT (_DAC_IF_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IF */
/* Bit fields for DAC IFS */
#define _DAC_IFS_RESETVALUE 0x00000000UL /**< Default value for DAC_IFS */
#define _DAC_IFS_MASK 0x00000033UL /**< Mask for DAC_IFS */
#define DAC_IFS_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Flag Set */
#define _DAC_IFS_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
#define _DAC_IFS_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
#define _DAC_IFS_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
#define DAC_IFS_CH0_DEFAULT (_DAC_IFS_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IFS */
#define DAC_IFS_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Flag Set */
#define _DAC_IFS_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
#define _DAC_IFS_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
#define _DAC_IFS_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
#define DAC_IFS_CH1_DEFAULT (_DAC_IFS_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IFS */
#define DAC_IFS_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag Set */
#define _DAC_IFS_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
#define _DAC_IFS_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
#define _DAC_IFS_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
#define DAC_IFS_CH0UF_DEFAULT (_DAC_IFS_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IFS */
#define DAC_IFS_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag Set */
#define _DAC_IFS_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
#define _DAC_IFS_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
#define _DAC_IFS_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
#define DAC_IFS_CH1UF_DEFAULT (_DAC_IFS_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IFS */
/* Bit fields for DAC IFC */
#define _DAC_IFC_RESETVALUE 0x00000000UL /**< Default value for DAC_IFC */
#define _DAC_IFC_MASK 0x00000033UL /**< Mask for DAC_IFC */
#define DAC_IFC_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Flag Clear */
#define _DAC_IFC_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
#define _DAC_IFC_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
#define _DAC_IFC_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
#define DAC_IFC_CH0_DEFAULT (_DAC_IFC_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IFC */
#define DAC_IFC_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Flag Clear */
#define _DAC_IFC_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
#define _DAC_IFC_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
#define _DAC_IFC_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
#define DAC_IFC_CH1_DEFAULT (_DAC_IFC_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IFC */
#define DAC_IFC_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag Clear */
#define _DAC_IFC_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
#define _DAC_IFC_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
#define _DAC_IFC_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
#define DAC_IFC_CH0UF_DEFAULT (_DAC_IFC_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IFC */
#define DAC_IFC_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag Clear */
#define _DAC_IFC_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
#define _DAC_IFC_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
#define _DAC_IFC_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
#define DAC_IFC_CH1UF_DEFAULT (_DAC_IFC_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IFC */
/* Bit fields for DAC CH0DATA */
#define _DAC_CH0DATA_RESETVALUE 0x00000000UL /**< Default value for DAC_CH0DATA */
#define _DAC_CH0DATA_MASK 0x00000FFFUL /**< Mask for DAC_CH0DATA */
#define _DAC_CH0DATA_DATA_SHIFT 0 /**< Shift value for DAC_DATA */
#define _DAC_CH0DATA_DATA_MASK 0xFFFUL /**< Bit mask for DAC_DATA */
#define _DAC_CH0DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0DATA */
#define DAC_CH0DATA_DATA_DEFAULT (_DAC_CH0DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH0DATA */
/* Bit fields for DAC CH1DATA */
#define _DAC_CH1DATA_RESETVALUE 0x00000000UL /**< Default value for DAC_CH1DATA */
#define _DAC_CH1DATA_MASK 0x00000FFFUL /**< Mask for DAC_CH1DATA */
#define _DAC_CH1DATA_DATA_SHIFT 0 /**< Shift value for DAC_DATA */
#define _DAC_CH1DATA_DATA_MASK 0xFFFUL /**< Bit mask for DAC_DATA */
#define _DAC_CH1DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1DATA */
#define DAC_CH1DATA_DATA_DEFAULT (_DAC_CH1DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH1DATA */
/* Bit fields for DAC COMBDATA */
#define _DAC_COMBDATA_RESETVALUE 0x00000000UL /**< Default value for DAC_COMBDATA */
#define _DAC_COMBDATA_MASK 0x0FFF0FFFUL /**< Mask for DAC_COMBDATA */
#define _DAC_COMBDATA_CH0DATA_SHIFT 0 /**< Shift value for DAC_CH0DATA */
#define _DAC_COMBDATA_CH0DATA_MASK 0xFFFUL /**< Bit mask for DAC_CH0DATA */
#define _DAC_COMBDATA_CH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_COMBDATA */
#define DAC_COMBDATA_CH0DATA_DEFAULT (_DAC_COMBDATA_CH0DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_COMBDATA */
#define _DAC_COMBDATA_CH1DATA_SHIFT 16 /**< Shift value for DAC_CH1DATA */
#define _DAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL /**< Bit mask for DAC_CH1DATA */
#define _DAC_COMBDATA_CH1DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_COMBDATA */
#define DAC_COMBDATA_CH1DATA_DEFAULT (_DAC_COMBDATA_CH1DATA_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_COMBDATA */
/* Bit fields for DAC CAL */
#define _DAC_CAL_RESETVALUE 0x00400000UL /**< Default value for DAC_CAL */
#define _DAC_CAL_MASK 0x007F3F3FUL /**< Mask for DAC_CAL */
#define _DAC_CAL_CH0OFFSET_SHIFT 0 /**< Shift value for DAC_CH0OFFSET */
#define _DAC_CAL_CH0OFFSET_MASK 0x3FUL /**< Bit mask for DAC_CH0OFFSET */
#define _DAC_CAL_CH0OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CAL */
#define DAC_CAL_CH0OFFSET_DEFAULT (_DAC_CAL_CH0OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CAL */
#define _DAC_CAL_CH1OFFSET_SHIFT 8 /**< Shift value for DAC_CH1OFFSET */
#define _DAC_CAL_CH1OFFSET_MASK 0x3F00UL /**< Bit mask for DAC_CH1OFFSET */
#define _DAC_CAL_CH1OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CAL */
#define DAC_CAL_CH1OFFSET_DEFAULT (_DAC_CAL_CH1OFFSET_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_CAL */
#define _DAC_CAL_GAIN_SHIFT 16 /**< Shift value for DAC_GAIN */
#define _DAC_CAL_GAIN_MASK 0x7F0000UL /**< Bit mask for DAC_GAIN */
#define _DAC_CAL_GAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for DAC_CAL */
#define DAC_CAL_GAIN_DEFAULT (_DAC_CAL_GAIN_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_CAL */
/* Bit fields for DAC BIASPROG */
#define _DAC_BIASPROG_RESETVALUE 0x00004747UL /**< Default value for DAC_BIASPROG */
#define _DAC_BIASPROG_MASK 0x00004F4FUL /**< Mask for DAC_BIASPROG */
#define _DAC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for DAC_BIASPROG */
#define _DAC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for DAC_BIASPROG */
#define _DAC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for DAC_BIASPROG */
#define DAC_BIASPROG_BIASPROG_DEFAULT (_DAC_BIASPROG_BIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_BIASPROG */
#define DAC_BIASPROG_HALFBIAS (0x1UL << 6) /**< Half Bias Current */
#define _DAC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for DAC_HALFBIAS */
#define _DAC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for DAC_HALFBIAS */
#define _DAC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_BIASPROG */
#define DAC_BIASPROG_HALFBIAS_DEFAULT (_DAC_BIASPROG_HALFBIAS_DEFAULT << 6) /**< Shifted mode DEFAULT for DAC_BIASPROG */
#define _DAC_BIASPROG_OPA2BIASPROG_SHIFT 8 /**< Shift value for DAC_OPA2BIASPROG */
#define _DAC_BIASPROG_OPA2BIASPROG_MASK 0xF00UL /**< Bit mask for DAC_OPA2BIASPROG */
#define _DAC_BIASPROG_OPA2BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for DAC_BIASPROG */
#define DAC_BIASPROG_OPA2BIASPROG_DEFAULT (_DAC_BIASPROG_OPA2BIASPROG_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_BIASPROG */
#define DAC_BIASPROG_OPA2HALFBIAS (0x1UL << 14) /**< Half Bias Current */
#define _DAC_BIASPROG_OPA2HALFBIAS_SHIFT 14 /**< Shift value for DAC_OPA2HALFBIAS */
#define _DAC_BIASPROG_OPA2HALFBIAS_MASK 0x4000UL /**< Bit mask for DAC_OPA2HALFBIAS */
#define _DAC_BIASPROG_OPA2HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_BIASPROG */
#define DAC_BIASPROG_OPA2HALFBIAS_DEFAULT (_DAC_BIASPROG_OPA2HALFBIAS_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_BIASPROG */
/* Bit fields for DAC OPACTRL */
#define _DAC_OPACTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_OPACTRL */
#define _DAC_OPACTRL_MASK 0x01C3F1C7UL /**< Mask for DAC_OPACTRL */
#define DAC_OPACTRL_OPA0EN (0x1UL << 0) /**< OPA0 Enable */
#define _DAC_OPACTRL_OPA0EN_SHIFT 0 /**< Shift value for DAC_OPA0EN */
#define _DAC_OPACTRL_OPA0EN_MASK 0x1UL /**< Bit mask for DAC_OPA0EN */
#define _DAC_OPACTRL_OPA0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA0EN_DEFAULT (_DAC_OPACTRL_OPA0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA1EN (0x1UL << 1) /**< OPA1 Enable */
#define _DAC_OPACTRL_OPA1EN_SHIFT 1 /**< Shift value for DAC_OPA1EN */
#define _DAC_OPACTRL_OPA1EN_MASK 0x2UL /**< Bit mask for DAC_OPA1EN */
#define _DAC_OPACTRL_OPA1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA1EN_DEFAULT (_DAC_OPACTRL_OPA1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA2EN (0x1UL << 2) /**< OPA2 Enable */
#define _DAC_OPACTRL_OPA2EN_SHIFT 2 /**< Shift value for DAC_OPA2EN */
#define _DAC_OPACTRL_OPA2EN_MASK 0x4UL /**< Bit mask for DAC_OPA2EN */
#define _DAC_OPACTRL_OPA2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA2EN_DEFAULT (_DAC_OPACTRL_OPA2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA0HCMDIS (0x1UL << 6) /**< High Common Mode Disable. */
#define _DAC_OPACTRL_OPA0HCMDIS_SHIFT 6 /**< Shift value for DAC_OPA0HCMDIS */
#define _DAC_OPACTRL_OPA0HCMDIS_MASK 0x40UL /**< Bit mask for DAC_OPA0HCMDIS */
#define _DAC_OPACTRL_OPA0HCMDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA0HCMDIS_DEFAULT (_DAC_OPACTRL_OPA0HCMDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA1HCMDIS (0x1UL << 7) /**< High Common Mode Disable. */
#define _DAC_OPACTRL_OPA1HCMDIS_SHIFT 7 /**< Shift value for DAC_OPA1HCMDIS */
#define _DAC_OPACTRL_OPA1HCMDIS_MASK 0x80UL /**< Bit mask for DAC_OPA1HCMDIS */
#define _DAC_OPACTRL_OPA1HCMDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA1HCMDIS_DEFAULT (_DAC_OPACTRL_OPA1HCMDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA2HCMDIS (0x1UL << 8) /**< High Common Mode Disable. */
#define _DAC_OPACTRL_OPA2HCMDIS_SHIFT 8 /**< Shift value for DAC_OPA2HCMDIS */
#define _DAC_OPACTRL_OPA2HCMDIS_MASK 0x100UL /**< Bit mask for DAC_OPA2HCMDIS */
#define _DAC_OPACTRL_OPA2HCMDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA2HCMDIS_DEFAULT (_DAC_OPACTRL_OPA2HCMDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPACTRL */
#define _DAC_OPACTRL_OPA0LPFDIS_SHIFT 12 /**< Shift value for DAC_OPA0LPFDIS */
#define _DAC_OPACTRL_OPA0LPFDIS_MASK 0x3000UL /**< Bit mask for DAC_OPA0LPFDIS */
#define _DAC_OPACTRL_OPA0LPFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
#define _DAC_OPACTRL_OPA0LPFDIS_PLPFDIS 0x00000001UL /**< Mode PLPFDIS for DAC_OPACTRL */
#define _DAC_OPACTRL_OPA0LPFDIS_NLPFDIS 0x00000002UL /**< Mode NLPFDIS for DAC_OPACTRL */
#define DAC_OPACTRL_OPA0LPFDIS_DEFAULT (_DAC_OPACTRL_OPA0LPFDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA0LPFDIS_PLPFDIS (_DAC_OPACTRL_OPA0LPFDIS_PLPFDIS << 12) /**< Shifted mode PLPFDIS for DAC_OPACTRL */
#define DAC_OPACTRL_OPA0LPFDIS_NLPFDIS (_DAC_OPACTRL_OPA0LPFDIS_NLPFDIS << 12) /**< Shifted mode NLPFDIS for DAC_OPACTRL */
#define _DAC_OPACTRL_OPA1LPFDIS_SHIFT 14 /**< Shift value for DAC_OPA1LPFDIS */
#define _DAC_OPACTRL_OPA1LPFDIS_MASK 0xC000UL /**< Bit mask for DAC_OPA1LPFDIS */
#define _DAC_OPACTRL_OPA1LPFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
#define _DAC_OPACTRL_OPA1LPFDIS_PLPFDIS 0x00000001UL /**< Mode PLPFDIS for DAC_OPACTRL */
#define _DAC_OPACTRL_OPA1LPFDIS_NLPFDIS 0x00000002UL /**< Mode NLPFDIS for DAC_OPACTRL */
#define DAC_OPACTRL_OPA1LPFDIS_DEFAULT (_DAC_OPACTRL_OPA1LPFDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA1LPFDIS_PLPFDIS (_DAC_OPACTRL_OPA1LPFDIS_PLPFDIS << 14) /**< Shifted mode PLPFDIS for DAC_OPACTRL */
#define DAC_OPACTRL_OPA1LPFDIS_NLPFDIS (_DAC_OPACTRL_OPA1LPFDIS_NLPFDIS << 14) /**< Shifted mode NLPFDIS for DAC_OPACTRL */
#define _DAC_OPACTRL_OPA2LPFDIS_SHIFT 16 /**< Shift value for DAC_OPA2LPFDIS */
#define _DAC_OPACTRL_OPA2LPFDIS_MASK 0x30000UL /**< Bit mask for DAC_OPA2LPFDIS */
#define _DAC_OPACTRL_OPA2LPFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
#define _DAC_OPACTRL_OPA2LPFDIS_PLPFDIS 0x00000001UL /**< Mode PLPFDIS for DAC_OPACTRL */
#define _DAC_OPACTRL_OPA2LPFDIS_NLPFDIS 0x00000002UL /**< Mode NLPFDIS for DAC_OPACTRL */
#define DAC_OPACTRL_OPA2LPFDIS_DEFAULT (_DAC_OPACTRL_OPA2LPFDIS_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA2LPFDIS_PLPFDIS (_DAC_OPACTRL_OPA2LPFDIS_PLPFDIS << 16) /**< Shifted mode PLPFDIS for DAC_OPACTRL */
#define DAC_OPACTRL_OPA2LPFDIS_NLPFDIS (_DAC_OPACTRL_OPA2LPFDIS_NLPFDIS << 16) /**< Shifted mode NLPFDIS for DAC_OPACTRL */
#define DAC_OPACTRL_OPA0SHORT (0x1UL << 22) /**< Short the non-inverting and inverting input. */
#define _DAC_OPACTRL_OPA0SHORT_SHIFT 22 /**< Shift value for DAC_OPA0SHORT */
#define _DAC_OPACTRL_OPA0SHORT_MASK 0x400000UL /**< Bit mask for DAC_OPA0SHORT */
#define _DAC_OPACTRL_OPA0SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA0SHORT_DEFAULT (_DAC_OPACTRL_OPA0SHORT_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA1SHORT (0x1UL << 23) /**< Short the non-inverting and inverting input. */
#define _DAC_OPACTRL_OPA1SHORT_SHIFT 23 /**< Shift value for DAC_OPA1SHORT */
#define _DAC_OPACTRL_OPA1SHORT_MASK 0x800000UL /**< Bit mask for DAC_OPA1SHORT */
#define _DAC_OPACTRL_OPA1SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA1SHORT_DEFAULT (_DAC_OPACTRL_OPA1SHORT_DEFAULT << 23) /**< Shifted mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA2SHORT (0x1UL << 24) /**< Short the non-inverting and inverting input. */
#define _DAC_OPACTRL_OPA2SHORT_SHIFT 24 /**< Shift value for DAC_OPA2SHORT */
#define _DAC_OPACTRL_OPA2SHORT_MASK 0x1000000UL /**< Bit mask for DAC_OPA2SHORT */
#define _DAC_OPACTRL_OPA2SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
#define DAC_OPACTRL_OPA2SHORT_DEFAULT (_DAC_OPACTRL_OPA2SHORT_DEFAULT << 24) /**< Shifted mode DEFAULT for DAC_OPACTRL */
/* Bit fields for DAC OPAOFFSET */
#define _DAC_OPAOFFSET_RESETVALUE 0x00000020UL /**< Default value for DAC_OPAOFFSET */
#define _DAC_OPAOFFSET_MASK 0x0000003FUL /**< Mask for DAC_OPAOFFSET */
#define _DAC_OPAOFFSET_OPA2OFFSET_SHIFT 0 /**< Shift value for DAC_OPA2OFFSET */
#define _DAC_OPAOFFSET_OPA2OFFSET_MASK 0x3FUL /**< Bit mask for DAC_OPA2OFFSET */
#define _DAC_OPAOFFSET_OPA2OFFSET_DEFAULT 0x00000020UL /**< Mode DEFAULT for DAC_OPAOFFSET */
#define DAC_OPAOFFSET_OPA2OFFSET_DEFAULT (_DAC_OPAOFFSET_OPA2OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPAOFFSET */
/* Bit fields for DAC OPA0MUX */
#define _DAC_OPA0MUX_RESETVALUE 0x00400000UL /**< Default value for DAC_OPA0MUX */
#define _DAC_OPA0MUX_MASK 0x74C7F737UL /**< Mask for DAC_OPA0MUX */
#define _DAC_OPA0MUX_POSSEL_SHIFT 0 /**< Shift value for DAC_POSSEL */
#define _DAC_OPA0MUX_POSSEL_MASK 0x7UL /**< Bit mask for DAC_POSSEL */
#define _DAC_OPA0MUX_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
#define _DAC_OPA0MUX_POSSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
#define _DAC_OPA0MUX_POSSEL_DAC 0x00000001UL /**< Mode DAC for DAC_OPA0MUX */
#define _DAC_OPA0MUX_POSSEL_POSPAD 0x00000002UL /**< Mode POSPAD for DAC_OPA0MUX */
#define _DAC_OPA0MUX_POSSEL_OPA0INP 0x00000003UL /**< Mode OPA0INP for DAC_OPA0MUX */
#define _DAC_OPA0MUX_POSSEL_OPATAP 0x00000004UL /**< Mode OPATAP for DAC_OPA0MUX */
#define DAC_OPA0MUX_POSSEL_DEFAULT (_DAC_OPA0MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
#define DAC_OPA0MUX_POSSEL_DISABLE (_DAC_OPA0MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for DAC_OPA0MUX */
#define DAC_OPA0MUX_POSSEL_DAC (_DAC_OPA0MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for DAC_OPA0MUX */
#define DAC_OPA0MUX_POSSEL_POSPAD (_DAC_OPA0MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for DAC_OPA0MUX */
#define DAC_OPA0MUX_POSSEL_OPA0INP (_DAC_OPA0MUX_POSSEL_OPA0INP << 0) /**< Shifted mode OPA0INP for DAC_OPA0MUX */
#define DAC_OPA0MUX_POSSEL_OPATAP (_DAC_OPA0MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for DAC_OPA0MUX */
#define _DAC_OPA0MUX_NEGSEL_SHIFT 4 /**< Shift value for DAC_NEGSEL */
#define _DAC_OPA0MUX_NEGSEL_MASK 0x30UL /**< Bit mask for DAC_NEGSEL */
#define _DAC_OPA0MUX_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
#define _DAC_OPA0MUX_NEGSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
#define _DAC_OPA0MUX_NEGSEL_UG 0x00000001UL /**< Mode UG for DAC_OPA0MUX */
#define _DAC_OPA0MUX_NEGSEL_OPATAP 0x00000002UL /**< Mode OPATAP for DAC_OPA0MUX */
#define _DAC_OPA0MUX_NEGSEL_NEGPAD 0x00000003UL /**< Mode NEGPAD for DAC_OPA0MUX */
#define DAC_OPA0MUX_NEGSEL_DEFAULT (_DAC_OPA0MUX_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
#define DAC_OPA0MUX_NEGSEL_DISABLE (_DAC_OPA0MUX_NEGSEL_DISABLE << 4) /**< Shifted mode DISABLE for DAC_OPA0MUX */
#define DAC_OPA0MUX_NEGSEL_UG (_DAC_OPA0MUX_NEGSEL_UG << 4) /**< Shifted mode UG for DAC_OPA0MUX */
#define DAC_OPA0MUX_NEGSEL_OPATAP (_DAC_OPA0MUX_NEGSEL_OPATAP << 4) /**< Shifted mode OPATAP for DAC_OPA0MUX */
#define DAC_OPA0MUX_NEGSEL_NEGPAD (_DAC_OPA0MUX_NEGSEL_NEGPAD << 4) /**< Shifted mode NEGPAD for DAC_OPA0MUX */
#define _DAC_OPA0MUX_RESINMUX_SHIFT 8 /**< Shift value for DAC_RESINMUX */
#define _DAC_OPA0MUX_RESINMUX_MASK 0x700UL /**< Bit mask for DAC_RESINMUX */
#define _DAC_OPA0MUX_RESINMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
#define _DAC_OPA0MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
#define _DAC_OPA0MUX_RESINMUX_OPA0INP 0x00000001UL /**< Mode OPA0INP for DAC_OPA0MUX */
#define _DAC_OPA0MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for DAC_OPA0MUX */
#define _DAC_OPA0MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for DAC_OPA0MUX */
#define _DAC_OPA0MUX_RESINMUX_VSS 0x00000004UL /**< Mode VSS for DAC_OPA0MUX */
#define DAC_OPA0MUX_RESINMUX_DEFAULT (_DAC_OPA0MUX_RESINMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
#define DAC_OPA0MUX_RESINMUX_DISABLE (_DAC_OPA0MUX_RESINMUX_DISABLE << 8) /**< Shifted mode DISABLE for DAC_OPA0MUX */
#define DAC_OPA0MUX_RESINMUX_OPA0INP (_DAC_OPA0MUX_RESINMUX_OPA0INP << 8) /**< Shifted mode OPA0INP for DAC_OPA0MUX */
#define DAC_OPA0MUX_RESINMUX_NEGPAD (_DAC_OPA0MUX_RESINMUX_NEGPAD << 8) /**< Shifted mode NEGPAD for DAC_OPA0MUX */
#define DAC_OPA0MUX_RESINMUX_POSPAD (_DAC_OPA0MUX_RESINMUX_POSPAD << 8) /**< Shifted mode POSPAD for DAC_OPA0MUX */
#define DAC_OPA0MUX_RESINMUX_VSS (_DAC_OPA0MUX_RESINMUX_VSS << 8) /**< Shifted mode VSS for DAC_OPA0MUX */
#define DAC_OPA0MUX_PPEN (0x1UL << 12) /**< OPA0 Positive Pad Input Enable */
#define _DAC_OPA0MUX_PPEN_SHIFT 12 /**< Shift value for DAC_PPEN */
#define _DAC_OPA0MUX_PPEN_MASK 0x1000UL /**< Bit mask for DAC_PPEN */
#define _DAC_OPA0MUX_PPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
#define DAC_OPA0MUX_PPEN_DEFAULT (_DAC_OPA0MUX_PPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
#define DAC_OPA0MUX_NPEN (0x1UL << 13) /**< OPA0 Negative Pad Input Enable */
#define _DAC_OPA0MUX_NPEN_SHIFT 13 /**< Shift value for DAC_NPEN */
#define _DAC_OPA0MUX_NPEN_MASK 0x2000UL /**< Bit mask for DAC_NPEN */
#define _DAC_OPA0MUX_NPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
#define DAC_OPA0MUX_NPEN_DEFAULT (_DAC_OPA0MUX_NPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
#define _DAC_OPA0MUX_OUTPEN_SHIFT 14 /**< Shift value for DAC_OUTPEN */
#define _DAC_OPA0MUX_OUTPEN_MASK 0x7C000UL /**< Bit mask for DAC_OUTPEN */
#define _DAC_OPA0MUX_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
#define _DAC_OPA0MUX_OUTPEN_OUT0 0x00000001UL /**< Mode OUT0 for DAC_OPA0MUX */
#define _DAC_OPA0MUX_OUTPEN_OUT1 0x00000002UL /**< Mode OUT1 for DAC_OPA0MUX */
#define _DAC_OPA0MUX_OUTPEN_OUT2 0x00000004UL /**< Mode OUT2 for DAC_OPA0MUX */
#define _DAC_OPA0MUX_OUTPEN_OUT3 0x00000008UL /**< Mode OUT3 for DAC_OPA0MUX */
#define _DAC_OPA0MUX_OUTPEN_OUT4 0x00000010UL /**< Mode OUT4 for DAC_OPA0MUX */
#define DAC_OPA0MUX_OUTPEN_DEFAULT (_DAC_OPA0MUX_OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
#define DAC_OPA0MUX_OUTPEN_OUT0 (_DAC_OPA0MUX_OUTPEN_OUT0 << 14) /**< Shifted mode OUT0 for DAC_OPA0MUX */
#define DAC_OPA0MUX_OUTPEN_OUT1 (_DAC_OPA0MUX_OUTPEN_OUT1 << 14) /**< Shifted mode OUT1 for DAC_OPA0MUX */
#define DAC_OPA0MUX_OUTPEN_OUT2 (_DAC_OPA0MUX_OUTPEN_OUT2 << 14) /**< Shifted mode OUT2 for DAC_OPA0MUX */
#define DAC_OPA0MUX_OUTPEN_OUT3 (_DAC_OPA0MUX_OUTPEN_OUT3 << 14) /**< Shifted mode OUT3 for DAC_OPA0MUX */
#define DAC_OPA0MUX_OUTPEN_OUT4 (_DAC_OPA0MUX_OUTPEN_OUT4 << 14) /**< Shifted mode OUT4 for DAC_OPA0MUX */
#define _DAC_OPA0MUX_OUTMODE_SHIFT 22 /**< Shift value for DAC_OUTMODE */
#define _DAC_OPA0MUX_OUTMODE_MASK 0xC00000UL /**< Bit mask for DAC_OUTMODE */
#define _DAC_OPA0MUX_OUTMODE_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
#define _DAC_OPA0MUX_OUTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_OPA0MUX */
#define _DAC_OPA0MUX_OUTMODE_MAIN 0x00000001UL /**< Mode MAIN for DAC_OPA0MUX */
#define _DAC_OPA0MUX_OUTMODE_ALT 0x00000002UL /**< Mode ALT for DAC_OPA0MUX */
#define _DAC_OPA0MUX_OUTMODE_ALL 0x00000003UL /**< Mode ALL for DAC_OPA0MUX */
#define DAC_OPA0MUX_OUTMODE_DISABLE (_DAC_OPA0MUX_OUTMODE_DISABLE << 22) /**< Shifted mode DISABLE for DAC_OPA0MUX */
#define DAC_OPA0MUX_OUTMODE_DEFAULT (_DAC_OPA0MUX_OUTMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
#define DAC_OPA0MUX_OUTMODE_MAIN (_DAC_OPA0MUX_OUTMODE_MAIN << 22) /**< Shifted mode MAIN for DAC_OPA0MUX */
#define DAC_OPA0MUX_OUTMODE_ALT (_DAC_OPA0MUX_OUTMODE_ALT << 22) /**< Shifted mode ALT for DAC_OPA0MUX */
#define DAC_OPA0MUX_OUTMODE_ALL (_DAC_OPA0MUX_OUTMODE_ALL << 22) /**< Shifted mode ALL for DAC_OPA0MUX */
#define DAC_OPA0MUX_NEXTOUT (0x1UL << 26) /**< OPA0 Next Enable */
#define _DAC_OPA0MUX_NEXTOUT_SHIFT 26 /**< Shift value for DAC_NEXTOUT */
#define _DAC_OPA0MUX_NEXTOUT_MASK 0x4000000UL /**< Bit mask for DAC_NEXTOUT */
#define _DAC_OPA0MUX_NEXTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
#define DAC_OPA0MUX_NEXTOUT_DEFAULT (_DAC_OPA0MUX_NEXTOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
#define _DAC_OPA0MUX_RESSEL_SHIFT 28 /**< Shift value for DAC_RESSEL */
#define _DAC_OPA0MUX_RESSEL_MASK 0x70000000UL /**< Bit mask for DAC_RESSEL */
#define _DAC_OPA0MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
#define _DAC_OPA0MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for DAC_OPA0MUX */
#define _DAC_OPA0MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for DAC_OPA0MUX */
#define _DAC_OPA0MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for DAC_OPA0MUX */
#define _DAC_OPA0MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for DAC_OPA0MUX */
#define _DAC_OPA0MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for DAC_OPA0MUX */
#define _DAC_OPA0MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for DAC_OPA0MUX */
#define _DAC_OPA0MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for DAC_OPA0MUX */
#define _DAC_OPA0MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for DAC_OPA0MUX */
#define DAC_OPA0MUX_RESSEL_DEFAULT (_DAC_OPA0MUX_RESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
#define DAC_OPA0MUX_RESSEL_RES0 (_DAC_OPA0MUX_RESSEL_RES0 << 28) /**< Shifted mode RES0 for DAC_OPA0MUX */
#define DAC_OPA0MUX_RESSEL_RES1 (_DAC_OPA0MUX_RESSEL_RES1 << 28) /**< Shifted mode RES1 for DAC_OPA0MUX */
#define DAC_OPA0MUX_RESSEL_RES2 (_DAC_OPA0MUX_RESSEL_RES2 << 28) /**< Shifted mode RES2 for DAC_OPA0MUX */
#define DAC_OPA0MUX_RESSEL_RES3 (_DAC_OPA0MUX_RESSEL_RES3 << 28) /**< Shifted mode RES3 for DAC_OPA0MUX */
#define DAC_OPA0MUX_RESSEL_RES4 (_DAC_OPA0MUX_RESSEL_RES4 << 28) /**< Shifted mode RES4 for DAC_OPA0MUX */
#define DAC_OPA0MUX_RESSEL_RES5 (_DAC_OPA0MUX_RESSEL_RES5 << 28) /**< Shifted mode RES5 for DAC_OPA0MUX */
#define DAC_OPA0MUX_RESSEL_RES6 (_DAC_OPA0MUX_RESSEL_RES6 << 28) /**< Shifted mode RES6 for DAC_OPA0MUX */
#define DAC_OPA0MUX_RESSEL_RES7 (_DAC_OPA0MUX_RESSEL_RES7 << 28) /**< Shifted mode RES7 for DAC_OPA0MUX */
/* Bit fields for DAC OPA1MUX */
#define _DAC_OPA1MUX_RESETVALUE 0x00000000UL /**< Default value for DAC_OPA1MUX */
#define _DAC_OPA1MUX_MASK 0x74C7F737UL /**< Mask for DAC_OPA1MUX */
#define _DAC_OPA1MUX_POSSEL_SHIFT 0 /**< Shift value for DAC_POSSEL */
#define _DAC_OPA1MUX_POSSEL_MASK 0x7UL /**< Bit mask for DAC_POSSEL */
#define _DAC_OPA1MUX_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
#define _DAC_OPA1MUX_POSSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
#define _DAC_OPA1MUX_POSSEL_DAC 0x00000001UL /**< Mode DAC for DAC_OPA1MUX */
#define _DAC_OPA1MUX_POSSEL_POSPAD 0x00000002UL /**< Mode POSPAD for DAC_OPA1MUX */
#define _DAC_OPA1MUX_POSSEL_OPA0INP 0x00000003UL /**< Mode OPA0INP for DAC_OPA1MUX */
#define _DAC_OPA1MUX_POSSEL_OPATAP 0x00000004UL /**< Mode OPATAP for DAC_OPA1MUX */
#define DAC_OPA1MUX_POSSEL_DEFAULT (_DAC_OPA1MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
#define DAC_OPA1MUX_POSSEL_DISABLE (_DAC_OPA1MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for DAC_OPA1MUX */
#define DAC_OPA1MUX_POSSEL_DAC (_DAC_OPA1MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for DAC_OPA1MUX */
#define DAC_OPA1MUX_POSSEL_POSPAD (_DAC_OPA1MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for DAC_OPA1MUX */
#define DAC_OPA1MUX_POSSEL_OPA0INP (_DAC_OPA1MUX_POSSEL_OPA0INP << 0) /**< Shifted mode OPA0INP for DAC_OPA1MUX */
#define DAC_OPA1MUX_POSSEL_OPATAP (_DAC_OPA1MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for DAC_OPA1MUX */
#define _DAC_OPA1MUX_NEGSEL_SHIFT 4 /**< Shift value for DAC_NEGSEL */
#define _DAC_OPA1MUX_NEGSEL_MASK 0x30UL /**< Bit mask for DAC_NEGSEL */
#define _DAC_OPA1MUX_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
#define _DAC_OPA1MUX_NEGSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
#define _DAC_OPA1MUX_NEGSEL_UG 0x00000001UL /**< Mode UG for DAC_OPA1MUX */
#define _DAC_OPA1MUX_NEGSEL_OPATAP 0x00000002UL /**< Mode OPATAP for DAC_OPA1MUX */
#define _DAC_OPA1MUX_NEGSEL_NEGPAD 0x00000003UL /**< Mode NEGPAD for DAC_OPA1MUX */
#define DAC_OPA1MUX_NEGSEL_DEFAULT (_DAC_OPA1MUX_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
#define DAC_OPA1MUX_NEGSEL_DISABLE (_DAC_OPA1MUX_NEGSEL_DISABLE << 4) /**< Shifted mode DISABLE for DAC_OPA1MUX */
#define DAC_OPA1MUX_NEGSEL_UG (_DAC_OPA1MUX_NEGSEL_UG << 4) /**< Shifted mode UG for DAC_OPA1MUX */
#define DAC_OPA1MUX_NEGSEL_OPATAP (_DAC_OPA1MUX_NEGSEL_OPATAP << 4) /**< Shifted mode OPATAP for DAC_OPA1MUX */
#define DAC_OPA1MUX_NEGSEL_NEGPAD (_DAC_OPA1MUX_NEGSEL_NEGPAD << 4) /**< Shifted mode NEGPAD for DAC_OPA1MUX */
#define _DAC_OPA1MUX_RESINMUX_SHIFT 8 /**< Shift value for DAC_RESINMUX */
#define _DAC_OPA1MUX_RESINMUX_MASK 0x700UL /**< Bit mask for DAC_RESINMUX */
#define _DAC_OPA1MUX_RESINMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
#define _DAC_OPA1MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
#define _DAC_OPA1MUX_RESINMUX_OPA0INP 0x00000001UL /**< Mode OPA0INP for DAC_OPA1MUX */
#define _DAC_OPA1MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for DAC_OPA1MUX */
#define _DAC_OPA1MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for DAC_OPA1MUX */
#define _DAC_OPA1MUX_RESINMUX_VSS 0x00000004UL /**< Mode VSS for DAC_OPA1MUX */
#define DAC_OPA1MUX_RESINMUX_DEFAULT (_DAC_OPA1MUX_RESINMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
#define DAC_OPA1MUX_RESINMUX_DISABLE (_DAC_OPA1MUX_RESINMUX_DISABLE << 8) /**< Shifted mode DISABLE for DAC_OPA1MUX */
#define DAC_OPA1MUX_RESINMUX_OPA0INP (_DAC_OPA1MUX_RESINMUX_OPA0INP << 8) /**< Shifted mode OPA0INP for DAC_OPA1MUX */
#define DAC_OPA1MUX_RESINMUX_NEGPAD (_DAC_OPA1MUX_RESINMUX_NEGPAD << 8) /**< Shifted mode NEGPAD for DAC_OPA1MUX */
#define DAC_OPA1MUX_RESINMUX_POSPAD (_DAC_OPA1MUX_RESINMUX_POSPAD << 8) /**< Shifted mode POSPAD for DAC_OPA1MUX */
#define DAC_OPA1MUX_RESINMUX_VSS (_DAC_OPA1MUX_RESINMUX_VSS << 8) /**< Shifted mode VSS for DAC_OPA1MUX */
#define DAC_OPA1MUX_PPEN (0x1UL << 12) /**< OPA1 Positive Pad Input Enable */
#define _DAC_OPA1MUX_PPEN_SHIFT 12 /**< Shift value for DAC_PPEN */
#define _DAC_OPA1MUX_PPEN_MASK 0x1000UL /**< Bit mask for DAC_PPEN */
#define _DAC_OPA1MUX_PPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
#define DAC_OPA1MUX_PPEN_DEFAULT (_DAC_OPA1MUX_PPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
#define DAC_OPA1MUX_NPEN (0x1UL << 13) /**< OPA1 Negative Pad Input Enable */
#define _DAC_OPA1MUX_NPEN_SHIFT 13 /**< Shift value for DAC_NPEN */
#define _DAC_OPA1MUX_NPEN_MASK 0x2000UL /**< Bit mask for DAC_NPEN */
#define _DAC_OPA1MUX_NPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
#define DAC_OPA1MUX_NPEN_DEFAULT (_DAC_OPA1MUX_NPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
#define _DAC_OPA1MUX_OUTPEN_SHIFT 14 /**< Shift value for DAC_OUTPEN */
#define _DAC_OPA1MUX_OUTPEN_MASK 0x7C000UL /**< Bit mask for DAC_OUTPEN */
#define _DAC_OPA1MUX_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
#define _DAC_OPA1MUX_OUTPEN_OUT0 0x00000001UL /**< Mode OUT0 for DAC_OPA1MUX */
#define _DAC_OPA1MUX_OUTPEN_OUT1 0x00000002UL /**< Mode OUT1 for DAC_OPA1MUX */
#define _DAC_OPA1MUX_OUTPEN_OUT2 0x00000004UL /**< Mode OUT2 for DAC_OPA1MUX */
#define _DAC_OPA1MUX_OUTPEN_OUT3 0x00000008UL /**< Mode OUT3 for DAC_OPA1MUX */
#define _DAC_OPA1MUX_OUTPEN_OUT4 0x00000010UL /**< Mode OUT4 for DAC_OPA1MUX */
#define DAC_OPA1MUX_OUTPEN_DEFAULT (_DAC_OPA1MUX_OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
#define DAC_OPA1MUX_OUTPEN_OUT0 (_DAC_OPA1MUX_OUTPEN_OUT0 << 14) /**< Shifted mode OUT0 for DAC_OPA1MUX */
#define DAC_OPA1MUX_OUTPEN_OUT1 (_DAC_OPA1MUX_OUTPEN_OUT1 << 14) /**< Shifted mode OUT1 for DAC_OPA1MUX */
#define DAC_OPA1MUX_OUTPEN_OUT2 (_DAC_OPA1MUX_OUTPEN_OUT2 << 14) /**< Shifted mode OUT2 for DAC_OPA1MUX */
#define DAC_OPA1MUX_OUTPEN_OUT3 (_DAC_OPA1MUX_OUTPEN_OUT3 << 14) /**< Shifted mode OUT3 for DAC_OPA1MUX */
#define DAC_OPA1MUX_OUTPEN_OUT4 (_DAC_OPA1MUX_OUTPEN_OUT4 << 14) /**< Shifted mode OUT4 for DAC_OPA1MUX */
#define _DAC_OPA1MUX_OUTMODE_SHIFT 22 /**< Shift value for DAC_OUTMODE */
#define _DAC_OPA1MUX_OUTMODE_MASK 0xC00000UL /**< Bit mask for DAC_OUTMODE */
#define _DAC_OPA1MUX_OUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
#define _DAC_OPA1MUX_OUTMODE_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
#define _DAC_OPA1MUX_OUTMODE_MAIN 0x00000001UL /**< Mode MAIN for DAC_OPA1MUX */
#define _DAC_OPA1MUX_OUTMODE_ALT 0x00000002UL /**< Mode ALT for DAC_OPA1MUX */
#define _DAC_OPA1MUX_OUTMODE_ALL 0x00000003UL /**< Mode ALL for DAC_OPA1MUX */
#define DAC_OPA1MUX_OUTMODE_DEFAULT (_DAC_OPA1MUX_OUTMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
#define DAC_OPA1MUX_OUTMODE_DISABLE (_DAC_OPA1MUX_OUTMODE_DISABLE << 22) /**< Shifted mode DISABLE for DAC_OPA1MUX */
#define DAC_OPA1MUX_OUTMODE_MAIN (_DAC_OPA1MUX_OUTMODE_MAIN << 22) /**< Shifted mode MAIN for DAC_OPA1MUX */
#define DAC_OPA1MUX_OUTMODE_ALT (_DAC_OPA1MUX_OUTMODE_ALT << 22) /**< Shifted mode ALT for DAC_OPA1MUX */
#define DAC_OPA1MUX_OUTMODE_ALL (_DAC_OPA1MUX_OUTMODE_ALL << 22) /**< Shifted mode ALL for DAC_OPA1MUX */
#define DAC_OPA1MUX_NEXTOUT (0x1UL << 26) /**< OPA1 Next Enable */
#define _DAC_OPA1MUX_NEXTOUT_SHIFT 26 /**< Shift value for DAC_NEXTOUT */
#define _DAC_OPA1MUX_NEXTOUT_MASK 0x4000000UL /**< Bit mask for DAC_NEXTOUT */
#define _DAC_OPA1MUX_NEXTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
#define DAC_OPA1MUX_NEXTOUT_DEFAULT (_DAC_OPA1MUX_NEXTOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
#define _DAC_OPA1MUX_RESSEL_SHIFT 28 /**< Shift value for DAC_RESSEL */
#define _DAC_OPA1MUX_RESSEL_MASK 0x70000000UL /**< Bit mask for DAC_RESSEL */
#define _DAC_OPA1MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
#define _DAC_OPA1MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for DAC_OPA1MUX */
#define _DAC_OPA1MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for DAC_OPA1MUX */
#define _DAC_OPA1MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for DAC_OPA1MUX */
#define _DAC_OPA1MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for DAC_OPA1MUX */
#define _DAC_OPA1MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for DAC_OPA1MUX */
#define _DAC_OPA1MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for DAC_OPA1MUX */
#define _DAC_OPA1MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for DAC_OPA1MUX */
#define _DAC_OPA1MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for DAC_OPA1MUX */
#define DAC_OPA1MUX_RESSEL_DEFAULT (_DAC_OPA1MUX_RESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
#define DAC_OPA1MUX_RESSEL_RES0 (_DAC_OPA1MUX_RESSEL_RES0 << 28) /**< Shifted mode RES0 for DAC_OPA1MUX */
#define DAC_OPA1MUX_RESSEL_RES1 (_DAC_OPA1MUX_RESSEL_RES1 << 28) /**< Shifted mode RES1 for DAC_OPA1MUX */
#define DAC_OPA1MUX_RESSEL_RES2 (_DAC_OPA1MUX_RESSEL_RES2 << 28) /**< Shifted mode RES2 for DAC_OPA1MUX */
#define DAC_OPA1MUX_RESSEL_RES3 (_DAC_OPA1MUX_RESSEL_RES3 << 28) /**< Shifted mode RES3 for DAC_OPA1MUX */
#define DAC_OPA1MUX_RESSEL_RES4 (_DAC_OPA1MUX_RESSEL_RES4 << 28) /**< Shifted mode RES4 for DAC_OPA1MUX */
#define DAC_OPA1MUX_RESSEL_RES5 (_DAC_OPA1MUX_RESSEL_RES5 << 28) /**< Shifted mode RES5 for DAC_OPA1MUX */
#define DAC_OPA1MUX_RESSEL_RES6 (_DAC_OPA1MUX_RESSEL_RES6 << 28) /**< Shifted mode RES6 for DAC_OPA1MUX */
#define DAC_OPA1MUX_RESSEL_RES7 (_DAC_OPA1MUX_RESSEL_RES7 << 28) /**< Shifted mode RES7 for DAC_OPA1MUX */
/* Bit fields for DAC OPA2MUX */
#define _DAC_OPA2MUX_RESETVALUE 0x00000000UL /**< Default value for DAC_OPA2MUX */
#define _DAC_OPA2MUX_MASK 0x7440F737UL /**< Mask for DAC_OPA2MUX */
#define _DAC_OPA2MUX_POSSEL_SHIFT 0 /**< Shift value for DAC_POSSEL */
#define _DAC_OPA2MUX_POSSEL_MASK 0x7UL /**< Bit mask for DAC_POSSEL */
#define _DAC_OPA2MUX_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
#define _DAC_OPA2MUX_POSSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA2MUX */
#define _DAC_OPA2MUX_POSSEL_POSPAD 0x00000002UL /**< Mode POSPAD for DAC_OPA2MUX */
#define _DAC_OPA2MUX_POSSEL_OPA1INP 0x00000003UL /**< Mode OPA1INP for DAC_OPA2MUX */
#define _DAC_OPA2MUX_POSSEL_OPATAP 0x00000004UL /**< Mode OPATAP for DAC_OPA2MUX */
#define DAC_OPA2MUX_POSSEL_DEFAULT (_DAC_OPA2MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
#define DAC_OPA2MUX_POSSEL_DISABLE (_DAC_OPA2MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for DAC_OPA2MUX */
#define DAC_OPA2MUX_POSSEL_POSPAD (_DAC_OPA2MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for DAC_OPA2MUX */
#define DAC_OPA2MUX_POSSEL_OPA1INP (_DAC_OPA2MUX_POSSEL_OPA1INP << 0) /**< Shifted mode OPA1INP for DAC_OPA2MUX */
#define DAC_OPA2MUX_POSSEL_OPATAP (_DAC_OPA2MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for DAC_OPA2MUX */
#define _DAC_OPA2MUX_NEGSEL_SHIFT 4 /**< Shift value for DAC_NEGSEL */
#define _DAC_OPA2MUX_NEGSEL_MASK 0x30UL /**< Bit mask for DAC_NEGSEL */
#define _DAC_OPA2MUX_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
#define _DAC_OPA2MUX_NEGSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA2MUX */
#define _DAC_OPA2MUX_NEGSEL_UG 0x00000001UL /**< Mode UG for DAC_OPA2MUX */
#define _DAC_OPA2MUX_NEGSEL_OPATAP 0x00000002UL /**< Mode OPATAP for DAC_OPA2MUX */
#define _DAC_OPA2MUX_NEGSEL_NEGPAD 0x00000003UL /**< Mode NEGPAD for DAC_OPA2MUX */
#define DAC_OPA2MUX_NEGSEL_DEFAULT (_DAC_OPA2MUX_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
#define DAC_OPA2MUX_NEGSEL_DISABLE (_DAC_OPA2MUX_NEGSEL_DISABLE << 4) /**< Shifted mode DISABLE for DAC_OPA2MUX */
#define DAC_OPA2MUX_NEGSEL_UG (_DAC_OPA2MUX_NEGSEL_UG << 4) /**< Shifted mode UG for DAC_OPA2MUX */
#define DAC_OPA2MUX_NEGSEL_OPATAP (_DAC_OPA2MUX_NEGSEL_OPATAP << 4) /**< Shifted mode OPATAP for DAC_OPA2MUX */
#define DAC_OPA2MUX_NEGSEL_NEGPAD (_DAC_OPA2MUX_NEGSEL_NEGPAD << 4) /**< Shifted mode NEGPAD for DAC_OPA2MUX */
#define _DAC_OPA2MUX_RESINMUX_SHIFT 8 /**< Shift value for DAC_RESINMUX */
#define _DAC_OPA2MUX_RESINMUX_MASK 0x700UL /**< Bit mask for DAC_RESINMUX */
#define _DAC_OPA2MUX_RESINMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
#define _DAC_OPA2MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA2MUX */
#define _DAC_OPA2MUX_RESINMUX_OPA1INP 0x00000001UL /**< Mode OPA1INP for DAC_OPA2MUX */
#define _DAC_OPA2MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for DAC_OPA2MUX */
#define _DAC_OPA2MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for DAC_OPA2MUX */
#define _DAC_OPA2MUX_RESINMUX_VSS 0x00000004UL /**< Mode VSS for DAC_OPA2MUX */
#define DAC_OPA2MUX_RESINMUX_DEFAULT (_DAC_OPA2MUX_RESINMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
#define DAC_OPA2MUX_RESINMUX_DISABLE (_DAC_OPA2MUX_RESINMUX_DISABLE << 8) /**< Shifted mode DISABLE for DAC_OPA2MUX */
#define DAC_OPA2MUX_RESINMUX_OPA1INP (_DAC_OPA2MUX_RESINMUX_OPA1INP << 8) /**< Shifted mode OPA1INP for DAC_OPA2MUX */
#define DAC_OPA2MUX_RESINMUX_NEGPAD (_DAC_OPA2MUX_RESINMUX_NEGPAD << 8) /**< Shifted mode NEGPAD for DAC_OPA2MUX */
#define DAC_OPA2MUX_RESINMUX_POSPAD (_DAC_OPA2MUX_RESINMUX_POSPAD << 8) /**< Shifted mode POSPAD for DAC_OPA2MUX */
#define DAC_OPA2MUX_RESINMUX_VSS (_DAC_OPA2MUX_RESINMUX_VSS << 8) /**< Shifted mode VSS for DAC_OPA2MUX */
#define DAC_OPA2MUX_PPEN (0x1UL << 12) /**< OPA2 Positive Pad Input Enable */
#define _DAC_OPA2MUX_PPEN_SHIFT 12 /**< Shift value for DAC_PPEN */
#define _DAC_OPA2MUX_PPEN_MASK 0x1000UL /**< Bit mask for DAC_PPEN */
#define _DAC_OPA2MUX_PPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
#define DAC_OPA2MUX_PPEN_DEFAULT (_DAC_OPA2MUX_PPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
#define DAC_OPA2MUX_NPEN (0x1UL << 13) /**< OPA2 Negative Pad Input Enable */
#define _DAC_OPA2MUX_NPEN_SHIFT 13 /**< Shift value for DAC_NPEN */
#define _DAC_OPA2MUX_NPEN_MASK 0x2000UL /**< Bit mask for DAC_NPEN */
#define _DAC_OPA2MUX_NPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
#define DAC_OPA2MUX_NPEN_DEFAULT (_DAC_OPA2MUX_NPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
#define _DAC_OPA2MUX_OUTPEN_SHIFT 14 /**< Shift value for DAC_OUTPEN */
#define _DAC_OPA2MUX_OUTPEN_MASK 0xC000UL /**< Bit mask for DAC_OUTPEN */
#define _DAC_OPA2MUX_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
#define _DAC_OPA2MUX_OUTPEN_OUT0 0x00000001UL /**< Mode OUT0 for DAC_OPA2MUX */
#define _DAC_OPA2MUX_OUTPEN_OUT1 0x00000002UL /**< Mode OUT1 for DAC_OPA2MUX */
#define DAC_OPA2MUX_OUTPEN_DEFAULT (_DAC_OPA2MUX_OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
#define DAC_OPA2MUX_OUTPEN_OUT0 (_DAC_OPA2MUX_OUTPEN_OUT0 << 14) /**< Shifted mode OUT0 for DAC_OPA2MUX */
#define DAC_OPA2MUX_OUTPEN_OUT1 (_DAC_OPA2MUX_OUTPEN_OUT1 << 14) /**< Shifted mode OUT1 for DAC_OPA2MUX */
#define DAC_OPA2MUX_OUTMODE (0x1UL << 22) /**< Output Select */
#define _DAC_OPA2MUX_OUTMODE_SHIFT 22 /**< Shift value for DAC_OUTMODE */
#define _DAC_OPA2MUX_OUTMODE_MASK 0x400000UL /**< Bit mask for DAC_OUTMODE */
#define _DAC_OPA2MUX_OUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
#define DAC_OPA2MUX_OUTMODE_DEFAULT (_DAC_OPA2MUX_OUTMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
#define DAC_OPA2MUX_NEXTOUT (0x1UL << 26) /**< OPA2 Next Enable */
#define _DAC_OPA2MUX_NEXTOUT_SHIFT 26 /**< Shift value for DAC_NEXTOUT */
#define _DAC_OPA2MUX_NEXTOUT_MASK 0x4000000UL /**< Bit mask for DAC_NEXTOUT */
#define _DAC_OPA2MUX_NEXTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
#define DAC_OPA2MUX_NEXTOUT_DEFAULT (_DAC_OPA2MUX_NEXTOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
#define _DAC_OPA2MUX_RESSEL_SHIFT 28 /**< Shift value for DAC_RESSEL */
#define _DAC_OPA2MUX_RESSEL_MASK 0x70000000UL /**< Bit mask for DAC_RESSEL */
#define _DAC_OPA2MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
#define _DAC_OPA2MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for DAC_OPA2MUX */
#define _DAC_OPA2MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for DAC_OPA2MUX */
#define _DAC_OPA2MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for DAC_OPA2MUX */
#define _DAC_OPA2MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for DAC_OPA2MUX */
#define _DAC_OPA2MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for DAC_OPA2MUX */
#define _DAC_OPA2MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for DAC_OPA2MUX */
#define _DAC_OPA2MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for DAC_OPA2MUX */
#define _DAC_OPA2MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for DAC_OPA2MUX */
#define DAC_OPA2MUX_RESSEL_DEFAULT (_DAC_OPA2MUX_RESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
#define DAC_OPA2MUX_RESSEL_RES0 (_DAC_OPA2MUX_RESSEL_RES0 << 28) /**< Shifted mode RES0 for DAC_OPA2MUX */
#define DAC_OPA2MUX_RESSEL_RES1 (_DAC_OPA2MUX_RESSEL_RES1 << 28) /**< Shifted mode RES1 for DAC_OPA2MUX */
#define DAC_OPA2MUX_RESSEL_RES2 (_DAC_OPA2MUX_RESSEL_RES2 << 28) /**< Shifted mode RES2 for DAC_OPA2MUX */
#define DAC_OPA2MUX_RESSEL_RES3 (_DAC_OPA2MUX_RESSEL_RES3 << 28) /**< Shifted mode RES3 for DAC_OPA2MUX */
#define DAC_OPA2MUX_RESSEL_RES4 (_DAC_OPA2MUX_RESSEL_RES4 << 28) /**< Shifted mode RES4 for DAC_OPA2MUX */
#define DAC_OPA2MUX_RESSEL_RES5 (_DAC_OPA2MUX_RESSEL_RES5 << 28) /**< Shifted mode RES5 for DAC_OPA2MUX */
#define DAC_OPA2MUX_RESSEL_RES6 (_DAC_OPA2MUX_RESSEL_RES6 << 28) /**< Shifted mode RES6 for DAC_OPA2MUX */
#define DAC_OPA2MUX_RESSEL_RES7 (_DAC_OPA2MUX_RESSEL_RES7 << 28) /**< Shifted mode RES7 for DAC_OPA2MUX */
/** @} End of group EFM32WG_DAC */

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/**************************************************************************//**
* @file efm32wg_devinfo.h
* @brief EFM32WG_DEVINFO register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_DEVINFO
* @{
*****************************************************************************/
typedef struct
{
__I uint32_t CAL; /**< Calibration temperature and checksum */
__I uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */
__I uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */
__I uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */
uint32_t RESERVED0[2]; /**< Reserved */
__I uint32_t DAC0CAL0; /**< DAC calibrartion register 0 */
__I uint32_t DAC0CAL1; /**< DAC calibrartion register 1 */
__I uint32_t DAC0CAL2; /**< DAC calibrartion register 2 */
__I uint32_t AUXHFRCOCAL0; /**< AUXHFRCO calibration register 0 */
__I uint32_t AUXHFRCOCAL1; /**< AUXHFRCO calibration register 1 */
__I uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */
__I uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */
__I uint32_t MEMINFO; /**< Memory information */
uint32_t RESERVED2[2]; /**< Reserved */
__I uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
__I uint32_t UNIQUEH; /**< High 32 bits of device unique number */
__I uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */
__I uint32_t PART; /**< Part description */
} DEVINFO_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_DEVINFO_BitFields
* @{
*****************************************************************************/
/* Bit fields for EFM32WG_DEVINFO */
#define _DEVINFO_CAL_CRC_MASK 0x0000FFFFUL /**< Integrity CRC checksum mask */
#define _DEVINFO_CAL_CRC_SHIFT 0 /**< Integrity CRC checksum shift */
#define _DEVINFO_CAL_TEMP_MASK 0x00FF0000UL /**< Calibration temperature, DegC, mask */
#define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Calibration temperature shift */
#define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL /**< Gain for 1V25 reference, mask */
#define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8 /**< Gain for 1V25 reference, shift */
#define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL /**< Offset for 1V25 reference, mask */
#define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT 0 /**< Offset for 1V25 reference, shift */
#define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK 0x7F000000UL /**< Gain for 2V5 reference, mask */
#define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24 /**< Gain for 2V5 reference, shift */
#define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL /**< Offset for 2V5 reference, mask */
#define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16 /**< Offset for 2V5 reference, shift */
#define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL /**< Gain for VDD reference, mask */
#define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8 /**< Gain for VDD reference, shift */
#define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL /**< Offset for VDD reference, mask */
#define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT 0 /**< Offset for VDD reference, shift */
#define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK 0x7F000000UL /**< Gain 5VDIFF for 5VDIFF reference, mask */
#define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24 /**< Gain for 5VDIFF reference, mask */
#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL /**< Offset for 5VDIFF reference, mask */
#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16 /**< Offset for 5VDIFF reference, shift */
#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL /**< Offset for 2XVDDVSS reference, mask */
#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0 /**< Offset for 2XVDDVSS reference, shift */
#define _DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL /**< Temperature reading at 1V25 reference, mask */
#define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20 /**< Temperature reading at 1V25 reference, DegC */
#define _DEVINFO_DAC0CAL0_1V25_GAIN_MASK 0x007F0000UL /**< Gain for 1V25 reference, mask */
#define _DEVINFO_DAC0CAL0_1V25_GAIN_SHIFT 16 /**< Gain for 1V25 reference, shift */
#define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for 1V25 reference, mask */
#define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for 1V25 reference, shift */
#define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for 1V25 reference, mask */
#define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for 1V25 reference, shift */
#define _DEVINFO_DAC0CAL1_2V5_GAIN_MASK 0x007F0000UL /**< Gain for 2V5 reference, mask */
#define _DEVINFO_DAC0CAL1_2V5_GAIN_SHIFT 16 /**< Gain for 2V5 reference, shift */
#define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for 2V5 reference, mask */
#define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for 2V5 reference, shift */
#define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for 2V5 reference, mask */
#define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for 2V5 reference, shift */
#define _DEVINFO_DAC0CAL2_VDD_GAIN_MASK 0x007F0000UL /**< Gain for VDD reference, mask */
#define _DEVINFO_DAC0CAL2_VDD_GAIN_SHIFT 16 /**< Gain for VDD reference, shift */
#define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for VDD reference, mask */
#define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for VDD reference, shift */
#define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for VDD reference, mask */
#define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for VDD reference, shift*/
#define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL1_BAND28_MASK 0x0000FF00UL /**< 28MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT 8 /**< 28MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL1_BAND28_MASK 0x0000FF00UL /**< 28MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL1_BAND28_SHIFT 8 /**< 28MHz tuning value for HFRCO, mask */
#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Flash page size (refer to ref.man for encoding) mask */
#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Flash page size shift */
#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Lower part of 64-bit device unique number */
#define _DEVINFO_UNIQUEL_SHIFT 0 /**< Unique Low 32-bit shift */
#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< High part of 64-bit device unique number */
#define _DEVINFO_UNIQUEH_SHIFT 0 /**< Unique High 32-bit shift */
#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Flash size in kilobytes */
#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Bit position for flash size */
#define _DEVINFO_MSIZE_FLASH_MASK 0x0000FFFFUL /**< SRAM size in kilobytes */
#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Bit position for SRAM size */
#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Production revision */
#define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Bit position for production revision */
#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL /**< Device Family, 0x47 for Gecko */
#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Bit position for device family */
/* Legacy family #defines */
#define _DEVINFO_PART_DEVICE_FAMILY_G 71 /**< Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_GG 72 /**< Giant Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_TG 73 /**< Tiny Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_LG 74 /**< Leopard Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_WG 75 /**< Wonder Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_ZG 76 /**< Zero Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_HG 77 /**< Happy Gecko Device Family */
/* New style family #defines */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 71 /**< Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 72 /**< Giant Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 73 /**< Tiny Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 74 /**< Leopard Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 75 /**< Wonder Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 76 /**< Zero Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 77 /**< Happy Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 120 /**< EZR Wonder Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 121 /**< EZR Leopard Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 122 /**< EZR Happy Gecko Device Family */
#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /**< Device number */
#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Bit position for device number */
/** @} End of group EFM32WG_DEVINFO */

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/**************************************************************************//**
* @file efm32wg_dma_ch.h
* @brief EFM32WG_DMA_CH register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @brief DMA_CH EFM32WG DMA CH
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Channel Control Register */
} DMA_CH_TypeDef;

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/**************************************************************************//**
* @file efm32wg_dma_descriptor.h
* @brief EFM32WG_DMA_DESCRIPTOR register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_DMA_DESCRIPTOR
* @{
*****************************************************************************/
typedef struct
{
/* Note! Use of double __IO (volatile) qualifier to ensure that both */
/* pointer and referenced memory are declared volatile. */
__IO void * __IO SRCEND; /**< DMA source address end */
__IO void * __IO DSTEND; /**< DMA destination address end */
__IO uint32_t CTRL; /**< DMA control register */
__IO uint32_t USER; /**< DMA padding register, available for user */
} DMA_DESCRIPTOR_TypeDef; /** @} */

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/**************************************************************************//**
* @file efm32wg_dmactrl.h
* @brief EFM32WG_DMACTRL register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_DMACTRL_BitFields
* @{
*****************************************************************************/
#define _DMA_CTRL_DST_INC_MASK 0xC0000000UL /**< Data increment for destination, bit mask */
#define _DMA_CTRL_DST_INC_SHIFT 30 /**< Data increment for destination, shift value */
#define _DMA_CTRL_DST_INC_BYTE 0x00 /**< Byte/8-bit increment */
#define _DMA_CTRL_DST_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
#define _DMA_CTRL_DST_INC_WORD 0x02 /**< Word/32-bit increment */
#define _DMA_CTRL_DST_INC_NONE 0x03 /**< No increment */
#define DMA_CTRL_DST_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
#define DMA_CTRL_DST_INC_HALFWORD 0x40000000UL /**< Half word/16-bit increment */
#define DMA_CTRL_DST_INC_WORD 0x80000000UL /**< Word/32-bit increment */
#define DMA_CTRL_DST_INC_NONE 0xC0000000UL /**< No increment */
#define _DMA_CTRL_DST_SIZE_MASK 0x30000000UL /**< Data size for destination - MUST be the same as source, bit mask */
#define _DMA_CTRL_DST_SIZE_SHIFT 28 /**< Data size for destination - MUST be the same as source, shift value */
#define _DMA_CTRL_DST_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
#define _DMA_CTRL_DST_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
#define _DMA_CTRL_DST_SIZE_WORD 0x02 /**< Word/32-bit data size */
#define _DMA_CTRL_DST_SIZE_RSVD 0x03 /**< Reserved */
#define DMA_CTRL_DST_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
#define DMA_CTRL_DST_SIZE_HALFWORD 0x10000000UL /**< Half word/16-bit data size */
#define DMA_CTRL_DST_SIZE_WORD 0x20000000UL /**< Word/32-bit data size */
#define DMA_CTRL_DST_SIZE_RSVD 0x30000000UL /**< Reserved - do not use */
#define _DMA_CTRL_SRC_INC_MASK 0x0C000000UL /**< Data increment for source, bit mask */
#define _DMA_CTRL_SRC_INC_SHIFT 26 /**< Data increment for source, shift value */
#define _DMA_CTRL_SRC_INC_BYTE 0x00 /**< Byte/8-bit increment */
#define _DMA_CTRL_SRC_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
#define _DMA_CTRL_SRC_INC_WORD 0x02 /**< Word/32-bit increment */
#define _DMA_CTRL_SRC_INC_NONE 0x03 /**< No increment */
#define DMA_CTRL_SRC_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
#define DMA_CTRL_SRC_INC_HALFWORD 0x04000000UL /**< Half word/16-bit increment */
#define DMA_CTRL_SRC_INC_WORD 0x08000000UL /**< Word/32-bit increment */
#define DMA_CTRL_SRC_INC_NONE 0x0C000000UL /**< No increment */
#define _DMA_CTRL_SRC_SIZE_MASK 0x03000000UL /**< Data size for source - MUST be the same as destination, bit mask */
#define _DMA_CTRL_SRC_SIZE_SHIFT 24 /**< Data size for source - MUST be the same as destination, shift value */
#define _DMA_CTRL_SRC_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
#define _DMA_CTRL_SRC_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
#define _DMA_CTRL_SRC_SIZE_WORD 0x02 /**< Word/32-bit data size */
#define _DMA_CTRL_SRC_SIZE_RSVD 0x03 /**< Reserved */
#define DMA_CTRL_SRC_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
#define DMA_CTRL_SRC_SIZE_HALFWORD 0x01000000UL /**< Half word/16-bit data size */
#define DMA_CTRL_SRC_SIZE_WORD 0x02000000UL /**< Word/32-bit data size */
#define DMA_CTRL_SRC_SIZE_RSVD 0x03000000UL /**< Reserved - do not use */
#define _DMA_CTRL_DST_PROT_CTRL_MASK 0x00E00000UL /**< Protection flag for destination, bit mask */
#define _DMA_CTRL_DST_PROT_CTRL_SHIFT 21 /**< Protection flag for destination, shift value */
#define DMA_CTRL_DST_PROT_PRIVILEGED 0x00200000UL /**< Privileged mode for destination */
#define DMA_CTRL_DST_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for destination */
#define _DMA_CTRL_SRC_PROT_CTRL_MASK 0x001C0000UL /**< Protection flag for source, bit mask */
#define _DMA_CTRL_SRC_PROT_CTRL_SHIFT 18 /**< Protection flag for source, shift value */
#define DMA_CTRL_SRC_PROT_PRIVILEGED 0x00040000UL /**< Privileged mode for destination */
#define DMA_CTRL_SRC_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for destination */
#define _DMA_CTRL_PROT_NON_PRIVILEGED 0x00 /**< Protection bits to indicate non-privileged access */
#define _DMA_CTRL_PROT_PRIVILEGED 0x01 /**< Protection bits to indicate privileged access */
#define _DMA_CTRL_R_POWER_MASK 0x0003C000UL /**< DMA arbitration mask */
#define _DMA_CTRL_R_POWER_SHIFT 14 /**< Number of DMA cycles before controller does new arbitration in 2^R */
#define _DMA_CTRL_R_POWER_1 0x00 /**< Arbitrate after each transfer */
#define _DMA_CTRL_R_POWER_2 0x01 /**< Arbitrate after every 2 transfers */
#define _DMA_CTRL_R_POWER_4 0x02 /**< Arbitrate after every 4 transfers */
#define _DMA_CTRL_R_POWER_8 0x03 /**< Arbitrate after every 8 transfers */
#define _DMA_CTRL_R_POWER_16 0x04 /**< Arbitrate after every 16 transfers */
#define _DMA_CTRL_R_POWER_32 0x05 /**< Arbitrate after every 32 transfers */
#define _DMA_CTRL_R_POWER_64 0x06 /**< Arbitrate after every 64 transfers */
#define _DMA_CTRL_R_POWER_128 0x07 /**< Arbitrate after every 128 transfers */
#define _DMA_CTRL_R_POWER_256 0x08 /**< Arbitrate after every 256 transfers */
#define _DMA_CTRL_R_POWER_512 0x09 /**< Arbitrate after every 512 transfers */
#define _DMA_CTRL_R_POWER_1024 0x0a /**< Arbitrate after every 1024 transfers */
#define DMA_CTRL_R_POWER_1 0x00000000UL /**< Arbitrate after each transfer */
#define DMA_CTRL_R_POWER_2 0x00004000UL /**< Arbitrate after every 2 transfers */
#define DMA_CTRL_R_POWER_4 0x00008000UL /**< Arbitrate after every 4 transfers */
#define DMA_CTRL_R_POWER_8 0x0000c000UL /**< Arbitrate after every 8 transfers */
#define DMA_CTRL_R_POWER_16 0x00010000UL /**< Arbitrate after every 16 transfers */
#define DMA_CTRL_R_POWER_32 0x00014000UL /**< Arbitrate after every 32 transfers */
#define DMA_CTRL_R_POWER_64 0x00018000UL /**< Arbitrate after every 64 transfers */
#define DMA_CTRL_R_POWER_128 0x0001c000UL /**< Arbitrate after every 128 transfers */
#define DMA_CTRL_R_POWER_256 0x00020000UL /**< Arbitrate after every 256 transfers */
#define DMA_CTRL_R_POWER_512 0x00024000UL /**< Arbitrate after every 512 transfers */
#define DMA_CTRL_R_POWER_1024 0x00028000UL /**< Arbitrate after every 1024 transfers */
#define _DMA_CTRL_N_MINUS_1_MASK 0x00003FF0UL /**< Number of DMA transfers minus 1, bit mask. See PL230 documentation */
#define _DMA_CTRL_N_MINUS_1_SHIFT 4 /**< Number of DMA transfers minus 1, shift mask. See PL230 documentation */
#define _DMA_CTRL_NEXT_USEBURST_MASK 0x00000008UL /**< DMA useburst_set[C] is 1 when using scatter-gather DMA and using alternate data */
#define _DMA_CTRL_NEXT_USEBURST_SHIFT 3 /**< DMA useburst shift */
#define _DMA_CTRL_CYCLE_CTRL_MASK 0x00000007UL /**< DMA Cycle control bit mask - basic/auto/ping-poing/scath-gath */
#define _DMA_CTRL_CYCLE_CTRL_SHIFT 0 /**< DMA Cycle control bit shift */
#define _DMA_CTRL_CYCLE_CTRL_INVALID 0x00 /**< Invalid cycle type */
#define _DMA_CTRL_CYCLE_CTRL_BASIC 0x01 /**< Basic cycle type */
#define _DMA_CTRL_CYCLE_CTRL_AUTO 0x02 /**< Auto cycle type */
#define _DMA_CTRL_CYCLE_CTRL_PINGPONG 0x03 /**< PingPong cycle type */
#define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x04 /**< Memory scatter gather cycle type */
#define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x05 /**< Memory scatter gather using alternate structure */
#define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x06 /**< Peripheral scatter gather cycle type */
#define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x07 /**< Peripheral scatter gather cycle type using alternate structure */
#define DMA_CTRL_CYCLE_CTRL_INVALID 0x00000000UL /**< Invalid cycle type */
#define DMA_CTRL_CYCLE_CTRL_BASIC 0x00000001UL /**< Basic cycle type */
#define DMA_CTRL_CYCLE_CTRL_AUTO 0x00000002UL /**< Auto cycle type */
#define DMA_CTRL_CYCLE_CTRL_PINGPONG 0x00000003UL /**< PingPong cycle type */
#define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x000000004UL /**< Memory scatter gather cycle type */
#define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x000000005UL /**< Memory scatter gather using alternate structure */
#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x000000006UL /**< Peripheral scatter gather cycle type */
#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
/** @} End of group EFM32WG_DMA */

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/**************************************************************************//**
* @file efm32wg_dmareq.h
* @brief EFM32WG_DMAREQ register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_DMAREQ_BitFields
* @{
*****************************************************************************/
#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
#define DMAREQ_DAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for DAC0_CH0 */
#define DMAREQ_DAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for DAC0_CH1 */
#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
#define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
#define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */
#define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */
#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */
#define DMAREQ_USART2_RXDATAVRIGHT ((14 << 16) + 3) /**< DMA channel select for USART2_RXDATAVRIGHT */
#define DMAREQ_USART2_TXBLRIGHT ((14 << 16) + 4) /**< DMA channel select for USART2_TXBLRIGHT */
#define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
#define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
#define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
#define DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */
#define DMAREQ_LEUART1_TXBL ((17 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */
#define DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */
#define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
#define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
#define DMAREQ_I2C1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */
#define DMAREQ_I2C1_TXBL ((21 << 16) + 1) /**< DMA channel select for I2C1_TXBL */
#define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
#define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
#define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
#define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
#define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
#define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
#define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
#define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
#define DMAREQ_TIMER2_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */
#define DMAREQ_TIMER2_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */
#define DMAREQ_TIMER2_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */
#define DMAREQ_TIMER2_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */
#define DMAREQ_TIMER3_UFOF ((27 << 16) + 0) /**< DMA channel select for TIMER3_UFOF */
#define DMAREQ_TIMER3_CC0 ((27 << 16) + 1) /**< DMA channel select for TIMER3_CC0 */
#define DMAREQ_TIMER3_CC1 ((27 << 16) + 2) /**< DMA channel select for TIMER3_CC1 */
#define DMAREQ_TIMER3_CC2 ((27 << 16) + 3) /**< DMA channel select for TIMER3_CC2 */
#define DMAREQ_UART0_RXDATAV ((44 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */
#define DMAREQ_UART0_TXBL ((44 << 16) + 1) /**< DMA channel select for UART0_TXBL */
#define DMAREQ_UART0_TXEMPTY ((44 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */
#define DMAREQ_UART1_RXDATAV ((45 << 16) + 0) /**< DMA channel select for UART1_RXDATAV */
#define DMAREQ_UART1_TXBL ((45 << 16) + 1) /**< DMA channel select for UART1_TXBL */
#define DMAREQ_UART1_TXEMPTY ((45 << 16) + 2) /**< DMA channel select for UART1_TXEMPTY */
#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
#define DMAREQ_AES_DATAWR ((49 << 16) + 0) /**< DMA channel select for AES_DATAWR */
#define DMAREQ_AES_XORDATAWR ((49 << 16) + 1) /**< DMA channel select for AES_XORDATAWR */
#define DMAREQ_AES_DATARD ((49 << 16) + 2) /**< DMA channel select for AES_DATARD */
#define DMAREQ_AES_KEYWR ((49 << 16) + 3) /**< DMA channel select for AES_KEYWR */
#define DMAREQ_LESENSE_BUFDATAV ((50 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */
#define DMAREQ_EBI_PXL0EMPTY ((51 << 16) + 0) /**< DMA channel select for EBI_PXL0EMPTY */
#define DMAREQ_EBI_PXL1EMPTY ((51 << 16) + 1) /**< DMA channel select for EBI_PXL1EMPTY */
#define DMAREQ_EBI_PXLFULL ((51 << 16) + 2) /**< DMA channel select for EBI_PXLFULL */
#define DMAREQ_EBI_DDEMPTY ((51 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */
/** @} End of group EFM32WG_DMAREQ */

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/**************************************************************************//**
* @file efm32wg_emu.h
* @brief EFM32WG_EMU register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_EMU
* @{
* @brief EFM32WG_EMU Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
uint32_t RESERVED0[1]; /**< Reserved for future use **/
__IO uint32_t LOCK; /**< Configuration Lock Register */
uint32_t RESERVED1[6]; /**< Reserved for future use **/
__IO uint32_t AUXCTRL; /**< Auxiliary Control Register */
uint32_t RESERVED2[1]; /**< Reserved for future use **/
__IO uint32_t EM4CONF; /**< Energy mode 4 configuration register */
__IO uint32_t BUCTRL; /**< Backup Power configuration register */
__IO uint32_t PWRCONF; /**< Power connection configuration register */
__IO uint32_t BUINACT; /**< Backup mode inactive configuration register */
__IO uint32_t BUACT; /**< Backup mode active configuration register */
__I uint32_t STATUS; /**< Status register */
__IO uint32_t ROUTE; /**< I/O Routing Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t BUBODBUVINCAL; /**< BU_VIN Backup BOD calibration */
__IO uint32_t BUBODUNREGCAL; /**< Unregulated power Backup BOD calibration */
} EMU_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_EMU_BitFields
* @{
*****************************************************************************/
/* Bit fields for EMU CTRL */
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
#define _EMU_CTRL_EMVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
#define _EMU_CTRL_EMVREG_REDUCED 0x00000000UL /**< Mode REDUCED for EMU_CTRL */
#define _EMU_CTRL_EMVREG_FULL 0x00000001UL /**< Mode FULL for EMU_CTRL */
#define EMU_CTRL_EMVREG_DEFAULT (_EMU_CTRL_EMVREG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_EMVREG_REDUCED (_EMU_CTRL_EMVREG_REDUCED << 0) /**< Shifted mode REDUCED for EMU_CTRL */
#define EMU_CTRL_EMVREG_FULL (_EMU_CTRL_EMVREG_FULL << 0) /**< Shifted mode FULL for EMU_CTRL */
#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */
#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */
#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */
#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */
#define _EMU_CTRL_EM4CTRL_SHIFT 2 /**< Shift value for EMU_EM4CTRL */
#define _EMU_CTRL_EM4CTRL_MASK 0xCUL /**< Bit mask for EMU_EM4CTRL */
#define _EMU_CTRL_EM4CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_EM4CTRL_DEFAULT (_EMU_CTRL_EM4CTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */
/* Bit fields for EMU LOCK */
#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */
#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
/* Bit fields for EMU AUXCTRL */
#define _EMU_AUXCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_AUXCTRL */
#define _EMU_AUXCTRL_MASK 0x00000001UL /**< Mask for EMU_AUXCTRL */
#define EMU_AUXCTRL_HRCCLR (0x1UL << 0) /**< Hard Reset Cause Clear */
#define _EMU_AUXCTRL_HRCCLR_SHIFT 0 /**< Shift value for EMU_HRCCLR */
#define _EMU_AUXCTRL_HRCCLR_MASK 0x1UL /**< Bit mask for EMU_HRCCLR */
#define _EMU_AUXCTRL_HRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_AUXCTRL */
#define EMU_AUXCTRL_HRCCLR_DEFAULT (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_AUXCTRL */
/* Bit fields for EMU EM4CONF */
#define _EMU_EM4CONF_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CONF */
#define _EMU_EM4CONF_MASK 0x0001001FUL /**< Mask for EMU_EM4CONF */
#define EMU_EM4CONF_VREGEN (0x1UL << 0) /**< EM4 voltage regulator enable */
#define _EMU_EM4CONF_VREGEN_SHIFT 0 /**< Shift value for EMU_VREGEN */
#define _EMU_EM4CONF_VREGEN_MASK 0x1UL /**< Bit mask for EMU_VREGEN */
#define _EMU_EM4CONF_VREGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CONF */
#define EMU_EM4CONF_VREGEN_DEFAULT (_EMU_EM4CONF_VREGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CONF */
#define EMU_EM4CONF_BURTCWU (0x1UL << 1) /**< Backup RTC EM4 wakeup enable */
#define _EMU_EM4CONF_BURTCWU_SHIFT 1 /**< Shift value for EMU_BURTCWU */
#define _EMU_EM4CONF_BURTCWU_MASK 0x2UL /**< Bit mask for EMU_BURTCWU */
#define _EMU_EM4CONF_BURTCWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CONF */
#define EMU_EM4CONF_BURTCWU_DEFAULT (_EMU_EM4CONF_BURTCWU_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CONF */
#define _EMU_EM4CONF_OSC_SHIFT 2 /**< Shift value for EMU_OSC */
#define _EMU_EM4CONF_OSC_MASK 0xCUL /**< Bit mask for EMU_OSC */
#define _EMU_EM4CONF_OSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CONF */
#define _EMU_EM4CONF_OSC_ULFRCO 0x00000000UL /**< Mode ULFRCO for EMU_EM4CONF */
#define _EMU_EM4CONF_OSC_LFRCO 0x00000001UL /**< Mode LFRCO for EMU_EM4CONF */
#define _EMU_EM4CONF_OSC_LFXO 0x00000002UL /**< Mode LFXO for EMU_EM4CONF */
#define EMU_EM4CONF_OSC_DEFAULT (_EMU_EM4CONF_OSC_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CONF */
#define EMU_EM4CONF_OSC_ULFRCO (_EMU_EM4CONF_OSC_ULFRCO << 2) /**< Shifted mode ULFRCO for EMU_EM4CONF */
#define EMU_EM4CONF_OSC_LFRCO (_EMU_EM4CONF_OSC_LFRCO << 2) /**< Shifted mode LFRCO for EMU_EM4CONF */
#define EMU_EM4CONF_OSC_LFXO (_EMU_EM4CONF_OSC_LFXO << 2) /**< Shifted mode LFXO for EMU_EM4CONF */
#define EMU_EM4CONF_BUBODRSTDIS (0x1UL << 4) /**< Disable reset from Backup BOD in EM4 */
#define _EMU_EM4CONF_BUBODRSTDIS_SHIFT 4 /**< Shift value for EMU_BUBODRSTDIS */
#define _EMU_EM4CONF_BUBODRSTDIS_MASK 0x10UL /**< Bit mask for EMU_BUBODRSTDIS */
#define _EMU_EM4CONF_BUBODRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CONF */
#define EMU_EM4CONF_BUBODRSTDIS_DEFAULT (_EMU_EM4CONF_BUBODRSTDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CONF */
#define EMU_EM4CONF_LOCKCONF (0x1UL << 16) /**< EM4 configuration lock enable */
#define _EMU_EM4CONF_LOCKCONF_SHIFT 16 /**< Shift value for EMU_LOCKCONF */
#define _EMU_EM4CONF_LOCKCONF_MASK 0x10000UL /**< Bit mask for EMU_LOCKCONF */
#define _EMU_EM4CONF_LOCKCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CONF */
#define EMU_EM4CONF_LOCKCONF_DEFAULT (_EMU_EM4CONF_LOCKCONF_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CONF */
/* Bit fields for EMU BUCTRL */
#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */
#define _EMU_BUCTRL_MASK 0x0000006FUL /**< Mask for EMU_BUCTRL */
#define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable backup mode */
#define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
#define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */
#define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable backup mode status export */
#define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */
#define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */
#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */
#define EMU_BUCTRL_BODCAL (0x1UL << 2) /**< Enable BOD calibration mode */
#define _EMU_BUCTRL_BODCAL_SHIFT 2 /**< Shift value for EMU_BODCAL */
#define _EMU_BUCTRL_BODCAL_MASK 0x4UL /**< Bit mask for EMU_BODCAL */
#define _EMU_BUCTRL_BODCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
#define EMU_BUCTRL_BODCAL_DEFAULT (_EMU_BUCTRL_BODCAL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */
#define EMU_BUCTRL_BUMODEBODEN (0x1UL << 3) /**< Enable brown out detection on BU_VIN when in backup mode */
#define _EMU_BUCTRL_BUMODEBODEN_SHIFT 3 /**< Shift value for EMU_BUMODEBODEN */
#define _EMU_BUCTRL_BUMODEBODEN_MASK 0x8UL /**< Bit mask for EMU_BUMODEBODEN */
#define _EMU_BUCTRL_BUMODEBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
#define EMU_BUCTRL_BUMODEBODEN_DEFAULT (_EMU_BUCTRL_BUMODEBODEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUCTRL */
#define _EMU_BUCTRL_PROBE_SHIFT 5 /**< Shift value for EMU_PROBE */
#define _EMU_BUCTRL_PROBE_MASK 0x60UL /**< Bit mask for EMU_PROBE */
#define _EMU_BUCTRL_PROBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
#define _EMU_BUCTRL_PROBE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_BUCTRL */
#define _EMU_BUCTRL_PROBE_VDDDREG 0x00000001UL /**< Mode VDDDREG for EMU_BUCTRL */
#define _EMU_BUCTRL_PROBE_BUIN 0x00000002UL /**< Mode BUIN for EMU_BUCTRL */
#define _EMU_BUCTRL_PROBE_BUOUT 0x00000003UL /**< Mode BUOUT for EMU_BUCTRL */
#define EMU_BUCTRL_PROBE_DEFAULT (_EMU_BUCTRL_PROBE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BUCTRL */
#define EMU_BUCTRL_PROBE_DISABLE (_EMU_BUCTRL_PROBE_DISABLE << 5) /**< Shifted mode DISABLE for EMU_BUCTRL */
#define EMU_BUCTRL_PROBE_VDDDREG (_EMU_BUCTRL_PROBE_VDDDREG << 5) /**< Shifted mode VDDDREG for EMU_BUCTRL */
#define EMU_BUCTRL_PROBE_BUIN (_EMU_BUCTRL_PROBE_BUIN << 5) /**< Shifted mode BUIN for EMU_BUCTRL */
#define EMU_BUCTRL_PROBE_BUOUT (_EMU_BUCTRL_PROBE_BUOUT << 5) /**< Shifted mode BUOUT for EMU_BUCTRL */
/* Bit fields for EMU PWRCONF */
#define _EMU_PWRCONF_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCONF */
#define _EMU_PWRCONF_MASK 0x0000001FUL /**< Mask for EMU_PWRCONF */
#define EMU_PWRCONF_VOUTWEAK (0x1UL << 0) /**< BU_VOUT weak enable */
#define _EMU_PWRCONF_VOUTWEAK_SHIFT 0 /**< Shift value for EMU_VOUTWEAK */
#define _EMU_PWRCONF_VOUTWEAK_MASK 0x1UL /**< Bit mask for EMU_VOUTWEAK */
#define _EMU_PWRCONF_VOUTWEAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCONF */
#define EMU_PWRCONF_VOUTWEAK_DEFAULT (_EMU_PWRCONF_VOUTWEAK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRCONF */
#define EMU_PWRCONF_VOUTMED (0x1UL << 1) /**< BU_VOUT medium enable */
#define _EMU_PWRCONF_VOUTMED_SHIFT 1 /**< Shift value for EMU_VOUTMED */
#define _EMU_PWRCONF_VOUTMED_MASK 0x2UL /**< Bit mask for EMU_VOUTMED */
#define _EMU_PWRCONF_VOUTMED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCONF */
#define EMU_PWRCONF_VOUTMED_DEFAULT (_EMU_PWRCONF_VOUTMED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_PWRCONF */
#define EMU_PWRCONF_VOUTSTRONG (0x1UL << 2) /**< BU_VOUT strong enable */
#define _EMU_PWRCONF_VOUTSTRONG_SHIFT 2 /**< Shift value for EMU_VOUTSTRONG */
#define _EMU_PWRCONF_VOUTSTRONG_MASK 0x4UL /**< Bit mask for EMU_VOUTSTRONG */
#define _EMU_PWRCONF_VOUTSTRONG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCONF */
#define EMU_PWRCONF_VOUTSTRONG_DEFAULT (_EMU_PWRCONF_VOUTSTRONG_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_PWRCONF */
#define _EMU_PWRCONF_PWRRES_SHIFT 3 /**< Shift value for EMU_PWRRES */
#define _EMU_PWRCONF_PWRRES_MASK 0x18UL /**< Bit mask for EMU_PWRRES */
#define _EMU_PWRCONF_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCONF */
#define _EMU_PWRCONF_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_PWRCONF */
#define _EMU_PWRCONF_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_PWRCONF */
#define _EMU_PWRCONF_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_PWRCONF */
#define _EMU_PWRCONF_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_PWRCONF */
#define EMU_PWRCONF_PWRRES_DEFAULT (_EMU_PWRCONF_PWRRES_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_PWRCONF */
#define EMU_PWRCONF_PWRRES_RES0 (_EMU_PWRCONF_PWRRES_RES0 << 3) /**< Shifted mode RES0 for EMU_PWRCONF */
#define EMU_PWRCONF_PWRRES_RES1 (_EMU_PWRCONF_PWRRES_RES1 << 3) /**< Shifted mode RES1 for EMU_PWRCONF */
#define EMU_PWRCONF_PWRRES_RES2 (_EMU_PWRCONF_PWRRES_RES2 << 3) /**< Shifted mode RES2 for EMU_PWRCONF */
#define EMU_PWRCONF_PWRRES_RES3 (_EMU_PWRCONF_PWRRES_RES3 << 3) /**< Shifted mode RES3 for EMU_PWRCONF */
/* Bit fields for EMU BUINACT */
#define _EMU_BUINACT_RESETVALUE 0x0000000BUL /**< Default value for EMU_BUINACT */
#define _EMU_BUINACT_MASK 0x0000007FUL /**< Mask for EMU_BUINACT */
#define _EMU_BUINACT_BUENTHRES_SHIFT 0 /**< Shift value for EMU_BUENTHRES */
#define _EMU_BUINACT_BUENTHRES_MASK 0x7UL /**< Bit mask for EMU_BUENTHRES */
#define _EMU_BUINACT_BUENTHRES_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_BUINACT */
#define EMU_BUINACT_BUENTHRES_DEFAULT (_EMU_BUINACT_BUENTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUINACT */
#define _EMU_BUINACT_BUENRANGE_SHIFT 3 /**< Shift value for EMU_BUENRANGE */
#define _EMU_BUINACT_BUENRANGE_MASK 0x18UL /**< Bit mask for EMU_BUENRANGE */
#define _EMU_BUINACT_BUENRANGE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BUINACT */
#define EMU_BUINACT_BUENRANGE_DEFAULT (_EMU_BUINACT_BUENRANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUINACT */
#define _EMU_BUINACT_PWRCON_SHIFT 5 /**< Shift value for EMU_PWRCON */
#define _EMU_BUINACT_PWRCON_MASK 0x60UL /**< Bit mask for EMU_PWRCON */
#define _EMU_BUINACT_PWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUINACT */
#define _EMU_BUINACT_PWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUINACT */
#define _EMU_BUINACT_PWRCON_BUMAIN 0x00000001UL /**< Mode BUMAIN for EMU_BUINACT */
#define _EMU_BUINACT_PWRCON_MAINBU 0x00000002UL /**< Mode MAINBU for EMU_BUINACT */
#define _EMU_BUINACT_PWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUINACT */
#define EMU_BUINACT_PWRCON_DEFAULT (_EMU_BUINACT_PWRCON_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BUINACT */
#define EMU_BUINACT_PWRCON_NONE (_EMU_BUINACT_PWRCON_NONE << 5) /**< Shifted mode NONE for EMU_BUINACT */
#define EMU_BUINACT_PWRCON_BUMAIN (_EMU_BUINACT_PWRCON_BUMAIN << 5) /**< Shifted mode BUMAIN for EMU_BUINACT */
#define EMU_BUINACT_PWRCON_MAINBU (_EMU_BUINACT_PWRCON_MAINBU << 5) /**< Shifted mode MAINBU for EMU_BUINACT */
#define EMU_BUINACT_PWRCON_NODIODE (_EMU_BUINACT_PWRCON_NODIODE << 5) /**< Shifted mode NODIODE for EMU_BUINACT */
/* Bit fields for EMU BUACT */
#define _EMU_BUACT_RESETVALUE 0x0000000BUL /**< Default value for EMU_BUACT */
#define _EMU_BUACT_MASK 0x0000007FUL /**< Mask for EMU_BUACT */
#define _EMU_BUACT_BUEXTHRES_SHIFT 0 /**< Shift value for EMU_BUEXTHRES */
#define _EMU_BUACT_BUEXTHRES_MASK 0x7UL /**< Bit mask for EMU_BUEXTHRES */
#define _EMU_BUACT_BUEXTHRES_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_BUACT */
#define EMU_BUACT_BUEXTHRES_DEFAULT (_EMU_BUACT_BUEXTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUACT */
#define _EMU_BUACT_BUEXRANGE_SHIFT 3 /**< Shift value for EMU_BUEXRANGE */
#define _EMU_BUACT_BUEXRANGE_MASK 0x18UL /**< Bit mask for EMU_BUEXRANGE */
#define _EMU_BUACT_BUEXRANGE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BUACT */
#define EMU_BUACT_BUEXRANGE_DEFAULT (_EMU_BUACT_BUEXRANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUACT */
#define _EMU_BUACT_PWRCON_SHIFT 5 /**< Shift value for EMU_PWRCON */
#define _EMU_BUACT_PWRCON_MASK 0x60UL /**< Bit mask for EMU_PWRCON */
#define _EMU_BUACT_PWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUACT */
#define _EMU_BUACT_PWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUACT */
#define _EMU_BUACT_PWRCON_BUMAIN 0x00000001UL /**< Mode BUMAIN for EMU_BUACT */
#define _EMU_BUACT_PWRCON_MAINBU 0x00000002UL /**< Mode MAINBU for EMU_BUACT */
#define _EMU_BUACT_PWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUACT */
#define EMU_BUACT_PWRCON_DEFAULT (_EMU_BUACT_PWRCON_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BUACT */
#define EMU_BUACT_PWRCON_NONE (_EMU_BUACT_PWRCON_NONE << 5) /**< Shifted mode NONE for EMU_BUACT */
#define EMU_BUACT_PWRCON_BUMAIN (_EMU_BUACT_PWRCON_BUMAIN << 5) /**< Shifted mode BUMAIN for EMU_BUACT */
#define EMU_BUACT_PWRCON_MAINBU (_EMU_BUACT_PWRCON_MAINBU << 5) /**< Shifted mode MAINBU for EMU_BUACT */
#define EMU_BUACT_PWRCON_NODIODE (_EMU_BUACT_PWRCON_NODIODE << 5) /**< Shifted mode NODIODE for EMU_BUACT */
/* Bit fields for EMU STATUS */
#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */
#define _EMU_STATUS_MASK 0x00000001UL /**< Mask for EMU_STATUS */
#define EMU_STATUS_BURDY (0x1UL << 0) /**< Backup mode ready */
#define _EMU_STATUS_BURDY_SHIFT 0 /**< Shift value for EMU_BURDY */
#define _EMU_STATUS_BURDY_MASK 0x1UL /**< Bit mask for EMU_BURDY */
#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */
/* Bit fields for EMU ROUTE */
#define _EMU_ROUTE_RESETVALUE 0x00000001UL /**< Default value for EMU_ROUTE */
#define _EMU_ROUTE_MASK 0x00000001UL /**< Mask for EMU_ROUTE */
#define EMU_ROUTE_BUVINPEN (0x1UL << 0) /**< BU_VIN Pin Enable */
#define _EMU_ROUTE_BUVINPEN_SHIFT 0 /**< Shift value for EMU_BUVINPEN */
#define _EMU_ROUTE_BUVINPEN_MASK 0x1UL /**< Bit mask for EMU_BUVINPEN */
#define _EMU_ROUTE_BUVINPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_ROUTE */
#define EMU_ROUTE_BUVINPEN_DEFAULT (_EMU_ROUTE_BUVINPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_ROUTE */
/* Bit fields for EMU IF */
#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */
#define _EMU_IF_MASK 0x00000001UL /**< Mask for EMU_IF */
#define EMU_IF_BURDY (0x1UL << 0) /**< Backup functionality ready Interrupt Flag */
#define _EMU_IF_BURDY_SHIFT 0 /**< Shift value for EMU_BURDY */
#define _EMU_IF_BURDY_MASK 0x1UL /**< Bit mask for EMU_BURDY */
#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */
/* Bit fields for EMU IFS */
#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */
#define _EMU_IFS_MASK 0x00000001UL /**< Mask for EMU_IFS */
#define EMU_IFS_BURDY (0x1UL << 0) /**< Set Backup functionality ready Interrupt Flag */
#define _EMU_IFS_BURDY_SHIFT 0 /**< Shift value for EMU_BURDY */
#define _EMU_IFS_BURDY_MASK 0x1UL /**< Bit mask for EMU_BURDY */
#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */
/* Bit fields for EMU IFC */
#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */
#define _EMU_IFC_MASK 0x00000001UL /**< Mask for EMU_IFC */
#define EMU_IFC_BURDY (0x1UL << 0) /**< Clear Backup functionality ready Interrupt Flag */
#define _EMU_IFC_BURDY_SHIFT 0 /**< Shift value for EMU_BURDY */
#define _EMU_IFC_BURDY_MASK 0x1UL /**< Bit mask for EMU_BURDY */
#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */
/* Bit fields for EMU IEN */
#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */
#define _EMU_IEN_MASK 0x00000001UL /**< Mask for EMU_IEN */
#define EMU_IEN_BURDY (0x1UL << 0) /**< Backup functionality ready Interrupt Enable */
#define _EMU_IEN_BURDY_SHIFT 0 /**< Shift value for EMU_BURDY */
#define _EMU_IEN_BURDY_MASK 0x1UL /**< Bit mask for EMU_BURDY */
#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */
/* Bit fields for EMU BUBODBUVINCAL */
#define _EMU_BUBODBUVINCAL_RESETVALUE 0x0000000BUL /**< Default value for EMU_BUBODBUVINCAL */
#define _EMU_BUBODBUVINCAL_MASK 0x0000001FUL /**< Mask for EMU_BUBODBUVINCAL */
#define _EMU_BUBODBUVINCAL_THRES_SHIFT 0 /**< Shift value for EMU_THRES */
#define _EMU_BUBODBUVINCAL_THRES_MASK 0x7UL /**< Bit mask for EMU_THRES */
#define _EMU_BUBODBUVINCAL_THRES_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_BUBODBUVINCAL */
#define EMU_BUBODBUVINCAL_THRES_DEFAULT (_EMU_BUBODBUVINCAL_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUBODBUVINCAL */
#define _EMU_BUBODBUVINCAL_RANGE_SHIFT 3 /**< Shift value for EMU_RANGE */
#define _EMU_BUBODBUVINCAL_RANGE_MASK 0x18UL /**< Bit mask for EMU_RANGE */
#define _EMU_BUBODBUVINCAL_RANGE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BUBODBUVINCAL */
#define EMU_BUBODBUVINCAL_RANGE_DEFAULT (_EMU_BUBODBUVINCAL_RANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUBODBUVINCAL */
/* Bit fields for EMU BUBODUNREGCAL */
#define _EMU_BUBODUNREGCAL_RESETVALUE 0x0000000BUL /**< Default value for EMU_BUBODUNREGCAL */
#define _EMU_BUBODUNREGCAL_MASK 0x0000001FUL /**< Mask for EMU_BUBODUNREGCAL */
#define _EMU_BUBODUNREGCAL_THRES_SHIFT 0 /**< Shift value for EMU_THRES */
#define _EMU_BUBODUNREGCAL_THRES_MASK 0x7UL /**< Bit mask for EMU_THRES */
#define _EMU_BUBODUNREGCAL_THRES_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_BUBODUNREGCAL */
#define EMU_BUBODUNREGCAL_THRES_DEFAULT (_EMU_BUBODUNREGCAL_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUBODUNREGCAL */
#define _EMU_BUBODUNREGCAL_RANGE_SHIFT 3 /**< Shift value for EMU_RANGE */
#define _EMU_BUBODUNREGCAL_RANGE_MASK 0x18UL /**< Bit mask for EMU_RANGE */
#define _EMU_BUBODUNREGCAL_RANGE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BUBODUNREGCAL */
#define EMU_BUBODUNREGCAL_RANGE_DEFAULT (_EMU_BUBODUNREGCAL_RANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUBODUNREGCAL */
/** @} End of group EFM32WG_EMU */

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/**************************************************************************//**
* @file efm32wg_etm.h
* @brief EFM32WG_ETM register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_ETM
* @{
* @brief EFM32WG_ETM Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t ETMCR; /**< Main Control Register */
__I uint32_t ETMCCR; /**< Configuration Code Register */
__IO uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */
uint32_t RESERVED0[1]; /**< Reserved for future use **/
__IO uint32_t ETMSR; /**< ETM Status Register */
__I uint32_t ETMSCR; /**< ETM System Configuration Register */
uint32_t RESERVED1[2]; /**< Reserved for future use **/
__IO uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */
__IO uint32_t ETMTECR1; /**< ETM Trace control Register */
uint32_t RESERVED2[1]; /**< Reserved for future use **/
__IO uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */
uint32_t RESERVED3[68]; /**< Reserved for future use **/
__IO uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */
uint32_t RESERVED4[39]; /**< Reserved for future use **/
__IO uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */
__I uint32_t ETMIDR; /**< ID Register */
__I uint32_t ETMCCER; /**< Configuration Code Extension Register */
uint32_t RESERVED5[1]; /**< Reserved for future use **/
__IO uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */
uint32_t RESERVED6[1]; /**< Reserved for future use **/
__IO uint32_t ETMTSEVR; /**< Timestamp Event Register */
uint32_t RESERVED7[1]; /**< Reserved for future use **/
__IO uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */
uint32_t RESERVED8[1]; /**< Reserved for future use **/
__I uint32_t ETMIDR2; /**< ETM ID Register 2 */
uint32_t RESERVED9[66]; /**< Reserved for future use **/
__I uint32_t ETMPDSR; /**< Device Power-down Status Register */
uint32_t RESERVED10[754]; /**< Reserved for future use **/
__IO uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */
uint32_t RESERVED11[1]; /**< Reserved for future use **/
__O uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */
uint32_t RESERVED12[1]; /**< Reserved for future use **/
__I uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */
uint32_t RESERVED13[1]; /**< Reserved for future use **/
__O uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */
uint32_t RESERVED14[1]; /**< Reserved for future use **/
__IO uint32_t ETMITCTRL; /**< ETM Integration Control Register */
uint32_t RESERVED15[39]; /**< Reserved for future use **/
__IO uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */
__IO uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */
uint32_t RESERVED16[2]; /**< Reserved for future use **/
__IO uint32_t ETMLAR; /**< ETM Lock Access Register */
__I uint32_t ETMLSR; /**< Lock Status Register */
__I uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */
uint32_t RESERVED17[4]; /**< Reserved for future use **/
__I uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */
__I uint32_t ETMPIDR4; /**< Peripheral ID4 Register */
__O uint32_t ETMPIDR5; /**< Peripheral ID5 Register */
__O uint32_t ETMPIDR6; /**< Peripheral ID6 Register */
__O uint32_t ETMPIDR7; /**< Peripheral ID7 Register */
__I uint32_t ETMPIDR0; /**< Peripheral ID0 Register */
__I uint32_t ETMPIDR1; /**< Peripheral ID1 Register */
__I uint32_t ETMPIDR2; /**< Peripheral ID2 Register */
__I uint32_t ETMPIDR3; /**< Peripheral ID3 Register */
__I uint32_t ETMCIDR0; /**< Component ID0 Register */
__I uint32_t ETMCIDR1; /**< Component ID1 Register */
__I uint32_t ETMCIDR2; /**< Component ID2 Register */
__I uint32_t ETMCIDR3; /**< Component ID3 Register */
} ETM_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_ETM_BitFields
* @{
*****************************************************************************/
/* Bit fields for ETM ETMCR */
#define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */
#define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */
#define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */
#define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */
#define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */
#define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */
#define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */
#define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */
#define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */
#define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */
#define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */
#define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */
#define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */
#define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */
#define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */
#define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */
#define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */
#define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */
#define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */
#define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */
#define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */
#define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */
#define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */
#define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */
#define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */
#define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */
#define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */
#define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */
#define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */
#define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */
#define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */
#define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */
#define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */
#define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */
#define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */
#define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */
#define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */
/* Bit fields for ETM ETMCCR */
#define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */
#define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */
#define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */
#define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */
#define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */
#define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */
#define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */
#define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */
#define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */
#define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */
#define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */
#define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */
#define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */
#define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */
#define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */
#define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
#define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */
#define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */
#define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */
#define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */
#define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */
#define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */
#define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */
#define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */
#define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */
#define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */
#define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */
#define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */
#define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */
#define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */
#define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */
#define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */
#define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */
#define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */
#define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */
#define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */
#define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */
#define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */
#define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */
/* Bit fields for ETM ETMTRIGGER */
#define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */
#define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */
#define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
#define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
#define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
#define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
#define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
#define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
#define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
#define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
#define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */
#define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */
#define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
#define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
/* Bit fields for ETM ETMSR */
#define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */
#define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */
#define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */
#define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */
#define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */
#define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
#define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */
#define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */
#define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */
#define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */
#define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */
#define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */
#define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */
#define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */
#define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */
#define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
#define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */
#define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */
#define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */
#define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */
#define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
#define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */
/* Bit fields for ETM ETMSCR */
#define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */
#define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */
#define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */
#define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */
#define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_Reserved (0x1UL << 3) /**< Reserved */
#define _ETM_ETMSCR_Reserved_SHIFT 3 /**< Shift value for ETM_Reserved */
#define _ETM_ETMSCR_Reserved_MASK 0x8UL /**< Bit mask for ETM_Reserved */
#define _ETM_ETMSCR_Reserved_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_Reserved_DEFAULT (_ETM_ETMSCR_Reserved_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */
#define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */
#define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */
#define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */
#define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */
#define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */
#define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */
#define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */
#define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */
#define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */
#define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */
#define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */
#define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */
#define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */
#define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */
#define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */
#define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */
#define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */
#define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */
/* Bit fields for ETM ETMTEEVR */
#define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */
#define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */
#define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
#define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
#define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
#define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
#define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
#define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
#define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
#define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
#define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */
#define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */
#define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
#define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
/* Bit fields for ETM ETMTECR1 */
#define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */
#define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */
#define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */
#define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */
#define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
#define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
#define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */
#define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */
#define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
#define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
#define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */
#define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */
#define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */
#define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
#define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */
#define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */
#define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
#define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */
#define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */
#define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */
#define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */
#define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */
#define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
#define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */
#define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */
#define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
#define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */
#define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */
/* Bit fields for ETM ETMFFLR */
#define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */
#define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */
#define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */
#define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */
#define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */
#define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */
/* Bit fields for ETM ETMCNTRLDVR1 */
#define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */
#define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */
#define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */
#define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */
#define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */
#define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */
/* Bit fields for ETM ETMSYNCFR */
#define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */
#define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */
#define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */
#define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */
#define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */
#define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */
/* Bit fields for ETM ETMIDR */
#define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */
#define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */
#define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */
#define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */
#define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */
#define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */
#define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */
#define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */
#define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */
#define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */
#define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */
#define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */
#define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */
#define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */
#define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */
#define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */
#define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */
#define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */
#define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */
#define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */
#define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */
#define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */
#define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */
#define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */
#define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */
/* Bit fields for ETM ETMCCER */
#define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */
#define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */
#define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */
#define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */
#define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */
#define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */
#define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */
#define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */
#define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */
#define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */
#define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */
#define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */
#define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */
#define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */
#define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */
#define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */
#define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */
#define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */
#define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */
#define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */
#define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */
#define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */
#define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */
#define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */
#define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */
#define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */
#define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */
#define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */
#define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */
#define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */
#define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */
#define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */
#define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */
#define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */
#define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */
/* Bit fields for ETM ETMTESSEICR */
#define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */
#define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */
#define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */
#define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */
#define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
#define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
#define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */
#define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */
#define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
#define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
/* Bit fields for ETM ETMTSEVR */
#define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */
#define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */
#define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */
#define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */
#define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
#define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
#define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */
#define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */
#define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
#define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
#define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */
#define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */
#define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
#define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
/* Bit fields for ETM ETMTRACEIDR */
#define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */
#define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */
#define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */
#define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */
#define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */
#define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */
/* Bit fields for ETM ETMIDR2 */
#define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */
#define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */
#define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */
#define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */
#define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */
#define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
#define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */
#define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */
#define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
#define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */
#define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */
#define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */
#define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */
#define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */
#define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
#define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */
#define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */
#define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
#define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */
#define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */
/* Bit fields for ETM ETMPDSR */
#define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */
#define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */
#define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */
#define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */
#define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */
#define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */
#define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */
/* Bit fields for ETM ETMISCIN */
#define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */
#define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */
#define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */
#define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */
#define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
#define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
#define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */
#define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */
#define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */
#define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
#define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
/* Bit fields for ETM ITTRIGOUT */
#define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */
#define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */
#define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */
#define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */
#define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */
#define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */
#define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */
/* Bit fields for ETM ETMITATBCTR2 */
#define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */
#define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */
#define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */
#define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */
#define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */
#define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */
#define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */
/* Bit fields for ETM ETMITATBCTR0 */
#define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */
#define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */
#define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */
#define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */
#define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */
#define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */
#define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */
/* Bit fields for ETM ETMITCTRL */
#define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */
#define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */
#define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */
#define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */
#define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */
#define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */
#define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */
/* Bit fields for ETM ETMCLAIMSET */
#define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */
#define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */
#define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */
#define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */
#define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */
#define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */
/* Bit fields for ETM ETMCLAIMCLR */
#define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */
#define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */
#define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */
#define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */
#define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */
#define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */
#define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */
/* Bit fields for ETM ETMLAR */
#define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */
#define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */
#define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */
#define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */
#define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */
#define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */
#define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */
/* Bit fields for ETM ETMLSR */
#define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */
#define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */
#define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */
#define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */
#define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */
#define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
#define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */
#define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */
#define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */
#define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */
#define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
#define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */
/* Bit fields for ETM ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */
#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */
#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
#define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */
#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */
#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */
#define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */
#define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
#define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */
#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */
#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
#define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
/* Bit fields for ETM ETMDEVTYPE */
#define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */
#define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */
#define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */
#define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */
#define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
#define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
#define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */
#define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */
#define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
#define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
/* Bit fields for ETM ETMPIDR4 */
#define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */
#define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */
#define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */
#define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */
#define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
#define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
#define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */
#define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */
#define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
#define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
/* Bit fields for ETM ETMPIDR5 */
#define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */
#define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */
/* Bit fields for ETM ETMPIDR6 */
#define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */
#define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */
/* Bit fields for ETM ETMPIDR7 */
#define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */
#define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */
/* Bit fields for ETM ETMPIDR0 */
#define _ETM_ETMPIDR0_RESETVALUE 0x00000024UL /**< Default value for ETM_ETMPIDR0 */
#define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */
#define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
#define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */
#define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000024UL /**< Mode DEFAULT for ETM_ETMPIDR0 */
#define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */
/* Bit fields for ETM ETMPIDR1 */
#define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */
#define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */
#define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
#define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */
#define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */
#define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
#define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */
#define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */
#define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */
#define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
/* Bit fields for ETM ETMPIDR2 */
#define _ETM_ETMPIDR2_RESETVALUE 0x0000003BUL /**< Default value for ETM_ETMPIDR2 */
#define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */
#define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */
#define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */
#define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
#define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
#define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */
#define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */
#define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */
#define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
#define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
#define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */
#define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */
#define _ETM_ETMPIDR2_REV_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
#define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
/* Bit fields for ETM ETMPIDR3 */
#define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */
#define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */
#define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */
#define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */
#define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
#define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
#define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */
#define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */
#define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
#define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
/* Bit fields for ETM ETMCIDR0 */
#define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */
#define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */
#define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
#define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
#define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */
#define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */
/* Bit fields for ETM ETMCIDR1 */
#define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */
#define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */
#define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
#define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
#define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */
#define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */
/* Bit fields for ETM ETMCIDR2 */
#define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */
#define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */
#define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
#define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
#define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */
#define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */
/* Bit fields for ETM ETMCIDR3 */
#define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */
#define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */
#define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
#define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
#define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */
#define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */
/** @} End of group EFM32WG_ETM */

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/**************************************************************************//**
* @file efm32wg_fpueh.h
* @brief EFM32WG_FPUEH register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_FPUEH
* @{
* @brief EFM32WG_FPUEH Register Declaration
*****************************************************************************/
typedef struct
{
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
} FPUEH_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_FPUEH_BitFields
* @{
*****************************************************************************/
/* Bit fields for FPUEH IF */
#define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */
#define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */
#define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */
#define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
#define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
#define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */
#define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
#define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
#define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */
#define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
#define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
#define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */
#define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
#define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
#define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */
#define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
#define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
#define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */
#define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
#define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
#define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */
/* Bit fields for FPUEH IFS */
#define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */
#define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */
#define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */
#define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
#define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
#define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */
#define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
#define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
#define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */
#define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
#define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
#define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */
#define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
#define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
#define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */
#define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
#define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
#define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */
#define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
#define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
#define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */
/* Bit fields for FPUEH IFC */
#define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */
#define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */
#define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */
#define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
#define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
#define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */
#define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
#define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
#define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */
#define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
#define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
#define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */
#define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
#define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
#define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */
#define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
#define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
#define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */
#define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
#define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
#define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */
/* Bit fields for FPUEH IEN */
#define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */
#define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */
#define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */
#define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
#define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
#define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */
#define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
#define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
#define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */
#define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
#define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
#define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */
#define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
#define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
#define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */
#define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
#define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
#define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */
#define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
#define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
#define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */
/** @} End of group EFM32WG_FPUEH */

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/**************************************************************************//**
* @file efm32wg_gpio_p.h
* @brief EFM32WG_GPIO_P register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @brief GPIO_P EFM32WG GPIO P
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Port Control Register */
__IO uint32_t MODEL; /**< Port Pin Mode Low Register */
__IO uint32_t MODEH; /**< Port Pin Mode High Register */
__IO uint32_t DOUT; /**< Port Data Out Register */
__O uint32_t DOUTSET; /**< Port Data Out Set Register */
__O uint32_t DOUTCLR; /**< Port Data Out Clear Register */
__O uint32_t DOUTTGL; /**< Port Data Out Toggle Register */
__I uint32_t DIN; /**< Port Data In Register */
__IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register */
} GPIO_P_TypeDef;

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/**************************************************************************//**
* @file efm32wg_i2c.h
* @brief EFM32WG_I2C register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_I2C
* @{
* @brief EFM32WG_I2C Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t CMD; /**< Command Register */
__I uint32_t STATE; /**< State Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t CLKDIV; /**< Clock Division Register */
__IO uint32_t SADDR; /**< Slave Address Register */
__IO uint32_t SADDRMASK; /**< Slave Address Mask Register */
__I uint32_t RXDATA; /**< Receive Buffer Data Register */
__I uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
__IO uint32_t TXDATA; /**< Transmit Buffer Data Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t ROUTE; /**< I/O Routing Register */
} I2C_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_I2C_BitFields
* @{
*****************************************************************************/
/* Bit fields for I2C CTRL */
#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
#define _I2C_CTRL_MASK 0x0007B37FUL /**< Mask for I2C_CTRL */
#define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */
#define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */
#define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */
#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */
#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */
#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */
#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */
#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */
#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */
#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */
#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */
#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */
#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */
#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */
#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */
#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */
#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */
#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */
#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */
#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */
#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */
#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */
#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */
#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */
#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */
#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */
#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */
#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
#define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
#define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
#define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */
#define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */
#define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */
#define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */
#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */
#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */
#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
#define _I2C_CTRL_CLTO_320PPC 0x00000004UL /**< Mode 320PPC for I2C_CTRL */
#define _I2C_CTRL_CLTO_1024PPC 0x00000005UL /**< Mode 1024PPC for I2C_CTRL */
#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */
#define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */
#define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */
#define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */
#define I2C_CTRL_CLTO_320PPC (_I2C_CTRL_CLTO_320PPC << 16) /**< Shifted mode 320PPC for I2C_CTRL */
#define I2C_CTRL_CLTO_1024PPC (_I2C_CTRL_CLTO_1024PPC << 16) /**< Shifted mode 1024PPC for I2C_CTRL */
/* Bit fields for I2C CMD */
#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */
#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */
#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */
#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */
#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */
#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */
#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */
#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */
#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */
#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */
#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */
#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */
#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */
#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */
#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
/* Bit fields for I2C STATE */
#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */
#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */
#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */
#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */
#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */
#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */
#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */
#define I2C_STATE_MASTER (0x1UL << 1) /**< Master */
#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */
#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */
#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */
#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */
#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */
#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */
#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */
#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */
#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */
#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */
#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */
#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */
#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */
#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */
#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */
#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */
#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */
#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */
#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */
#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */
#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */
#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */
#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */
#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */
#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */
#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */
#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */
#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */
#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */
#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */
#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */
/* Bit fields for I2C STATUS */
#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */
#define _I2C_STATUS_MASK 0x000001FFUL /**< Mask for I2C_STATUS */
#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */
#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */
#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */
#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */
#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */
#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */
#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */
#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */
#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */
#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */
#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */
#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */
#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */
#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */
#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */
#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */
#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */
#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */
#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */
#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */
#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */
#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */
#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
/* Bit fields for I2C CLKDIV */
#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */
#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */
#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */
#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */
#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */
#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
/* Bit fields for I2C SADDR */
#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */
#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */
#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */
#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */
#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */
#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
/* Bit fields for I2C SADDRMASK */
#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */
#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */
#define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */
#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */
#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */
#define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
/* Bit fields for I2C RXDATA */
#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */
#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */
#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */
#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */
#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */
#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
/* Bit fields for I2C RXDATAP */
#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */
#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */
#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */
#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */
#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */
#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
/* Bit fields for I2C TXDATA */
#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */
#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */
#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */
#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */
#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */
#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
/* Bit fields for I2C IF */
#define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */
#define _I2C_IF_MASK 0x0001FFFFUL /**< Mask for I2C_IF */
#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */
#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */
#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */
#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */
#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */
/* Bit fields for I2C IFS */
#define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */
#define _I2C_IFS_MASK 0x0001FFCFUL /**< Mask for I2C_IFS */
#define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */
#define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */
#define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */
#define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_RSTART (0x1UL << 1) /**< Set Repeated START Interrupt Flag */
#define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
#define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_ADDR (0x1UL << 2) /**< Set Address Interrupt Flag */
#define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
#define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_TXC (0x1UL << 3) /**< Set Transfer Completed Interrupt Flag */
#define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
#define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_ACK (0x1UL << 6) /**< Set Acknowledge Received Interrupt Flag */
#define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
#define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_NACK (0x1UL << 7) /**< Set Not Acknowledge Received Interrupt Flag */
#define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
#define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */
#define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
#define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set Arbitration Lost Interrupt Flag */
#define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
#define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_BUSERR (0x1UL << 10) /**< Set Bus Error Interrupt Flag */
#define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
#define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set Bus Held Interrupt Flag */
#define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
#define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_TXOF (0x1UL << 12) /**< Set Transmit Buffer Overflow Interrupt Flag */
#define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
#define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_RXUF (0x1UL << 13) /**< Set Receive Buffer Underflow Interrupt Flag */
#define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
#define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_BITO (0x1UL << 14) /**< Set Bus Idle Timeout Interrupt Flag */
#define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
#define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_CLTO (0x1UL << 15) /**< Set Clock Low Interrupt Flag */
#define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
#define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */
#define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
#define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */
/* Bit fields for I2C IFC */
#define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */
#define _I2C_IFC_MASK 0x0001FFCFUL /**< Mask for I2C_IFC */
#define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */
#define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */
#define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */
#define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_RSTART (0x1UL << 1) /**< Clear Repeated START Interrupt Flag */
#define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
#define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_ADDR (0x1UL << 2) /**< Clear Address Interrupt Flag */
#define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
#define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_TXC (0x1UL << 3) /**< Clear Transfer Completed Interrupt Flag */
#define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
#define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_ACK (0x1UL << 6) /**< Clear Acknowledge Received Interrupt Flag */
#define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
#define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_NACK (0x1UL << 7) /**< Clear Not Acknowledge Received Interrupt Flag */
#define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
#define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */
#define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
#define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear Arbitration Lost Interrupt Flag */
#define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
#define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear Bus Error Interrupt Flag */
#define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
#define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear Bus Held Interrupt Flag */
#define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
#define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_TXOF (0x1UL << 12) /**< Clear Transmit Buffer Overflow Interrupt Flag */
#define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
#define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_RXUF (0x1UL << 13) /**< Clear Receive Buffer Underflow Interrupt Flag */
#define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
#define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_BITO (0x1UL << 14) /**< Clear Bus Idle Timeout Interrupt Flag */
#define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
#define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_CLTO (0x1UL << 15) /**< Clear Clock Low Interrupt Flag */
#define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
#define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */
#define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
#define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */
/* Bit fields for I2C IEN */
#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */
#define _I2C_IEN_MASK 0x0001FFFFUL /**< Mask for I2C_IEN */
#define I2C_IEN_START (0x1UL << 0) /**< START Condition Interrupt Enable */
#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */
#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */
#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Enable */
#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Enable */
#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Enable */
#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer level Interrupt Enable */
#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Enable */
#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Enable */
#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Enable */
#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */
#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Enable */
#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Enable */
#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Enable */
#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Enable */
#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Enable */
#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Enable */
#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Interrupt Enable */
#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */
#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */
/* Bit fields for I2C ROUTE */
#define _I2C_ROUTE_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTE */
#define _I2C_ROUTE_MASK 0x00000703UL /**< Mask for I2C_ROUTE */
#define I2C_ROUTE_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */
#define _I2C_ROUTE_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */
#define _I2C_ROUTE_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */
#define _I2C_ROUTE_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
#define I2C_ROUTE_SDAPEN_DEFAULT (_I2C_ROUTE_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTE */
#define I2C_ROUTE_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */
#define _I2C_ROUTE_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */
#define _I2C_ROUTE_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */
#define _I2C_ROUTE_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
#define I2C_ROUTE_SCLPEN_DEFAULT (_I2C_ROUTE_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTE */
#define _I2C_ROUTE_LOCATION_SHIFT 8 /**< Shift value for I2C_LOCATION */
#define _I2C_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for I2C_LOCATION */
#define _I2C_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTE */
#define _I2C_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
#define _I2C_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTE */
#define _I2C_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTE */
#define _I2C_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTE */
#define _I2C_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTE */
#define _I2C_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTE */
#define _I2C_ROUTE_LOCATION_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTE */
#define I2C_ROUTE_LOCATION_LOC0 (_I2C_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTE */
#define I2C_ROUTE_LOCATION_DEFAULT (_I2C_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTE */
#define I2C_ROUTE_LOCATION_LOC1 (_I2C_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTE */
#define I2C_ROUTE_LOCATION_LOC2 (_I2C_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTE */
#define I2C_ROUTE_LOCATION_LOC3 (_I2C_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTE */
#define I2C_ROUTE_LOCATION_LOC4 (_I2C_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTE */
#define I2C_ROUTE_LOCATION_LOC5 (_I2C_ROUTE_LOCATION_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTE */
#define I2C_ROUTE_LOCATION_LOC6 (_I2C_ROUTE_LOCATION_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTE */
/** @} End of group EFM32WG_I2C */

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FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Include/efm32wg_lcd.h Normal file
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/**************************************************************************//**
* @file efm32wg_lcd.h
* @brief EFM32WG_LCD register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_LCD
* @{
* @brief EFM32WG_LCD Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t DISPCTRL; /**< Display Control Register */
__IO uint32_t SEGEN; /**< Segment Enable Register */
__IO uint32_t BACTRL; /**< Blink and Animation Control Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t AREGA; /**< Animation Register A */
__IO uint32_t AREGB; /**< Animation Register B */
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
uint32_t RESERVED0[5]; /**< Reserved for future use **/
__IO uint32_t SEGD0L; /**< Segment Data Low Register 0 */
__IO uint32_t SEGD1L; /**< Segment Data Low Register 1 */
__IO uint32_t SEGD2L; /**< Segment Data Low Register 2 */
__IO uint32_t SEGD3L; /**< Segment Data Low Register 3 */
__IO uint32_t SEGD0H; /**< Segment Data High Register 0 */
__IO uint32_t SEGD1H; /**< Segment Data High Register 1 */
__IO uint32_t SEGD2H; /**< Segment Data High Register 2 */
__IO uint32_t SEGD3H; /**< Segment Data High Register 3 */
__IO uint32_t FREEZE; /**< Freeze Register */
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
uint32_t RESERVED1[19]; /**< Reserved for future use **/
__IO uint32_t SEGD4H; /**< Segment Data High Register 4 */
__IO uint32_t SEGD5H; /**< Segment Data High Register 5 */
__IO uint32_t SEGD6H; /**< Segment Data High Register 6 */
__IO uint32_t SEGD7H; /**< Segment Data High Register 7 */
uint32_t RESERVED2[2]; /**< Reserved for future use **/
__IO uint32_t SEGD4L; /**< Segment Data Low Register 4 */
__IO uint32_t SEGD5L; /**< Segment Data Low Register 5 */
__IO uint32_t SEGD6L; /**< Segment Data Low Register 6 */
__IO uint32_t SEGD7L; /**< Segment Data Low Register 7 */
} LCD_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_LCD_BitFields
* @{
*****************************************************************************/
/* Bit fields for LCD CTRL */
#define _LCD_CTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_CTRL */
#define _LCD_CTRL_MASK 0x00800007UL /**< Mask for LCD_CTRL */
#define LCD_CTRL_EN (0x1UL << 0) /**< LCD Enable */
#define _LCD_CTRL_EN_SHIFT 0 /**< Shift value for LCD_EN */
#define _LCD_CTRL_EN_MASK 0x1UL /**< Bit mask for LCD_EN */
#define _LCD_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
#define LCD_CTRL_EN_DEFAULT (_LCD_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CTRL */
#define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */
#define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */
#define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
#define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */
#define _LCD_CTRL_UDCTRL_FCEVENT 0x00000001UL /**< Mode FCEVENT for LCD_CTRL */
#define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL /**< Mode FRAMESTART for LCD_CTRL */
#define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */
#define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */
#define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */
#define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */
#define LCD_CTRL_DSC (0x1UL << 23) /**< Direct Segment Control */
#define _LCD_CTRL_DSC_SHIFT 23 /**< Shift value for LCD_DSC */
#define _LCD_CTRL_DSC_MASK 0x800000UL /**< Bit mask for LCD_DSC */
#define _LCD_CTRL_DSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
#define LCD_CTRL_DSC_DEFAULT (_LCD_CTRL_DSC_DEFAULT << 23) /**< Shifted mode DEFAULT for LCD_CTRL */
/* Bit fields for LCD DISPCTRL */
#define _LCD_DISPCTRL_RESETVALUE 0x000C1F00UL /**< Default value for LCD_DISPCTRL */
#define _LCD_DISPCTRL_MASK 0x005D9F1FUL /**< Mask for LCD_DISPCTRL */
#define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */
#define _LCD_DISPCTRL_MUX_MASK 0x3UL /**< Bit mask for LCD_MUX */
#define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
#define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
#define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */
#define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */
#define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */
#define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
#define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */
#define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */
#define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */
#define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */
#define _LCD_DISPCTRL_BIAS_SHIFT 2 /**< Shift value for LCD_BIAS */
#define _LCD_DISPCTRL_BIAS_MASK 0xCUL /**< Bit mask for LCD_BIAS */
#define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
#define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
#define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */
#define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */
#define _LCD_DISPCTRL_BIAS_ONEFOURTH 0x00000003UL /**< Mode ONEFOURTH for LCD_DISPCTRL */
#define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
#define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 2) /**< Shifted mode STATIC for LCD_DISPCTRL */
#define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 2) /**< Shifted mode ONEHALF for LCD_DISPCTRL */
#define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 2) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */
#define LCD_DISPCTRL_BIAS_ONEFOURTH (_LCD_DISPCTRL_BIAS_ONEFOURTH << 2) /**< Shifted mode ONEFOURTH for LCD_DISPCTRL */
#define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */
#define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */
#define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */
#define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
#define _LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL /**< Mode LOWPOWER for LCD_DISPCTRL */
#define _LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL /**< Mode NORMAL for LCD_DISPCTRL */
#define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
#define LCD_DISPCTRL_WAVE_LOWPOWER (_LCD_DISPCTRL_WAVE_LOWPOWER << 4) /**< Shifted mode LOWPOWER for LCD_DISPCTRL */
#define LCD_DISPCTRL_WAVE_NORMAL (_LCD_DISPCTRL_WAVE_NORMAL << 4) /**< Shifted mode NORMAL for LCD_DISPCTRL */
#define _LCD_DISPCTRL_CONLEV_SHIFT 8 /**< Shift value for LCD_CONLEV */
#define _LCD_DISPCTRL_CONLEV_MASK 0x1F00UL /**< Bit mask for LCD_CONLEV */
#define _LCD_DISPCTRL_CONLEV_MIN 0x00000000UL /**< Mode MIN for LCD_DISPCTRL */
#define _LCD_DISPCTRL_CONLEV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LCD_DISPCTRL */
#define _LCD_DISPCTRL_CONLEV_MAX 0x0000001FUL /**< Mode MAX for LCD_DISPCTRL */
#define LCD_DISPCTRL_CONLEV_MIN (_LCD_DISPCTRL_CONLEV_MIN << 8) /**< Shifted mode MIN for LCD_DISPCTRL */
#define LCD_DISPCTRL_CONLEV_DEFAULT (_LCD_DISPCTRL_CONLEV_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
#define LCD_DISPCTRL_CONLEV_MAX (_LCD_DISPCTRL_CONLEV_MAX << 8) /**< Shifted mode MAX for LCD_DISPCTRL */
#define LCD_DISPCTRL_CONCONF (0x1UL << 15) /**< Contrast Configuration */
#define _LCD_DISPCTRL_CONCONF_SHIFT 15 /**< Shift value for LCD_CONCONF */
#define _LCD_DISPCTRL_CONCONF_MASK 0x8000UL /**< Bit mask for LCD_CONCONF */
#define _LCD_DISPCTRL_CONCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
#define _LCD_DISPCTRL_CONCONF_VLCD 0x00000000UL /**< Mode VLCD for LCD_DISPCTRL */
#define _LCD_DISPCTRL_CONCONF_GND 0x00000001UL /**< Mode GND for LCD_DISPCTRL */
#define LCD_DISPCTRL_CONCONF_DEFAULT (_LCD_DISPCTRL_CONCONF_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
#define LCD_DISPCTRL_CONCONF_VLCD (_LCD_DISPCTRL_CONCONF_VLCD << 15) /**< Shifted mode VLCD for LCD_DISPCTRL */
#define LCD_DISPCTRL_CONCONF_GND (_LCD_DISPCTRL_CONCONF_GND << 15) /**< Shifted mode GND for LCD_DISPCTRL */
#define LCD_DISPCTRL_VLCDSEL (0x1UL << 16) /**< VLCD Selection */
#define _LCD_DISPCTRL_VLCDSEL_SHIFT 16 /**< Shift value for LCD_VLCDSEL */
#define _LCD_DISPCTRL_VLCDSEL_MASK 0x10000UL /**< Bit mask for LCD_VLCDSEL */
#define _LCD_DISPCTRL_VLCDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
#define _LCD_DISPCTRL_VLCDSEL_VDD 0x00000000UL /**< Mode VDD for LCD_DISPCTRL */
#define _LCD_DISPCTRL_VLCDSEL_VEXTBOOST 0x00000001UL /**< Mode VEXTBOOST for LCD_DISPCTRL */
#define LCD_DISPCTRL_VLCDSEL_DEFAULT (_LCD_DISPCTRL_VLCDSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
#define LCD_DISPCTRL_VLCDSEL_VDD (_LCD_DISPCTRL_VLCDSEL_VDD << 16) /**< Shifted mode VDD for LCD_DISPCTRL */
#define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (_LCD_DISPCTRL_VLCDSEL_VEXTBOOST << 16) /**< Shifted mode VEXTBOOST for LCD_DISPCTRL */
#define _LCD_DISPCTRL_VBLEV_SHIFT 18 /**< Shift value for LCD_VBLEV */
#define _LCD_DISPCTRL_VBLEV_MASK 0x1C0000UL /**< Bit mask for LCD_VBLEV */
#define _LCD_DISPCTRL_VBLEV_LEVEL0 0x00000000UL /**< Mode LEVEL0 for LCD_DISPCTRL */
#define _LCD_DISPCTRL_VBLEV_LEVEL1 0x00000001UL /**< Mode LEVEL1 for LCD_DISPCTRL */
#define _LCD_DISPCTRL_VBLEV_LEVEL2 0x00000002UL /**< Mode LEVEL2 for LCD_DISPCTRL */
#define _LCD_DISPCTRL_VBLEV_DEFAULT 0x00000003UL /**< Mode DEFAULT for LCD_DISPCTRL */
#define _LCD_DISPCTRL_VBLEV_LEVEL3 0x00000003UL /**< Mode LEVEL3 for LCD_DISPCTRL */
#define _LCD_DISPCTRL_VBLEV_LEVEL4 0x00000004UL /**< Mode LEVEL4 for LCD_DISPCTRL */
#define _LCD_DISPCTRL_VBLEV_LEVEL5 0x00000005UL /**< Mode LEVEL5 for LCD_DISPCTRL */
#define _LCD_DISPCTRL_VBLEV_LEVEL6 0x00000006UL /**< Mode LEVEL6 for LCD_DISPCTRL */
#define _LCD_DISPCTRL_VBLEV_LEVEL7 0x00000007UL /**< Mode LEVEL7 for LCD_DISPCTRL */
#define LCD_DISPCTRL_VBLEV_LEVEL0 (_LCD_DISPCTRL_VBLEV_LEVEL0 << 18) /**< Shifted mode LEVEL0 for LCD_DISPCTRL */
#define LCD_DISPCTRL_VBLEV_LEVEL1 (_LCD_DISPCTRL_VBLEV_LEVEL1 << 18) /**< Shifted mode LEVEL1 for LCD_DISPCTRL */
#define LCD_DISPCTRL_VBLEV_LEVEL2 (_LCD_DISPCTRL_VBLEV_LEVEL2 << 18) /**< Shifted mode LEVEL2 for LCD_DISPCTRL */
#define LCD_DISPCTRL_VBLEV_DEFAULT (_LCD_DISPCTRL_VBLEV_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
#define LCD_DISPCTRL_VBLEV_LEVEL3 (_LCD_DISPCTRL_VBLEV_LEVEL3 << 18) /**< Shifted mode LEVEL3 for LCD_DISPCTRL */
#define LCD_DISPCTRL_VBLEV_LEVEL4 (_LCD_DISPCTRL_VBLEV_LEVEL4 << 18) /**< Shifted mode LEVEL4 for LCD_DISPCTRL */
#define LCD_DISPCTRL_VBLEV_LEVEL5 (_LCD_DISPCTRL_VBLEV_LEVEL5 << 18) /**< Shifted mode LEVEL5 for LCD_DISPCTRL */
#define LCD_DISPCTRL_VBLEV_LEVEL6 (_LCD_DISPCTRL_VBLEV_LEVEL6 << 18) /**< Shifted mode LEVEL6 for LCD_DISPCTRL */
#define LCD_DISPCTRL_VBLEV_LEVEL7 (_LCD_DISPCTRL_VBLEV_LEVEL7 << 18) /**< Shifted mode LEVEL7 for LCD_DISPCTRL */
#define LCD_DISPCTRL_MUXE (0x1UL << 22) /**< Extended Mux Configuration */
#define _LCD_DISPCTRL_MUXE_SHIFT 22 /**< Shift value for LCD_MUXE */
#define _LCD_DISPCTRL_MUXE_MASK 0x400000UL /**< Bit mask for LCD_MUXE */
#define _LCD_DISPCTRL_MUXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
#define _LCD_DISPCTRL_MUXE_MUX 0x00000000UL /**< Mode MUX for LCD_DISPCTRL */
#define _LCD_DISPCTRL_MUXE_MUXE 0x00000001UL /**< Mode MUXE for LCD_DISPCTRL */
#define LCD_DISPCTRL_MUXE_DEFAULT (_LCD_DISPCTRL_MUXE_DEFAULT << 22) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
#define LCD_DISPCTRL_MUXE_MUX (_LCD_DISPCTRL_MUXE_MUX << 22) /**< Shifted mode MUX for LCD_DISPCTRL */
#define LCD_DISPCTRL_MUXE_MUXE (_LCD_DISPCTRL_MUXE_MUXE << 22) /**< Shifted mode MUXE for LCD_DISPCTRL */
/* Bit fields for LCD SEGEN */
#define _LCD_SEGEN_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN */
#define _LCD_SEGEN_MASK 0x000003FFUL /**< Mask for LCD_SEGEN */
#define _LCD_SEGEN_SEGEN_SHIFT 0 /**< Shift value for LCD_SEGEN */
#define _LCD_SEGEN_SEGEN_MASK 0x3FFUL /**< Bit mask for LCD_SEGEN */
#define _LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN */
#define LCD_SEGEN_SEGEN_DEFAULT (_LCD_SEGEN_SEGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGEN */
/* Bit fields for LCD BACTRL */
#define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */
#define _LCD_BACTRL_MASK 0x10FF01FFUL /**< Mask for LCD_BACTRL */
#define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */
#define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */
#define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */
#define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */
#define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */
#define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */
#define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */
#define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */
#define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */
#define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */
#define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */
#define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
#define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
#define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
#define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */
#define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
#define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
#define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */
#define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */
#define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
#define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
#define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
#define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */
#define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
#define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */
#define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */
#define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */
#define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */
#define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */
#define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */
#define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */
#define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */
#define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */
#define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */
#define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define _LCD_BACTRL_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */
#define _LCD_BACTRL_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */
#define _LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define _LCD_BACTRL_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACTRL */
#define _LCD_BACTRL_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACTRL */
#define _LCD_BACTRL_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACTRL */
#define _LCD_BACTRL_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACTRL */
#define LCD_BACTRL_FCPRESC_DEFAULT (_LCD_BACTRL_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_FCPRESC_DIV1 (_LCD_BACTRL_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACTRL */
#define LCD_BACTRL_FCPRESC_DIV2 (_LCD_BACTRL_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACTRL */
#define LCD_BACTRL_FCPRESC_DIV4 (_LCD_BACTRL_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACTRL */
#define LCD_BACTRL_FCPRESC_DIV8 (_LCD_BACTRL_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACTRL */
#define _LCD_BACTRL_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */
#define _LCD_BACTRL_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */
#define _LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_FCTOP_DEFAULT (_LCD_BACTRL_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_ALOC (0x1UL << 28) /**< Animation Location */
#define _LCD_BACTRL_ALOC_SHIFT 28 /**< Shift value for LCD_ALOC */
#define _LCD_BACTRL_ALOC_MASK 0x10000000UL /**< Bit mask for LCD_ALOC */
#define _LCD_BACTRL_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
#define _LCD_BACTRL_ALOC_SEG0TO7 0x00000000UL /**< Mode SEG0TO7 for LCD_BACTRL */
#define _LCD_BACTRL_ALOC_SEG8TO15 0x00000001UL /**< Mode SEG8TO15 for LCD_BACTRL */
#define LCD_BACTRL_ALOC_DEFAULT (_LCD_BACTRL_ALOC_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_BACTRL */
#define LCD_BACTRL_ALOC_SEG0TO7 (_LCD_BACTRL_ALOC_SEG0TO7 << 28) /**< Shifted mode SEG0TO7 for LCD_BACTRL */
#define LCD_BACTRL_ALOC_SEG8TO15 (_LCD_BACTRL_ALOC_SEG8TO15 << 28) /**< Shifted mode SEG8TO15 for LCD_BACTRL */
/* Bit fields for LCD STATUS */
#define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */
#define _LCD_STATUS_MASK 0x0000010FUL /**< Mask for LCD_STATUS */
#define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */
#define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */
#define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
#define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */
#define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */
#define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */
#define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */
#define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
#define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */
/* Bit fields for LCD AREGA */
#define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */
#define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */
#define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */
#define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */
#define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */
#define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */
/* Bit fields for LCD AREGB */
#define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */
#define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */
#define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */
#define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */
#define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */
#define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */
/* Bit fields for LCD IF */
#define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */
#define _LCD_IF_MASK 0x00000001UL /**< Mask for LCD_IF */
#define LCD_IF_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag */
#define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */
#define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
#define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */
#define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */
/* Bit fields for LCD IFS */
#define _LCD_IFS_RESETVALUE 0x00000000UL /**< Default value for LCD_IFS */
#define _LCD_IFS_MASK 0x00000001UL /**< Mask for LCD_IFS */
#define LCD_IFS_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Set */
#define _LCD_IFS_FC_SHIFT 0 /**< Shift value for LCD_FC */
#define _LCD_IFS_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
#define _LCD_IFS_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFS */
#define LCD_IFS_FC_DEFAULT (_LCD_IFS_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFS */
/* Bit fields for LCD IFC */
#define _LCD_IFC_RESETVALUE 0x00000000UL /**< Default value for LCD_IFC */
#define _LCD_IFC_MASK 0x00000001UL /**< Mask for LCD_IFC */
#define LCD_IFC_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Clear */
#define _LCD_IFC_FC_SHIFT 0 /**< Shift value for LCD_FC */
#define _LCD_IFC_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
#define _LCD_IFC_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFC */
#define LCD_IFC_FC_DEFAULT (_LCD_IFC_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFC */
/* Bit fields for LCD IEN */
#define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */
#define _LCD_IEN_MASK 0x00000001UL /**< Mask for LCD_IEN */
#define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter Interrupt Enable */
#define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */
#define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
#define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */
#define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */
/* Bit fields for LCD SEGD0L */
#define _LCD_SEGD0L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0L */
#define _LCD_SEGD0L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD0L */
#define _LCD_SEGD0L_SEGD0L_SHIFT 0 /**< Shift value for LCD_SEGD0L */
#define _LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD0L */
#define _LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0L */
#define LCD_SEGD0L_SEGD0L_DEFAULT (_LCD_SEGD0L_SEGD0L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0L */
/* Bit fields for LCD SEGD1L */
#define _LCD_SEGD1L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1L */
#define _LCD_SEGD1L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD1L */
#define _LCD_SEGD1L_SEGD1L_SHIFT 0 /**< Shift value for LCD_SEGD1L */
#define _LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD1L */
#define _LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1L */
#define LCD_SEGD1L_SEGD1L_DEFAULT (_LCD_SEGD1L_SEGD1L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1L */
/* Bit fields for LCD SEGD2L */
#define _LCD_SEGD2L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2L */
#define _LCD_SEGD2L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD2L */
#define _LCD_SEGD2L_SEGD2L_SHIFT 0 /**< Shift value for LCD_SEGD2L */
#define _LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD2L */
#define _LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2L */
#define LCD_SEGD2L_SEGD2L_DEFAULT (_LCD_SEGD2L_SEGD2L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2L */
/* Bit fields for LCD SEGD3L */
#define _LCD_SEGD3L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3L */
#define _LCD_SEGD3L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD3L */
#define _LCD_SEGD3L_SEGD3L_SHIFT 0 /**< Shift value for LCD_SEGD3L */
#define _LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD3L */
#define _LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3L */
#define LCD_SEGD3L_SEGD3L_DEFAULT (_LCD_SEGD3L_SEGD3L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3L */
/* Bit fields for LCD SEGD0H */
#define _LCD_SEGD0H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0H */
#define _LCD_SEGD0H_MASK 0x000000FFUL /**< Mask for LCD_SEGD0H */
#define _LCD_SEGD0H_SEGD0H_SHIFT 0 /**< Shift value for LCD_SEGD0H */
#define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL /**< Bit mask for LCD_SEGD0H */
#define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0H */
#define LCD_SEGD0H_SEGD0H_DEFAULT (_LCD_SEGD0H_SEGD0H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0H */
/* Bit fields for LCD SEGD1H */
#define _LCD_SEGD1H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1H */
#define _LCD_SEGD1H_MASK 0x000000FFUL /**< Mask for LCD_SEGD1H */
#define _LCD_SEGD1H_SEGD1H_SHIFT 0 /**< Shift value for LCD_SEGD1H */
#define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL /**< Bit mask for LCD_SEGD1H */
#define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1H */
#define LCD_SEGD1H_SEGD1H_DEFAULT (_LCD_SEGD1H_SEGD1H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1H */
/* Bit fields for LCD SEGD2H */
#define _LCD_SEGD2H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2H */
#define _LCD_SEGD2H_MASK 0x000000FFUL /**< Mask for LCD_SEGD2H */
#define _LCD_SEGD2H_SEGD2H_SHIFT 0 /**< Shift value for LCD_SEGD2H */
#define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL /**< Bit mask for LCD_SEGD2H */
#define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2H */
#define LCD_SEGD2H_SEGD2H_DEFAULT (_LCD_SEGD2H_SEGD2H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2H */
/* Bit fields for LCD SEGD3H */
#define _LCD_SEGD3H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3H */
#define _LCD_SEGD3H_MASK 0x000000FFUL /**< Mask for LCD_SEGD3H */
#define _LCD_SEGD3H_SEGD3H_SHIFT 0 /**< Shift value for LCD_SEGD3H */
#define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL /**< Bit mask for LCD_SEGD3H */
#define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3H */
#define LCD_SEGD3H_SEGD3H_DEFAULT (_LCD_SEGD3H_SEGD3H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3H */
/* Bit fields for LCD FREEZE */
#define _LCD_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LCD_FREEZE */
#define _LCD_FREEZE_MASK 0x00000001UL /**< Mask for LCD_FREEZE */
#define LCD_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
#define _LCD_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LCD_REGFREEZE */
#define _LCD_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LCD_REGFREEZE */
#define _LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */
#define _LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LCD_FREEZE */
#define _LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LCD_FREEZE */
#define LCD_FREEZE_REGFREEZE_DEFAULT (_LCD_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FREEZE */
#define LCD_FREEZE_REGFREEZE_UPDATE (_LCD_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LCD_FREEZE */
#define LCD_FREEZE_REGFREEZE_FREEZE (_LCD_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LCD_FREEZE */
/* Bit fields for LCD SYNCBUSY */
#define _LCD_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LCD_SYNCBUSY */
#define _LCD_SYNCBUSY_MASK 0x000FFFFFUL /**< Mask for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
#define _LCD_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LCD_CTRL */
#define _LCD_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LCD_CTRL */
#define _LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_CTRL_DEFAULT (_LCD_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_BACTRL (0x1UL << 1) /**< BACTRL Register Busy */
#define _LCD_SYNCBUSY_BACTRL_SHIFT 1 /**< Shift value for LCD_BACTRL */
#define _LCD_SYNCBUSY_BACTRL_MASK 0x2UL /**< Bit mask for LCD_BACTRL */
#define _LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_BACTRL_DEFAULT (_LCD_SYNCBUSY_BACTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_AREGA (0x1UL << 2) /**< AREGA Register Busy */
#define _LCD_SYNCBUSY_AREGA_SHIFT 2 /**< Shift value for LCD_AREGA */
#define _LCD_SYNCBUSY_AREGA_MASK 0x4UL /**< Bit mask for LCD_AREGA */
#define _LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_AREGA_DEFAULT (_LCD_SYNCBUSY_AREGA_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_AREGB (0x1UL << 3) /**< AREGB Register Busy */
#define _LCD_SYNCBUSY_AREGB_SHIFT 3 /**< Shift value for LCD_AREGB */
#define _LCD_SYNCBUSY_AREGB_MASK 0x8UL /**< Bit mask for LCD_AREGB */
#define _LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_AREGB_DEFAULT (_LCD_SYNCBUSY_AREGB_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD0L (0x1UL << 4) /**< SEGD0L Register Busy */
#define _LCD_SYNCBUSY_SEGD0L_SHIFT 4 /**< Shift value for LCD_SEGD0L */
#define _LCD_SYNCBUSY_SEGD0L_MASK 0x10UL /**< Bit mask for LCD_SEGD0L */
#define _LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD0L_DEFAULT (_LCD_SYNCBUSY_SEGD0L_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD1L (0x1UL << 5) /**< SEGD1L Register Busy */
#define _LCD_SYNCBUSY_SEGD1L_SHIFT 5 /**< Shift value for LCD_SEGD1L */
#define _LCD_SYNCBUSY_SEGD1L_MASK 0x20UL /**< Bit mask for LCD_SEGD1L */
#define _LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD1L_DEFAULT (_LCD_SYNCBUSY_SEGD1L_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD2L (0x1UL << 6) /**< SEGD2L Register Busy */
#define _LCD_SYNCBUSY_SEGD2L_SHIFT 6 /**< Shift value for LCD_SEGD2L */
#define _LCD_SYNCBUSY_SEGD2L_MASK 0x40UL /**< Bit mask for LCD_SEGD2L */
#define _LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD2L_DEFAULT (_LCD_SYNCBUSY_SEGD2L_DEFAULT << 6) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD3L (0x1UL << 7) /**< SEGD3L Register Busy */
#define _LCD_SYNCBUSY_SEGD3L_SHIFT 7 /**< Shift value for LCD_SEGD3L */
#define _LCD_SYNCBUSY_SEGD3L_MASK 0x80UL /**< Bit mask for LCD_SEGD3L */
#define _LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD3L_DEFAULT (_LCD_SYNCBUSY_SEGD3L_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD0H (0x1UL << 8) /**< SEGD0H Register Busy */
#define _LCD_SYNCBUSY_SEGD0H_SHIFT 8 /**< Shift value for LCD_SEGD0H */
#define _LCD_SYNCBUSY_SEGD0H_MASK 0x100UL /**< Bit mask for LCD_SEGD0H */
#define _LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD0H_DEFAULT (_LCD_SYNCBUSY_SEGD0H_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD1H (0x1UL << 9) /**< SEGD1H Register Busy */
#define _LCD_SYNCBUSY_SEGD1H_SHIFT 9 /**< Shift value for LCD_SEGD1H */
#define _LCD_SYNCBUSY_SEGD1H_MASK 0x200UL /**< Bit mask for LCD_SEGD1H */
#define _LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD1H_DEFAULT (_LCD_SYNCBUSY_SEGD1H_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD2H (0x1UL << 10) /**< SEGD2H Register Busy */
#define _LCD_SYNCBUSY_SEGD2H_SHIFT 10 /**< Shift value for LCD_SEGD2H */
#define _LCD_SYNCBUSY_SEGD2H_MASK 0x400UL /**< Bit mask for LCD_SEGD2H */
#define _LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD2H_DEFAULT (_LCD_SYNCBUSY_SEGD2H_DEFAULT << 10) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD3H (0x1UL << 11) /**< SEGD3H Register Busy */
#define _LCD_SYNCBUSY_SEGD3H_SHIFT 11 /**< Shift value for LCD_SEGD3H */
#define _LCD_SYNCBUSY_SEGD3H_MASK 0x800UL /**< Bit mask for LCD_SEGD3H */
#define _LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD3H_DEFAULT (_LCD_SYNCBUSY_SEGD3H_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD4H (0x1UL << 12) /**< SEGD4H Register Busy */
#define _LCD_SYNCBUSY_SEGD4H_SHIFT 12 /**< Shift value for LCD_SEGD4H */
#define _LCD_SYNCBUSY_SEGD4H_MASK 0x1000UL /**< Bit mask for LCD_SEGD4H */
#define _LCD_SYNCBUSY_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD4H_DEFAULT (_LCD_SYNCBUSY_SEGD4H_DEFAULT << 12) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD5H (0x1UL << 13) /**< SEGD5H Register Busy */
#define _LCD_SYNCBUSY_SEGD5H_SHIFT 13 /**< Shift value for LCD_SEGD5H */
#define _LCD_SYNCBUSY_SEGD5H_MASK 0x2000UL /**< Bit mask for LCD_SEGD5H */
#define _LCD_SYNCBUSY_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD5H_DEFAULT (_LCD_SYNCBUSY_SEGD5H_DEFAULT << 13) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD6H (0x1UL << 14) /**< SEGD6H Register Busy */
#define _LCD_SYNCBUSY_SEGD6H_SHIFT 14 /**< Shift value for LCD_SEGD6H */
#define _LCD_SYNCBUSY_SEGD6H_MASK 0x4000UL /**< Bit mask for LCD_SEGD6H */
#define _LCD_SYNCBUSY_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD6H_DEFAULT (_LCD_SYNCBUSY_SEGD6H_DEFAULT << 14) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD7H (0x1UL << 15) /**< SEGD7H Register Busy */
#define _LCD_SYNCBUSY_SEGD7H_SHIFT 15 /**< Shift value for LCD_SEGD7H */
#define _LCD_SYNCBUSY_SEGD7H_MASK 0x8000UL /**< Bit mask for LCD_SEGD7H */
#define _LCD_SYNCBUSY_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD7H_DEFAULT (_LCD_SYNCBUSY_SEGD7H_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD4L (0x1UL << 16) /**< SEGD4L Register Busy */
#define _LCD_SYNCBUSY_SEGD4L_SHIFT 16 /**< Shift value for LCD_SEGD4L */
#define _LCD_SYNCBUSY_SEGD4L_MASK 0x10000UL /**< Bit mask for LCD_SEGD4L */
#define _LCD_SYNCBUSY_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD4L_DEFAULT (_LCD_SYNCBUSY_SEGD4L_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD5L (0x1UL << 17) /**< SEGD5L Register Busy */
#define _LCD_SYNCBUSY_SEGD5L_SHIFT 17 /**< Shift value for LCD_SEGD5L */
#define _LCD_SYNCBUSY_SEGD5L_MASK 0x20000UL /**< Bit mask for LCD_SEGD5L */
#define _LCD_SYNCBUSY_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD5L_DEFAULT (_LCD_SYNCBUSY_SEGD5L_DEFAULT << 17) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD6L (0x1UL << 18) /**< SEGD6L Register Busy */
#define _LCD_SYNCBUSY_SEGD6L_SHIFT 18 /**< Shift value for LCD_SEGD6L */
#define _LCD_SYNCBUSY_SEGD6L_MASK 0x40000UL /**< Bit mask for LCD_SEGD6L */
#define _LCD_SYNCBUSY_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD6L_DEFAULT (_LCD_SYNCBUSY_SEGD6L_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD7L (0x1UL << 19) /**< SEGD7L Register Busy */
#define _LCD_SYNCBUSY_SEGD7L_SHIFT 19 /**< Shift value for LCD_SEGD7L */
#define _LCD_SYNCBUSY_SEGD7L_MASK 0x80000UL /**< Bit mask for LCD_SEGD7L */
#define _LCD_SYNCBUSY_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
#define LCD_SYNCBUSY_SEGD7L_DEFAULT (_LCD_SYNCBUSY_SEGD7L_DEFAULT << 19) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
/* Bit fields for LCD SEGD4H */
#define _LCD_SEGD4H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4H */
#define _LCD_SEGD4H_MASK 0x000000FFUL /**< Mask for LCD_SEGD4H */
#define _LCD_SEGD4H_SEGD4H_SHIFT 0 /**< Shift value for LCD_SEGD4H */
#define _LCD_SEGD4H_SEGD4H_MASK 0xFFUL /**< Bit mask for LCD_SEGD4H */
#define _LCD_SEGD4H_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4H */
#define LCD_SEGD4H_SEGD4H_DEFAULT (_LCD_SEGD4H_SEGD4H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4H */
/* Bit fields for LCD SEGD5H */
#define _LCD_SEGD5H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5H */
#define _LCD_SEGD5H_MASK 0x000000FFUL /**< Mask for LCD_SEGD5H */
#define _LCD_SEGD5H_SEGD5H_SHIFT 0 /**< Shift value for LCD_SEGD5H */
#define _LCD_SEGD5H_SEGD5H_MASK 0xFFUL /**< Bit mask for LCD_SEGD5H */
#define _LCD_SEGD5H_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5H */
#define LCD_SEGD5H_SEGD5H_DEFAULT (_LCD_SEGD5H_SEGD5H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5H */
/* Bit fields for LCD SEGD6H */
#define _LCD_SEGD6H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6H */
#define _LCD_SEGD6H_MASK 0x000000FFUL /**< Mask for LCD_SEGD6H */
#define _LCD_SEGD6H_SEGD6H_SHIFT 0 /**< Shift value for LCD_SEGD6H */
#define _LCD_SEGD6H_SEGD6H_MASK 0xFFUL /**< Bit mask for LCD_SEGD6H */
#define _LCD_SEGD6H_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6H */
#define LCD_SEGD6H_SEGD6H_DEFAULT (_LCD_SEGD6H_SEGD6H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6H */
/* Bit fields for LCD SEGD7H */
#define _LCD_SEGD7H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7H */
#define _LCD_SEGD7H_MASK 0x000000FFUL /**< Mask for LCD_SEGD7H */
#define _LCD_SEGD7H_SEGD7H_SHIFT 0 /**< Shift value for LCD_SEGD7H */
#define _LCD_SEGD7H_SEGD7H_MASK 0xFFUL /**< Bit mask for LCD_SEGD7H */
#define _LCD_SEGD7H_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7H */
#define LCD_SEGD7H_SEGD7H_DEFAULT (_LCD_SEGD7H_SEGD7H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7H */
/* Bit fields for LCD SEGD4L */
#define _LCD_SEGD4L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4L */
#define _LCD_SEGD4L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD4L */
#define _LCD_SEGD4L_SEGD4L_SHIFT 0 /**< Shift value for LCD_SEGD4L */
#define _LCD_SEGD4L_SEGD4L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD4L */
#define _LCD_SEGD4L_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4L */
#define LCD_SEGD4L_SEGD4L_DEFAULT (_LCD_SEGD4L_SEGD4L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4L */
/* Bit fields for LCD SEGD5L */
#define _LCD_SEGD5L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5L */
#define _LCD_SEGD5L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD5L */
#define _LCD_SEGD5L_SEGD5L_SHIFT 0 /**< Shift value for LCD_SEGD5L */
#define _LCD_SEGD5L_SEGD5L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD5L */
#define _LCD_SEGD5L_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5L */
#define LCD_SEGD5L_SEGD5L_DEFAULT (_LCD_SEGD5L_SEGD5L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5L */
/* Bit fields for LCD SEGD6L */
#define _LCD_SEGD6L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6L */
#define _LCD_SEGD6L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD6L */
#define _LCD_SEGD6L_SEGD6L_SHIFT 0 /**< Shift value for LCD_SEGD6L */
#define _LCD_SEGD6L_SEGD6L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD6L */
#define _LCD_SEGD6L_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6L */
#define LCD_SEGD6L_SEGD6L_DEFAULT (_LCD_SEGD6L_SEGD6L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6L */
/* Bit fields for LCD SEGD7L */
#define _LCD_SEGD7L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7L */
#define _LCD_SEGD7L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD7L */
#define _LCD_SEGD7L_SEGD7L_SHIFT 0 /**< Shift value for LCD_SEGD7L */
#define _LCD_SEGD7L_SEGD7L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD7L */
#define _LCD_SEGD7L_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7L */
#define LCD_SEGD7L_SEGD7L_DEFAULT (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7L */
/** @} End of group EFM32WG_LCD */

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/**************************************************************************//**
* @file efm32wg_lesense_buf.h
* @brief EFM32WG_LESENSE_BUF register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @brief LESENSE_BUF EFM32WG LESENSE BUF
*****************************************************************************/
typedef struct
{
__IO uint32_t DATA; /**< Scan results */
} LESENSE_BUF_TypeDef;

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/**************************************************************************//**
* @file efm32wg_lesense_ch.h
* @brief EFM32WG_LESENSE_CH register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @brief LESENSE_CH EFM32WG LESENSE CH
*****************************************************************************/
typedef struct
{
__IO uint32_t TIMING; /**< Scan configuration */
__IO uint32_t INTERACT; /**< Scan configuration */
__IO uint32_t EVAL; /**< Scan configuration */
uint32_t RESERVED0[1]; /**< Reserved future */
} LESENSE_CH_TypeDef;

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/**************************************************************************//**
* @file efm32wg_lesense_st.h
* @brief EFM32WG_LESENSE_ST register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @brief LESENSE_ST EFM32WG LESENSE ST
*****************************************************************************/
typedef struct
{
__IO uint32_t TCONFA; /**< State transition configuration A */
__IO uint32_t TCONFB; /**< State transition configuration B */
} LESENSE_ST_TypeDef;

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/**************************************************************************//**
* @file efm32wg_letimer.h
* @brief EFM32WG_LETIMER register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_LETIMER
* @{
* @brief EFM32WG_LETIMER Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t CMD; /**< Command Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t CNT; /**< Counter Value Register */
__IO uint32_t COMP0; /**< Compare Value Register 0 */
__IO uint32_t COMP1; /**< Compare Value Register 1 */
__IO uint32_t REP0; /**< Repeat Counter Register 0 */
__IO uint32_t REP1; /**< Repeat Counter Register 1 */
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t FREEZE; /**< Freeze Register */
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
uint32_t RESERVED0[2]; /**< Reserved for future use **/
__IO uint32_t ROUTE; /**< I/O Routing Register */
} LETIMER_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_LETIMER_BitFields
* @{
*****************************************************************************/
/* Bit fields for LETIMER CTRL */
#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */
#define _LETIMER_CTRL_MASK 0x00001FFFUL /**< Mask for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */
#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */
#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */
#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */
#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */
#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */
#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */
#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */
#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */
#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */
#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */
#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */
#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */
#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */
#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */
#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 Is Top Value */
#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */
#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */
#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_RTCC0TEN (0x1UL << 10) /**< RTC Compare 0 Trigger Enable */
#define _LETIMER_CTRL_RTCC0TEN_SHIFT 10 /**< Shift value for LETIMER_RTCC0TEN */
#define _LETIMER_CTRL_RTCC0TEN_MASK 0x400UL /**< Bit mask for LETIMER_RTCC0TEN */
#define _LETIMER_CTRL_RTCC0TEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_RTCC0TEN_DEFAULT (_LETIMER_CTRL_RTCC0TEN_DEFAULT << 10) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_RTCC1TEN (0x1UL << 11) /**< RTC Compare 1 Trigger Enable */
#define _LETIMER_CTRL_RTCC1TEN_SHIFT 11 /**< Shift value for LETIMER_RTCC1TEN */
#define _LETIMER_CTRL_RTCC1TEN_MASK 0x800UL /**< Bit mask for LETIMER_RTCC1TEN */
#define _LETIMER_CTRL_RTCC1TEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_RTCC1TEN_DEFAULT (_LETIMER_CTRL_RTCC1TEN_DEFAULT << 11) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */
#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */
#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */
#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */
/* Bit fields for LETIMER CMD */
#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */
#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */
#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */
#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */
#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */
#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */
#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */
#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */
#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */
#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */
#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */
#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */
#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */
#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */
#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */
#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */
#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */
#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */
/* Bit fields for LETIMER STATUS */
#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */
#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */
#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */
#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */
#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */
#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */
#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */
/* Bit fields for LETIMER CNT */
#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */
#define _LETIMER_CNT_MASK 0x0000FFFFUL /**< Mask for LETIMER_CNT */
#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */
#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for LETIMER_CNT */
#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */
#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */
/* Bit fields for LETIMER COMP0 */
#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */
#define _LETIMER_COMP0_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP0 */
#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP0 */
#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */
#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */
/* Bit fields for LETIMER COMP1 */
#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */
#define _LETIMER_COMP1_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP1 */
#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */
#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP1 */
#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */
#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */
/* Bit fields for LETIMER REP0 */
#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */
#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */
#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */
#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */
#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */
#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */
/* Bit fields for LETIMER REP1 */
#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */
#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */
#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */
#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */
#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */
#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */
/* Bit fields for LETIMER IF */
#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */
#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */
#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */
#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */
#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */
#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */
#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */
#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */
/* Bit fields for LETIMER IFS */
#define _LETIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFS */
#define _LETIMER_IFS_MASK 0x0000001FUL /**< Mask for LETIMER_IFS */
#define LETIMER_IFS_COMP0 (0x1UL << 0) /**< Set Compare Match 0 Interrupt Flag */
#define _LETIMER_IFS_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
#define _LETIMER_IFS_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_COMP1 (0x1UL << 1) /**< Set Compare Match 1 Interrupt Flag */
#define _LETIMER_IFS_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
#define _LETIMER_IFS_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_UF (0x1UL << 2) /**< Set Underflow Interrupt Flag */
#define _LETIMER_IFS_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
#define _LETIMER_IFS_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_REP0 (0x1UL << 3) /**< Set Repeat Counter 0 Interrupt Flag */
#define _LETIMER_IFS_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
#define _LETIMER_IFS_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_REP1 (0x1UL << 4) /**< Set Repeat Counter 1 Interrupt Flag */
#define _LETIMER_IFS_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
#define _LETIMER_IFS_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFS */
/* Bit fields for LETIMER IFC */
#define _LETIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFC */
#define _LETIMER_IFC_MASK 0x0000001FUL /**< Mask for LETIMER_IFC */
#define LETIMER_IFC_COMP0 (0x1UL << 0) /**< Clear Compare Match 0 Interrupt Flag */
#define _LETIMER_IFC_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
#define _LETIMER_IFC_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_COMP1 (0x1UL << 1) /**< Clear Compare Match 1 Interrupt Flag */
#define _LETIMER_IFC_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
#define _LETIMER_IFC_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_UF (0x1UL << 2) /**< Clear Underflow Interrupt Flag */
#define _LETIMER_IFC_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
#define _LETIMER_IFC_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_REP0 (0x1UL << 3) /**< Clear Repeat Counter 0 Interrupt Flag */
#define _LETIMER_IFC_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
#define _LETIMER_IFC_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_REP1 (0x1UL << 4) /**< Clear Repeat Counter 1 Interrupt Flag */
#define _LETIMER_IFC_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
#define _LETIMER_IFC_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFC */
/* Bit fields for LETIMER IEN */
#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */
#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */
#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */
#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */
#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */
#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */
#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */
#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */
/* Bit fields for LETIMER FREEZE */
#define _LETIMER_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_FREEZE */
#define _LETIMER_FREEZE_MASK 0x00000001UL /**< Mask for LETIMER_FREEZE */
#define LETIMER_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
#define _LETIMER_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LETIMER_REGFREEZE */
#define _LETIMER_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LETIMER_REGFREEZE */
#define _LETIMER_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_FREEZE */
#define _LETIMER_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LETIMER_FREEZE */
#define _LETIMER_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LETIMER_FREEZE */
#define LETIMER_FREEZE_REGFREEZE_DEFAULT (_LETIMER_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_FREEZE */
#define LETIMER_FREEZE_REGFREEZE_UPDATE (_LETIMER_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LETIMER_FREEZE */
#define LETIMER_FREEZE_REGFREEZE_FREEZE (_LETIMER_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LETIMER_FREEZE */
/* Bit fields for LETIMER SYNCBUSY */
#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */
#define _LETIMER_SYNCBUSY_MASK 0x0000003FUL /**< Mask for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
#define _LETIMER_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LETIMER_CTRL */
#define _LETIMER_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LETIMER_CTRL */
#define _LETIMER_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CTRL_DEFAULT (_LETIMER_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LETIMER_CMD */
#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LETIMER_CMD */
#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_COMP0 (0x1UL << 2) /**< COMP0 Register Busy */
#define _LETIMER_SYNCBUSY_COMP0_SHIFT 2 /**< Shift value for LETIMER_COMP0 */
#define _LETIMER_SYNCBUSY_COMP0_MASK 0x4UL /**< Bit mask for LETIMER_COMP0 */
#define _LETIMER_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_COMP0_DEFAULT (_LETIMER_SYNCBUSY_COMP0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_COMP1 (0x1UL << 3) /**< COMP1 Register Busy */
#define _LETIMER_SYNCBUSY_COMP1_SHIFT 3 /**< Shift value for LETIMER_COMP1 */
#define _LETIMER_SYNCBUSY_COMP1_MASK 0x8UL /**< Bit mask for LETIMER_COMP1 */
#define _LETIMER_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_COMP1_DEFAULT (_LETIMER_SYNCBUSY_COMP1_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_REP0 (0x1UL << 4) /**< REP0 Register Busy */
#define _LETIMER_SYNCBUSY_REP0_SHIFT 4 /**< Shift value for LETIMER_REP0 */
#define _LETIMER_SYNCBUSY_REP0_MASK 0x10UL /**< Bit mask for LETIMER_REP0 */
#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_REP1 (0x1UL << 5) /**< REP1 Register Busy */
#define _LETIMER_SYNCBUSY_REP1_SHIFT 5 /**< Shift value for LETIMER_REP1 */
#define _LETIMER_SYNCBUSY_REP1_MASK 0x20UL /**< Bit mask for LETIMER_REP1 */
#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
/* Bit fields for LETIMER ROUTE */
#define _LETIMER_ROUTE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTE */
#define _LETIMER_ROUTE_MASK 0x00000703UL /**< Mask for LETIMER_ROUTE */
#define LETIMER_ROUTE_OUT0PEN (0x1UL << 0) /**< Output 0 Pin Enable */
#define _LETIMER_ROUTE_OUT0PEN_SHIFT 0 /**< Shift value for LETIMER_OUT0PEN */
#define _LETIMER_ROUTE_OUT0PEN_MASK 0x1UL /**< Bit mask for LETIMER_OUT0PEN */
#define _LETIMER_ROUTE_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTE */
#define LETIMER_ROUTE_OUT0PEN_DEFAULT (_LETIMER_ROUTE_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTE */
#define LETIMER_ROUTE_OUT1PEN (0x1UL << 1) /**< Output 1 Pin Enable */
#define _LETIMER_ROUTE_OUT1PEN_SHIFT 1 /**< Shift value for LETIMER_OUT1PEN */
#define _LETIMER_ROUTE_OUT1PEN_MASK 0x2UL /**< Bit mask for LETIMER_OUT1PEN */
#define _LETIMER_ROUTE_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTE */
#define LETIMER_ROUTE_OUT1PEN_DEFAULT (_LETIMER_ROUTE_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTE */
#define _LETIMER_ROUTE_LOCATION_SHIFT 8 /**< Shift value for LETIMER_LOCATION */
#define _LETIMER_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for LETIMER_LOCATION */
#define _LETIMER_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTE */
#define _LETIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTE */
#define _LETIMER_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTE */
#define _LETIMER_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTE */
#define _LETIMER_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTE */
#define LETIMER_ROUTE_LOCATION_LOC0 (_LETIMER_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for LETIMER_ROUTE */
#define LETIMER_ROUTE_LOCATION_DEFAULT (_LETIMER_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTE */
#define LETIMER_ROUTE_LOCATION_LOC1 (_LETIMER_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for LETIMER_ROUTE */
#define LETIMER_ROUTE_LOCATION_LOC2 (_LETIMER_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for LETIMER_ROUTE */
#define LETIMER_ROUTE_LOCATION_LOC3 (_LETIMER_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTE */
/** @} End of group EFM32WG_LETIMER */

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FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Include/efm32wg_leuart.h Normal file
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/**************************************************************************//**
* @file efm32wg_leuart.h
* @brief EFM32WG_LEUART register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_LEUART
* @{
* @brief EFM32WG_LEUART Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t CMD; /**< Command Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t CLKDIV; /**< Clock Control Register */
__IO uint32_t STARTFRAME; /**< Start Frame Register */
__IO uint32_t SIGFRAME; /**< Signal Frame Register */
__I uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */
__I uint32_t RXDATA; /**< Receive Buffer Data Register */
__I uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */
__IO uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */
__IO uint32_t TXDATA; /**< Transmit Buffer Data Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t PULSECTRL; /**< Pulse Control Register */
__IO uint32_t FREEZE; /**< Freeze Register */
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
uint32_t RESERVED0[3]; /**< Reserved for future use **/
__IO uint32_t ROUTE; /**< I/O Routing Register */
uint32_t RESERVED1[21]; /**< Reserved for future use **/
__IO uint32_t INPUT; /**< LEUART Input Register */
} LEUART_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_LEUART_BitFields
* @{
*****************************************************************************/
/* Bit fields for LEUART CTRL */
#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */
#define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */
#define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */
#define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */
#define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */
#define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */
#define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */
#define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */
#define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */
#define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */
#define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */
#define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */
#define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */
#define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */
#define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
#define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */
#define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */
#define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */
#define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */
#define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */
#define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */
#define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */
#define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */
#define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */
#define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */
#define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */
#define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */
#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input And Output */
#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */
#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */
#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA On Error */
#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */
#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */
#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */
#define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */
#define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */
#define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */
#define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */
#define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */
#define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */
#define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */
#define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */
#define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */
#define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */
#define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */
#define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */
#define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */
#define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */
#define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */
#define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */
#define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */
#define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */
#define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */
#define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */
#define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */
#define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */
#define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
#define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */
#define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */
#define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */
#define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */
#define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */
#define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */
#define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */
/* Bit fields for LEUART CMD */
#define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */
#define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */
#define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
#define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */
#define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */
#define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
#define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */
#define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */
#define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
#define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */
#define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */
#define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
#define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */
#define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */
#define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */
#define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */
#define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */
#define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */
#define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */
#define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */
#define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
#define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */
#define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */
#define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */
#define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */
#define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */
#define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */
/* Bit fields for LEUART STATUS */
#define _LEUART_STATUS_RESETVALUE 0x00000010UL /**< Default value for LEUART_STATUS */
#define _LEUART_STATUS_MASK 0x0000003FUL /**< Mask for LEUART_STATUS */
#define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
#define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */
#define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */
#define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
#define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */
#define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */
#define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */
#define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */
#define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */
#define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */
#define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */
#define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */
#define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */
#define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */
#define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */
#define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */
#define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */
#define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */
#define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */
/* Bit fields for LEUART CLKDIV */
#define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */
#define _LEUART_CLKDIV_MASK 0x00007FF8UL /**< Mask for LEUART_CLKDIV */
#define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */
#define _LEUART_CLKDIV_DIV_MASK 0x7FF8UL /**< Bit mask for LEUART_DIV */
#define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */
#define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */
/* Bit fields for LEUART STARTFRAME */
#define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */
#define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */
#define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */
#define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */
#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */
#define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */
/* Bit fields for LEUART SIGFRAME */
#define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */
#define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */
#define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */
#define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */
#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */
#define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */
/* Bit fields for LEUART RXDATAX */
#define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */
#define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */
#define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
#define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */
#define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
#define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
#define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */
#define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */
#define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */
#define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
#define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
#define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */
#define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */
#define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */
#define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
#define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
/* Bit fields for LEUART RXDATA */
#define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */
#define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */
#define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
#define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */
#define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */
#define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */
/* Bit fields for LEUART RXDATAXP */
#define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */
#define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */
#define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */
#define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */
#define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
#define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
#define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */
#define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */
#define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */
#define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
#define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
#define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */
#define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */
#define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */
#define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
#define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
/* Bit fields for LEUART TXDATAX */
#define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */
#define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */
#define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */
#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
#define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */
#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */
#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
#define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
#define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */
#define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */
#define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */
#define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
#define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
#define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
#define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */
#define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */
#define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
#define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
/* Bit fields for LEUART TXDATA */
#define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */
#define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */
#define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
#define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */
#define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */
#define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */
/* Bit fields for LEUART IF */
#define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */
#define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */
#define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
#define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
#define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
#define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
#define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
#define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
#define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
#define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
#define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
#define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */
#define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
#define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
#define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */
#define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
#define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
#define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */
#define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
#define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
#define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */
#define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
#define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
#define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */
#define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
#define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
#define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */
#define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
#define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
#define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */
#define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
#define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
#define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */
#define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
#define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
#define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */
/* Bit fields for LEUART IFS */
#define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */
#define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */
#define LEUART_IFS_TXC (0x1UL << 0) /**< Set TX Complete Interrupt Flag */
#define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
#define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
#define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RX Overflow Interrupt Flag */
#define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
#define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
#define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RX Underflow Interrupt Flag */
#define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
#define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
#define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TX Overflow Interrupt Flag */
#define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
#define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
#define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_PERR (0x1UL << 6) /**< Set Parity Error Interrupt Flag */
#define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
#define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
#define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_FERR (0x1UL << 7) /**< Set Framing Error Interrupt Flag */
#define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
#define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
#define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_MPAF (0x1UL << 8) /**< Set Multi-Processor Address Frame Interrupt Flag */
#define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
#define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
#define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_STARTF (0x1UL << 9) /**< Set Start Frame Interrupt Flag */
#define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
#define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
#define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_SIGF (0x1UL << 10) /**< Set Signal Frame Interrupt Flag */
#define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
#define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
#define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */
/* Bit fields for LEUART IFC */
#define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */
#define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */
#define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TX Complete Interrupt Flag */
#define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
#define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
#define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RX Overflow Interrupt Flag */
#define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
#define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
#define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RX Underflow Interrupt Flag */
#define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
#define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
#define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TX Overflow Interrupt Flag */
#define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
#define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
#define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_PERR (0x1UL << 6) /**< Clear Parity Error Interrupt Flag */
#define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
#define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
#define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_FERR (0x1UL << 7) /**< Clear Framing Error Interrupt Flag */
#define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
#define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
#define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear Multi-Processor Address Frame Interrupt Flag */
#define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
#define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
#define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear Start-Frame Interrupt Flag */
#define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
#define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
#define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear Signal-Frame Interrupt Flag */
#define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
#define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
#define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */
/* Bit fields for LEUART IEN */
#define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */
#define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */
#define LEUART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */
#define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
#define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
#define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */
#define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
#define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
#define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */
#define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
#define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
#define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Enable */
#define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
#define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
#define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Enable */
#define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
#define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
#define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Enable */
#define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
#define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
#define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_PERR (0x1UL << 6) /**< Parity Error Interrupt Enable */
#define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
#define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
#define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_FERR (0x1UL << 7) /**< Framing Error Interrupt Enable */
#define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
#define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
#define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Enable */
#define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
#define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
#define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_STARTF (0x1UL << 9) /**< Start Frame Interrupt Enable */
#define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
#define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
#define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Enable */
#define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
#define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
#define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */
/* Bit fields for LEUART PULSECTRL */
#define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */
#define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */
#define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */
#define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */
#define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
#define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
#define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */
#define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */
#define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */
#define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
#define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
#define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */
#define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */
#define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */
#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
#define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
/* Bit fields for LEUART FREEZE */
#define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */
#define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */
#define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
#define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */
#define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */
#define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */
#define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */
#define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */
#define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */
#define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */
#define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */
/* Bit fields for LEUART SYNCBUSY */
#define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */
#define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
#define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */
#define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */
#define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
#define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */
#define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */
#define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */
#define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */
#define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */
#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */
#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */
#define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */
#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */
#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */
#define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */
#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */
#define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */
#define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */
#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */
#define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */
#define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */
#define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */
#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */
#define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */
#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
/* Bit fields for LEUART ROUTE */
#define _LEUART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTE */
#define _LEUART_ROUTE_MASK 0x00000703UL /**< Mask for LEUART_ROUTE */
#define LEUART_ROUTE_RXPEN (0x1UL << 0) /**< RX Pin Enable */
#define _LEUART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */
#define _LEUART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */
#define _LEUART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */
#define LEUART_ROUTE_RXPEN_DEFAULT (_LEUART_ROUTE_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTE */
#define LEUART_ROUTE_TXPEN (0x1UL << 1) /**< TX Pin Enable */
#define _LEUART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */
#define _LEUART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */
#define _LEUART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */
#define LEUART_ROUTE_TXPEN_DEFAULT (_LEUART_ROUTE_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTE */
#define _LEUART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for LEUART_LOCATION */
#define _LEUART_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for LEUART_LOCATION */
#define _LEUART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTE */
#define _LEUART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */
#define _LEUART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTE */
#define _LEUART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTE */
#define _LEUART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTE */
#define _LEUART_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTE */
#define LEUART_ROUTE_LOCATION_LOC0 (_LEUART_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTE */
#define LEUART_ROUTE_LOCATION_DEFAULT (_LEUART_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTE */
#define LEUART_ROUTE_LOCATION_LOC1 (_LEUART_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTE */
#define LEUART_ROUTE_LOCATION_LOC2 (_LEUART_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTE */
#define LEUART_ROUTE_LOCATION_LOC3 (_LEUART_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTE */
#define LEUART_ROUTE_LOCATION_LOC4 (_LEUART_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTE */
/* Bit fields for LEUART INPUT */
#define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */
#define _LEUART_INPUT_MASK 0x0000001FUL /**< Mask for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */
#define _LEUART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for LEUART_RXPRSSEL */
#define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */
#define LEUART_INPUT_RXPRS (0x1UL << 4) /**< PRS RX Enable */
#define _LEUART_INPUT_RXPRS_SHIFT 4 /**< Shift value for LEUART_RXPRS */
#define _LEUART_INPUT_RXPRS_MASK 0x10UL /**< Bit mask for LEUART_RXPRS */
#define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_INPUT */
/** @} End of group EFM32WG_LEUART */

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FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Include/efm32wg_msc.h Normal file
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/**************************************************************************//**
* @file efm32wg_msc.h
* @brief EFM32WG_MSC register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_MSC
* @{
* @brief EFM32WG_MSC Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Memory System Control Register */
__IO uint32_t READCTRL; /**< Read Control Register */
__IO uint32_t WRITECTRL; /**< Write Control Register */
__IO uint32_t WRITECMD; /**< Write Command Register */
__IO uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
uint32_t RESERVED0[1]; /**< Reserved for future use **/
__IO uint32_t WDATA; /**< Write Data Register */
__I uint32_t STATUS; /**< Status Register */
uint32_t RESERVED1[3]; /**< Reserved for future use **/
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t LOCK; /**< Configuration Lock Register */
__IO uint32_t CMD; /**< Command Register */
__I uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
__I uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
uint32_t RESERVED2[1]; /**< Reserved for future use **/
__IO uint32_t TIMEBASE; /**< Flash Write and Erase Timebase */
__IO uint32_t MASSLOCK; /**< Mass Erase Lock Register */
} MSC_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_MSC_BitFields
* @{
*****************************************************************************/
/* Bit fields for MSC CTRL */
#define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */
#define _MSC_CTRL_MASK 0x00000001UL /**< Mask for MSC_CTRL */
#define MSC_CTRL_BUSFAULT (0x1UL << 0) /**< Bus Fault Response Enable */
#define _MSC_CTRL_BUSFAULT_SHIFT 0 /**< Shift value for MSC_BUSFAULT */
#define _MSC_CTRL_BUSFAULT_MASK 0x1UL /**< Bit mask for MSC_BUSFAULT */
#define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL /**< Mode GENERATE for MSC_CTRL */
#define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */
#define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL /**< Mode IGNORE for MSC_CTRL */
#define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0) /**< Shifted mode GENERATE for MSC_CTRL */
#define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */
#define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0) /**< Shifted mode IGNORE for MSC_CTRL */
/* Bit fields for MSC READCTRL */
#define _MSC_READCTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_READCTRL */
#define _MSC_READCTRL_MASK 0x000300FFUL /**< Mask for MSC_READCTRL */
#define _MSC_READCTRL_MODE_SHIFT 0 /**< Shift value for MSC_MODE */
#define _MSC_READCTRL_MODE_MASK 0x7UL /**< Bit mask for MSC_MODE */
#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */
#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */
#define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL /**< Mode WS0SCBTP for MSC_READCTRL */
#define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL /**< Mode WS1SCBTP for MSC_READCTRL */
#define _MSC_READCTRL_MODE_WS2 0x00000004UL /**< Mode WS2 for MSC_READCTRL */
#define _MSC_READCTRL_MODE_WS2SCBTP 0x00000005UL /**< Mode WS2SCBTP for MSC_READCTRL */
#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0) /**< Shifted mode WS0 for MSC_READCTRL */
#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0) /**< Shifted mode WS1 for MSC_READCTRL */
#define MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0) /**< Shifted mode WS0SCBTP for MSC_READCTRL */
#define MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0) /**< Shifted mode WS1SCBTP for MSC_READCTRL */
#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 0) /**< Shifted mode WS2 for MSC_READCTRL */
#define MSC_READCTRL_MODE_WS2SCBTP (_MSC_READCTRL_MODE_WS2SCBTP << 0) /**< Shifted mode WS2SCBTP for MSC_READCTRL */
#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */
#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */
#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */
#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */
#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */
#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */
#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */
#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */
#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */
#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */
#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */
#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */
#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_RAMCEN (0x1UL << 7) /**< RAM Cache Enable */
#define _MSC_READCTRL_RAMCEN_SHIFT 7 /**< Shift value for MSC_RAMCEN */
#define _MSC_READCTRL_RAMCEN_MASK 0x80UL /**< Bit mask for MSC_RAMCEN */
#define _MSC_READCTRL_RAMCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_RAMCEN_DEFAULT (_MSC_READCTRL_RAMCEN_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_READCTRL */
#define _MSC_READCTRL_BUSSTRATEGY_SHIFT 16 /**< Shift value for MSC_BUSSTRATEGY */
#define _MSC_READCTRL_BUSSTRATEGY_MASK 0x30000UL /**< Bit mask for MSC_BUSSTRATEGY */
#define _MSC_READCTRL_BUSSTRATEGY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
#define _MSC_READCTRL_BUSSTRATEGY_CPU 0x00000000UL /**< Mode CPU for MSC_READCTRL */
#define _MSC_READCTRL_BUSSTRATEGY_DMA 0x00000001UL /**< Mode DMA for MSC_READCTRL */
#define _MSC_READCTRL_BUSSTRATEGY_DMAEM1 0x00000002UL /**< Mode DMAEM1 for MSC_READCTRL */
#define _MSC_READCTRL_BUSSTRATEGY_NONE 0x00000003UL /**< Mode NONE for MSC_READCTRL */
#define MSC_READCTRL_BUSSTRATEGY_DEFAULT (_MSC_READCTRL_BUSSTRATEGY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_BUSSTRATEGY_CPU (_MSC_READCTRL_BUSSTRATEGY_CPU << 16) /**< Shifted mode CPU for MSC_READCTRL */
#define MSC_READCTRL_BUSSTRATEGY_DMA (_MSC_READCTRL_BUSSTRATEGY_DMA << 16) /**< Shifted mode DMA for MSC_READCTRL */
#define MSC_READCTRL_BUSSTRATEGY_DMAEM1 (_MSC_READCTRL_BUSSTRATEGY_DMAEM1 << 16) /**< Shifted mode DMAEM1 for MSC_READCTRL */
#define MSC_READCTRL_BUSSTRATEGY_NONE (_MSC_READCTRL_BUSSTRATEGY_NONE << 16) /**< Shifted mode NONE for MSC_READCTRL */
/* Bit fields for MSC WRITECTRL */
#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */
#define _MSC_WRITECTRL_MASK 0x00000003UL /**< Mask for MSC_WRITECTRL */
#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */
#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */
#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */
#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */
#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */
#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
/* Bit fields for MSC WRITECMD */
#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
#define _MSC_WRITECMD_MASK 0x0000113FUL /**< Mask for MSC_WRITECMD */
#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */
#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */
#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */
#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */
#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */
#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */
#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */
#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */
#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */
#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */
#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */
#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */
#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */
#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */
#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */
#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */
#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */
#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */
#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */
#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */
#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */
#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */
#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */
#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */
#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
/* Bit fields for MSC ADDRB */
#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */
#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */
#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */
#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */
#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */
#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
/* Bit fields for MSC WDATA */
#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */
#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */
#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */
#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */
#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */
#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
/* Bit fields for MSC STATUS */
#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */
#define _MSC_STATUS_MASK 0x0000007FUL /**< Mask for MSC_STATUS */
#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */
#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */
#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */
#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */
#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */
#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */
#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */
#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */
#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */
#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */
#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */
#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */
#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */
#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */
#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */
#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */
#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */
#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */
#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */
#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */
#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */
#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */
/* Bit fields for MSC IF */
#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */
#define _MSC_IF_MASK 0x0000000FUL /**< Mask for MSC_IF */
#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */
#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */
#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */
#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */
#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */
#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */
#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */
#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */
/* Bit fields for MSC IFS */
#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */
#define _MSC_IFS_MASK 0x0000000FUL /**< Mask for MSC_IFS */
#define MSC_IFS_ERASE (0x1UL << 0) /**< Erase Done Interrupt Set */
#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */
#define MSC_IFS_WRITE (0x1UL << 1) /**< Write Done Interrupt Set */
#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */
#define MSC_IFS_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Set */
#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */
#define MSC_IFS_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Set */
#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */
/* Bit fields for MSC IFC */
#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */
#define _MSC_IFC_MASK 0x0000000FUL /**< Mask for MSC_IFC */
#define MSC_IFC_ERASE (0x1UL << 0) /**< Erase Done Interrupt Clear */
#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */
#define MSC_IFC_WRITE (0x1UL << 1) /**< Write Done Interrupt Clear */
#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */
#define MSC_IFC_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Clear */
#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */
#define MSC_IFC_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Clear */
#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */
/* Bit fields for MSC IEN */
#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */
#define _MSC_IEN_MASK 0x0000000FUL /**< Mask for MSC_IEN */
#define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt Enable */
#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */
#define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt Enable */
#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */
#define MSC_IEN_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Enable */
#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */
#define MSC_IEN_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Enable */
#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */
/* Bit fields for MSC LOCK */
#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */
#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
/* Bit fields for MSC CMD */
#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */
#define _MSC_CMD_MASK 0x00000007UL /**< Mask for MSC_CMD */
#define MSC_CMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */
#define _MSC_CMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */
#define _MSC_CMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */
#define _MSC_CMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
#define MSC_CMD_INVCACHE_DEFAULT (_MSC_CMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
#define MSC_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */
#define _MSC_CMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */
#define _MSC_CMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */
#define _MSC_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
#define MSC_CMD_STARTPC_DEFAULT (_MSC_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */
#define MSC_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */
#define _MSC_CMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */
#define _MSC_CMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */
#define _MSC_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
#define MSC_CMD_STOPPC_DEFAULT (_MSC_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CMD */
/* Bit fields for MSC CACHEHITS */
#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */
#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */
#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */
#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */
#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */
#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */
/* Bit fields for MSC CACHEMISSES */
#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */
#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */
#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */
#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */
#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */
#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */
/* Bit fields for MSC TIMEBASE */
#define _MSC_TIMEBASE_RESETVALUE 0x00000010UL /**< Default value for MSC_TIMEBASE */
#define _MSC_TIMEBASE_MASK 0x0001003FUL /**< Mask for MSC_TIMEBASE */
#define _MSC_TIMEBASE_BASE_SHIFT 0 /**< Shift value for MSC_BASE */
#define _MSC_TIMEBASE_BASE_MASK 0x3FUL /**< Bit mask for MSC_BASE */
#define _MSC_TIMEBASE_BASE_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_TIMEBASE */
#define MSC_TIMEBASE_BASE_DEFAULT (_MSC_TIMEBASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_TIMEBASE */
#define MSC_TIMEBASE_PERIOD (0x1UL << 16) /**< Sets the timebase period */
#define _MSC_TIMEBASE_PERIOD_SHIFT 16 /**< Shift value for MSC_PERIOD */
#define _MSC_TIMEBASE_PERIOD_MASK 0x10000UL /**< Bit mask for MSC_PERIOD */
#define _MSC_TIMEBASE_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_TIMEBASE */
#define _MSC_TIMEBASE_PERIOD_1US 0x00000000UL /**< Mode 1US for MSC_TIMEBASE */
#define _MSC_TIMEBASE_PERIOD_5US 0x00000001UL /**< Mode 5US for MSC_TIMEBASE */
#define MSC_TIMEBASE_PERIOD_DEFAULT (_MSC_TIMEBASE_PERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_TIMEBASE */
#define MSC_TIMEBASE_PERIOD_1US (_MSC_TIMEBASE_PERIOD_1US << 16) /**< Shifted mode 1US for MSC_TIMEBASE */
#define MSC_TIMEBASE_PERIOD_5US (_MSC_TIMEBASE_PERIOD_5US << 16) /**< Shifted mode 5US for MSC_TIMEBASE */
/* Bit fields for MSC MASSLOCK */
#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */
#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
/** @} End of group EFM32WG_MSC */

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/**************************************************************************//**
* @file efm32wg_pcnt.h
* @brief EFM32WG_PCNT register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_PCNT
* @{
* @brief EFM32WG_PCNT Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t CMD; /**< Command Register */
__I uint32_t STATUS; /**< Status Register */
__I uint32_t CNT; /**< Counter Value Register */
__I uint32_t TOP; /**< Top Value Register */
__IO uint32_t TOPB; /**< Top Value Buffer Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t ROUTE; /**< I/O Routing Register */
__IO uint32_t FREEZE; /**< Freeze Register */
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
uint32_t RESERVED0[1]; /**< Reserved for future use **/
__IO uint32_t AUXCNT; /**< Auxiliary Counter Value Register */
__IO uint32_t INPUT; /**< PCNT Input Register */
} PCNT_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_PCNT_BitFields
* @{
*****************************************************************************/
/* Bit fields for PCNT CTRL */
#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */
#define _PCNT_CTRL_MASK 0x0000CF3FUL /**< Mask for PCNT_CTRL */
#define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */
#define _PCNT_CTRL_MODE_MASK 0x3UL /**< Bit mask for PCNT_MODE */
#define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */
#define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL /**< Mode OVSSINGLE for PCNT_CTRL */
#define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */
#define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */
#define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for PCNT_CTRL */
#define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CTRL */
#define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */
#define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */
#define PCNT_CTRL_CNTDIR (0x1UL << 2) /**< Non-Quadrature Mode Counter Direction Control */
#define _PCNT_CTRL_CNTDIR_SHIFT 2 /**< Shift value for PCNT_CNTDIR */
#define _PCNT_CTRL_CNTDIR_MASK 0x4UL /**< Bit mask for PCNT_CNTDIR */
#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */
#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */
#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 2) /**< Shifted mode UP for PCNT_CTRL */
#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 2) /**< Shifted mode DOWN for PCNT_CTRL */
#define PCNT_CTRL_EDGE (0x1UL << 3) /**< Edge Select */
#define _PCNT_CTRL_EDGE_SHIFT 3 /**< Shift value for PCNT_EDGE */
#define _PCNT_CTRL_EDGE_MASK 0x8UL /**< Bit mask for PCNT_EDGE */
#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */
#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */
#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 3) /**< Shifted mode POS for PCNT_CTRL */
#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 3) /**< Shifted mode NEG for PCNT_CTRL */
#define PCNT_CTRL_FILT (0x1UL << 4) /**< Enable Digital Pulse Width Filter */
#define _PCNT_CTRL_FILT_SHIFT 4 /**< Shift value for PCNT_FILT */
#define _PCNT_CTRL_FILT_MASK 0x10UL /**< Bit mask for PCNT_FILT */
#define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_RSTEN (0x1UL << 5) /**< Enable PCNT Clock Domain Reset */
#define _PCNT_CTRL_RSTEN_SHIFT 5 /**< Shift value for PCNT_RSTEN */
#define _PCNT_CTRL_RSTEN_MASK 0x20UL /**< Bit mask for PCNT_RSTEN */
#define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_HYST (0x1UL << 8) /**< Enable Hysteresis */
#define _PCNT_CTRL_HYST_SHIFT 8 /**< Shift value for PCNT_HYST */
#define _PCNT_CTRL_HYST_MASK 0x100UL /**< Bit mask for PCNT_HYST */
#define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count direction determined by S1 */
#define _PCNT_CTRL_S1CDIR_SHIFT 9 /**< Shift value for PCNT_S1CDIR */
#define _PCNT_CTRL_S1CDIR_MASK 0x200UL /**< Bit mask for PCNT_S1CDIR */
#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_CNTEV_SHIFT 10 /**< Shift value for PCNT_CNTEV */
#define _PCNT_CTRL_CNTEV_MASK 0xC00UL /**< Bit mask for PCNT_CNTEV */
#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */
#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */
#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */
#define _PCNT_CTRL_CNTEV_NONE 0x00000003UL /**< Mode NONE for PCNT_CTRL */
#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 10) /**< Shifted mode BOTH for PCNT_CTRL */
#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 10) /**< Shifted mode UP for PCNT_CTRL */
#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 10) /**< Shifted mode DOWN for PCNT_CTRL */
#define PCNT_CTRL_CNTEV_NONE (_PCNT_CTRL_CNTEV_NONE << 10) /**< Shifted mode NONE for PCNT_CTRL */
#define _PCNT_CTRL_AUXCNTEV_SHIFT 14 /**< Shift value for PCNT_AUXCNTEV */
#define _PCNT_CTRL_AUXCNTEV_MASK 0xC000UL /**< Bit mask for PCNT_AUXCNTEV */
#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_AUXCNTEV_NONE 0x00000000UL /**< Mode NONE for PCNT_CTRL */
#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */
#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */
#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000003UL /**< Mode BOTH for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 14) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTEV_NONE (_PCNT_CTRL_AUXCNTEV_NONE << 14) /**< Shifted mode NONE for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 14) /**< Shifted mode UP for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 14) /**< Shifted mode DOWN for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 14) /**< Shifted mode BOTH for PCNT_CTRL */
/* Bit fields for PCNT CMD */
#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */
#define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */
#define PCNT_CMD_LCNTIM (0x1UL << 0) /**< Load CNT Immediately */
#define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */
#define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */
#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_LTOPBIM (0x1UL << 1) /**< Load TOPB Immediately */
#define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */
#define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */
#define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */
/* Bit fields for PCNT STATUS */
#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */
#define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */
#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */
#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */
#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */
#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */
#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */
#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */
#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */
#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */
/* Bit fields for PCNT CNT */
#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */
#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */
#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */
#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */
#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */
#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */
/* Bit fields for PCNT TOP */
#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */
#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */
#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */
#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */
#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */
#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */
/* Bit fields for PCNT TOPB */
#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */
#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */
#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */
#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */
#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */
#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */
/* Bit fields for PCNT IF */
#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */
#define _PCNT_IF_MASK 0x0000000FUL /**< Mask for PCNT_IF */
#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */
#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */
#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */
#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */
#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */
#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */
#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */
#define PCNT_IF_AUXOF (0x1UL << 3) /**< Overflow Interrupt Read Flag */
#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */
/* Bit fields for PCNT IFS */
#define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */
#define _PCNT_IFS_MASK 0x0000000FUL /**< Mask for PCNT_IFS */
#define PCNT_IFS_UF (0x1UL << 0) /**< Underflow interrupt set */
#define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */
#define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
#define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_OF (0x1UL << 1) /**< Overflow Interrupt Set */
#define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */
#define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
#define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Set */
#define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
#define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
#define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Set */
#define _PCNT_IFS_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
#define _PCNT_IFS_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
#define _PCNT_IFS_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_AUXOF_DEFAULT (_PCNT_IFS_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFS */
/* Bit fields for PCNT IFC */
#define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */
#define _PCNT_IFC_MASK 0x0000000FUL /**< Mask for PCNT_IFC */
#define PCNT_IFC_UF (0x1UL << 0) /**< Underflow Interrupt Clear */
#define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */
#define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
#define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_OF (0x1UL << 1) /**< Overflow Interrupt Clear */
#define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */
#define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
#define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Clear */
#define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
#define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
#define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Clear */
#define _PCNT_IFC_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
#define _PCNT_IFC_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
#define _PCNT_IFC_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_AUXOF_DEFAULT (_PCNT_IFC_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFC */
/* Bit fields for PCNT IEN */
#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */
#define _PCNT_IEN_MASK 0x0000000FUL /**< Mask for PCNT_IEN */
#define PCNT_IEN_UF (0x1UL << 0) /**< Underflow Interrupt Enable */
#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */
#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_OF (0x1UL << 1) /**< Overflow Interrupt Enable */
#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */
#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */
#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Enable */
#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */
/* Bit fields for PCNT ROUTE */
#define _PCNT_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTE */
#define _PCNT_ROUTE_MASK 0x00000700UL /**< Mask for PCNT_ROUTE */
#define _PCNT_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PCNT_LOCATION */
#define _PCNT_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PCNT_LOCATION */
#define _PCNT_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTE */
#define _PCNT_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTE */
#define _PCNT_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTE */
#define _PCNT_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTE */
#define _PCNT_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTE */
#define PCNT_ROUTE_LOCATION_LOC0 (_PCNT_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PCNT_ROUTE */
#define PCNT_ROUTE_LOCATION_DEFAULT (_PCNT_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTE */
#define PCNT_ROUTE_LOCATION_LOC1 (_PCNT_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PCNT_ROUTE */
#define PCNT_ROUTE_LOCATION_LOC2 (_PCNT_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for PCNT_ROUTE */
#define PCNT_ROUTE_LOCATION_LOC3 (_PCNT_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for PCNT_ROUTE */
/* Bit fields for PCNT FREEZE */
#define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */
#define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */
#define PCNT_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
#define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */
#define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */
#define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */
#define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */
#define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */
#define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */
#define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */
#define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */
/* Bit fields for PCNT SYNCBUSY */
#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */
#define _PCNT_SYNCBUSY_MASK 0x00000007UL /**< Mask for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */
#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */
#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */
#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */
#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_TOPB (0x1UL << 2) /**< TOPB Register Busy */
#define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */
#define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */
#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
/* Bit fields for PCNT AUXCNT */
#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */
#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */
#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */
#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */
#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */
#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */
/* Bit fields for PCNT INPUT */
#define _PCNT_INPUT_RESETVALUE 0x00000000UL /**< Default value for PCNT_INPUT */
#define _PCNT_INPUT_MASK 0x000007DFUL /**< Mask for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_SHIFT 0 /**< Shift value for PCNT_S0PRSSEL */
#define _PCNT_INPUT_S0PRSSEL_MASK 0xFUL /**< Bit mask for PCNT_S0PRSSEL */
#define _PCNT_INPUT_S0PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_DEFAULT (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH0 (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH1 (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH2 (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH3 (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH4 (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH5 (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH6 (_PCNT_INPUT_S0PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH7 (_PCNT_INPUT_S0PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH8 (_PCNT_INPUT_S0PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH9 (_PCNT_INPUT_S0PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH10 (_PCNT_INPUT_S0PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH11 (_PCNT_INPUT_S0PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSEN (0x1UL << 4) /**< S0IN PRS Enable */
#define _PCNT_INPUT_S0PRSEN_SHIFT 4 /**< Shift value for PCNT_S0PRSEN */
#define _PCNT_INPUT_S0PRSEN_MASK 0x10UL /**< Bit mask for PCNT_S0PRSEN */
#define _PCNT_INPUT_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
#define PCNT_INPUT_S0PRSEN_DEFAULT (_PCNT_INPUT_S0PRSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_SHIFT 6 /**< Shift value for PCNT_S1PRSSEL */
#define _PCNT_INPUT_S1PRSSEL_MASK 0x3C0UL /**< Bit mask for PCNT_S1PRSSEL */
#define _PCNT_INPUT_S1PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_DEFAULT (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH0 (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH1 (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH2 (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH3 (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH4 (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH5 (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH6 (_PCNT_INPUT_S1PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH7 (_PCNT_INPUT_S1PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH8 (_PCNT_INPUT_S1PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH9 (_PCNT_INPUT_S1PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH10 (_PCNT_INPUT_S1PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH11 (_PCNT_INPUT_S1PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSEN (0x1UL << 10) /**< S1IN PRS Enable */
#define _PCNT_INPUT_S1PRSEN_SHIFT 10 /**< Shift value for PCNT_S1PRSEN */
#define _PCNT_INPUT_S1PRSEN_MASK 0x400UL /**< Bit mask for PCNT_S1PRSEN */
#define _PCNT_INPUT_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_INPUT */
/** @} End of group EFM32WG_PCNT */

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/**************************************************************************//**
* @file efm32wg_prs.h
* @brief EFM32WG_PRS register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_PRS
* @{
* @brief EFM32WG_PRS Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t SWPULSE; /**< Software Pulse Register */
__IO uint32_t SWLEVEL; /**< Software Level Register */
__IO uint32_t ROUTE; /**< I/O Routing Register */
uint32_t RESERVED0[1]; /**< Reserved registers */
PRS_CH_TypeDef CH[12]; /**< Channel registers */
} PRS_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_PRS_BitFields
* @{
*****************************************************************************/
/* Bit fields for PRS SWPULSE */
#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */
#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */
#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */
#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */
#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */
#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */
#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */
#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */
#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */
#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */
#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */
#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */
#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */
#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */
#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */
#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */
#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */
#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */
#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */
#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */
#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */
#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */
#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */
#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */
#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */
#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */
#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */
#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */
#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */
#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */
#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */
#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */
#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */
#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */
#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */
#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */
#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */
#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */
#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */
/* Bit fields for PRS SWLEVEL */
#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */
#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */
#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */
#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */
#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */
#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */
#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */
#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */
#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */
#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */
#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */
#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */
#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */
#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */
#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */
#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */
#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */
#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */
#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */
#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */
#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */
#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */
#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */
#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */
#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */
#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */
#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */
#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */
#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */
#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */
#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */
#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */
#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */
#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */
#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */
#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */
#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */
#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
/* Bit fields for PRS ROUTE */
#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */
#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */
#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */
#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */
#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */
#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */
#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */
#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */
#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */
#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */
#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */
#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */
#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */
#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */
#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */
#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */
#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */
#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */
#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */
#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */
#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */
#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */
#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */
#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */
#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */
/* Bit fields for PRS CH_CTRL */
#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */
#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */
#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */
#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */
#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */
#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_USB 0x00000024UL /**< Mode USB for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */
#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 16) /**< Shifted mode USB for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */
#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */
#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */
#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */
#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */
#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */
#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */
#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */
#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */
#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */
#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */
#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */
#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */
#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */
#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */
#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
/** @} End of group EFM32WG_PRS */

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FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Include/efm32wg_prs_ch.h Normal file
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/**************************************************************************//**
* @file efm32wg_prs_ch.h
* @brief EFM32WG_PRS_CH register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @brief PRS_CH EFM32WG PRS CH
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Channel Control Register */
} PRS_CH_TypeDef;

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/**************************************************************************//**
* @file efm32wg_prs_signals.h
* @brief EFM32WG_PRS_SIGNALS register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup EFM32WG_PRS_Signals
* @{
* @brief PRS Signal names
*****************************************************************************/
#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */
#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */
#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */
#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */
#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */
#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */
#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */
#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */
#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */
#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */
#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */
#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */
#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */
#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */
#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */
#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */
#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */
#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */
#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */
#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */
#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */
#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */
#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */
#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */
#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */
#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */
#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */
#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */
#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */
#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */
#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */
#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */
#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */
#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */
#define PRS_USB_SOF ((36 << 16) + 0) /**< PRS USB Start of Frame */
#define PRS_USB_SOFSR ((36 << 16) + 1) /**< PRS USB Start of Frame Sent/Received */
#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */
#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */
#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */
#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */
#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */
#define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */
#define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */
#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */
#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */
#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */
#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */
#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */
#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */
#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */
#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */
#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */
#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */
#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */
#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */
#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */
#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */
#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */
#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */
#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */
#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */
#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */
#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */
#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */
#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */
#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */
#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */
#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */
#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */
#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */
#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */
#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */
#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */
#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */
#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */
#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */
#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */
#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */
#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */
#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */
#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */
#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */
/** @} End of group EFM32WG_PRS */

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/**************************************************************************//**
* @file efm32wg_rmu.h
* @brief EFM32WG_RMU register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_RMU
* @{
* @brief EFM32WG_RMU Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__I uint32_t RSTCAUSE; /**< Reset Cause Register */
__O uint32_t CMD; /**< Command Register */
} RMU_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_RMU_BitFields
* @{
*****************************************************************************/
/* Bit fields for RMU CTRL */
#define _RMU_CTRL_RESETVALUE 0x00000002UL /**< Default value for RMU_CTRL */
#define _RMU_CTRL_MASK 0x00000003UL /**< Mask for RMU_CTRL */
#define RMU_CTRL_LOCKUPRDIS (0x1UL << 0) /**< Lockup Reset Disable */
#define _RMU_CTRL_LOCKUPRDIS_SHIFT 0 /**< Shift value for RMU_LOCKUPRDIS */
#define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL /**< Bit mask for RMU_LOCKUPRDIS */
#define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */
#define RMU_CTRL_LOCKUPRDIS_DEFAULT (_RMU_CTRL_LOCKUPRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */
#define RMU_CTRL_BURSTEN (0x1UL << 1) /**< Backup domain reset enable */
#define _RMU_CTRL_BURSTEN_SHIFT 1 /**< Shift value for RMU_BURSTEN */
#define _RMU_CTRL_BURSTEN_MASK 0x2UL /**< Bit mask for RMU_BURSTEN */
#define _RMU_CTRL_BURSTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for RMU_CTRL */
#define RMU_CTRL_BURSTEN_DEFAULT (_RMU_CTRL_BURSTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_CTRL */
/* Bit fields for RMU RSTCAUSE */
#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */
#define _RMU_RSTCAUSE_MASK 0x0000FFFFUL /**< Mask for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */
#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */
#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */
#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODUNREGRST (0x1UL << 1) /**< Brown Out Detector Unregulated Domain Reset */
#define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1 /**< Shift value for RMU_BODUNREGRST */
#define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL /**< Bit mask for RMU_BODUNREGRST */
#define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODUNREGRST_DEFAULT (_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODREGRST (0x1UL << 2) /**< Brown Out Detector Regulated Domain Reset */
#define _RMU_RSTCAUSE_BODREGRST_SHIFT 2 /**< Shift value for RMU_BODREGRST */
#define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL /**< Bit mask for RMU_BODREGRST */
#define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODREGRST_DEFAULT (_RMU_RSTCAUSE_BODREGRST_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EXTRST (0x1UL << 3) /**< External Pin Reset */
#define _RMU_RSTCAUSE_EXTRST_SHIFT 3 /**< Shift value for RMU_EXTRST */
#define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL /**< Bit mask for RMU_EXTRST */
#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_WDOGRST (0x1UL << 4) /**< Watchdog Reset */
#define _RMU_RSTCAUSE_WDOGRST_SHIFT 4 /**< Shift value for RMU_WDOGRST */
#define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL /**< Bit mask for RMU_WDOGRST */
#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 5) /**< LOCKUP Reset */
#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5 /**< Shift value for RMU_LOCKUPRST */
#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL /**< Bit mask for RMU_LOCKUPRST */
#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 5) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 6) /**< System Request Reset */
#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6 /**< Shift value for RMU_SYSREQRST */
#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL /**< Bit mask for RMU_SYSREQRST */
#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 6) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EM4RST (0x1UL << 7) /**< EM4 Reset */
#define _RMU_RSTCAUSE_EM4RST_SHIFT 7 /**< Shift value for RMU_EM4RST */
#define _RMU_RSTCAUSE_EM4RST_MASK 0x80UL /**< Bit mask for RMU_EM4RST */
#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 7) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EM4WURST (0x1UL << 8) /**< EM4 Wake-up Reset */
#define _RMU_RSTCAUSE_EM4WURST_SHIFT 8 /**< Shift value for RMU_EM4WURST */
#define _RMU_RSTCAUSE_EM4WURST_MASK 0x100UL /**< Bit mask for RMU_EM4WURST */
#define _RMU_RSTCAUSE_EM4WURST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EM4WURST_DEFAULT (_RMU_RSTCAUSE_EM4WURST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODAVDD0 (0x1UL << 9) /**< AVDD0 Bod Reset */
#define _RMU_RSTCAUSE_BODAVDD0_SHIFT 9 /**< Shift value for RMU_BODAVDD0 */
#define _RMU_RSTCAUSE_BODAVDD0_MASK 0x200UL /**< Bit mask for RMU_BODAVDD0 */
#define _RMU_RSTCAUSE_BODAVDD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODAVDD0_DEFAULT (_RMU_RSTCAUSE_BODAVDD0_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODAVDD1 (0x1UL << 10) /**< AVDD1 Bod Reset */
#define _RMU_RSTCAUSE_BODAVDD1_SHIFT 10 /**< Shift value for RMU_BODAVDD1 */
#define _RMU_RSTCAUSE_BODAVDD1_MASK 0x400UL /**< Bit mask for RMU_BODAVDD1 */
#define _RMU_RSTCAUSE_BODAVDD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODAVDD1_DEFAULT (_RMU_RSTCAUSE_BODAVDD1_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODVDDDREG (0x1UL << 11) /**< Backup Brown Out Detector, VDD_DREG */
#define _RMU_RSTCAUSE_BUBODVDDDREG_SHIFT 11 /**< Shift value for RMU_BUBODVDDDREG */
#define _RMU_RSTCAUSE_BUBODVDDDREG_MASK 0x800UL /**< Bit mask for RMU_BUBODVDDDREG */
#define _RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT (_RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODBUVIN (0x1UL << 12) /**< Backup Brown Out Detector, BU_VIN */
#define _RMU_RSTCAUSE_BUBODBUVIN_SHIFT 12 /**< Shift value for RMU_BUBODBUVIN */
#define _RMU_RSTCAUSE_BUBODBUVIN_MASK 0x1000UL /**< Bit mask for RMU_BUBODBUVIN */
#define _RMU_RSTCAUSE_BUBODBUVIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODBUVIN_DEFAULT (_RMU_RSTCAUSE_BUBODBUVIN_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODUNREG (0x1UL << 13) /**< Backup Brown Out Detector Unregulated Domain */
#define _RMU_RSTCAUSE_BUBODUNREG_SHIFT 13 /**< Shift value for RMU_BUBODUNREG */
#define _RMU_RSTCAUSE_BUBODUNREG_MASK 0x2000UL /**< Bit mask for RMU_BUBODUNREG */
#define _RMU_RSTCAUSE_BUBODUNREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODUNREG_DEFAULT (_RMU_RSTCAUSE_BUBODUNREG_DEFAULT << 13) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODREG (0x1UL << 14) /**< Backup Brown Out Detector Regulated Domain */
#define _RMU_RSTCAUSE_BUBODREG_SHIFT 14 /**< Shift value for RMU_BUBODREG */
#define _RMU_RSTCAUSE_BUBODREG_MASK 0x4000UL /**< Bit mask for RMU_BUBODREG */
#define _RMU_RSTCAUSE_BUBODREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODREG_DEFAULT (_RMU_RSTCAUSE_BUBODREG_DEFAULT << 14) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUMODERST (0x1UL << 15) /**< Backup mode reset */
#define _RMU_RSTCAUSE_BUMODERST_SHIFT 15 /**< Shift value for RMU_BUMODERST */
#define _RMU_RSTCAUSE_BUMODERST_MASK 0x8000UL /**< Bit mask for RMU_BUMODERST */
#define _RMU_RSTCAUSE_BUMODERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUMODERST_DEFAULT (_RMU_RSTCAUSE_BUMODERST_DEFAULT << 15) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
/* Bit fields for RMU CMD */
#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */
#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */
#define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */
#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */
#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */
#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */
#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
/** @} End of group EFM32WG_RMU */

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/**************************************************************************//**
* @file efm32wg_romtable.h
* @brief EFM32WG_ROMTABLE register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_ROMTABLE
* @{
* @brief Chip Information, Revision numbers
*****************************************************************************/
typedef struct
{
__I uint32_t PID4; /**< JEP_106_BANK */
__I uint32_t PID5; /**< Unused */
__I uint32_t PID6; /**< Unused */
__I uint32_t PID7; /**< Unused */
__I uint32_t PID0; /**< Chip family LSB, chip major revision */
__I uint32_t PID1; /**< JEP_106_NO, Chip family MSB */
__I uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */
__I uint32_t PID3; /**< Chip minor rev LSB */
__I uint32_t CID0; /**< Unused */
} ROMTABLE_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_ROMTABLE_BitFields
* @{
*****************************************************************************/
/* Bit fields for EFM32WG_ROMTABLE */
#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */
#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */
#define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL /**< CHIP MAJOR Revison, mask */
#define _ROMTABLE_PID0_REVMAJOR_SHIFT 0 /**< CHIP MAJOR Revison, shift */
#define _ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL /**< Most Significant Bits [5:2] of CHIP FAMILY, mask */
#define _ROMTABLE_PID1_FAMILYMSB_SHIFT 0 /**< Most Significant Bits [5:2] of CHIP FAMILY, shift */
#define _ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */
#define _ROMTABLE_PID2_REVMINORMSB_SHIFT 4 /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */
#define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /**< Least Significant Bits [3:0] of CHIP MINOR revision, mask */
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
/** @} End of group EFM32WG_ROMTABLE */

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/**************************************************************************//**
* @file efm32wg_rtc.h
* @brief EFM32WG_RTC register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_RTC
* @{
* @brief EFM32WG_RTC Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t CNT; /**< Counter Value Register */
__IO uint32_t COMP0; /**< Compare Value Register 0 */
__IO uint32_t COMP1; /**< Compare Value Register 1 */
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t FREEZE; /**< Freeze Register */
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
} RTC_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_RTC_BitFields
* @{
*****************************************************************************/
/* Bit fields for RTC CTRL */
#define _RTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTC_CTRL */
#define _RTC_CTRL_MASK 0x00000007UL /**< Mask for RTC_CTRL */
#define RTC_CTRL_EN (0x1UL << 0) /**< RTC Enable */
#define _RTC_CTRL_EN_SHIFT 0 /**< Shift value for RTC_EN */
#define _RTC_CTRL_EN_MASK 0x1UL /**< Bit mask for RTC_EN */
#define _RTC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
#define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CTRL */
#define RTC_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
#define _RTC_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for RTC_DEBUGRUN */
#define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for RTC_DEBUGRUN */
#define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
#define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_CTRL */
#define RTC_CTRL_COMP0TOP (0x1UL << 2) /**< Compare Channel 0 is Top Value */
#define _RTC_CTRL_COMP0TOP_SHIFT 2 /**< Shift value for RTC_COMP0TOP */
#define _RTC_CTRL_COMP0TOP_MASK 0x4UL /**< Bit mask for RTC_COMP0TOP */
#define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
#define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /**< Mode DISABLE for RTC_CTRL */
#define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /**< Mode ENABLE for RTC_CTRL */
#define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_CTRL */
#define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) /**< Shifted mode DISABLE for RTC_CTRL */
#define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) /**< Shifted mode ENABLE for RTC_CTRL */
/* Bit fields for RTC CNT */
#define _RTC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTC_CNT */
#define _RTC_CNT_MASK 0x00FFFFFFUL /**< Mask for RTC_CNT */
#define _RTC_CNT_CNT_SHIFT 0 /**< Shift value for RTC_CNT */
#define _RTC_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for RTC_CNT */
#define _RTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CNT */
#define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CNT */
/* Bit fields for RTC COMP0 */
#define _RTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP0 */
#define _RTC_COMP0_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP0 */
#define _RTC_COMP0_COMP0_SHIFT 0 /**< Shift value for RTC_COMP0 */
#define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP0 */
#define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP0 */
#define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP0 */
/* Bit fields for RTC COMP1 */
#define _RTC_COMP1_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP1 */
#define _RTC_COMP1_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP1 */
#define _RTC_COMP1_COMP1_SHIFT 0 /**< Shift value for RTC_COMP1 */
#define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP1 */
#define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP1 */
#define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP1 */
/* Bit fields for RTC IF */
#define _RTC_IF_RESETVALUE 0x00000000UL /**< Default value for RTC_IF */
#define _RTC_IF_MASK 0x00000007UL /**< Mask for RTC_IF */
#define RTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
#define _RTC_IF_OF_SHIFT 0 /**< Shift value for RTC_OF */
#define _RTC_IF_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
#define _RTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
#define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IF */
#define RTC_IF_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Flag */
#define _RTC_IF_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
#define _RTC_IF_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
#define _RTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
#define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IF */
#define RTC_IF_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Flag */
#define _RTC_IF_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
#define _RTC_IF_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
#define _RTC_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
#define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IF */
/* Bit fields for RTC IFS */
#define _RTC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTC_IFS */
#define _RTC_IFS_MASK 0x00000007UL /**< Mask for RTC_IFS */
#define RTC_IFS_OF (0x1UL << 0) /**< Set Overflow Interrupt Flag */
#define _RTC_IFS_OF_SHIFT 0 /**< Shift value for RTC_OF */
#define _RTC_IFS_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
#define _RTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
#define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFS */
#define RTC_IFS_COMP0 (0x1UL << 1) /**< Set Compare match 0 Interrupt Flag */
#define _RTC_IFS_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
#define _RTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
#define _RTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
#define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFS */
#define RTC_IFS_COMP1 (0x1UL << 2) /**< Set Compare match 1 Interrupt Flag */
#define _RTC_IFS_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
#define _RTC_IFS_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
#define _RTC_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
#define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFS */
/* Bit fields for RTC IFC */
#define _RTC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTC_IFC */
#define _RTC_IFC_MASK 0x00000007UL /**< Mask for RTC_IFC */
#define RTC_IFC_OF (0x1UL << 0) /**< Clear Overflow Interrupt Flag */
#define _RTC_IFC_OF_SHIFT 0 /**< Shift value for RTC_OF */
#define _RTC_IFC_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
#define _RTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
#define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFC */
#define RTC_IFC_COMP0 (0x1UL << 1) /**< Clear Compare match 0 Interrupt Flag */
#define _RTC_IFC_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
#define _RTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
#define _RTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
#define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFC */
#define RTC_IFC_COMP1 (0x1UL << 2) /**< Clear Compare match 1 Interrupt Flag */
#define _RTC_IFC_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
#define _RTC_IFC_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
#define _RTC_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
#define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFC */
/* Bit fields for RTC IEN */
#define _RTC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTC_IEN */
#define _RTC_IEN_MASK 0x00000007UL /**< Mask for RTC_IEN */
#define RTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */
#define _RTC_IEN_OF_SHIFT 0 /**< Shift value for RTC_OF */
#define _RTC_IEN_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
#define _RTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
#define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IEN */
#define RTC_IEN_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Enable */
#define _RTC_IEN_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
#define _RTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
#define _RTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
#define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IEN */
#define RTC_IEN_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Enable */
#define _RTC_IEN_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
#define _RTC_IEN_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
#define _RTC_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
#define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IEN */
/* Bit fields for RTC FREEZE */
#define _RTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for RTC_FREEZE */
#define _RTC_FREEZE_MASK 0x00000001UL /**< Mask for RTC_FREEZE */
#define RTC_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
#define _RTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for RTC_REGFREEZE */
#define _RTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for RTC_REGFREEZE */
#define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_FREEZE */
#define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for RTC_FREEZE */
#define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for RTC_FREEZE */
#define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_FREEZE */
#define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for RTC_FREEZE */
#define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for RTC_FREEZE */
/* Bit fields for RTC SYNCBUSY */
#define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTC_SYNCBUSY */
#define _RTC_SYNCBUSY_MASK 0x00000007UL /**< Mask for RTC_SYNCBUSY */
#define RTC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
#define _RTC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for RTC_CTRL */
#define _RTC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for RTC_CTRL */
#define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
#define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
#define RTC_SYNCBUSY_COMP0 (0x1UL << 1) /**< COMP0 Register Busy */
#define _RTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
#define _RTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
#define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
#define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
#define RTC_SYNCBUSY_COMP1 (0x1UL << 2) /**< COMP1 Register Busy */
#define _RTC_SYNCBUSY_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
#define _RTC_SYNCBUSY_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
#define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
#define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
/** @} End of group EFM32WG_RTC */

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/**************************************************************************//**
* @file efm32wg_timer.h
* @brief EFM32WG_TIMER register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_TIMER
* @{
* @brief EFM32WG_TIMER Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t CMD; /**< Command Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t TOP; /**< Counter Top Value Register */
__IO uint32_t TOPB; /**< Counter Top Value Buffer Register */
__IO uint32_t CNT; /**< Counter Value Register */
__IO uint32_t ROUTE; /**< I/O Routing Register */
uint32_t RESERVED0[1]; /**< Reserved registers */
TIMER_CC_TypeDef CC[3]; /**< Compare/Capture Channel */
uint32_t RESERVED1[4]; /**< Reserved for future use **/
__IO uint32_t DTCTRL; /**< DTI Control Register */
__IO uint32_t DTTIME; /**< DTI Time Control Register */
__IO uint32_t DTFC; /**< DTI Fault Configuration Register */
__IO uint32_t DTOGEN; /**< DTI Output Generation Enable Register */
__I uint32_t DTFAULT; /**< DTI Fault Register */
__O uint32_t DTFAULTC; /**< DTI Fault Clear Register */
__IO uint32_t DTLOCK; /**< DTI Configuration Lock Register */
} TIMER_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_TIMER_BitFields
* @{
*****************************************************************************/
/* Bit fields for TIMER CTRL */
#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */
#define _TIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for TIMER_CTRL */
#define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
#define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
#define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */
#define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */
#define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */
#define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */
#define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for TIMER_CTRL */
#define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CTRL */
#define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */
#define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CTRL */
#define TIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */
#define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */
#define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */
#define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */
#define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */
#define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */
#define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */
#define _TIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */
#define _TIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */
#define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */
#define _TIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */
#define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CTRL */
#define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CTRL */
#define TIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */
#define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */
#define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */
#define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */
#define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */
#define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */
#define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */
#define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */
#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for TIMER_CTRL */
#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for TIMER_CTRL */
#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for TIMER_CTRL */
#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */
#define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */
#define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */
#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for TIMER_CTRL */
#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for TIMER_CTRL */
#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for TIMER_CTRL */
#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */
#define TIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */
#define _TIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */
#define _TIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
#define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
#define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */
#define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */
#define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */
#define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */
#define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for TIMER_CTRL */
#define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */
#define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */
#define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */
#define TIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */
#define _TIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */
#define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
#define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
#define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
#define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
#define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_RSSCOIST_DEFAULT (_TIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CTRL */
/* Bit fields for TIMER CMD */
#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */
#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */
#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */
#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */
#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */
#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */
#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */
#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */
#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */
#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */
/* Bit fields for TIMER STATUS */
#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */
#define _TIMER_STATUS_MASK 0x07070707UL /**< Mask for TIMER_STATUS */
#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */
#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */
#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */
#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */
#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */
#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */
#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */
#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */
#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */
#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */
#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */
#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */
#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */
#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */
#define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */
#define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */
#define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */
#define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */
#define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */
#define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */
#define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */
#define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */
#define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */
#define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */
#define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */
#define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */
#define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */
#define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */
#define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */
#define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */
#define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */
#define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */
#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */
#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */
#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */
#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */
#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */
#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */
#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */
#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */
#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */
#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */
#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */
#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */
#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */
#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */
/* Bit fields for TIMER IEN */
#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */
#define _TIMER_IEN_MASK 0x00000773UL /**< Mask for TIMER_IEN */
#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */
#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */
#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */
#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */
#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Enable */
#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Enable */
#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Enable */
#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Enable */
#define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
#define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
#define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Enable */
#define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
#define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
#define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Enable */
#define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
#define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
#define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */
/* Bit fields for TIMER IF */
#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */
#define _TIMER_IF_MASK 0x00000773UL /**< Mask for TIMER_IF */
#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */
#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */
#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */
#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */
#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */
#define TIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */
#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */
#define TIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */
#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */
#define TIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */
#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */
#define TIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
#define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
#define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
#define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
#define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IF */
#define TIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
#define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
#define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
#define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
#define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IF */
#define TIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
#define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
#define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
#define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
#define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */
/* Bit fields for TIMER IFS */
#define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */
#define _TIMER_IFS_MASK 0x00000773UL /**< Mask for TIMER_IFS */
#define TIMER_IFS_OF (0x1UL << 0) /**< Overflow Interrupt Flag Set */
#define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */
#define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
#define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_UF (0x1UL << 1) /**< Underflow Interrupt Flag Set */
#define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */
#define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
#define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag Set */
#define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
#define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
#define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag Set */
#define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
#define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
#define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag Set */
#define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
#define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
#define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set */
#define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
#define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
#define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set */
#define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
#define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
#define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set */
#define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
#define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
#define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */
/* Bit fields for TIMER IFC */
#define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */
#define _TIMER_IFC_MASK 0x00000773UL /**< Mask for TIMER_IFC */
#define TIMER_IFC_OF (0x1UL << 0) /**< Overflow Interrupt Flag Clear */
#define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */
#define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
#define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_UF (0x1UL << 1) /**< Underflow Interrupt Flag Clear */
#define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */
#define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
#define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag Clear */
#define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
#define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
#define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag Clear */
#define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
#define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
#define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag Clear */
#define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
#define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
#define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Clear */
#define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
#define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
#define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear */
#define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
#define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
#define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear */
#define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
#define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
#define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */
/* Bit fields for TIMER TOP */
#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */
#define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */
#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */
#define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */
#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */
#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */
/* Bit fields for TIMER TOPB */
#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */
#define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */
#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */
#define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */
#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */
#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */
/* Bit fields for TIMER CNT */
#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */
#define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */
#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */
#define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */
#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */
#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */
/* Bit fields for TIMER ROUTE */
#define _TIMER_ROUTE_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTE */
#define _TIMER_ROUTE_MASK 0x00070707UL /**< Mask for TIMER_ROUTE */
#define TIMER_ROUTE_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */
#define _TIMER_ROUTE_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */
#define _TIMER_ROUTE_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */
#define _TIMER_ROUTE_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
#define TIMER_ROUTE_CC0PEN_DEFAULT (_TIMER_ROUTE_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTE */
#define TIMER_ROUTE_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */
#define _TIMER_ROUTE_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */
#define _TIMER_ROUTE_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */
#define _TIMER_ROUTE_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
#define TIMER_ROUTE_CC1PEN_DEFAULT (_TIMER_ROUTE_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_ROUTE */
#define TIMER_ROUTE_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */
#define _TIMER_ROUTE_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */
#define _TIMER_ROUTE_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */
#define _TIMER_ROUTE_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
#define TIMER_ROUTE_CC2PEN_DEFAULT (_TIMER_ROUTE_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_ROUTE */
#define TIMER_ROUTE_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */
#define _TIMER_ROUTE_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */
#define _TIMER_ROUTE_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */
#define _TIMER_ROUTE_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
#define TIMER_ROUTE_CDTI0PEN_DEFAULT (_TIMER_ROUTE_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTE */
#define TIMER_ROUTE_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */
#define _TIMER_ROUTE_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */
#define _TIMER_ROUTE_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */
#define _TIMER_ROUTE_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
#define TIMER_ROUTE_CDTI1PEN_DEFAULT (_TIMER_ROUTE_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_ROUTE */
#define TIMER_ROUTE_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */
#define _TIMER_ROUTE_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */
#define _TIMER_ROUTE_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */
#define _TIMER_ROUTE_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
#define TIMER_ROUTE_CDTI2PEN_DEFAULT (_TIMER_ROUTE_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_SHIFT 16 /**< Shift value for TIMER_LOCATION */
#define _TIMER_ROUTE_LOCATION_MASK 0x70000UL /**< Bit mask for TIMER_LOCATION */
#define _TIMER_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_LOC0 (_TIMER_ROUTE_LOCATION_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_DEFAULT (_TIMER_ROUTE_LOCATION_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_LOC1 (_TIMER_ROUTE_LOCATION_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_LOC2 (_TIMER_ROUTE_LOCATION_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_LOC3 (_TIMER_ROUTE_LOCATION_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_LOC4 (_TIMER_ROUTE_LOCATION_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_LOC5 (_TIMER_ROUTE_LOCATION_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTE */
/* Bit fields for TIMER CC_CTRL */
#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_MASK 0x0F3F3F17UL /**< Mask for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
#define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
#define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */
#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */
#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */
#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */
#define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */
#define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */
#define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */
#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */
#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */
#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */
#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */
#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */
#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */
#define _TIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */
#define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH8 (_TIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH9 (_TIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH10 (_TIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH11 (_TIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_INSEL (0x1UL << 20) /**< Input Selection */
#define _TIMER_CC_CTRL_INSEL_SHIFT 20 /**< Shift value for TIMER_INSEL */
#define _TIMER_CC_CTRL_INSEL_MASK 0x100000UL /**< Bit mask for TIMER_INSEL */
#define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 20) /**< Shifted mode PIN for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 20) /**< Shifted mode PRS for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_FILT (0x1UL << 21) /**< Digital Filter */
#define _TIMER_CC_CTRL_FILT_SHIFT 21 /**< Shift value for TIMER_FILT */
#define _TIMER_CC_CTRL_FILT_MASK 0x200000UL /**< Bit mask for TIMER_FILT */
#define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 21) /**< Shifted mode DISABLE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 21) /**< Shifted mode ENABLE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */
#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */
#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */
#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */
#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */
/* Bit fields for TIMER CC_CCV */
#define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */
#define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */
#define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */
#define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */
#define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */
#define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */
/* Bit fields for TIMER CC_CCVP */
#define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */
#define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */
#define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */
#define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */
#define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */
#define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */
/* Bit fields for TIMER CC_CCVB */
#define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */
#define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */
#define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */
#define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */
#define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */
#define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */
/* Bit fields for TIMER DTCTRL */
#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */
#define _TIMER_DTCTRL_MASK 0x010000FFUL /**< Mask for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */
#define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */
#define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */
#define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */
#define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */
#define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */
#define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */
#define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */
#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */
#define _TIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */
#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH8 (_TIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH9 (_TIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH10 (_TIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH11 (_TIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */
#define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */
#define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */
#define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
/* Bit fields for TIMER DTTIME */
#define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */
#define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */
#define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */
#define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */
#define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */
#define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
#define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */
#define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */
#define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */
#define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
#define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */
/* Bit fields for TIMER DTFC */
#define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */
#define _TIMER_DTFC_MASK 0x0F030707UL /**< Mask for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */
#define _TIMER_DTFC_DTPRS0FSEL_MASK 0x7UL /**< Bit mask for TIMER_DTPRS0FSEL */
#define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */
#define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */
#define _TIMER_DTFC_DTPRS1FSEL_MASK 0x700UL /**< Bit mask for TIMER_DTPRS1FSEL */
#define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */
#define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */
#define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */
#define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */
#define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */
#define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
#define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */
#define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */
#define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */
#define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */
#define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */
#define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFC */
#define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */
#define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFC */
#define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */
#define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */
#define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */
#define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */
#define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
#define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */
#define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */
#define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */
#define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */
#define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
#define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFC */
#define TIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */
#define _TIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */
#define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */
#define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
#define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFC */
#define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */
#define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */
#define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */
#define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
#define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */
/* Bit fields for TIMER DTOGEN */
#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */
#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */
#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */
#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */
#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */
#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */
#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */
#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */
#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */
#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */
#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */
#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */
#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */
#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */
#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */
#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */
#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */
#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */
#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */
#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
/* Bit fields for TIMER DTFAULT */
#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */
#define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */
#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */
#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */
#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */
#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */
#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */
#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */
#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */
#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */
#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */
#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */
#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */
#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */
#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
/* Bit fields for TIMER DTFAULTC */
#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */
#define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */
#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */
#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */
#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */
#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */
#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */
#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */
#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */
#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */
#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */
#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
#define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */
#define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */
#define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */
#define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
#define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
/* Bit fields for TIMER DTLOCK */
#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */
#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
/** @} End of group EFM32WG_TIMER */

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/**************************************************************************//**
* @file efm32wg_timer_cc.h
* @brief EFM32WG_TIMER_CC register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @brief TIMER_CC EFM32WG TIMER CC
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< CC Channel Control Register */
__IO uint32_t CCV; /**< CC Channel Value Register */
__I uint32_t CCVP; /**< CC Channel Value Peek Register */
__IO uint32_t CCVB; /**< CC Channel Buffer Register */
} TIMER_CC_TypeDef;

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/**************************************************************************//**
* @file efm32wg_usb_diep.h
* @brief EFM32WG_USB_DIEP register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @brief USB_DIEP EFM32WG USB DIEP
*****************************************************************************/
typedef struct
{
__IO uint32_t CTL; /**< Device IN Endpoint x+1 Control Register */
uint32_t RESERVED0[1]; /**< Reserved for future use **/
__IO uint32_t INT; /**< Device IN Endpoint x+1 Interrupt Register */
uint32_t RESERVED1[1]; /**< Reserved for future use **/
__IO uint32_t TSIZ; /**< Device IN Endpoint x+1 Transfer Size Register */
__IO uint32_t DMAADDR; /**< Device IN Endpoint x+1 DMA Address Register */
__I uint32_t TXFSTS; /**< Device IN Endpoint x+1 Transmit FIFO Status Register */
uint32_t RESERVED2[1]; /**< Reserved future */
} USB_DIEP_TypeDef;

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FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Include/efm32wg_usb_doep.h Normal file
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/**************************************************************************//**
* @file efm32wg_usb_doep.h
* @brief EFM32WG_USB_DOEP register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @brief USB_DOEP EFM32WG USB DOEP
*****************************************************************************/
typedef struct
{
__IO uint32_t CTL; /**< Device OUT Endpoint x+1 Control Register */
uint32_t RESERVED0[1]; /**< Reserved for future use **/
__IO uint32_t INT; /**< Device OUT Endpoint x+1 Interrupt Register */
uint32_t RESERVED1[1]; /**< Reserved for future use **/
__IO uint32_t TSIZ; /**< Device OUT Endpoint x+1 Transfer Size Register */
__IO uint32_t DMAADDR; /**< Device OUT Endpoint x+1 DMA Address Register */
uint32_t RESERVED2[2]; /**< Reserved future */
} USB_DOEP_TypeDef;

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/**************************************************************************//**
* @file efm32wg_usb_hc.h
* @brief EFM32WG_USB_HC register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @brief USB_HC EFM32WG USB HC
*****************************************************************************/
typedef struct
{
__IO uint32_t CHAR; /**< Host Channel x Characteristics Register */
uint32_t RESERVED0[1]; /**< Reserved for future use **/
__IO uint32_t INT; /**< Host Channel x Interrupt Register */
__IO uint32_t INTMSK; /**< Host Channel x Interrupt Mask Register */
__IO uint32_t TSIZ; /**< Host Channel x Transfer Size Register */
__IO uint32_t DMAADDR; /**< Host Channel x DMA Address Register */
uint32_t RESERVED1[2]; /**< Reserved future */
} USB_HC_TypeDef;

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/**************************************************************************//**
* @file efm32wg_vcmp.h
* @brief EFM32WG_VCMP register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_VCMP
* @{
* @brief EFM32WG_VCMP Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t INPUTSEL; /**< Input Selection Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
} VCMP_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_VCMP_BitFields
* @{
*****************************************************************************/
/* Bit fields for VCMP CTRL */
#define _VCMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for VCMP_CTRL */
#define _VCMP_CTRL_MASK 0x4F030715UL /**< Mask for VCMP_CTRL */
#define VCMP_CTRL_EN (0x1UL << 0) /**< Voltage Supply Comparator Enable */
#define _VCMP_CTRL_EN_SHIFT 0 /**< Shift value for VCMP_EN */
#define _VCMP_CTRL_EN_MASK 0x1UL /**< Bit mask for VCMP_EN */
#define _VCMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_EN_DEFAULT (_VCMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */
#define _VCMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for VCMP_INACTVAL */
#define _VCMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for VCMP_INACTVAL */
#define _VCMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_INACTVAL_DEFAULT (_VCMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_HYSTEN (0x1UL << 4) /**< Hysteresis Enable */
#define _VCMP_CTRL_HYSTEN_SHIFT 4 /**< Shift value for VCMP_HYSTEN */
#define _VCMP_CTRL_HYSTEN_MASK 0x10UL /**< Bit mask for VCMP_HYSTEN */
#define _VCMP_CTRL_HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_HYSTEN_DEFAULT (_VCMP_CTRL_HYSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for VCMP_WARMTIME */
#define _VCMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for VCMP_WARMTIME */
#define _VCMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_DEFAULT (_VCMP_CTRL_WARMTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_4CYCLES (_VCMP_CTRL_WARMTIME_4CYCLES << 8) /**< Shifted mode 4CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_8CYCLES (_VCMP_CTRL_WARMTIME_8CYCLES << 8) /**< Shifted mode 8CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_16CYCLES (_VCMP_CTRL_WARMTIME_16CYCLES << 8) /**< Shifted mode 16CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_32CYCLES (_VCMP_CTRL_WARMTIME_32CYCLES << 8) /**< Shifted mode 32CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_64CYCLES (_VCMP_CTRL_WARMTIME_64CYCLES << 8) /**< Shifted mode 64CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_128CYCLES (_VCMP_CTRL_WARMTIME_128CYCLES << 8) /**< Shifted mode 128CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_256CYCLES (_VCMP_CTRL_WARMTIME_256CYCLES << 8) /**< Shifted mode 256CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_512CYCLES (_VCMP_CTRL_WARMTIME_512CYCLES << 8) /**< Shifted mode 512CYCLES for VCMP_CTRL */
#define VCMP_CTRL_IRISE (0x1UL << 16) /**< Rising Edge Interrupt Sense */
#define _VCMP_CTRL_IRISE_SHIFT 16 /**< Shift value for VCMP_IRISE */
#define _VCMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for VCMP_IRISE */
#define _VCMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_IRISE_DEFAULT (_VCMP_CTRL_IRISE_DEFAULT << 16) /**< Shifted mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_IFALL (0x1UL << 17) /**< Falling Edge Interrupt Sense */
#define _VCMP_CTRL_IFALL_SHIFT 17 /**< Shift value for VCMP_IFALL */
#define _VCMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for VCMP_IFALL */
#define _VCMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_IFALL_DEFAULT (_VCMP_CTRL_IFALL_DEFAULT << 17) /**< Shifted mode DEFAULT for VCMP_CTRL */
#define _VCMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for VCMP_BIASPROG */
#define _VCMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for VCMP_BIASPROG */
#define _VCMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_BIASPROG_DEFAULT (_VCMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_HALFBIAS (0x1UL << 30) /**< Half Bias Current */
#define _VCMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for VCMP_HALFBIAS */
#define _VCMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for VCMP_HALFBIAS */
#define _VCMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_HALFBIAS_DEFAULT (_VCMP_CTRL_HALFBIAS_DEFAULT << 30) /**< Shifted mode DEFAULT for VCMP_CTRL */
/* Bit fields for VCMP INPUTSEL */
#define _VCMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for VCMP_INPUTSEL */
#define _VCMP_INPUTSEL_MASK 0x0000013FUL /**< Mask for VCMP_INPUTSEL */
#define _VCMP_INPUTSEL_TRIGLEVEL_SHIFT 0 /**< Shift value for VCMP_TRIGLEVEL */
#define _VCMP_INPUTSEL_TRIGLEVEL_MASK 0x3FUL /**< Bit mask for VCMP_TRIGLEVEL */
#define _VCMP_INPUTSEL_TRIGLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */
#define VCMP_INPUTSEL_TRIGLEVEL_DEFAULT (_VCMP_INPUTSEL_TRIGLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */
#define VCMP_INPUTSEL_LPREF (0x1UL << 8) /**< Low Power Reference */
#define _VCMP_INPUTSEL_LPREF_SHIFT 8 /**< Shift value for VCMP_LPREF */
#define _VCMP_INPUTSEL_LPREF_MASK 0x100UL /**< Bit mask for VCMP_LPREF */
#define _VCMP_INPUTSEL_LPREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */
#define VCMP_INPUTSEL_LPREF_DEFAULT (_VCMP_INPUTSEL_LPREF_DEFAULT << 8) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */
/* Bit fields for VCMP STATUS */
#define _VCMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for VCMP_STATUS */
#define _VCMP_STATUS_MASK 0x00000003UL /**< Mask for VCMP_STATUS */
#define VCMP_STATUS_VCMPACT (0x1UL << 0) /**< Voltage Supply Comparator Active */
#define _VCMP_STATUS_VCMPACT_SHIFT 0 /**< Shift value for VCMP_VCMPACT */
#define _VCMP_STATUS_VCMPACT_MASK 0x1UL /**< Bit mask for VCMP_VCMPACT */
#define _VCMP_STATUS_VCMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */
#define VCMP_STATUS_VCMPACT_DEFAULT (_VCMP_STATUS_VCMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_STATUS */
#define VCMP_STATUS_VCMPOUT (0x1UL << 1) /**< Voltage Supply Comparator Output */
#define _VCMP_STATUS_VCMPOUT_SHIFT 1 /**< Shift value for VCMP_VCMPOUT */
#define _VCMP_STATUS_VCMPOUT_MASK 0x2UL /**< Bit mask for VCMP_VCMPOUT */
#define _VCMP_STATUS_VCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */
#define VCMP_STATUS_VCMPOUT_DEFAULT (_VCMP_STATUS_VCMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_STATUS */
/* Bit fields for VCMP IEN */
#define _VCMP_IEN_RESETVALUE 0x00000000UL /**< Default value for VCMP_IEN */
#define _VCMP_IEN_MASK 0x00000003UL /**< Mask for VCMP_IEN */
#define VCMP_IEN_EDGE (0x1UL << 0) /**< Edge Trigger Interrupt Enable */
#define _VCMP_IEN_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
#define _VCMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
#define _VCMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */
#define VCMP_IEN_EDGE_DEFAULT (_VCMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IEN */
#define VCMP_IEN_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Enable */
#define _VCMP_IEN_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
#define _VCMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
#define _VCMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */
#define VCMP_IEN_WARMUP_DEFAULT (_VCMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IEN */
/* Bit fields for VCMP IF */
#define _VCMP_IF_RESETVALUE 0x00000000UL /**< Default value for VCMP_IF */
#define _VCMP_IF_MASK 0x00000003UL /**< Mask for VCMP_IF */
#define VCMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */
#define _VCMP_IF_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
#define _VCMP_IF_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
#define _VCMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */
#define VCMP_IF_EDGE_DEFAULT (_VCMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IF */
#define VCMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */
#define _VCMP_IF_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
#define _VCMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
#define _VCMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */
#define VCMP_IF_WARMUP_DEFAULT (_VCMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IF */
/* Bit fields for VCMP IFS */
#define _VCMP_IFS_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFS */
#define _VCMP_IFS_MASK 0x00000003UL /**< Mask for VCMP_IFS */
#define VCMP_IFS_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Set */
#define _VCMP_IFS_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
#define _VCMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
#define _VCMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */
#define VCMP_IFS_EDGE_DEFAULT (_VCMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IFS */
#define VCMP_IFS_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Set */
#define _VCMP_IFS_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
#define _VCMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
#define _VCMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */
#define VCMP_IFS_WARMUP_DEFAULT (_VCMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFS */
/* Bit fields for VCMP IFC */
#define _VCMP_IFC_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFC */
#define _VCMP_IFC_MASK 0x00000003UL /**< Mask for VCMP_IFC */
#define VCMP_IFC_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Clear */
#define _VCMP_IFC_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
#define _VCMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
#define _VCMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */
#define VCMP_IFC_EDGE_DEFAULT (_VCMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IFC */
#define VCMP_IFC_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Clear */
#define _VCMP_IFC_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
#define _VCMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
#define _VCMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */
#define VCMP_IFC_WARMUP_DEFAULT (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */
/** @} End of group EFM32WG_VCMP */

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/**************************************************************************//**
* @file efm32wg_wdog.h
* @brief EFM32WG_WDOG register and bit field definitions
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32WG_WDOG
* @{
* @brief EFM32WG_WDOG Register Declaration
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t CMD; /**< Command Register */
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
} WDOG_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32WG_WDOG_BitFields
* @{
*****************************************************************************/
/* Bit fields for WDOG CTRL */
#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */
#define _WDOG_CTRL_MASK 0x00003F7FUL /**< Mask for WDOG_CTRL */
#define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */
#define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */
#define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */
#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
#define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */
#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */
#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */
#define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */
#define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */
#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */
#define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */
#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */
#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration lock */
#define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */
#define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */
#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */
#define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */
#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */
#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */
#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */
#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */
#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */
#define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */
#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */
#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */
#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */
#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */
#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */
#define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */
#define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */
#define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */
/* Bit fields for WDOG CMD */
#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */
#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */
#define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */
#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */
#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */
#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */
#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */
#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */
#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */
#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */
#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */
/* Bit fields for WDOG SYNCBUSY */
#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */
#define _WDOG_SYNCBUSY_MASK 0x00000003UL /**< Mask for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
#define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */
#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */
#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
#define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */
#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */
#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
/** @} End of group EFM32WG_WDOG */

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FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Include/em_device.h Normal file
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/**************************************************************************//**
* @file em_device.h
* @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories
* microcontroller devices
*
* This is a convenience header file for defining the part number on the
* build command line, instead of specifying the part specific header file.
*
* @verbatim
* Example: Add "-DEFM32G890F128" to your build options, to define part
* Add "#include "em_device.h" to your source files
*
*
* @endverbatim
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#ifndef __SILICON_LABS_EM_DEVICE_H__
#define __SILICON_LABS_EM_DEVICE_H__
#if defined(EFM32WG230F128)
#include "efm32wg230f128.h"
#elif defined(EFM32WG230F256)
#include "efm32wg230f256.h"
#elif defined(EFM32WG230F64)
#include "efm32wg230f64.h"
#elif defined(EFM32WG232F128)
#include "efm32wg232f128.h"
#elif defined(EFM32WG232F256)
#include "efm32wg232f256.h"
#elif defined(EFM32WG232F64)
#include "efm32wg232f64.h"
#elif defined(EFM32WG280F128)
#include "efm32wg280f128.h"
#elif defined(EFM32WG280F256)
#include "efm32wg280f256.h"
#elif defined(EFM32WG280F64)
#include "efm32wg280f64.h"
#elif defined(EFM32WG290F128)
#include "efm32wg290f128.h"
#elif defined(EFM32WG290F256)
#include "efm32wg290f256.h"
#elif defined(EFM32WG290F64)
#include "efm32wg290f64.h"
#elif defined(EFM32WG295F128)
#include "efm32wg295f128.h"
#elif defined(EFM32WG295F256)
#include "efm32wg295f256.h"
#elif defined(EFM32WG295F64)
#include "efm32wg295f64.h"
#elif defined(EFM32WG330F128)
#include "efm32wg330f128.h"
#elif defined(EFM32WG330F256)
#include "efm32wg330f256.h"
#elif defined(EFM32WG330F64)
#include "efm32wg330f64.h"
#elif defined(EFM32WG332F128)
#include "efm32wg332f128.h"
#elif defined(EFM32WG332F256)
#include "efm32wg332f256.h"
#elif defined(EFM32WG332F64)
#include "efm32wg332f64.h"
#elif defined(EFM32WG360F128)
#include "efm32wg360f128.h"
#elif defined(EFM32WG360F256)
#include "efm32wg360f256.h"
#elif defined(EFM32WG360F64)
#include "efm32wg360f64.h"
#elif defined(EFM32WG380F128)
#include "efm32wg380f128.h"
#elif defined(EFM32WG380F256)
#include "efm32wg380f256.h"
#elif defined(EFM32WG380F64)
#include "efm32wg380f64.h"
#elif defined(EFM32WG390F128)
#include "efm32wg390f128.h"
#elif defined(EFM32WG390F256)
#include "efm32wg390f256.h"
#elif defined(EFM32WG390F64)
#include "efm32wg390f64.h"
#elif defined(EFM32WG395F128)
#include "efm32wg395f128.h"
#elif defined(EFM32WG395F256)
#include "efm32wg395f256.h"
#elif defined(EFM32WG395F64)
#include "efm32wg395f64.h"
#elif defined(EFM32WG840F128)
#include "efm32wg840f128.h"
#elif defined(EFM32WG840F256)
#include "efm32wg840f256.h"
#elif defined(EFM32WG840F64)
#include "efm32wg840f64.h"
#elif defined(EFM32WG842F128)
#include "efm32wg842f128.h"
#elif defined(EFM32WG842F256)
#include "efm32wg842f256.h"
#elif defined(EFM32WG842F64)
#include "efm32wg842f64.h"
#elif defined(EFM32WG880F128)
#include "efm32wg880f128.h"
#elif defined(EFM32WG880F256)
#include "efm32wg880f256.h"
#elif defined(EFM32WG880F64)
#include "efm32wg880f64.h"
#elif defined(EFM32WG890F128)
#include "efm32wg890f128.h"
#elif defined(EFM32WG890F256)
#include "efm32wg890f256.h"
#elif defined(EFM32WG890F64)
#include "efm32wg890f64.h"
#elif defined(EFM32WG895F128)
#include "efm32wg895f128.h"
#elif defined(EFM32WG895F256)
#include "efm32wg895f256.h"
#elif defined(EFM32WG895F64)
#include "efm32wg895f64.h"
#elif defined(EFM32WG900F256)
#include "efm32wg900f256.h"
#elif defined(EFM32WG940F128)
#include "efm32wg940f128.h"
#elif defined(EFM32WG940F256)
#include "efm32wg940f256.h"
#elif defined(EFM32WG940F64)
#include "efm32wg940f64.h"
#elif defined(EFM32WG942F128)
#include "efm32wg942f128.h"
#elif defined(EFM32WG942F256)
#include "efm32wg942f256.h"
#elif defined(EFM32WG942F64)
#include "efm32wg942f64.h"
#elif defined(EFM32WG980F128)
#include "efm32wg980f128.h"
#elif defined(EFM32WG980F256)
#include "efm32wg980f256.h"
#elif defined(EFM32WG980F64)
#include "efm32wg980f64.h"
#elif defined(EFM32WG990F128)
#include "efm32wg990f128.h"
#elif defined(EFM32WG990F256)
#include "efm32wg990f256.h"
#elif defined(EFM32WG990F64)
#include "efm32wg990f64.h"
#elif defined(EFM32WG995F128)
#include "efm32wg995f128.h"
#elif defined(EFM32WG995F256)
#include "efm32wg995f256.h"
#elif defined(EFM32WG995F64)
#include "efm32wg995f64.h"
#else
#error "em_device.h: PART NUMBER undefined"
#endif
#endif /* __SILICON_LABS_EM_DEVICE_H__ */

139
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Include/system_efm32wg.h Normal file
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/***************************************************************************//**
* @file system_efm32wg.h
* @brief CMSIS Cortex-M4 System Layer for EFM32WG devices.
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#ifndef __SYSTEM_EFM32WG_H
#define __SYSTEM_EFM32WG_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
/* Interrupt routines - prototypes */
#if defined(_EFM32_WONDER_FAMILY)
void Reset_Handler(void);
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void DMA_IRQHandler(void);
void GPIO_EVEN_IRQHandler(void);
void TIMER0_IRQHandler(void);
void USART0_RX_IRQHandler(void);
void USART0_TX_IRQHandler(void);
void USB_IRQHandler(void);
void ACMP0_IRQHandler(void);
void ADC0_IRQHandler(void);
void DAC0_IRQHandler(void);
void I2C0_IRQHandler(void);
void I2C1_IRQHandler(void);
void GPIO_ODD_IRQHandler(void);
void TIMER1_IRQHandler(void);
void TIMER2_IRQHandler(void);
void TIMER3_IRQHandler(void);
void USART1_RX_IRQHandler(void);
void USART1_TX_IRQHandler(void);
void LESENSE_IRQHandler(void);
void USART2_RX_IRQHandler(void);
void USART2_TX_IRQHandler(void);
void UART0_RX_IRQHandler(void);
void UART0_TX_IRQHandler(void);
void UART1_RX_IRQHandler(void);
void UART1_TX_IRQHandler(void);
void LEUART0_IRQHandler(void);
void LEUART1_IRQHandler(void);
void LETIMER0_IRQHandler(void);
void PCNT0_IRQHandler(void);
void PCNT1_IRQHandler(void);
void PCNT2_IRQHandler(void);
void RTC_IRQHandler(void);
void BURTC_IRQHandler(void);
void CMU_IRQHandler(void);
void VCMP_IRQHandler(void);
void LCD_IRQHandler(void);
void MSC_IRQHandler(void);
void AES_IRQHandler(void);
void EBI_IRQHandler(void);
void EMU_IRQHandler(void);
void FPUEH_IRQHandler(void);
#endif
uint32_t SystemCoreClockGet(void);
/**************************************************************************//**
* @brief
* Update CMSIS SystemCoreClock variable.
*
* @details
* CMSIS defines a global variable SystemCoreClock that shall hold the
* core frequency in Hz. If the core frequency is dynamically changed, the
* variable must be kept updated in order to be CMSIS compliant.
*
* Notice that if only changing core clock frequency through the EFM32 CMU
* API, this variable will be kept updated. This function is only provided
* for CMSIS compliance and if a user modifies the the core clock outside
* the CMU API.
*****************************************************************************/
static __INLINE void SystemCoreClockUpdate(void)
{
SystemCoreClockGet();
}
void SystemInit(void);
uint32_t SystemHFClockGet(void);
uint32_t SystemHFXOClockGet(void);
void SystemHFXOClockSet(uint32_t freq);
uint32_t SystemLFRCOClockGet(void);
uint32_t SystemULFRCOClockGet(void);
uint32_t SystemLFXOClockGet(void);
void SystemLFXOClockSet(uint32_t freq);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_EFM32WG_H */

207
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Source/GCC/efm32wg.ld Normal file
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/* Linker script for Silicon Labs EFM32WG devices */
/* */
/* This file is subject to the license terms as defined in ARM's */
/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of */
/* Example Code. */
/* */
/* Silicon Laboratories, Inc. 2015 */
/* */
/* Version 4.0.0 */
/* */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 32768
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
/*
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (__etext2)
LONG (__data2_start__)
LONG (__data2_end__ - __data2_start__)
__copy_table_end__ = .;
} > FLASH
*/
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
/*
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__bss2_start__)
LONG (__bss2_end__ - __bss2_start__)
__zero_table_end__ = .;
} > FLASH
*/
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN (4);
*(.ram)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__HeapBase = .;
__end__ = .;
end = __end__;
_end = __end__;
KEEP(*(.heap*))
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
KEEP(*(.stack*))
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Check if FLASH usage exceeds FLASH size */
ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !")
}

339
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Source/GCC/startup_efm32wg.S Normal file
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/* @file startup_efm32wg.S
* @brief startup file for Silicon Labs EFM32WG devices.
* For use with GCC for ARM Embedded Processors
* @version 4.0.0
* Date: 12 June 2014
*
*/
/* Copyright (c) 2011 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv7-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00000400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000C00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long Default_Handler /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long Default_Handler /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long DMA_IRQHandler /* 0 - DMA */
.long GPIO_EVEN_IRQHandler /* 1 - GPIO_EVEN */
.long TIMER0_IRQHandler /* 2 - TIMER0 */
.long USART0_RX_IRQHandler /* 3 - USART0_RX */
.long USART0_TX_IRQHandler /* 4 - USART0_TX */
.long USB_IRQHandler /* 5 - USB */
.long ACMP0_IRQHandler /* 6 - ACMP0 */
.long ADC0_IRQHandler /* 7 - ADC0 */
.long DAC0_IRQHandler /* 8 - DAC0 */
.long I2C0_IRQHandler /* 9 - I2C0 */
.long I2C1_IRQHandler /* 10 - I2C1 */
.long GPIO_ODD_IRQHandler /* 11 - GPIO_ODD */
.long TIMER1_IRQHandler /* 12 - TIMER1 */
.long TIMER2_IRQHandler /* 13 - TIMER2 */
.long TIMER3_IRQHandler /* 14 - TIMER3 */
.long USART1_RX_IRQHandler /* 15 - USART1_RX */
.long USART1_TX_IRQHandler /* 16 - USART1_TX */
.long LESENSE_IRQHandler /* 17 - LESENSE */
.long USART2_RX_IRQHandler /* 18 - USART2_RX */
.long USART2_TX_IRQHandler /* 19 - USART2_TX */
.long UART0_RX_IRQHandler /* 20 - UART0_RX */
.long UART0_TX_IRQHandler /* 21 - UART0_TX */
.long UART1_RX_IRQHandler /* 22 - UART1_RX */
.long UART1_TX_IRQHandler /* 23 - UART1_TX */
.long LEUART0_IRQHandler /* 24 - LEUART0 */
.long LEUART1_IRQHandler /* 25 - LEUART1 */
.long LETIMER0_IRQHandler /* 26 - LETIMER0 */
.long PCNT0_IRQHandler /* 27 - PCNT0 */
.long PCNT1_IRQHandler /* 28 - PCNT1 */
.long PCNT2_IRQHandler /* 29 - PCNT2 */
.long RTC_IRQHandler /* 30 - RTC */
.long BURTC_IRQHandler /* 31 - BURTC */
.long CMU_IRQHandler /* 32 - CMU */
.long VCMP_IRQHandler /* 33 - VCMP */
.long LCD_IRQHandler /* 34 - LCD */
.long MSC_IRQHandler /* 35 - MSC */
.long AES_IRQHandler /* 36 - AES */
.long EBI_IRQHandler /* 37 - EBI */
.long EMU_IRQHandler /* 38 - EMU */
.long FPUEH_IRQHandler /* 39 - FPUEH */
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
#ifndef __NO_SYSTEM_INIT
ldr r0, =SystemInit
blx r0
#endif
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler DMA_IRQHandler
def_irq_handler GPIO_EVEN_IRQHandler
def_irq_handler TIMER0_IRQHandler
def_irq_handler USART0_RX_IRQHandler
def_irq_handler USART0_TX_IRQHandler
def_irq_handler USB_IRQHandler
def_irq_handler ACMP0_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler DAC0_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler GPIO_ODD_IRQHandler
def_irq_handler TIMER1_IRQHandler
def_irq_handler TIMER2_IRQHandler
def_irq_handler TIMER3_IRQHandler
def_irq_handler USART1_RX_IRQHandler
def_irq_handler USART1_TX_IRQHandler
def_irq_handler LESENSE_IRQHandler
def_irq_handler USART2_RX_IRQHandler
def_irq_handler USART2_TX_IRQHandler
def_irq_handler UART0_RX_IRQHandler
def_irq_handler UART0_TX_IRQHandler
def_irq_handler UART1_RX_IRQHandler
def_irq_handler UART1_TX_IRQHandler
def_irq_handler LEUART0_IRQHandler
def_irq_handler LEUART1_IRQHandler
def_irq_handler LETIMER0_IRQHandler
def_irq_handler PCNT0_IRQHandler
def_irq_handler PCNT1_IRQHandler
def_irq_handler PCNT2_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler BURTC_IRQHandler
def_irq_handler CMU_IRQHandler
def_irq_handler VCMP_IRQHandler
def_irq_handler LCD_IRQHandler
def_irq_handler MSC_IRQHandler
def_irq_handler AES_IRQHandler
def_irq_handler EBI_IRQHandler
def_irq_handler EMU_IRQHandler
def_irq_handler FPUEH_IRQHandler
.end

338
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Source/GCC/startup_efm32wg.c Normal file
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/*
* @file startup_efm32wg.c
* @brief CMSIS Compatible EFM32WG startup file in C.
* Should be used with GCC 'GNU Tools ARM Embedded'
* @version 4.0.0
* Date: 12 June 2014
*
*/
/* Copyright (c) 2011 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
Linker generated Symbols
*----------------------------------------------------------------------------*/
extern uint32_t __etext;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __copy_table_start__;
extern uint32_t __copy_table_end__;
extern uint32_t __zero_table_start__;
extern uint32_t __zero_table_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __StackTop;
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
typedef void( *pFunc )( void );
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
#ifndef __START
extern void _start(void) __attribute__((noreturn)); /* Pre Main (C library entry point) */
#else
extern int __START(void) __attribute__((noreturn)); /* main entry point */
#endif
#ifndef __NO_SYSTEM_INIT
extern void SystemInit (void); /* CMSIS System Initialization */
#endif
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void Default_Handler(void); /* Default empty handler */
void Reset_Handler(void); /* Reset Handler */
/*----------------------------------------------------------------------------
User Initial Stack & Heap
*----------------------------------------------------------------------------*/
#ifndef __STACK_SIZE
#define __STACK_SIZE 0x00000400
#endif
static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
#ifndef __HEAP_SIZE
#define __HEAP_SIZE 0x00000C00
#endif
#if __HEAP_SIZE > 0
static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
#endif
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Cortex-M Processor Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/* Part Specific Interrupts */
void DMA_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void GPIO_EVEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void USART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void USART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void USB_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void ACMP0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void ADC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void DAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void I2C0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void I2C1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void GPIO_ODD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void TIMER2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void TIMER3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void USART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void USART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void LESENSE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void USART2_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void USART2_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void UART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void UART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void UART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void UART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void LEUART0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void LEUART1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void LETIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void PCNT0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void PCNT1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void PCNT2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void RTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void BURTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void CMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void VCMP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void LCD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void MSC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void AES_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void EBI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void EMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
void FPUEH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
/* Cortex-M Exception Handlers */
(pFunc)&__StackTop, /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* NMI Handler */
HardFault_Handler, /* Hard Fault Handler */
MemManage_Handler, /* MPU Fault Handler */
BusFault_Handler, /* Bus Fault Handler */
UsageFault_Handler, /* Usage Fault Handler */
Default_Handler, /* Reserved */
Default_Handler, /* Reserved */
Default_Handler, /* Reserved */
Default_Handler, /* Reserved */
SVC_Handler, /* SVCall Handler */
DebugMon_Handler, /* Debug Monitor Handler */
Default_Handler, /* Reserved */
PendSV_Handler, /* PendSV Handler */
SysTick_Handler, /* SysTick Handler */
/* External interrupts */
DMA_IRQHandler, /* 0 - DMA */
GPIO_EVEN_IRQHandler, /* 1 - GPIO_EVEN */
TIMER0_IRQHandler, /* 2 - TIMER0 */
USART0_RX_IRQHandler, /* 3 - USART0_RX */
USART0_TX_IRQHandler, /* 4 - USART0_TX */
USB_IRQHandler, /* 5 - USB */
ACMP0_IRQHandler, /* 6 - ACMP0 */
ADC0_IRQHandler, /* 7 - ADC0 */
DAC0_IRQHandler, /* 8 - DAC0 */
I2C0_IRQHandler, /* 9 - I2C0 */
I2C1_IRQHandler, /* 10 - I2C1 */
GPIO_ODD_IRQHandler, /* 11 - GPIO_ODD */
TIMER1_IRQHandler, /* 12 - TIMER1 */
TIMER2_IRQHandler, /* 13 - TIMER2 */
TIMER3_IRQHandler, /* 14 - TIMER3 */
USART1_RX_IRQHandler, /* 15 - USART1_RX */
USART1_TX_IRQHandler, /* 16 - USART1_TX */
LESENSE_IRQHandler, /* 17 - LESENSE */
USART2_RX_IRQHandler, /* 18 - USART2_RX */
USART2_TX_IRQHandler, /* 19 - USART2_TX */
UART0_RX_IRQHandler, /* 20 - UART0_RX */
UART0_TX_IRQHandler, /* 21 - UART0_TX */
UART1_RX_IRQHandler, /* 22 - UART1_RX */
UART1_TX_IRQHandler, /* 23 - UART1_TX */
LEUART0_IRQHandler, /* 24 - LEUART0 */
LEUART1_IRQHandler, /* 25 - LEUART1 */
LETIMER0_IRQHandler, /* 26 - LETIMER0 */
PCNT0_IRQHandler, /* 27 - PCNT0 */
PCNT1_IRQHandler, /* 28 - PCNT1 */
PCNT2_IRQHandler, /* 29 - PCNT2 */
RTC_IRQHandler, /* 30 - RTC */
BURTC_IRQHandler, /* 31 - BURTC */
CMU_IRQHandler, /* 32 - CMU */
VCMP_IRQHandler, /* 33 - VCMP */
LCD_IRQHandler, /* 34 - LCD */
MSC_IRQHandler, /* 35 - MSC */
AES_IRQHandler, /* 36 - AES */
EBI_IRQHandler, /* 37 - EBI */
EMU_IRQHandler, /* 38 - EMU */
FPUEH_IRQHandler, /* 39 - FPUEH */
};
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void) {
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
#ifndef __NO_SYSTEM_INIT
SystemInit();
#endif
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
pTable = &__copy_table_start__;
for (; pTable < &__copy_table_end__; pTable = pTable + 3)
{
pSrc = (uint32_t*)*(pTable + 0);
pDest = (uint32_t*)*(pTable + 1);
for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; )
{
*pDest++ = *pSrc++;
}
}
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
pSrc = &__etext;
pDest = &__data_start__;
for ( ; pDest < &__data_end__ ; )
{
*pDest++ = *pSrc++;
}
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
pTable = &__zero_table_start__;
for (; pTable < &__zero_table_end__; pTable = pTable + 2)
{
pDest = (uint32_t*)*(pTable + 0);
for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; )
{
*pDest++ = 0;
}
}
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_start__;
for ( ; pDest < &__bss_end__ ; )
{
*pDest++ = 0ul;
}
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __START
#define __START _start
#endif
__START();
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

388
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Source/system_efm32wg.c Normal file
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/***************************************************************************//**
* @file system_efm32wg.c
* @brief CMSIS Cortex-M4 System Layer for EFM32WG devices.
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#include <stdint.h>
#include "em_device.h"
/*******************************************************************************
****************************** DEFINES ************************************
******************************************************************************/
/** LFRCO frequency, tuned to below frequency during manufacturing. */
#define EFM32_LFRCO_FREQ (32768UL)
#define EFM32_ULFRCO_FREQ (1000UL)
/*******************************************************************************
************************** LOCAL VARIABLES ********************************
******************************************************************************/
/* System oscillator frequencies. These frequencies are normally constant */
/* for a target, but they are made configurable in order to allow run-time */
/* handling of different boards. The crystal oscillator clocks can be set */
/* compile time to a non-default value by defining respective EFM32_nFXO_FREQ */
/* values according to board design. By defining the EFM32_nFXO_FREQ to 0, */
/* one indicates that the oscillator is not present, in order to save some */
/* SW footprint. */
#ifndef EFM32_HFXO_FREQ
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
#define EFM32_HFXO_FREQ (48000000UL)
#else
#define EFM32_HFXO_FREQ (32000000UL)
#endif
#endif
/* Do not define variable if HF crystal oscillator not present */
#if (EFM32_HFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System HFXO clock. */
static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
#ifndef EFM32_LFXO_FREQ
#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
#endif
/* Do not define variable if LF crystal oscillator not present */
#if (EFM32_LFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System LFXO clock. */
static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
/* Inline function to get the chip's Production Revision. */
__STATIC_INLINE uint8_t GetProdRev(void)
{
return ((DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK)
>> _DEVINFO_PART_PROD_REV_SHIFT);
}
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
/**
* @brief
* System System Clock Frequency (Core Clock).
*
* @details
* Required CMSIS global variable that must be kept up-to-date.
*/
uint32_t SystemCoreClock;
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
/***************************************************************************//**
* @brief
* Get the current core clock frequency.
*
* @details
* Calculate and get the current core clock frequency based on the current
* configuration. Assuming that the SystemCoreClock global variable is
* maintained, the core clock frequency is stored in that variable as well.
* This function will however calculate the core clock based on actual HW
* configuration. It will also update the SystemCoreClock global variable.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* The current core clock frequency in Hz.
******************************************************************************/
uint32_t SystemCoreClockGet(void)
{
uint32_t ret;
ret = SystemHFClockGet();
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
/* Leopard/Giant/Wonder Gecko has an additional divider */
ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));
#endif
ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
/* Keep CMSIS variable up-to-date just in case */
SystemCoreClock = ret;
return ret;
}
/***************************************************************************//**
* @brief
* Get the current HFCLK frequency.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* The current HFCLK frequency in Hz.
******************************************************************************/
uint32_t SystemHFClockGet(void)
{
uint32_t ret;
switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
{
case CMU_STATUS_LFXOSEL:
#if (EFM32_LFXO_FREQ > 0)
ret = SystemLFXOClock;
#else
/* We should not get here, since core should not be clocked. May */
/* be caused by a misconfiguration though. */
ret = 0;
#endif
break;
case CMU_STATUS_LFRCOSEL:
ret = EFM32_LFRCO_FREQ;
break;
case CMU_STATUS_HFXOSEL:
#if (EFM32_HFXO_FREQ > 0)
ret = SystemHFXOClock;
#else
/* We should not get here, since core should not be clocked. May */
/* be caused by a misconfiguration though. */
ret = 0;
#endif
break;
default: /* CMU_STATUS_HFRCOSEL */
switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
{
case CMU_HFRCOCTRL_BAND_28MHZ:
ret = 28000000;
break;
case CMU_HFRCOCTRL_BAND_21MHZ:
ret = 21000000;
break;
case CMU_HFRCOCTRL_BAND_14MHZ:
ret = 14000000;
break;
case CMU_HFRCOCTRL_BAND_11MHZ:
ret = 11000000;
break;
case CMU_HFRCOCTRL_BAND_7MHZ:
if ( GetProdRev() >= 19 )
ret = 6600000;
else
ret = 7000000;
break;
case CMU_HFRCOCTRL_BAND_1MHZ:
if ( GetProdRev() >= 19 )
ret = 1200000;
else
ret = 1000000;
break;
default:
ret = 0;
break;
}
break;
}
return ret;
}
/**************************************************************************//**
* @brief
* Get high frequency crystal oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* HFXO frequency in Hz.
*****************************************************************************/
uint32_t SystemHFXOClockGet(void)
{
/* External crystal oscillator present? */
#if (EFM32_HFXO_FREQ > 0)
return SystemHFXOClock;
#else
return 0;
#endif
}
/**************************************************************************//**
* @brief
* Set high frequency crystal oscillator clock frequency for target system.
*
* @note
* This function is mainly provided for being able to handle target systems
* with different HF crystal oscillator frequencies run-time. If used, it
* should probably only be used once during system startup.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @param[in] freq
* HFXO frequency in Hz used for target.
*****************************************************************************/
void SystemHFXOClockSet(uint32_t freq)
{
/* External crystal oscillator present? */
#if (EFM32_HFXO_FREQ > 0)
SystemHFXOClock = freq;
/* Update core clock frequency if HFXO is used to clock core */
if (CMU->STATUS & CMU_STATUS_HFXOSEL)
{
/* The function will update the global variable */
SystemCoreClockGet();
}
#else
(void)freq; /* Unused parameter */
#endif
}
/**************************************************************************//**
* @brief
* Initialize the system.
*
* @details
* Do required generic HW system init.
*
* @note
* This function is invoked during system init, before the main() routine
* and any data has been initialized. For this reason, it cannot do any
* initialization of variables etc.
*****************************************************************************/
void SystemInit(void)
{
/* Set floating point coprosessor access mode. */
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
}
/**************************************************************************//**
* @brief
* Get low frequency RC oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* LFRCO frequency in Hz.
*****************************************************************************/
uint32_t SystemLFRCOClockGet(void)
{
/* Currently we assume that this frequency is properly tuned during */
/* manufacturing and is not changed after reset. If future requirements */
/* for re-tuning by user, we can add support for that. */
return EFM32_LFRCO_FREQ;
}
/**************************************************************************//**
* @brief
* Get ultra low frequency RC oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* ULFRCO frequency in Hz.
*****************************************************************************/
uint32_t SystemULFRCOClockGet(void)
{
/* The ULFRCO frequency is not tuned, and can be very inaccurate */
return EFM32_ULFRCO_FREQ;
}
/**************************************************************************//**
* @brief
* Get low frequency crystal oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* LFXO frequency in Hz.
*****************************************************************************/
uint32_t SystemLFXOClockGet(void)
{
/* External crystal oscillator present? */
#if (EFM32_LFXO_FREQ > 0)
return SystemLFXOClock;
#else
return 0;
#endif
}
/**************************************************************************//**
* @brief
* Set low frequency crystal oscillator clock frequency for target system.
*
* @note
* This function is mainly provided for being able to handle target systems
* with different HF crystal oscillator frequencies run-time. If used, it
* should probably only be used once during system startup.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @param[in] freq
* LFXO frequency in Hz used for target.
*****************************************************************************/
void SystemLFXOClockSet(uint32_t freq)
{
/* External crystal oscillator present? */
#if (EFM32_LFXO_FREQ > 0)
SystemLFXOClock = freq;
/* Update core clock frequency if LFXO is used to clock core */
if (CMU->STATUS & CMU_STATUS_LFXOSEL)
{
/* The function will update the global variable */
SystemCoreClockGet();
}
#else
(void)freq; /* Unused parameter */
#endif
}

17
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/kits/EFM32WG_STK3800/Changes-EFM32WG_STK3800.txt Normal file
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================ Revision history ============================================
4.0.0:
- Removed wrist based support from biometric demo.
- Contact Silicon Labs for wrist based HRM solution.
3.20.12:
- Fixed MSD device example, formatting now OK on WinXP.
3.20.5:
- Added EM4+RTC mode demo in emode example.
- Added new USB composite device example project.
3.20.2:
- Added FreeRTOS tickless and blink demo
3.20.0:
- Initial revision.

41
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/kits/EFM32WG_STK3800/Readme-EFM32WG_STK3800.txt Normal file
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====== Kit Examples ======
This package include examples for the EFM32WG_STK3800 Wonder Gecko development
kit from Silicon Labs.
====== Dependencies ======
This package _requires_ the EM_BSP_COMMON and EFM32 CMSIS packages to be
installed at the same level as this package. If you did not get this as part
of the Simplicity Studio application, you should also download and install the
EFM32 CMSIS package. See the Changes file for required version.
The CMSIS package requires C99 support, and so does this package.
====== File structure ======
kits/EFM32WG_STK3800/config
Configuration data for BSP and Drivers in EM_BSP_COMMON.
kits/EFM32WG_STK3800/examples
Several example projects demonstrating various capabilities of the
EFM32WG990F256.
Project files for various IDEs/compilers are in subdirectories of
each example. Use these as a starting point for your own development
and prototyping of EFM32 Wonder Gecko software.
====== Updates ======
Silicon Labs continually works to provide updated and improved example code,
header files and other software of use for our customers. Please check
http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
for the latest releases.
====== License ======
License information for use of the source code is given at the top of
all C files.
(C) Copyright Silicon Laboratories Inc. 2015. All rights reserved.

113
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END-USER LICENSE AGREEMENT
IMPORTANT: READ CAREFULLY
BEFORE AGREEING TO TERMS
THIS PRODUCT CONTAINS CERTAIN COMPUTER PROGRAMS AND OTHER THIRD PARTY
PROPRIETARY MATERIAL ("LICENSED PRODUCT"), THE USE OF WHICH IS SUBJECT TO THIS
END-USER LICENSE AGREEMENT. INDICATING YOUR AGREEMENT CONSTITUTES YOUR AND
(IF APPLICABLE) YOUR COMPANY'S ASSENT TO AND ACCEPTANCE OF THIS END-USER LICENSE
AGREEMENT (THE "LICENSE" OR "AGREEMENT"). IF YOU DO NOT AGREE WITH ALL OF THE
TERMS, YOU MUST NOT USE THIS PRODUCT. WRITTEN APPROVAL IS NOT A PREREQUISITE TO
THE VALIDITY OR ENFORCEABILITY OF THIS AGREEMENT, AND NO SOLICITATION OF SUCH
WRITTEN APPROVAL BY OR ON BEHALF OF SILICON LABORATORIES, INC. ("SILICON LABS")
SHALL BE CONSTRUED AS AN INFERENCE TO THE CONTRARY. IF THESE TERMS ARE
CONSIDERED AN OFFER BY SILICON LABS, ACCEPTANCE IS EXPRESSLY LIMITED TO THESE
TERMS.
LICENSE AND WARRANTY: The Licensed Product and the embedded Software which is
made the subject of this License is either the property of SILICON LABS or a
third party from whom SILICON LABS has the authorization to distribute to you
subject to the terms of this Agreement. This Licensed Product is protected by
state, federal, and international copyright law. Although SILICON LABS continues
to own the Licensed Product and the right to distribute the embedded third party
Software, you will have certain rights to use the Licensed Product and the
embedded Software after your acceptance of this License. Except as may be
modified by a license addendum which accompanies this License, your rights and
obligations with respect to the use of this Product and the embedded software
are as follows:
1. AS APPROPRIATE WITH RESPECT TO THE LICENSED PRODUCT, YOU MAY: Use, copy,
distribute and make derivative works of the Software for any purpose,
including commercial applications, subject to the following restrictions:
(i) The origin of this software must not be misrepresented; (ii) you must
not claim that you wrote the original software; (iii) altered source
versions must be plainly marked as such, and must not be misrepresented as
being the original software; and (iv) any notices contained in the Software
may not be removed or altered, including notices in source code versions.
2. YOU MAY NOT: (A) Sublicense, assign, rent or lease any portion of the
Licensed Product or the embedded Software; or (B) Remove any product
identification, copyright or other notices that appear on the Licensed
Product or embedded Software.
3. Limited Use: Use of any of the Software is strictly limited to use in
systems containing one or more SILICON LABS products when the Software is
enabled to be functional. Any unauthorized use is expressly prohibited and
will constitute a breach of this Agreement.
4. Warranty: SILICON LABS does not warrant that the Licensed Product or
embedded Software will meet your requirements or that operation of the
Licensed Product will be uninterrupted or that the embedded Software will be
error-free. You agree that the Licensed Product is provided "AS IS" and
that SILICON LABS makes no warranty as to the Licensed Product or embedded
Software. SILICON LABS DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT, RELATED TO THE
SOFTWARE, ITS USE OR ANY INABILITY TO USE IT, THE RESULTS OF ITS USE AND
THIS AGREEMENT.
YOU MAY HAVE OTHER RIGHTS, WHICH VARY FROM STATE TO STATE.
5. Disclaimer of Damages: IN NO EVENT WILL SILICON LABS BE LIABLE TO YOU FOR
ANY SPECIAL, CONSEQUENTIAL, INDIRECT, OR SIMILAR DAMAGES, INCLUDING ANY LOST
PROFITS OR LOST DATA ARISING OUT OF THE USE OR INABILITY TO USE THE LICENSED
PRODUCT EVEN IF SILICON LABS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES.
SOME STATES DO NOT ALLOW THE LIMITATION OR EXCLUSION OF LIABILITY FOR
INCIDENTAL OR CONSEQUENTIAL DAMAGES. SO THE ABOVE LIMITATION OR EXCLUSION
MAY NOT APPLY TO YOU.
IN NO CASE SHALL SILICON LABS' LIABILITY EXCEED THE PURCHASE PRICE FOR THE
LICENSED PRODUCT. The disclaimers and limitations set forth above will
apply regardless of whether you accept the Licensed Software.
6. Term and Termination: The term of this Agreement and the License granted
herein shall begin upon use of the Licensed Product and continue in
perpetuity unless you breach any of the obligations set out under this
Agreement. Upon your breach of this Agreement by you, the license granted
hereunder shall terminate immediately and you shall cease all use of the
Licensed Products and return same as well as any copies of the Licensed
Product and/or embedded Software to SILICON LABS immediately. Termination
of this License upon your breach is only one remedy available to SILICON
LABS. In addition to termination of this Agreement upon your breach,
SILICON LABS shall be entitled to seek any and all other available remedies,
at law or at equity, arising from your breach.
7. Export: You shall comply with all applicable federal, provincial, state and
local laws, regulations and ordinances including but not limited to
applicable U.S. Export Administration Laws and Regulations. You shall not
export or re-export, or allow the export or re-export of the Licensed
Product, any component of the Licensed Product, or any copy of the embedded
Software in violation of any such restrictions, laws or regulations, or to
Cuba, Libya, North Korea, Iran, Iraq, or Rwanda or to any Group D:1 or E:2
country (or any national of such country) specified in the then current
Supplement No. 1 to Part 740, or, in violation of the embargo provisions in
Part 746, of the U.S. Export Administration Regulations (or any successor
regulations or supplement), except in compliance with and with all licenses
and approvals required under applicable export laws and regulations,
including without limitation, those of the U.S. Department of Commerce.
8. General: This Agreement will be governed by the laws of the State of Texas
and any applicable federal laws or regulations. The waiver by either Party
of any default or breach of this Agreement shall not constitute a waiver of
any other or subsequent default or breach. This Agreement constitutes the
complete and exclusive statement of the mutual understanding between you and
SILICON LABS with respect to this subject matter herein. This Agreement may
only be modified by a written addendum, which has been signed by both you
and SILICON LABS. Should you have any questions concerning this Agreement,
or if you desire to contact SILICON LABS for any reason, please write:
Silicon Laboratories, Inc.
400 West Cesar Chavez
Austin, Texas 78701, U.S.A.

43
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/kits/EFM32WG_STK3800/config/bspconfig.h Normal file
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/***************************************************************************//**
* @file
* @brief Provide BSP (board support package) configuration parameters.
* @version 4.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
*******************************************************************************
*
* This file is licensed under the Silabs License Agreement. See the file
* "Silabs_License_Agreement.txt" for details. Before using this software for
* any purpose, you must agree to the terms of that agreement.
*
******************************************************************************/
#ifndef __BSPCONFIG_H
#define __BSPCONFIG_H
#define BSP_STK
#define BSP_STK_2200
#define BSP_BCC_USART UART0
#define BSP_BCC_CLK cmuClock_UART0
#define BSP_BCC_LOCATION UART_ROUTE_LOCATION_LOC1
#define BSP_BCC_TXPORT gpioPortE
#define BSP_BCC_TXPIN 0
#define BSP_BCC_RXPORT gpioPortE
#define BSP_BCC_RXPIN 1
#define BSP_BCC_ENABLE_PORT gpioPortF
#define BSP_BCC_ENABLE_PIN 7
#define BSP_GPIO_LEDS
#define BSP_NO_OF_LEDS 2
#define BSP_GPIO_LEDARRAY_INIT {{gpioPortE,2},{gpioPortE,3}}
#define BSP_STK_USE_EBI
#define BSP_INIT_DEFAULT 0
#define BSP_BCP_VERSION 2
#include "bsp_bcp.h"
#endif

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/***************************************************************************//**
* @file
* @brief Low Energy Sensor (LESENSE) example configuration file.
* @version 4.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
*******************************************************************************
*
* This file is licensed under the Silabs License Agreement. See the file
* "Silabs_License_Agreement.txt" for details. Before using this software for
* any purpose, you must agree to the terms of that agreement.
*
******************************************************************************/
#include "em_lesense.h"
/***************************************************************************//**
* @addtogroup Drivers
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup CapSense
* @{
******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**************************************************************************//**
* Macro definitions
*****************************************************************************/
#define CAPLESENSE_SENSITIVITY_OFFS 1U
#define CAPLESENSE_NUMOF_SLIDERS 4 /**< Number of sliders */
#define CAPLESENSE_ACMP_VDD_SCALE LESENSE_ACMP_VDD_SCALE /**< Upper voltage threshold */
#define CAPLESENSE_SLIDER_PORT0 gpioPortC /**< Slider Port. GPIO Port C */
#define CAPLESENSE_SLIDER0_PORT CAPLESENSE_SLIDER_PORT0 /**< Slider 0 Port. GPIO Port C */
#define CAPLESENSE_SLIDER0_PIN 8UL /**< Slider 0 Pin 8 */
#define CAPLESENSE_SLIDER1_PORT CAPLESENSE_SLIDER_PORT0 /**< Slider 1 Port. GPIO Port C */
#define CAPLESENSE_SLIDER1_PIN 9UL /**< Slider 1 Pin 9 */
#define CAPLESENSE_SLIDER2_PORT CAPLESENSE_SLIDER_PORT0 /**< Slider 2 Port. GPIO Port C */
#define CAPLESENSE_SLIDER2_PIN 10UL /**< Slider 2 Pin 10 */
#define CAPLESENSE_SLIDER3_PORT CAPLESENSE_SLIDER_PORT0 /**< Slider 3 Port. GPIO Port C */
#define CAPLESENSE_SLIDER3_PIN 11UL /**< Slider 3 Pin 11 */
#define CAPLESENSE_CHANNEL_INT (LESENSE_IF_CH8 | LESENSE_IF_CH9 | LESENSE_IF_CH10 | LESENSE_IF_CH11)
#define LESENSE_CHANNELS 16 /**< Number of channels for the Low Energy Sensor Interface. */
#define SLIDER_PART0_CHANNEL 8 /**< Touch slider channel Part 0 */
#define SLIDER_PART1_CHANNEL 9 /**< Touch slider channel Part 1 */
#define SLIDER_PART2_CHANNEL 10 /**< Touch slider channel Part 2 */
#define SLIDER_PART3_CHANNEL 11 /**< Touch slider channel Part 3 */
/** Upper voltage threshold. */
#define LESENSE_ACMP_VDD_SCALE 0x37U
#define LESENSE_CAPSENSE_CH_IN_USE {\
/* Ch0, Ch1, Ch2, Ch3, Ch4, Ch5, Ch6, Ch7 */\
false, false, false, false, false, false, false, false,\
/* Ch8, Ch9, Ch10, Ch11, Ch12, Ch13, Ch14, Ch15 */\
true, true, true, true, false, false, false, false\
}
/** Configuration for capacitive sense channels in sense mode. */
#define LESENSE_CAPSENSE_CH_CONF_SENSE \
{ \
true, /* Enable scan channel. */ \
true, /* Enable the assigned pin on scan channel. */ \
false, /* Disable interrupts on channel. */ \
lesenseChPinExDis, /* GPIO pin is disabled during the excitation period. */ \
lesenseChPinIdleDis, /* GPIO pin is disabled during the idle period. */ \
false, /* Don't use alternate excitation pins for excitation. */ \
false, /* Disabled to shift results from this channel to the decoder register. */ \
false, /* Disabled to invert the scan result bit. */ \
true, /* Enabled to store counter value in the result buffer. */ \
lesenseClkLF, /* Use the LF clock for excitation timing. */ \
lesenseClkLF, /* Use the LF clock for sample timing. */ \
0x00U, /* Excitation time is set to 0 excitation clock cycles. */ \
0x0FU, /* Sample delay is set to 15(+1) sample clock cycles. */ \
0x00U, /* Measure delay is set to 0 excitation clock cycles.*/ \
LESENSE_ACMP_VDD_SCALE, /* ACMP threshold has been set to LESENSE_ACMP_VDD_SCALE. */ \
lesenseSampleModeCounter, /* ACMP will be used in comparison. */ \
lesenseSetIntLevel, /* Interrupt is generated if the sensor triggers. */ \
0x00U, /* Counter threshold has been set to 0x00. */ \
lesenseCompModeLess /* Compare mode has been set to trigger interrupt on "less". */ \
}
/** Configuration for capacitive sense channels in sleep mode. */
#define LESENSE_CAPSENSE_CH_CONF_SLEEP \
{ \
true, /* Enable scan channel. */ \
true, /* Enable the assigned pin on scan channel. */ \
true, /* Enable interrupts on channel. */ \
lesenseChPinExDis, /* GPIO pin is disabled during the excitation period. */ \
lesenseChPinIdleDis, /* GPIO pin is disabled during the idle period. */ \
false, /* Don't use alternate excitation pins for excitation. */ \
false, /* Disabled to shift results from this channel to the decoder register. */ \
false, /* Disabled to invert the scan result bit. */ \
true, /* Enabled to store counter value in the result buffer. */ \
lesenseClkLF, /* Use the LF clock for excitation timing. */ \
lesenseClkLF, /* Use the LF clock for sample timing. */ \
0x00U, /* Excitation time is set to 0 excitation clock cycles. */ \
0x01U, /* Sample delay is set to 1(+1) sample clock cycles. */ \
0x00U, /* Measure delay is set to 0 excitation clock cycles.*/ \
LESENSE_ACMP_VDD_SCALE, /* ACMP threshold has been set to LESENSE_ACMP_VDD_SCALE. */ \
lesenseSampleModeCounter, /* Counter will be used in comparison. */ \
lesenseSetIntLevel, /* Interrupt is generated if the sensor triggers. */ \
0x0EU, /* Counter threshold has been set to 0x0E. */ \
lesenseCompModeLess /* Compare mode has been set to trigger interrupt on "less". */ \
}
/** Configuration for disabled channels. */
#define LESENSE_DISABLED_CH_CONF \
{ \
false, /* Disable scan channel. */ \
false, /* Disable the assigned pin on scan channel. */ \
false, /* Disable interrupts on channel. */ \
lesenseChPinExDis, /* GPIO pin is disabled during the excitation period. */ \
lesenseChPinIdleDis, /* GPIO pin is disabled during the idle period. */ \
false, /* Don't use alternate excitation pins for excitation. */ \
false, /* Disabled to shift results from this channel to the decoder register. */ \
false, /* Disabled to invert the scan result bit. */ \
false, /* Disabled to store counter value in the result buffer. */ \
lesenseClkLF, /* Use the LF clock for excitation timing. */ \
lesenseClkLF, /* Use the LF clock for sample timing. */ \
0x00U, /* Excitation time is set to 5(+1) excitation clock cycles. */ \
0x00U, /* Sample delay is set to 7(+1) sample clock cycles. */ \
0x00U, /* Measure delay is set to 0 excitation clock cycles.*/ \
0x00U, /* ACMP threshold has been set to 0. */ \
lesenseSampleModeCounter, /* ACMP output will be used in comparison. */ \
lesenseSetIntNone, /* No interrupt is generated by the channel. */ \
0x00U, /* Counter threshold has been set to 0x01. */ \
lesenseCompModeLess /* Compare mode has been set to trigger interrupt on "less". */ \
}
/** Configuration for scan in sense mode. */
#define LESENSE_CAPSENSE_SCAN_CONF_SENSE \
{ \
{ \
LESENSE_DISABLED_CH_CONF, /* Channel 0. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 1. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 2. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 3. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 4. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 5. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 6. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 7. */ \
LESENSE_CAPSENSE_CH_CONF_SENSE, /* Channel 8. */ \
LESENSE_CAPSENSE_CH_CONF_SENSE, /* Channel 9. */ \
LESENSE_CAPSENSE_CH_CONF_SENSE, /* Channel 10. */ \
LESENSE_CAPSENSE_CH_CONF_SENSE, /* Channel 11. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 12. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 13. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 14. */ \
LESENSE_DISABLED_CH_CONF /* Channel 15. */ \
} \
}
/** Configuration for scan in sleep mode. */
#define LESENSE_CAPSENSE_SCAN_CONF_SLEEP \
{ \
{ \
LESENSE_DISABLED_CH_CONF, /* Channel 0. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 1. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 2. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 3. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 4. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 5. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 6. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 7. */ \
LESENSE_CAPSENSE_CH_CONF_SLEEP, /* Channel 8. */ \
LESENSE_CAPSENSE_CH_CONF_SLEEP, /* Channel 9. */ \
LESENSE_CAPSENSE_CH_CONF_SLEEP, /* Channel 10. */ \
LESENSE_CAPSENSE_CH_CONF_SLEEP, /* Channel 11. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 12. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 13. */ \
LESENSE_DISABLED_CH_CONF, /* Channel 14. */ \
LESENSE_DISABLED_CH_CONF /* Channel 15. */ \
} \
}
#ifdef __cplusplus
}
#endif
/** @} (end group CapSense) */
/** @} (end group Drivers) */

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FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/kits/EFM32WG_STK3800/config/i2cspmconfig.h Normal file
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/***************************************************************************//**
* @file i2cspmconfig.h
* @brief I2CSPM driver configuration file
* @version 4.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
*******************************************************************************
*
* This file is licensed under the Silabs License Agreement. See the file
* "Silabs_License_Agreement.txt" for details. Before using this software for
* any purpose, you must agree to the terms of that agreement.
*
******************************************************************************/
#ifndef __SILICON_LABS_I2CSPM_CONFIG_H__
#define __SILICON_LABS_I2CSPM_CONFIG_H__
/***************************************************************************//**
* @addtogroup Drivers
* @{
******************************************************************************/
/***************************************************************************//**
* @addtogroup I2CSPM
* @{
******************************************************************************/
/* I2C SPM driver config. This default override only works if one I2C interface
is in use. If multiple interfaces are in use, define the peripheral setup
inside the application in a I2CSPM_Init_TypeDef and then pass the initialization
struct to I2CSPM_Init(). */
#define I2CSPM_INIT_DEFAULT \
{ I2C0, /* Use I2C instance 0 */ \
gpioPortC, /* SCL port */ \
5, /* SCL pin */ \
gpioPortC, /* SDA port */ \
4, /* SDA pin */ \
0, /* Location */ \
0, /* Use currently configured reference clock */ \
I2C_FREQ_STANDARD_MAX, /* Set to standard rate */ \
i2cClockHLRStandard, /* Set to use 4:4 low/high duty cycle */ \
}
#define I2CSPM_TRANSFER_TIMEOUT 300000
/** @} (end addtogroup I2CSPM) */
/** @} (end addtogroup Drivers) */
#endif /* __SILICON_LABS_I2CSPM_CONFIG_H__ */

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/***************************************************************************//**
* @file
* @brief Provide stdio retargeting configuration parameters.
* @version 4.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
*******************************************************************************
*
* This file is licensed under the Silabs License Agreement. See the file
* "Silabs_License_Agreement.txt" for details. Before using this software for
* any purpose, you must agree to the terms of that agreement.
*
******************************************************************************/
#ifndef __RETARGETSERIALCONFIG_H
#define __RETARGETSERIALCONFIG_H
/* Override if needed with commandline parameter -DRETARGET_xxx */
#if !defined(RETARGET_USART1) && !defined(RETARGET_LEUART0)
#define RETARGET_USART1 /* Use USART1 by default. */
#endif
#if defined(RETARGET_USART1)
#define RETARGET_IRQ_NAME USART1_RX_IRQHandler /* USART IRQ Handler */
#define RETARGET_CLK cmuClock_USART1 /* HFPER Clock */
#define RETARGET_IRQn USART1_RX_IRQn /* IRQ number */
#define RETARGET_UART USART1 /* USART instance */
#define RETARGET_TX USART_Tx /* Set TX to USART_Tx */
#define RETARGET_RX USART_Rx /* Set RX to USART_Rx */
#define RETARGET_LOCATION USART_ROUTE_LOCATION_LOC1 /* Location of of the USART I/O pins */
#define RETARGET_TXPORT gpioPortD /* USART transmission port */
#define RETARGET_TXPIN 0 /* USART transmission pin */
#define RETARGET_RXPORT gpioPortD /* USART reception port */
#define RETARGET_RXPIN 1 /* USART reception pin */
#define RETARGET_USART 1 /* Includes em_usart.h */
#define RETARGET_PERIPHERAL_ENABLE()
#elif defined(RETARGET_LEUART0)
#define RETARGET_IRQ_NAME LEUART0_IRQHandler /* LEUART IRQ Handler */
#define RETARGET_CLK cmuClock_LEUART0 /* LFB Clock */
#define RETARGET_IRQn LEUART0_IRQn /* IRQ number */
#define RETARGET_UART LEUART0 /* LEUART instance */
#define RETARGET_TX LEUART_Tx /* Set TX to LEUART_Tx */
#define RETARGET_RX LEUART_Rx /* Set RX to LEUART_Rx */
#define RETARGET_TXPORT gpioPortD /* LEUART transmission port */
#define RETARGET_TXPIN 4 /* LEUART transmission pin */
#define RETARGET_RXPORT gpioPortD /* LEUART reception port */
#define RETARGET_RXPIN 5 /* LEUART reception pin */
#define RETARGET_LOCATION LEUART_ROUTE_LOCATION_LOC0 /* Location of of the LEUART I/O pins */
#define RETARGET_LEUART 1 /* Includes em_leuart.h */
#define RETARGET_PERIPHERAL_ENABLE()
#else
#error "Illegal USART/LEUART selection."
#endif
#endif

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/**************************************************************************//**
* @file
* @brief Segment LCD Config
* @version 4.0.0
******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
*******************************************************************************
*
* This file is licensed under the Silabs License Agreement. See the file
* "Silabs_License_Agreement.txt" for details. Before using this software for
* any purpose, you must agree to the terms of that agreement.
*
******************************************************************************/
#ifndef __SEGMENTLCDCONFIG_H
#define __SEGMENTLCDCONFIG_H
#include "em_lcd.h"
#ifdef __cplusplus
extern "C" {
#endif
/** Range of symbols available on display */
typedef enum {
LCD_SYMBOL_GECKO,
LCD_SYMBOL_ANT,
LCD_SYMBOL_PAD0,
LCD_SYMBOL_PAD1,
LCD_SYMBOL_EFM32,
LCD_SYMBOL_MINUS,
LCD_SYMBOL_COL3,
LCD_SYMBOL_COL5,
LCD_SYMBOL_COL10,
LCD_SYMBOL_DEGC,
LCD_SYMBOL_DEGF,
LCD_SYMBOL_DP2,
LCD_SYMBOL_DP3,
LCD_SYMBOL_DP4,
LCD_SYMBOL_DP5,
LCD_SYMBOL_DP6,
LCD_SYMBOL_DP10,
} lcdSymbol;
#define LCD_SYMBOL_GECKO_COM 1
#define LCD_SYMBOL_GECKO_SEG 12
#define LCD_SYMBOL_ANT_COM 0
#define LCD_SYMBOL_ANT_SEG 32
#define LCD_SYMBOL_PAD0_COM 3
#define LCD_SYMBOL_PAD0_SEG 39
#define LCD_SYMBOL_PAD1_COM 2
#define LCD_SYMBOL_PAD1_SEG 12
#define LCD_SYMBOL_EFM32_COM 0
#define LCD_SYMBOL_EFM32_SEG 28
#define LCD_SYMBOL_MINUS_COM 3
#define LCD_SYMBOL_MINUS_SEG 12
#define LCD_SYMBOL_COL3_COM 4
#define LCD_SYMBOL_COL3_SEG 12
#define LCD_SYMBOL_COL5_COM 0
#define LCD_SYMBOL_COL5_SEG 30
#define LCD_SYMBOL_COL10_COM 5
#define LCD_SYMBOL_COL10_SEG 39
#define LCD_SYMBOL_DEGC_COM 0
#define LCD_SYMBOL_DEGC_SEG 34
#define LCD_SYMBOL_DEGF_COM 0
#define LCD_SYMBOL_DEGF_SEG 35
#define LCD_SYMBOL_DP2_COM 7
#define LCD_SYMBOL_DP2_SEG 12
#define LCD_SYMBOL_DP3_COM 5
#define LCD_SYMBOL_DP3_SEG 12
#define LCD_SYMBOL_DP4_COM 6
#define LCD_SYMBOL_DP4_SEG 12
#define LCD_SYMBOL_DP5_COM 7
#define LCD_SYMBOL_DP5_SEG 29
#define LCD_SYMBOL_DP6_COM 7
#define LCD_SYMBOL_DP6_SEG 31
#define LCD_SYMBOL_DP10_COM 4
#define LCD_SYMBOL_DP10_SEG 39
/* LCD Controller Prescaler (divide LFACLK / 64) */
/* LFACLK_LCDpre = 512 Hz */
/* Set FDIV=0, means 512/1 = 512 Hz */
/* With octaplex mode, 512/16 => 32 Hz Frame Rate */
#define LCD_CMU_CLK_PRE cmuClkDiv_64
#define LCD_CMU_CLK_DIV cmuClkDiv_1
#define LCD_BOOST_LEVEL lcdVBoostLevel3
#define LCD_INIT_DEF \
{ true,\
lcdMuxOctaplex,\
lcdBiasOneFourth,\
lcdWaveLowPower,\
lcdVLCDSelVDD, \
lcdConConfVLCD }
#define LCD_NUMBER_OFF() \
do { \
LCD_SegmentSetHigh(1, 0x00000078, 0x00000000); \
LCD_SegmentSetHigh(2, 0x00000078, 0x00000000); \
LCD_SegmentSetHigh(3, 0x00000078, 0x00000000); \
LCD_SegmentSetHigh(4, 0x00000078, 0x00000000); \
LCD_SegmentSetHigh(5, 0x00000078, 0x00000000); \
LCD_SegmentSetHigh(6, 0x00000078, 0x00000000); \
LCD_SegmentSetHigh(7, 0x00000078, 0x00000000); \
} while (0)
#define LCD_ALPHA_NUMBER_OFF() \
do { \
LCD_SegmentSetLow(7, 0x500FE000, 0x00000000);\
LCD_SegmentSetLow(6, 0xF00FE000, 0x00000000);\
LCD_SegmentSetLow(5, 0xF00FE000, 0x00000000);\
LCD_SegmentSetLow(4, 0xF00FE000, 0x00000000);\
LCD_SegmentSetLow(3, 0xF00FE000, 0x00000000);\
LCD_SegmentSetLow(2, 0xF00FE000, 0x00000000);\
LCD_SegmentSetLow(1, 0xF00FE000, 0x00000000);\
LCD_SegmentSetLow(0, 0xA0000000, 0x00000000);\
LCD_SegmentSetHigh(7, 0x00000007, 0x00000000);\
LCD_SegmentSetHigh(6, 0x00000007, 0x00000000);\
LCD_SegmentSetHigh(5, 0x00000007, 0x00000000);\
LCD_SegmentSetHigh(4, 0x00000007, 0x00000000);\
LCD_SegmentSetHigh(3, 0x00000007, 0x00000000);\
LCD_SegmentSetHigh(2, 0x00000007, 0x00000000);\
LCD_SegmentSetHigh(1, 0x00000007, 0x00000000);\
} while(0)
#define LCD_ALL_SEGMENTS_OFF() \
do { \
LCD_SegmentSetLow(0, 0xF00FF000, 0x00000000);\
LCD_SegmentSetLow(1, 0xF00FF000, 0x00000000);\
LCD_SegmentSetLow(2, 0xF00FF000, 0x00000000);\
LCD_SegmentSetLow(3, 0xF00FF000, 0x00000000);\
LCD_SegmentSetLow(4, 0xF00FF000, 0x00000000);\
LCD_SegmentSetLow(5, 0xF00FF000, 0x00000000);\
LCD_SegmentSetLow(6, 0xF00FF000, 0x00000000);\
LCD_SegmentSetLow(7, 0xF00FF000, 0x00000000);\
LCD_SegmentSetHigh(0, 0x000000FF, 0x00000000);\
LCD_SegmentSetHigh(1, 0x000000FF, 0x00000000);\
LCD_SegmentSetHigh(2, 0x000000FF, 0x00000000);\
LCD_SegmentSetHigh(3, 0x000000FF, 0x00000000);\
LCD_SegmentSetHigh(4, 0x000000FF, 0x00000000);\
LCD_SegmentSetHigh(5, 0x000000FF, 0x00000000);\
LCD_SegmentSetHigh(6, 0x000000FF, 0x00000000);\
LCD_SegmentSetHigh(7, 0x000000FF, 0x00000000);\
} while(0)
#define LCD_ALL_SEGMENTS_ON() \
do { \
LCD_SegmentSetLow(0, 0xF00FF000, 0xFFFFFFFF);\
LCD_SegmentSetLow(1, 0xF00FF000, 0xFFFFFFFF);\
LCD_SegmentSetLow(2, 0xF00FF000, 0xFFFFFFFF);\
LCD_SegmentSetLow(3, 0xF00FF000, 0xFFFFFFFF);\
LCD_SegmentSetLow(4, 0xF00FF000, 0xFFFFFFFF);\
LCD_SegmentSetLow(5, 0xF00FF000, 0xFFFFFFFF);\
LCD_SegmentSetLow(6, 0xF00FF000, 0xFFFFFFFF);\
LCD_SegmentSetLow(7, 0xF00FF000, 0xFFFFFFFF);\
LCD_SegmentSetHigh(0, 0x000000FF, 0xFFFFFFFF);\
LCD_SegmentSetHigh(1, 0x000000FF, 0xFFFFFFFF);\
LCD_SegmentSetHigh(2, 0x000000FF, 0xFFFFFFFF);\
LCD_SegmentSetHigh(3, 0x000000FF, 0xFFFFFFFF);\
LCD_SegmentSetHigh(4, 0x000000FF, 0xFFFFFFFF);\
LCD_SegmentSetHigh(5, 0x000000FF, 0xFFFFFFFF);\
LCD_SegmentSetHigh(6, 0x000000FF, 0xFFFFFFFF);\
LCD_SegmentSetHigh(7, 0x000000FF, 0xFFFFFFFF);\
} while(0)
#define LCD_SEGMENTS_ENABLE() \
do { \
LCD_SegmentRangeEnable(lcdSegment12_15, true);\
LCD_SegmentRangeEnable(lcdSegment16_19, true);\
LCD_SegmentRangeEnable(lcdSegment28_31, true);\
LCD_SegmentRangeEnable(lcdSegment32_35, true);\
LCD_SegmentRangeEnable(lcdSegment36_39, true);\
} while(0)
#define LCD_DISPLAY_ENABLE() \
do { \
;\
} while(0)
#define EFM_DISPLAY_DEF {\
.Text = {\
{ /* 1 */\
.com[0] = 1, .com[1] = 1, .com[2] = 5, .com[3] = 7,\
.bit[0] = 13, .bit[1] = 14, .bit[2] = 14, .bit[3] = 14,\
.com[4] = 7, .com[5] = 3, .com[6] = 4, .com[7] = 2,\
.bit[4] = 13, .bit[5] = 13, .bit[6] = 13, .bit[7] = 13,\
.com[8] = 3, .com[9] = 2, .com[10] = 4, .com[11] = 6,\
.bit[8] = 14, .bit[9] = 14, .bit[10] = 14, .bit[11] = 14,\
.com[12] = 5, .com[13] = 6,\
.bit[12] = 13, .bit[13] = 13\
},\
{ /* 2 */\
.com[0] = 1, .com[1] = 1, .com[2] = 5, .com[3] = 7,\
.bit[0] = 15, .bit[1] = 16, .bit[2] = 16, .bit[3] = 16,\
.com[4] = 7, .com[5] = 3, .com[6] = 4, .com[7] = 2,\
.bit[4] = 15, .bit[5] = 15, .bit[6] = 15, .bit[7] = 15,\
.com[8] = 3, .com[9] = 2, .com[10] = 4, .com[11] = 6,\
.bit[8] = 16, .bit[9] = 16, .bit[10] = 16, .bit[11] = 16,\
.com[12] = 5, .com[13] = 6,\
.bit[12] = 15, .bit[13] = 15\
},\
{ /* 3 */\
.com[0] = 1, .com[1] = 1, .com[2] = 5, .com[3] = 7,\
.bit[0] = 17, .bit[1] = 18, .bit[2] = 18, .bit[3] = 18,\
.com[4] = 7, .com[5] = 3, .com[6] = 4, .com[7] = 2,\
.bit[4] = 17, .bit[5] = 17, .bit[6] = 17, .bit[7] = 17,\
.com[8] = 3, .com[9] = 2, .com[10] = 4, .com[11] = 6,\
.bit[8] = 18, .bit[9] = 18, .bit[10] = 18, .bit[11] = 18,\
.com[12] = 5, .com[13] = 6,\
.bit[12] = 17, .bit[13] = 17\
},\
{ /* 4 */\
.com[0] = 1, .com[1] = 1, .com[2] = 5, .com[3] = 7,\
.bit[0] = 19, .bit[1] = 28, .bit[2] = 28, .bit[3] = 28,\
.com[4] = 7, .com[5] = 3, .com[6] = 4, .com[7] = 2,\
.bit[4] = 19, .bit[5] = 19, .bit[6] = 19, .bit[7] = 19,\
.com[8] = 3, .com[9] = 2, .com[10] = 4, .com[11] = 6,\
.bit[8] = 28, .bit[9] = 28, .bit[10] = 28, .bit[11] = 28,\
.com[12] = 5, .com[13] = 6,\
.bit[12] = 19, .bit[13] = 19\
},\
{ /* 5 */\
.com[0] = 0, .com[1] = 1, .com[2] = 5, .com[3] = 7,\
.bit[0] = 29, .bit[1] = 30, .bit[2] = 30, .bit[3] = 30,\
.com[4] = 6, .com[5] = 2, .com[6] = 3, .com[7] = 1,\
.bit[4] = 29, .bit[5] = 29, .bit[6] = 29, .bit[7] = 29,\
.com[8] = 3, .com[9] = 2, .com[10] = 4, .com[11] = 6,\
.bit[8] = 30, .bit[9] = 30, .bit[10] = 30, .bit[11] = 30,\
.com[12] = 4, .com[13] = 5,\
.bit[12] = 29, .bit[13] = 29\
},\
{ /* 6 */\
.com[0] = 0, .com[1] = 1, .com[2] = 5, .com[3] = 7,\
.bit[0] = 31, .bit[1] = 32, .bit[2] = 32, .bit[3] = 32,\
.com[4] = 6, .com[5] = 2, .com[6] = 3, .com[7] = 1,\
.bit[4] = 31, .bit[5] = 31, .bit[6] = 31, .bit[7] = 31,\
.com[8] = 3, .com[9] = 2, .com[10] = 4, .com[11] = 6,\
.bit[8] = 32, .bit[9] = 32, .bit[10] = 32, .bit[11] = 32,\
.com[12] = 4, .com[13] = 5,\
.bit[12] = 31, .bit[13] = 31\
},\
{ /* 7 */\
.com[0] = 1, .com[1] = 1, .com[2] = 5, .com[3] = 7,\
.bit[0] = 33, .bit[1] = 34, .bit[2] = 34, .bit[3] = 34,\
.com[4] = 7, .com[5] = 3, .com[6] = 4, .com[7] = 2,\
.bit[4] = 33, .bit[5] = 33, .bit[6] = 33, .bit[7] = 33,\
.com[8] = 3, .com[9] = 2, .com[10] = 4, .com[11] = 6,\
.bit[8] = 34, .bit[9] = 34, .bit[10] = 34, .bit[11] = 34,\
.com[12] = 5, .com[13] = 6,\
.bit[12] = 33, .bit[13] = 33\
},\
},\
.Number = {\
{\
.com[0] = 7, .com[1] = 5, .com[2] = 2, .com[3] = 1,\
.bit[0] = 35, .bit[1] = 35, .bit[2] = 35, .bit[3] = 35,\
.com[4] = 3, .com[5] = 6, .com[6] = 4,\
.bit[4] = 35, .bit[5] = 35, .bit[6] = 35,\
},\
{\
.com[0] = 7, .com[1] = 5, .com[2] = 2, .com[3] = 1,\
.bit[0] = 36, .bit[1] = 36, .bit[2] = 36, .bit[3] = 36,\
.com[4] = 3, .com[5] = 6, .com[6] = 4,\
.bit[4] = 36, .bit[5] = 36, .bit[6] = 36,\
},\
{\
.com[0] = 7, .com[1] = 5, .com[2] = 2, .com[3] = 1,\
.bit[0] = 37, .bit[1] = 37, .bit[2] = 37, .bit[3] = 37,\
.com[4] = 3, .com[5] = 6, .com[6] = 4,\
.bit[4] = 37, .bit[5] = 37, .bit[6] = 37,\
},\
{\
.com[0] = 7, .com[1] = 5, .com[2] = 2, .com[3] = 1,\
.bit[0] = 38, .bit[1] = 38, .bit[2] = 38, .bit[3] = 38,\
.com[4] = 3, .com[5] = 6, .com[6] = 4,\
.bit[4] = 38, .bit[5] = 38, .bit[6] = 38,\
},\
},\
.EMode = {\
.com[0] = 0, .bit[0] = 39,\
.com[1] = 1, .bit[1] = 39,\
.com[2] = 7, .bit[2] = 39,\
.com[3] = 2, .bit[3] = 39,\
.com[4] = 6, .bit[4] = 39,\
},\
.ARing = {\
.com[0] = 0, .bit[0] = 19,\
.com[1] = 0, .bit[1] = 18,\
.com[2] = 0, .bit[2] = 17,\
.com[3] = 0, .bit[3] = 16,\
.com[4] = 0, .bit[4] = 15,\
.com[5] = 0, .bit[5] = 14,\
.com[6] = 0, .bit[6] = 13,\
.com[7] = 0, .bit[7] = 12,\
},\
.Battery = {\
.com[0] = 0, .bit[0] = 33,\
.com[1] = 0, .bit[1] = 37,\
.com[2] = 0, .bit[2] = 36,\
.com[3] = 0, .bit[3] = 38,\
}\
}
#ifdef __cplusplus
}
#endif
#endif

26
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/kits/EFM32WG_STK3800/config/traceconfig.h Normal file
View File

@ -0,0 +1,26 @@
/***************************************************************************//**
* @file
* @brief Provide SWO/ETM TRACE configuration parameters.
* @version 4.0.0
*******************************************************************************
* @section License
* <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
*******************************************************************************
*
* This file is licensed under the Silabs License Agreement. See the file
* "Silabs_License_Agreement.txt" for details. Before using this software for
* any purpose, you must agree to the terms of that agreement.
*
******************************************************************************/
#ifndef __TRACECONFIG_H
#define __TRACECONFIG_H
#define BSP_TRACE_SWO_LOCATION GPIO_ROUTE_SWLOCATION_LOC0
/* Enable output on pin - GPIO Port F, Pin 2. */
#define TRACE_ENABLE_PINS() \
GPIO->P[5].MODEL &= ~(_GPIO_P_MODEL_MODE2_MASK); \
GPIO->P[5].MODEL |= GPIO_P_MODEL_MODE2_PUSHPULL
#endif

2
FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/main.c
View File

@ -154,8 +154,6 @@ static void prvSetupHardware( void )
BSP_TraceProfilerSetup();
SLEEP_Init( NULL, NULL );
BSP_LedsInit();
//_RB_ SLEEP_SleepBlockBegin( ( SLEEP_EnergyMode_t ) ( configSLEEP_MODE+1 ) );
}
/*-----------------------------------------------------------*/

2
FreeRTOS/Demo/Common/include/fileIO.h
View File

@ -68,7 +68,7 @@
*/
#ifndef FILE_IO_H
#define FILE_OI_H
#define FILE_IO_H
void vDisplayMessage( const char * const pcMessageToPrint );
void vWriteMessageToDisk( const char * const pcMessage );

4
FreeRTOS/Source/event_groups.c
View File

@ -143,7 +143,7 @@ EventGroup_t *pxEventBits;
else
{
/* The user has provided a statically allocated event group - use it. */
pxEventBits = ( EventGroup_t * ) pxStaticEventGroup;
pxEventBits = ( EventGroup_t * ) pxStaticEventGroup; /*lint !e740 EventGroup_t and StaticEventGroup_t are guaranteed to have the same size and alignment requirement - checked by configASSERT(). */
}
if( pxEventBits != NULL )
@ -611,7 +611,7 @@ const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
/* Only free the memory if it was allocated dynamically. */
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
if( pxEventBits->ucStaticallyAllocated == pdFALSE )
if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
{
vPortFree( pxEventBits );
}

22
FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
View File

@ -202,10 +202,32 @@ not necessary for to use this port. They are defined so the common demo files
/* portNOP() is not required by this port. */
#define portNOP()
#define portINLINE __inline
#ifndef portFORCE_INLINE
#define portFORCE_INLINE inline __attribute__(( always_inline))
#endif
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
{
uint32_t ulCurrentInterrupt;
BaseType_t xReturn;
/* Obtain the number of the currently executing interrupt. */
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
if( ulCurrentInterrupt == 0 )
{
xReturn = pdFALSE;
}
else
{
xReturn = pdTRUE;
}
return xReturn;
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortRaiseBASEPRI( void )

8
FreeRTOS/Source/queue.c
View File

@ -390,13 +390,13 @@ size_t xQueueSizeInBytes;
/* The address of a statically allocated queue was passed in, use
it and note that the queue was not dynamically allocated so there is
no attempt to free it again should the queue be deleted. */
pxNewQueue = ( Queue_t * ) pxStaticQueue;
pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
pxNewQueue->ucStaticAllocationFlags = queueSTATICALLY_ALLOCATED_QUEUE_STRUCT;
}
if( pxNewQueue != NULL )
{
if( ( *ppucQueueStorage == NULL ) && ( xQueueSizeInBytes > 0 ) )
if( ( *ppucQueueStorage == NULL ) && ( xQueueSizeInBytes > ( size_t ) 0 ) )
{
/* A statically allocated queue storage area was not passed in,
so allocate the queue storage area dynamically. */
@ -2499,10 +2499,10 @@ BaseType_t xReturn;
#if ( configQUEUE_REGISTRY_SIZE > 0 )
const char *pcQueueGetQueueName( QueueHandle_t xQueue )
const char *pcQueueGetQueueName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
{
UBaseType_t ux;
const char *pcReturn = NULL;
const char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
/* Note there is nothing here to protect against another task adding or
removing entries from the registry while it is being searched. */

2
FreeRTOS/Source/tasks.c
View File

@ -3500,7 +3500,7 @@ TCB_t *pxNewTCB;
}
}
#endif /* INCLUDE_eTaskGetState */
#endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/
#if ( configUSE_TRACE_FACILITY == 1 )