From b49cf69600bb6be7920fbd693af17735654c6a5d Mon Sep 17 00:00:00 2001 From: Richard Barry Date: Tue, 30 Jun 2009 19:39:09 +0000 Subject: [PATCH] Add Virtex5 demo that uses the single precision floating point. --- .../RTOSDemo/FreeRTOSConfig.h | 115 + .../RTOSDemo/RTOSDemo_linker_script.ld | 226 ++ .../RTOSDemo/flop/flop-reg-test.c | 246 ++ .../RTOSDemo/flop/flop-reg-test.h | 58 + .../RTOSDemo/flop/flop.c | 402 +++ .../RTOSDemo/main.c | 701 +++++ .../RTOSDemo/partest/partest.c | 170 + .../RTOSDemo/serial/serial.c | 235 ++ .../Version_Changes.log | 15 + .../__xps/.dswkshop/MdtSvgBLKD_Dimensions.xsl | 173 ++ .../__xps/.dswkshop/MdtSvgDiag_Colors.xsl | 134 + .../__xps/.dswkshop/MdtSvgDiag_Globals.xsl | 46 + .../__xps/.dswkshop/MdtSvgDiag_StyleDefs.xsl | 580 ++++ .../MdtTinySvgBLKD_BusLaneSpaces.xsl | 2757 +++++++++++++++++ .../__xps/.dswkshop/MdtTinySvgBLKD_Busses.xsl | 534 ++++ .../.dswkshop/MdtTinySvgBLKD_Functions.xsl | 1110 +++++++ .../.dswkshop/MdtTinySvgBLKD_Globals.xsl | 115 + .../.dswkshop/MdtTinySvgBLKD_IOPorts.xsl | 490 +++ .../__xps/.dswkshop/MdtTinySvgBLKD_Main.xsl | 1549 +++++++++ .../.dswkshop/MdtTinySvgBLKD_Peripherals.xsl | 1582 ++++++++++ .../.dswkshop/MdtTinySvgBLKD_Processors.xsl | 462 +++ .../.dswkshop/MdtTinySvgDiag_BifShapes.xsl | 241 ++ .../__xps/.dswkshop/svg10.dtd | 1704 ++++++++++ .../__xps/bitinit.opt | 1 + .../__xps/ise/system.gise | 26 + .../__xps/ise/system.ise | Bin 0 -> 10983 bytes .../__xps/ise/system.xise | 42 + .../__xps/ise/system_xdb/tmp/ise.lock | Bin 0 -> 240 bytes .../HierarchicalDesign/HDProject/HDProject | Bin 0 -> 201 bytes .../HDProject/HDProject_StrTbl | Bin 0 -> 17 bytes .../__stored_object_table__ | Bin 0 -> 60 bytes .../PnAutoRun/Scripts/RunOnce_tcl | Bin 0 -> 27 bytes .../PnAutoRun/Scripts/RunOnce_tcl_StrTbl | Bin 0 -> 3817 bytes .../dpm_project_main/dpm_project_main | Bin 0 -> 25 bytes .../dpm_project_main/dpm_project_main_StrTbl | Bin 0 -> 10 bytes .../xreport/Gc_RvReportViewer-Current-Module | Bin 0 -> 27 bytes .../Gc_RvReportViewer-Current-Module_StrTbl | Bin 0 -> 18 bytes .../Gc_RvReportViewer-Module-Data-system | Bin 0 -> 381 bytes ...c_RvReportViewer-Module-Data-system_StrTbl | Bin 0 -> 23174 bytes ..._RvReportViewer-Module-DataFactory-Default | Bin 0 -> 387 bytes ...rtViewer-Module-DataFactory-Default_StrTbl | Bin 0 -> 15712 bytes .../tmp/ise/__REGISTRY__/Autonym/regkeys | 0 .../HierarchicalDesign/HDProject/regkeys | 24 + .../ise/__REGISTRY__/ProjectNavigator/regkeys | 3 + .../__REGISTRY__/ProjectNavigator11/regkeys | 6 + .../tmp/ise/__REGISTRY__/XSLTProcess/regkeys | 3 + .../__REGISTRY__/_ProjRepoInternal_/regkeys | 21 + .../tmp/ise/__REGISTRY__/bitgen/regkeys | 3 + .../tmp/ise/__REGISTRY__/bitinit/regkeys | 3 + .../tmp/ise/__REGISTRY__/common/regkeys | 12 + .../tmp/ise/__REGISTRY__/cpldfit/regkeys | 3 + .../tmp/ise/__REGISTRY__/dumpngdio/regkeys | 3 + .../tmp/ise/__REGISTRY__/fuse/regkeys | 3 + .../tmp/ise/__REGISTRY__/hprep6/regkeys | 3 + .../tmp/ise/__REGISTRY__/idem/regkeys | 3 + .../tmp/ise/__REGISTRY__/libgen/regkeys | 3 + .../tmp/ise/__REGISTRY__/map/regkeys | 3 + .../tmp/ise/__REGISTRY__/netgen/regkeys | 3 + .../tmp/ise/__REGISTRY__/ngc2edif/regkeys | 3 + .../tmp/ise/__REGISTRY__/ngcbuild/regkeys | 3 + .../tmp/ise/__REGISTRY__/ngdbuild/regkeys | 3 + .../tmp/ise/__REGISTRY__/par/regkeys | 3 + .../tmp/ise/__REGISTRY__/platgen/regkeys | 3 + .../tmp/ise/__REGISTRY__/runner/regkeys | 3 + .../tmp/ise/__REGISTRY__/simgen/regkeys | 3 + .../tmp/ise/__REGISTRY__/taengine/regkeys | 3 + .../tmp/ise/__REGISTRY__/trce/regkeys | 3 + .../tmp/ise/__REGISTRY__/tsim/regkeys | 3 + .../tmp/ise/__REGISTRY__/vhpcomp/regkeys | 3 + .../tmp/ise/__REGISTRY__/vlogcomp/regkeys | 3 + .../tmp/ise/__REGISTRY__/xpwr/regkeys | 3 + .../tmp/ise/__REGISTRY__/xreport/regkeys | 0 .../tmp/ise/__REGISTRY__/xst/regkeys | 3 + .../__xps/ise/system_xdb/tmp/ise/version | 10 + .../__xps/ise/xmsgprops.lst | 0 .../__xps/libgen.opt | 1 + .../__xps/platgen.opt | 2 + .../__xps/rtosdemo_compiler.opt | 20 + .../__xps/simgen.opt | 1 + .../__xps/system.filters | 121 + .../__xps/system.gui | 103 + .../__xps/xplorer.opt | 1 + .../__xps/xpsxflow.opt | 1 + .../blockdiagram/svg10.dtd | 1704 ++++++++++ .../blockdiagram/system.css | 446 +++ .../blockdiagram/system.svg | 1113 +++++++ .../data/system.ucf | 495 +++ .../etc/bitgen.ut | 14 + .../etc/download.cmd | 6 + .../etc/fast_runtime.opt | 83 + .../revup/system_mhs.11.1 | 474 +++ .../revup/system_mss.11.1 | 131 + .../revup/system_xmp.11.1 | 69 + .../system.bsb | 1 + .../system.log | 99 + .../system.make | 277 ++ .../system.mhs | 474 +++ .../system.mss | 131 + .../system.xmp | 69 + .../system_incl.make | 153 + 100 files changed, 19854 insertions(+) create mode 100644 Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h create mode 100644 Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld create mode 100644 Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c create mode 100644 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Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.log create mode 100644 Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.make create mode 100644 Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.mhs create mode 100644 Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.mss create mode 100644 Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.xmp create mode 100644 Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system_incl.make diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h new file mode 100644 index 000000000..7c18d73bc --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h @@ -0,0 +1,115 @@ +/* + FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License (version 2) as published + by the Free Software Foundation and modified by the FreeRTOS exception. + **NOTE** The exception to the GPL is included to allow you to distribute a + combined work that includes FreeRTOS.org without being obliged to provide + the source code for any proprietary components. Alternative commercial + license and support terms are also available upon request. See the + licensing section of http://www.FreeRTOS.org for full details. + + FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59 + Temple Place, Suite 330, Boston, MA 02111-1307 USA. + + + *************************************************************************** + * * + * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation * + * * + * This is a concise, step by step, 'hands on' guide that describes both * + * general multitasking concepts and FreeRTOS specifics. It presents and * + * explains numerous examples that are written using the FreeRTOS API. * + * Full source code for all the examples is provided in an accompanying * + * .zip file. * + * * + *************************************************************************** + + 1 tab == 4 spaces! + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 250 ) +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 200000000 ) /* Clock setup from start.asm in the demo application. */ +#define configTICK_RATE_HZ ( (portTickType) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 ) +#define configTOTAL_HEAP_SIZE ( (size_t) (80 * 1024) ) +#define configMAX_TASK_NAME_LEN ( 20 ) +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_TRACE_FACILITY 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_APPLICATION_TASK_TAG 1 +#define configUSE_FPU 1 + + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 4 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vResumeFromISR 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define configUSE_RECURSIVE_MUTEXES 1 + + +#if configUSE_FPU == 1 + /* Include the header that define the traceTASK_SWITCHED_IN() and + traceTASK_SWITCHED_OUT() macros to save and restore the floating + point registers for tasks that have requested this behaviour. */ + #include "FPU_Macros.h" +#endif + +#endif /* FREERTOS_CONFIG_H */ + + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld new file mode 100644 index 000000000..f4fc3bbc7 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld @@ -0,0 +1,226 @@ +/*******************************************************************/ +/* */ +/* This file is automatically generated by linker script generator.*/ +/* */ +/* Version: Xilinx EDK 11.1 EDK_L.29.1 */ +/* */ +/* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */ +/* */ +/* Description : PowerPC440 Linker Script */ +/* */ +/*******************************************************************/ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400; + +/* Define Memories in the system */ + +MEMORY +{ + DDR2_SDRAM_C_MEM_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x10000000 + SRAM_C_MEM0_BASEADDR : ORIGIN = 0xF8000000, LENGTH = 0x00100000 + xps_bram_if_cntlr_1 : ORIGIN = 0xFFFFE000, LENGTH = 0x00001F00 +} + +/* Specify the default entry point to the program */ + +ENTRY(_boot) +STARTUP(boot.o) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.vectors : { + __vectors_start = .; + *(.vectors) + __vectors_end = .; +} > SRAM_C_MEM0_BASEADDR + +.text : { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) +} > SRAM_C_MEM0_BASEADDR + +.init : { + KEEP (*(.init)) +} > SRAM_C_MEM0_BASEADDR + +.fini : { + KEEP (*(.fini)) +} > SRAM_C_MEM0_BASEADDR + +.rodata : { + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > SRAM_C_MEM0_BASEADDR + +.rodata1 : { + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > SRAM_C_MEM0_BASEADDR + +.sdata2 : { + __sdata2_start = .; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + __sdata2_end = .; +} > SRAM_C_MEM0_BASEADDR + +.sbss2 : { + __sbss2_start = .; + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + __sbss2_end = .; +} > SRAM_C_MEM0_BASEADDR + +.data : { + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __data_end = .; +} > SRAM_C_MEM0_BASEADDR + +.data1 : { + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > SRAM_C_MEM0_BASEADDR + +.got : { + *(.got) +} > SRAM_C_MEM0_BASEADDR + +.got1 : { + *(.got1) +} > SRAM_C_MEM0_BASEADDR + +.got2 : { + *(.got2) +} > SRAM_C_MEM0_BASEADDR + +.ctors : { + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > SRAM_C_MEM0_BASEADDR + +.dtors : { + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > SRAM_C_MEM0_BASEADDR + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > SRAM_C_MEM0_BASEADDR + +.eh_frame : { + *(.eh_frame) +} > SRAM_C_MEM0_BASEADDR + +.jcr : { + *(.jcr) +} > SRAM_C_MEM0_BASEADDR + +.gcc_except_table : { + *(.gcc_except_table) +} > SRAM_C_MEM0_BASEADDR + +.sdata : { + __sdata_start = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __sdata_end = .; +} > SRAM_C_MEM0_BASEADDR + +.sbss : { + __sbss_start = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + __sbss_end = .; +} > SRAM_C_MEM0_BASEADDR + +.tdata : { + __tdata_start = .; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __tdata_end = .; +} > SRAM_C_MEM0_BASEADDR + +.tbss : { + __tbss_start = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + __tbss_end = .; +} > SRAM_C_MEM0_BASEADDR + +.bss : { + __bss_start = .; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + __bss_end = .; +} > SRAM_C_MEM0_BASEADDR + +.boot0 0xFFFFFF00 : { + __boot0_start = .; + *(.boot0) + __boot0_end = .; +} + +.boot 0xFFFFFFFC : { + __boot_start = .; + *(.boot) + __boot_end = .; +} + +/* Generate Stack and Heap Sections */ + +.stack : { + _stack_end = .; + . += _STACK_SIZE; + . = ALIGN(16); + __stack = .; +} > SRAM_C_MEM0_BASEADDR + +.heap : { + . = ALIGN(16); + _heap_start = .; + . += _HEAP_SIZE; + . = ALIGN(16); + _heap_end = .; + _end = .; +} > SRAM_C_MEM0_BASEADDR + +} + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c new file mode 100644 index 000000000..79a650de6 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c @@ -0,0 +1,246 @@ +/* + FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License (version 2) as published + by the Free Software Foundation and modified by the FreeRTOS exception. + **NOTE** The exception to the GPL is included to allow you to distribute a + combined work that includes FreeRTOS.org without being obliged to provide + the source code for any proprietary components. Alternative commercial + license and support terms are also available upon request. See the + licensing section of http://www.FreeRTOS.org for full details. + + FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59 + Temple Place, Suite 330, Boston, MA 02111-1307 USA. + + + *************************************************************************** + * * + * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation * + * * + * This is a concise, step by step, 'hands on' guide that describes both * + * general multitasking concepts and FreeRTOS specifics. It presents and * + * explains numerous examples that are written using the FreeRTOS API. * + * Full source code for all the examples is provided in an accompanying * + * .zip file. * + * * + *************************************************************************** + + 1 tab == 4 spaces! + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * Tests the floating point context save and restore mechanism. + * + * Two tasks are created - each of which is allocated a buffer of + * portNO_FLOP_REGISTERS_TO_SAVE 32bit variables into which the flop context + * of the task is saved when the task is switched out, and from which the + * flop context of the task is restored when the task is switch in. Prior to + * the tasks being created each position in the two buffers is filled with a + * unique value - this way the flop context of each task is different. + * + * The two test tasks never block so are always in either the Running or + * Ready state. They execute at the lowest priority so will get pre-empted + * regularly, although the yield frequently so will not get much execution + * time. The lack of execution time is not a problem as its only the + * switching in and out that is being tested. + * + * Whenever a task is moved from the Ready to the Running state its flop + * context will be loaded from the buffer, but while the task is in the + * Running state the buffer is not used and can contain any value - in this + * case and for test purposes the task itself clears the buffer to zero. + * The next time the task is moved out of the Running state into the + * Ready state the flop context will once more get saved to the buffer - + * overwriting the zeros. + * + * Therefore whenever the task is not in the Running state its buffer contains + * the most recent values of its floating point registers - the zeroing out + * of the buffer while the task was executing being used to ensure the values + * the buffer contains are not stale. + * + * When neither test task is in the Running state the buffers should contain + * the unique values allocated before the tasks were created. If so then + * the floating point context has been maintained. This check is performed + * by the 'check' task (defined in main.c) by calling + * xAreFlopRegisterTestsStillRunning(). + * + * The test tasks also increment a value each time they execute. + * xAreFlopRegisterTestsStillRunning() also checks that this value has changed + * since it last ran to ensure the test tasks are still getting processing time. + */ + +/* Standard includes files. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/*-----------------------------------------------------------*/ + +#define flopNUMBER_OF_TASKS 2 +#define flopSTART_VALUE ( 0x1 ) + +/*-----------------------------------------------------------*/ + +/* The two test tasks as described at the top of this file. */ +static void vFlopTest1( void *pvParameters ); +static void vFlopTest2( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Buffers into which the flop registers will be saved. There is a buffer for +both tasks. */ +static volatile unsigned portLONG ulFlopRegisters[ flopNUMBER_OF_TASKS ][ portNO_FLOP_REGISTERS_TO_SAVE ]; + +/* Variables that are incremented by the tasks to indicate that they are still +running. */ +static volatile unsigned portLONG ulFlop1CycleCount = 0, ulFlop2CycleCount = 0; + +/*-----------------------------------------------------------*/ + +void vStartFlopRegTests( void ) +{ +xTaskHandle xTaskJustCreated; +unsigned portBASE_TYPE x, y, z = flopSTART_VALUE; + + /* Fill the arrays into which the flop registers are to be saved with + known values. These are the values that will be written to the flop + registers when the tasks start, and as the tasks do not perform any + flop operations the values should never change. Each position in the + buffer contains a different value so the flop context of each task + will be different. */ + for( x = 0; x < flopNUMBER_OF_TASKS; x++ ) + { + for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1); y++ ) + { + ulFlopRegisters[ x ][ y ] = z; + z++; + } + } + + + /* Create the first task. */ + xTaskCreate( vFlopTest1, ( signed portCHAR * ) "flop1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTaskJustCreated ); + + /* The task tag value is a value that can be associated with a task, but + is not used by the scheduler itself. Its use is down to the application so + it makes a convenient place in this case to store the pointer to the buffer + into which the flop context of the task will be stored. The first created + task uses ulFlopRegisters[ 0 ], the second ulFlopRegisters[ 1 ]. */ + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 0 ][ 0 ] ) ); + + /* Do the same for the second task. */ + xTaskCreate( vFlopTest2, ( signed portCHAR * ) "flop2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 1 ][ 0 ] ) ); +} +/*-----------------------------------------------------------*/ + +static void vFlopTest1( void *pvParameters ) +{ + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + for( ;; ) + { + /* The values from the buffer should have now been written to the flop + registers. Clear the buffer to ensure the same values then get written + back the next time the task runs. Being preempted during this memset + could cause the test to fail, hence the critical section. */ + portENTER_CRITICAL(); + memset( ( void * ) ulFlopRegisters[ 0 ], 0x00, ( portNO_FLOP_REGISTERS_TO_SAVE * sizeof( unsigned portBASE_TYPE ) ) ); + portEXIT_CRITICAL(); + + /* We don't have to do anything other than indicate that we are + still running. */ + ulFlop1CycleCount++; + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +static void vFlopTest2( void *pvParameters ) +{ + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + for( ;; ) + { + /* The values from the buffer should have now been written to the flop + registers. Clear the buffer to ensure the same values then get written + back the next time the task runs. */ + portENTER_CRITICAL(); + memset( ( void * ) ulFlopRegisters[ 1 ], 0x00, ( portNO_FLOP_REGISTERS_TO_SAVE * sizeof( unsigned portBASE_TYPE ) ) ); + portEXIT_CRITICAL(); + + /* We don't have to do anything other than indicate that we are + still running. */ + ulFlop2CycleCount++; + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreFlopRegisterTestsStillRunning( void ) +{ +portBASE_TYPE xReturn = pdPASS; +unsigned portBASE_TYPE x, y, z = flopSTART_VALUE; +static unsigned portLONG ulLastFlop1CycleCount = 0, ulLastFlop2CycleCount = 0; + + /* Called from the 'check' task. + + The flop tasks cannot be currently running, check their saved registers + are as expected. The tests tasks do not perform any flop operations so + their registers should be as per their initial setting. */ + for( x = 0; x < flopNUMBER_OF_TASKS; x++ ) + { + for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1 ); y++ ) + { + if( ulFlopRegisters[ x ][ y ] != z ) + { + xReturn = pdFAIL; + break; + } + + z++; + } + } + + /* Check both tasks have actually been swapped in and out since this function + last executed. */ + if( ulFlop1CycleCount == ulLastFlop1CycleCount ) + { + xReturn = pdFAIL; + } + + if( ulFlop2CycleCount == ulLastFlop2CycleCount ) + { + xReturn = pdFAIL; + } + + ulLastFlop1CycleCount = ulFlop1CycleCount; + ulLastFlop2CycleCount = ulFlop2CycleCount; + + return xReturn; +} + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h new file mode 100644 index 000000000..0bddeb218 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h @@ -0,0 +1,58 @@ +/* + FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License (version 2) as published + by the Free Software Foundation and modified by the FreeRTOS exception. + **NOTE** The exception to the GPL is included to allow you to distribute a + combined work that includes FreeRTOS.org without being obliged to provide + the source code for any proprietary components. Alternative commercial + license and support terms are also available upon request. See the + licensing section of http://www.FreeRTOS.org for full details. + + FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59 + Temple Place, Suite 330, Boston, MA 02111-1307 USA. + + + *************************************************************************** + * * + * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation * + * * + * This is a concise, step by step, 'hands on' guide that describes both * + * general multitasking concepts and FreeRTOS specifics. It presents and * + * explains numerous examples that are written using the FreeRTOS API. * + * Full source code for all the examples is provided in an accompanying * + * .zip file. * + * * + *************************************************************************** + + 1 tab == 4 spaces! + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef FLOP_REG_TEST_H +#define FLOP_REG_TEST_H + +void vStartFlopRegTests( void ); +portBASE_TYPE xAreFlopRegisterTestsStillRunning( void ); + +#endif diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c new file mode 100644 index 000000000..7e291b00f --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c @@ -0,0 +1,402 @@ +/* + FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License (version 2) as published + by the Free Software Foundation and modified by the FreeRTOS exception. + **NOTE** The exception to the GPL is included to allow you to distribute a + combined work that includes FreeRTOS.org without being obliged to provide + the source code for any proprietary components. Alternative commercial + license and support terms are also available upon request. See the + licensing section of http://www.FreeRTOS.org for full details. + + FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59 + Temple Place, Suite 330, Boston, MA 02111-1307 USA. + + + *************************************************************************** + * * + * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation * + * * + * This is a concise, step by step, 'hands on' guide that describes both * + * general multitasking concepts and FreeRTOS specifics. It presents and * + * explains numerous examples that are written using the FreeRTOS API. * + * Full source code for all the examples is provided in an accompanying * + * .zip file. * + * * + *************************************************************************** + + 1 tab == 4 spaces! + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * Creates eight tasks, each of which loops continuously performing a + * floating point calculation. + * + * All the tasks run at the idle priority and never block or yield. This causes + * all eight tasks to time slice with the idle task. Running at the idle priority + * means that these tasks will get pre-empted any time another task is ready to run + * or a time slice occurs. More often than not the pre-emption will occur mid + * calculation, creating a good test of the schedulers context switch mechanism - a + * calculation producing an unexpected result could be a symptom of a corruption in + * the context of a task. + * + * This file demonstrates the use of the task tag and traceTASK_SWITCHED_IN and + * traceTASK_SWITCHED_OUT macros to save and restore the floating point context. + */ + +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "flop.h" + +/* Misc. definitions. */ +#define mathSTACK_SIZE configMINIMAL_STACK_SIZE +#define mathNUMBER_OF_TASKS ( 8 ) + +/* Four tasks, each of which performs a different floating point calculation. +Each of the four is created twice. */ +static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a +task gets a calculation wrong it will stop incrementing its check variable. */ +static volatile unsigned portSHORT usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; + +/* Buffers into which the flop registers will be saved. There is a buffer for +each task created within this file. Zeroing out this array is the normal and +safe option as this will cause the task to start with all zeros in its flop +context. */ +static unsigned portLONG ulFlopRegisters[ mathNUMBER_OF_TASKS ][ portNO_FLOP_REGISTERS_TO_SAVE ]; + +/*-----------------------------------------------------------*/ + +void vStartMathTasks( unsigned portBASE_TYPE uxPriority ) +{ +xTaskHandle xTaskJustCreated; +portBASE_TYPE x, y; + + /* Place known values into the buffers into which the flop registers are + to be saved. This is for debug purposes only, it is not normally + required. The last position in each array is left at zero as the status + register will be loaded from there. + + It is intended that these values can be viewed being loaded into the + flop registers when a task is started - however the Insight debugger + does not seem to want to show the flop register values. */ + for( x = 0; x < mathNUMBER_OF_TASKS; x++ ) + { + for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1 ); y++ ) + { + ulFlopRegisters[ x ][ y ] = ( x + 1 ); + } + } + + /* Create the first task - passing it the address of the check variable + that it is going to increment. This check variable is used as an + indication that the task is still running. */ + xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, &xTaskJustCreated ); + + /* The task tag value is a value that can be associated with a task, but + is not used by the scheduler itself. Its use is down to the application so + it makes a convenient place in this case to store the pointer to the buffer + into which the flop context of the task will be stored. The first created + task uses ulFlopRegisters[ 0 ], the second ulFlopRegisters[ 1 ], etc. */ + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 0 ][ 0 ] ) ); + + /* Create another 7 tasks, allocating a buffer for each. */ + xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 1 ][ 0 ] ) ); + + xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 2 ][ 0 ] ) ); + + xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 3 ][ 0 ] ) ); + + xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 4 ][ 0 ] ) ); + + xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 5 ][ 0 ] ) ); + + xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 6 ][ 0 ] ) ); + + xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 7 ][ 0 ] ) ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask1, pvParameters ) +{ +volatile portFLOAT ff1, ff2, ff3, ff4; +volatile unsigned portSHORT *pusTaskCheckVariable; +volatile portFLOAT fAnswer; +portSHORT sError = pdFALSE; + + ff1 = 123.4567F; + ff2 = 2345.6789F; + ff3 = -918.222F; + + fAnswer = ( ff1 + ff2 ) * ff3; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for(;;) + { + ff1 = 123.4567F; + ff2 = 2345.6789F; + ff3 = -918.222F; + + ff4 = ( ff1 + ff2 ) * ff3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( ff4 - fAnswer ) > 0.001F ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask2, pvParameters ) +{ +volatile portFLOAT ff1, ff2, ff3, ff4; +volatile unsigned portSHORT *pusTaskCheckVariable; +volatile portFLOAT fAnswer; +portSHORT sError = pdFALSE; + + ff1 = -389.38F; + ff2 = 32498.2F; + ff3 = -2.0001F; + + fAnswer = ( ff1 / ff2 ) * ff3; + + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + ff1 = -389.38F; + ff2 = 32498.2F; + ff3 = -2.0001F; + + ff4 = ( ff1 / ff2 ) * ff3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( ff4 - fAnswer ) > 0.001F ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know + this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask3, pvParameters ) +{ +volatile portFLOAT *pfArray, fTotal1, fTotal2, fDifference; +volatile unsigned portSHORT *pusTaskCheckVariable; +const size_t xArraySize = 10; +size_t xPosition; +portSHORT sError = pdFALSE; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + pfArray = ( portFLOAT * ) pvPortMalloc( xArraySize * sizeof( portFLOAT ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + fTotal1 = 0.0F; + fTotal2 = 0.0F; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pfArray[ xPosition ] = ( portFLOAT ) xPosition + 5.5F; + fTotal1 += ( portFLOAT ) xPosition + 5.5F; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + fTotal2 += pfArray[ xPosition ]; + } + + fDifference = fTotal1 - fTotal2; + if( fabs( fDifference ) > 0.001F ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask4, pvParameters ) +{ +volatile portFLOAT *pfArray, fTotal1, fTotal2, fDifference; +volatile unsigned portSHORT *pusTaskCheckVariable; +const size_t xArraySize = 10; +size_t xPosition; +portSHORT sError = pdFALSE; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + pfArray = ( portFLOAT * ) pvPortMalloc( xArraySize * sizeof( portFLOAT ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + fTotal1 = 0.0F; + fTotal2 = 0.0F; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pfArray[ xPosition ] = ( portFLOAT ) xPosition * 12.123F; + fTotal1 += ( portFLOAT ) xPosition * 12.123F; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + fTotal2 += pfArray[ xPosition ]; + } + + fDifference = fTotal1 - fTotal2; + if( fabs( fDifference ) > 0.001F ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreMathsTaskStillRunning( void ) +{ +/* Keep a history of the check variables so we know if they have been incremented +since the last call. */ +static unsigned portSHORT usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; +portBASE_TYPE xReturn = pdTRUE, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + are still incrementing. */ + for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; + } + + return xReturn; +} + + + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c new file mode 100644 index 000000000..b53211980 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c @@ -0,0 +1,701 @@ +/* + FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License (version 2) as published + by the Free Software Foundation and modified by the FreeRTOS exception. + **NOTE** The exception to the GPL is included to allow you to distribute a + combined work that includes FreeRTOS.org without being obliged to provide + the source code for any proprietary components. Alternative commercial + license and support terms are also available upon request. See the + licensing section of http://www.FreeRTOS.org for full details. + + FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59 + Temple Place, Suite 330, Boston, MA 02111-1307 USA. + + + *************************************************************************** + * * + * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation * + * * + * This is a concise, step by step, 'hands on' guide that describes both * + * general multitasking concepts and FreeRTOS specifics. It presents and * + * explains numerous examples that are written using the FreeRTOS API. * + * Full source code for all the examples is provided in an accompanying * + * .zip file. * + * * + *************************************************************************** + + 1 tab == 4 spaces! + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * In addition to the standard demo tasks, the follow demo specific tasks are + * create: + * + * The "Check" task. This only executes every three seconds but has the highest + * priority so is guaranteed to get processor time. Its main function is to + * check that all the other tasks are still operational. Most tasks maintain + * a unique count that is incremented each time the task successfully completes + * its function. Should any error occur within such a task the count is + * permanently halted. The check task inspects the count of each task to ensure + * it has changed since the last time the check task executed. If all the count + * variables have changed all the tasks are still executing error free, and the + * check task toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + * The "Register Check" tasks. These tasks fill the CPU registers with known + * values, then check that each register still contains the expected value, the + * discovery of an unexpected value being indicative of an error in the RTOS + * context switch mechanism. The register check tasks operate at low priority + * so are switched in and out frequently. + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Xilinx library includes. */ +#include "xcache_l.h" +#include "xintc.h" + +/* Demo application includes. */ +#include "flash.h" +#include "integer.h" +#include "comtest2.h" +#include "semtest.h" +#include "BlockQ.h" +#include "dynamic.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "blocktim.h" +#include "death.h" +#include "partest.h" +#include "countsem.h" +#include "recmutex.h" +#include "flop.h" +#include "flop-reg-test.h" + +/* Priorities assigned to the demo tasks. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainFLOP_PRIORITY ( tskIDLE_PRIORITY ) + +/* The first LED used by the COM test and check tasks respectively. */ +#define mainCOM_TEST_LED ( 4 ) +#define mainCHECK_TEST_LED ( 3 ) + +/* The baud rate used by the comtest tasks is set by the hardware, so the +baud rate parameters passed into the comtest initialisation has no effect. */ +#define mainBAUD_SET_IN_HARDWARE ( 0 ) + +/* Delay periods used by the check task. If no errors have been found then +the check LED will toggle every mainNO_ERROR_CHECK_DELAY milliseconds. If an +error has been found at any time then the toggle rate will increase to +mainERROR_CHECK_DELAY milliseconds. */ +#define mainNO_ERROR_CHECK_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) + + +/* + * The tasks defined within this file - described within the comments at the + * head of this page. + */ +static void prvRegTestTask1( void *pvParameters ); +static void prvRegTestTask2( void *pvParameters ); +static void prvErrorChecks( void *pvParameters ); + +/* + * Called by the 'check' task to inspect all the standard demo tasks within + * the system, as described within the comments at the head of this page. + */ +static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ); + +/* + * Perform any hardware initialisation required by the demo application. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* xRegTestStatus will get set to pdFAIL by the regtest tasks if they +discover an unexpected value. */ +static volatile unsigned portBASE_TYPE xRegTestStatus = pdPASS; + +/* Counters used to ensure the regtest tasks are still running. */ +static volatile unsigned portLONG ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + + /* Must be called prior to installing any interrupt handlers! */ + vPortSetupInterruptController(); + + /* In this case prvSetupHardware() just enables the caches and and + configures the IO ports for the LED outputs. */ + prvSetupHardware(); + + /* Start the standard demo application tasks. Note that the baud rate used + by the comtest tasks is set by the hardware, so the baud rate parameter + passed has no effect. */ + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_SET_IN_HARDWARE, mainCOM_TEST_LED ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks ( mainQUEUE_BLOCK_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY ); + vStartQueuePeekTasks(); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartRecursiveMutexTasks(); + + #if ( configUSE_FPU == 1 ) + vStartMathTasks( mainFLOP_PRIORITY ); + vStartFlopRegTests(); + #endif + + /* Create the tasks defined within this file. */ + xTaskCreate( prvRegTestTask1, ( signed portCHAR * ) "Regtest1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTestTask2, ( signed portCHAR * ) "Regtest2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The suicide tasks must be started last as they record the number of other + tasks that exist within the system. The value is then used to ensure at run + time the number of tasks that exists is within expected bounds. */ + vCreateSuicidalTasks( mainDEATH_PRIORITY ); + + /* Now start the scheduler. Following this call the created tasks should + be executing. */ + vTaskStartScheduler(); + + /* vTaskStartScheduler() will only return if an error occurs while the + idle task is being created. */ + for( ;; ); + + return 0; +} +/*-----------------------------------------------------------*/ + +static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ) +{ +portBASE_TYPE lReturn = pdPASS; +static unsigned portLONG ulLastRegTest1Counter= 0UL, ulLastRegTest2Counter = 0UL; + + /* The demo tasks maintain a count that increments every cycle of the task + provided that the task has never encountered an error. This function + checks the counts maintained by the tasks to ensure they are still being + incremented. A count remaining at the same value between calls therefore + indicates that an error has been detected. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + #if ( configUSE_FPU == 1 ) + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreFlopRegisterTestsStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + #endif + + /* Have the register test tasks found any errors? */ + if( xRegTestStatus != pdPASS ) + { + lReturn = pdFAIL; + } + + /* Are the register test tasks still looping? */ + if( ulLastRegTest1Counter == ulRegTest1Counter ) + { + lReturn = pdFAIL; + } + else + { + ulLastRegTest1Counter = ulRegTest1Counter; + } + + if( ulLastRegTest2Counter == ulRegTest2Counter ) + { + lReturn = pdFAIL; + } + else + { + ulLastRegTest2Counter = ulRegTest2Counter; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + +static void prvErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY, xLastExecutionTime; +volatile unsigned portBASE_TYPE uxFreeStack; + + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + /* This call is just to demonstrate the use of the function - nothing is + done with the value. You would expect the stack high water mark to be + lower (the function to return a larger value) here at function entry than + later following calls to other functions. */ + uxFreeStack = uxTaskGetStackHighWaterMark( NULL ); + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Again just for demo purposes - uxFreeStack should have a lower value + here than following the call to uxTaskGetStackHighWaterMark() on the + task entry. */ + uxFreeStack = uxTaskGetStackHighWaterMark( NULL ); + + /* Wait until it is time to check again. The time we wait here depends + on whether an error has been detected or not. When an error is + detected the time is shortened resulting in a faster LED flash rate. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* See if the other tasks are all ok. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error occurred in one of the tasks so shorten the delay + period - which has the effect of increasing the frequency of the + LED toggle. */ + xDelayPeriod = mainERROR_CHECK_DELAY; + } + + /* Flash! */ + vParTestToggleLED( mainCHECK_TEST_LED ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + XCache_EnableICache( 0x80000000 ); + XCache_EnableDCache( 0x80000000 ); + + /* Setup the IO port for use with the LED outputs. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +void prvRegTest1Pass( void ) +{ + /* Called from the inline assembler - this cannot be static + otherwise it can get optimised away. */ + ulRegTest1Counter++; +} +/*-----------------------------------------------------------*/ + +void prvRegTest2Pass( void ) +{ + /* Called from the inline assembler - this cannot be static + otherwise it can get optimised away. */ + ulRegTest2Counter++; +} +/*-----------------------------------------------------------*/ + +void prvRegTestFail( void ) +{ + /* Called from the inline assembler - this cannot be static + otherwise it can get optimised away. */ + xRegTestStatus = pdFAIL; +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTask1( void *pvParameters ) +{ + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + /* The first register test task as described at the top of this file. The + values used in the registers are different to those use in the second + register test task. Also, unlike the second register test task, this task + yields between setting the register values and subsequently checking the + register values. */ + asm volatile + ( + "RegTest1Start: \n\t" \ + " \n\t" \ + " li 0, 301 \n\t" \ + " mtspr 256, 0 #USPRG0 \n\t" \ + " li 0, 501 \n\t" \ + " mtspr 8, 0 #LR \n\t" \ + " li 0, 4 \n\t" \ + " mtspr 1, 0 #XER \n\t" \ + " \n\t" \ + " li 0, 1 \n\t" \ + " li 2, 2 \n\t" \ + " li 3, 3 \n\t" \ + " li 4, 4 \n\t" \ + " li 5, 5 \n\t" \ + " li 6, 6 \n\t" \ + " li 7, 7 \n\t" \ + " li 8, 8 \n\t" \ + " li 9, 9 \n\t" \ + " li 10, 10 \n\t" \ + " li 11, 11 \n\t" \ + " li 12, 12 \n\t" \ + " li 13, 13 \n\t" \ + " li 14, 14 \n\t" \ + " li 15, 15 \n\t" \ + " li 16, 16 \n\t" \ + " li 17, 17 \n\t" \ + " li 18, 18 \n\t" \ + " li 19, 19 \n\t" \ + " li 20, 20 \n\t" \ + " li 21, 21 \n\t" \ + " li 22, 22 \n\t" \ + " li 23, 23 \n\t" \ + " li 24, 24 \n\t" \ + " li 25, 25 \n\t" \ + " li 26, 26 \n\t" \ + " li 27, 27 \n\t" \ + " li 28, 28 \n\t" \ + " li 29, 29 \n\t" \ + " li 30, 30 \n\t" \ + " li 31, 31 \n\t" \ + " \n\t" \ + " sc \n\t" \ + " nop \n\t" \ + " \n\t" \ + " cmpwi 0, 1 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 2, 2 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 3, 3 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 4, 4 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 5, 5 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 6, 6 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 7, 7 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 8, 8 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 9, 9 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 10, 10 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 11, 11 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 12, 12 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 13, 13 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 14, 14 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 15, 15 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 16, 16 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 17, 17 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 18, 18 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 19, 19 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 20, 20 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 21, 21 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 22, 22 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 23, 23 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 24, 24 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 25, 25 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 26, 26 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 27, 27 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 28, 28 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 29, 29 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 30, 30 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 31, 31 \n\t" \ + " bne RegTest1Fail \n\t" \ + " \n\t" \ + " mfspr 0, 256 #USPRG0 \n\t" \ + " cmpwi 0, 301 \n\t" \ + " bne RegTest1Fail \n\t" \ + " mfspr 0, 8 #LR \n\t" \ + " cmpwi 0, 501 \n\t" \ + " bne RegTest1Fail \n\t" \ + " mfspr 0, 1 #XER \n\t" \ + " cmpwi 0, 4 \n\t" \ + " bne RegTest1Fail \n\t" \ + " \n\t" \ + " bl prvRegTest1Pass \n\t" \ + " b RegTest1Start \n\t" \ + " \n\t" \ + "RegTest1Fail: \n\t" \ + " \n\t" \ + " \n\t" \ + " bl prvRegTestFail \n\t" \ + " b RegTest1Start \n\t" \ + ); +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTask2( void *pvParameters ) +{ + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + /* The second register test task as described at the top of this file. + Note that this task fills the registers with different values to the + first register test task. */ + asm volatile + ( + "RegTest2Start: \n\t" \ + " \n\t" \ + " li 0, 300 \n\t" \ + " mtspr 256, 0 #USPRG0 \n\t" \ + " li 0, 500 \n\t" \ + " mtspr 8, 0 #LR \n\t" \ + " li 0, 4 \n\t" \ + " mtspr 1, 0 #XER \n\t" \ + " \n\t" \ + " li 0, 11 \n\t" \ + " li 2, 12 \n\t" \ + " li 3, 13 \n\t" \ + " li 4, 14 \n\t" \ + " li 5, 15 \n\t" \ + " li 6, 16 \n\t" \ + " li 7, 17 \n\t" \ + " li 8, 18 \n\t" \ + " li 9, 19 \n\t" \ + " li 10, 110 \n\t" \ + " li 11, 111 \n\t" \ + " li 12, 112 \n\t" \ + " li 13, 113 \n\t" \ + " li 14, 114 \n\t" \ + " li 15, 115 \n\t" \ + " li 16, 116 \n\t" \ + " li 17, 117 \n\t" \ + " li 18, 118 \n\t" \ + " li 19, 119 \n\t" \ + " li 20, 120 \n\t" \ + " li 21, 121 \n\t" \ + " li 22, 122 \n\t" \ + " li 23, 123 \n\t" \ + " li 24, 124 \n\t" \ + " li 25, 125 \n\t" \ + " li 26, 126 \n\t" \ + " li 27, 127 \n\t" \ + " li 28, 128 \n\t" \ + " li 29, 129 \n\t" \ + " li 30, 130 \n\t" \ + " li 31, 131 \n\t" \ + " \n\t" \ + " cmpwi 0, 11 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 2, 12 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 3, 13 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 4, 14 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 5, 15 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 6, 16 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 7, 17 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 8, 18 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 9, 19 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 10, 110 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 11, 111 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 12, 112 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 13, 113 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 14, 114 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 15, 115 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 16, 116 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 17, 117 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 18, 118 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 19, 119 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 20, 120 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 21, 121 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 22, 122 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 23, 123 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 24, 124 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 25, 125 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 26, 126 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 27, 127 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 28, 128 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 29, 129 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 30, 130 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 31, 131 \n\t" \ + " bne RegTest2Fail \n\t" \ + " \n\t" \ + " mfspr 0, 256 #USPRG0 \n\t" \ + " cmpwi 0, 300 \n\t" \ + " bne RegTest2Fail \n\t" \ + " mfspr 0, 8 #LR \n\t" \ + " cmpwi 0, 500 \n\t" \ + " bne RegTest2Fail \n\t" \ + " mfspr 0, 1 #XER \n\t" \ + " cmpwi 0, 4 \n\t" \ + " bne RegTest2Fail \n\t" \ + " \n\t" \ + " bl prvRegTest2Pass \n\t" \ + " b RegTest2Start \n\t" \ + " \n\t" \ + "RegTest2Fail: \n\t" \ + " \n\t" \ + " \n\t" \ + " bl prvRegTestFail \n\t" \ + " b RegTest2Start \n\t" \ + ); +} +/*-----------------------------------------------------------*/ + +/* This hook function will get called if there is a suspected stack overflow. +An overflow can cause the task name to be corrupted, in which case the task +handle needs to be used to determine the offending task. */ +void vApplicationStackOverflowHook( xTaskHandle xTask, signed portCHAR *pcTaskName ); +void vApplicationStackOverflowHook( xTaskHandle xTask, signed portCHAR *pcTaskName ) +{ +/* To prevent the optimiser removing the variables. */ +volatile xTaskHandle xTaskIn = xTask; +volatile signed portCHAR *pcTaskNameIn = pcTaskName; + + /* Remove compiler warnings. */ + ( void ) xTaskIn; + ( void ) pcTaskNameIn; + + /* The following three calls are simply to stop compiler warnings about the + functions not being used - they are called from the inline assembly. */ + prvRegTest1Pass(); + prvRegTest2Pass(); + prvRegTestFail(); + + for( ;; ); +} + + + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c new file mode 100644 index 000000000..72eee5890 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c @@ -0,0 +1,170 @@ +/* + FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License (version 2) as published + by the Free Software Foundation and modified by the FreeRTOS exception. + **NOTE** The exception to the GPL is included to allow you to distribute a + combined work that includes FreeRTOS.org without being obliged to provide + the source code for any proprietary components. Alternative commercial + license and support terms are also available upon request. See the + licensing section of http://www.FreeRTOS.org for full details. + + FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59 + Temple Place, Suite 330, Boston, MA 02111-1307 USA. + + + *************************************************************************** + * * + * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation * + * * + * This is a concise, step by step, 'hands on' guide that describes both * + * general multitasking concepts and FreeRTOS specifics. It presents and * + * explains numerous examples that are written using the FreeRTOS API. * + * Full source code for all the examples is provided in an accompanying * + * .zip file. * + * * + *************************************************************************** + + 1 tab == 4 spaces! + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +/* Library includes. */ +#include "xparameters.h" +#include "xgpio_l.h" + +/* Misc hardware specific definitions. */ +#define partstALL_AS_OUTPUT 0x00 +#define partstCHANNEL_1 0x01 +#define partstMAX_8BIT_LED 0x07 + +/* The outputs are split into two IO sections, these variables maintain the +current value of either section. */ +static unsigned portBASE_TYPE uxCurrentOutput8Bit, uxCurrentOutput5Bit; + +/*-----------------------------------------------------------*/ +/* + * Setup the IO for the LED outputs. + */ +void vParTestInitialise( void ) +{ + /* Set both sets of LED's on the demo board to outputs. */ + XGpio_mSetDataDirection( XPAR_LEDS_8BIT_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); + XGpio_mSetDataDirection( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); + + /* Start with all outputs off. */ + uxCurrentOutput8Bit = 0; + XGpio_mSetDataReg( XPAR_LEDS_8BIT_BASEADDR, partstCHANNEL_1, 0x00 ); + uxCurrentOutput5Bit = 0; + XGpio_mSetDataReg( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, 0x00 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; + + portENTER_CRITICAL(); + { + /* Which IO section does the LED being set/cleared belong to? The + 4 bit or 5 bit outputs? */ + if( uxLED <= partstMAX_8BIT_LED ) + { + uxBaseAddress = XPAR_LEDS_8BIT_BASEADDR; + puxCurrentValue = &uxCurrentOutput5Bit; + } + else + { + uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; + puxCurrentValue = &uxCurrentOutput8Bit; + uxLED -= partstMAX_8BIT_LED; + } + + /* Setup the bit mask accordingly. */ + uxLED = 0x01 << uxLED; + + /* Maintain the current output value. */ + if( xValue ) + { + *puxCurrentValue |= uxLED; + } + else + { + *puxCurrentValue &= ~uxLED; + } + + /* Write the value to the port. */ + XGpio_mSetDataReg( uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; + + portENTER_CRITICAL(); + { + /* Which IO section does the LED being toggled belong to? The + 4 bit or 5 bit outputs? */ + if( uxLED <= partstMAX_8BIT_LED ) + { + + uxBaseAddress = XPAR_LEDS_8BIT_BASEADDR; + puxCurrentValue = &uxCurrentOutput5Bit; + } + else + { + uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; + puxCurrentValue = &uxCurrentOutput8Bit; + uxLED -= partstMAX_8BIT_LED; + } + + /* Setup the bit mask accordingly. */ + uxLED = 0x01 << uxLED; + + /* Maintain the current output value. */ + if( *puxCurrentValue & uxLED ) + { + *puxCurrentValue &= ~uxLED; + } + else + { + *puxCurrentValue |= uxLED; + } + + /* Write the value to the port. */ + XGpio_mSetDataReg(uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); + } + portEXIT_CRITICAL(); +} + + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c new file mode 100644 index 000000000..d5f005af3 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c @@ -0,0 +1,235 @@ +/* + FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License (version 2) as published + by the Free Software Foundation and modified by the FreeRTOS exception. + **NOTE** The exception to the GPL is included to allow you to distribute a + combined work that includes FreeRTOS.org without being obliged to provide + the source code for any proprietary components. Alternative commercial + license and support terms are also available upon request. See the + licensing section of http://www.FreeRTOS.org for full details. + + FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59 + Temple Place, Suite 330, Boston, MA 02111-1307 USA. + + + *************************************************************************** + * * + * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation * + * * + * This is a concise, step by step, 'hands on' guide that describes both * + * general multitasking concepts and FreeRTOS specifics. It presents and * + * explains numerous examples that are written using the FreeRTOS API. * + * Full source code for all the examples is provided in an accompanying * + * .zip file. * + * * + *************************************************************************** + + 1 tab == 4 spaces! + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/* Library includes. */ +#include "xparameters.h" +#include "xuartlite.h" +#include "xuartlite_l.h" + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/* Structure that maintains information on the UART being used. */ +static XUartLite xUART; + +/* + * Sample UART interrupt handler. Note this is used to demonstrate the kernel + * features and test the port - it is not intended to represent an efficient + * implementation. + */ +static void vSerialISR( XUartLite *pxUART ); + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ + /* NOTE: The baud rate used by this driver is determined by the hardware + parameterization of the UART Lite peripheral, and the baud value passed to + this function has no effect. */ + ( void ) ulWantedBaud; + + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Only initialise the UART if the queues were created correctly. */ + if( ( xRxedChars != NULL ) && ( xCharsForTx != NULL ) ) + { + + XUartLite_Initialize( &xUART, XPAR_RS232_UART_1_DEVICE_ID ); + XUartLite_ResetFifos( &xUART ); + XUartLite_DisableInterrupt( &xUART ); + + if( xPortInstallInterruptHandler( XPAR_XPS_INTC_0_RS232_UART_1_INTERRUPT_INTR, ( XInterruptHandler )vSerialISR, (void *)&xUART ) == pdPASS ) + { + /* xPortInstallInterruptHandler() could fail if + vPortSetupInterruptController() has not been called prior to this + function. */ + XUartLite_EnableInterrupt( &xUART ); + } + } + + /* There is only one port so the handle is not used. */ + return ( xComPortHandle ) 0; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports one UART. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +portBASE_TYPE xReturn = pdTRUE; + + /* Just to remove compiler warning. */ + ( void ) pxPort; + + portENTER_CRITICAL(); + { + /* If the UART FIFO is full we can block posting the new data on the + Tx queue. */ + if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_1_BASEADDR ) ) + { + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + xReturn = pdFAIL; + } + } + /* Otherwise, if there is data already in the queue we should add the + new data to the back of the queue to ensure the sequencing is + maintained. */ + else if( uxQueueMessagesWaiting( xCharsForTx ) ) + { + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + xReturn = pdFAIL; + } + } + /* If the UART FIFO is not full and there is no data already in the + queue we can write directly to the FIFO without disrupting the + sequence. */ + else + { + XIo_Out32( XPAR_RS232_UART_1_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar ); + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + +static void vSerialISR( XUartLite *pxUART ) +{ +unsigned portLONG ulISRStatus; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE, lDidSomething; +portCHAR cChar; + + /* Just to remove compiler warning. */ + ( void ) pxUART; + + do + { + lDidSomething = pdFALSE; + + ulISRStatus = XIo_In32( XPAR_RS232_UART_1_BASEADDR + XUL_STATUS_REG_OFFSET ); + + if( ( ulISRStatus & XUL_SR_RX_FIFO_VALID_DATA ) != 0 ) + { + /* A character is available - place it in the queue of received + characters. This might wake a task that was blocked waiting for + data. */ + cChar = ( portCHAR ) XIo_In32( XPAR_RS232_UART_1_BASEADDR + XUL_RX_FIFO_OFFSET ); + xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken ); + lDidSomething = pdTRUE; + } + + if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 ) + { + /* There is space in the FIFO - if there are any characters queue for + transmission they can be sent to the UART now. This might unblock a + task that was waiting for space to become available on the Tx queue. */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE ) + { + XIo_Out32( XPAR_RS232_UART_1_BASEADDR + XUL_TX_FIFO_OFFSET, cChar ); + lDidSomething = pdTRUE; + } + } + } while( lDidSomething == pdTRUE ); + + /* If we woke any tasks we may require a context switch. */ + if( xHigherPriorityTaskWoken ) + { + portYIELD_FROM_ISR(); + } +} + + + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/Version_Changes.log b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/Version_Changes.log new file mode 100644 index 000000000..817aa9bbd --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/Version_Changes.log @@ -0,0 +1,15 @@ + The following files will be modified: + system.mhs + system.mss + +-------------------------------------- + The following changes will be made: + Core ppc440mc_ddr2 2.00.a will be replaced by 2.00.b + Core clock_generator 3.00.a will be replaced by 3.01.a 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b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys @@ -0,0 +1,24 @@ +CommandLine-Map + +s +CommandLine-Ngdbuild + +s +CommandLine-Par + +s +CommandLine-Xst + +s +Previous-NGD + +s +Previous-NGM + +s +Previous-Packed-NCD + +s +Previous-Routed-NCD + +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys new file mode 100644 index 000000000..4bd7af120 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys @@ -0,0 +1,3 @@ +ISE_VERSION_LAST_SAVED_WITH +11.1 +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys new file mode 100644 index 000000000..f90e0607f --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys @@ -0,0 +1,6 @@ +ISE_VERSION_LAST_SAVED_WITH +11.1 +s +XISE_FILE +system.xise +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys new file mode 100644 index 000000000..87cda855f --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/XSLTProcess.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys new file mode 100644 index 000000000..c29a7fcf8 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys @@ -0,0 +1,21 @@ +ISE_VERSION_CREATED_WITH +11.1 +s +ISE_VERSION_LAST_SAVED_WITH +11.1 +s +LastRepoDir +E:\my_projects\Wittenstein\release\svn\main2\FreeRTOS\Demo\PPC440_FPU_Xilinx_Virtex5_GCC\__xps\ise\ +s +OBJSTORE_VERSION +1.3 +s +PROJECT_CREATION_TIMESTAMP +2009-06-13T13:10:25 +s +REGISTRY_VERSION +1.1 +s +REPOSITORY_VERSION +1.1 +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys new file mode 100644 index 000000000..949818c61 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/bitgen.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys new file mode 100644 index 000000000..dae1ec74d --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/bitinit.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/common/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/common/regkeys new file mode 100644 index 000000000..fac2f6efe --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/common/regkeys @@ -0,0 +1,12 @@ +IncrementalMessagingEnabled +true +s +MessageCaptureEnabled +true +s +MessageFilterFile +filter.filter +s +MessageFilteringEnabled +true +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys new file mode 100644 index 000000000..f3969b3ea --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/cpldfit.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys new file mode 100644 index 000000000..7e5b4bbcd --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/dumpngdio.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/fuse/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/fuse/regkeys new file mode 100644 index 000000000..77fa32d32 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/fuse/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/fuse.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys new file mode 100644 index 000000000..e654ecd77 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/hprep6.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/idem/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/idem/regkeys new file mode 100644 index 000000000..7b9c3214a --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/idem/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/idem.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/libgen/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/libgen/regkeys new file mode 100644 index 000000000..a2612daeb --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/libgen/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/libgen.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/map/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/map/regkeys new file mode 100644 index 000000000..447e64cb9 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/map/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/map.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/netgen/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/netgen/regkeys new file mode 100644 index 000000000..b15e57f97 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/netgen/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/netgen.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys new file mode 100644 index 000000000..2cb66e467 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/ngc2edif.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys new file mode 100644 index 000000000..af67ad186 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/ngcbuild.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys new file mode 100644 index 000000000..47ac460f4 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/ngdbuild.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/par/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/par/regkeys new file mode 100644 index 000000000..17ae8fbf3 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/par/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/par.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/platgen/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/platgen/regkeys new file mode 100644 index 000000000..d4497d267 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/platgen/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/platgen.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/runner/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/runner/regkeys new file mode 100644 index 000000000..d5e13d0a7 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/runner/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/runner.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/simgen/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/simgen/regkeys new file mode 100644 index 000000000..e12ea3860 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/simgen/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/simgen.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/taengine/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/taengine/regkeys new file mode 100644 index 000000000..fc0b03832 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/taengine/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/taengine.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/trce/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/trce/regkeys new file mode 100644 index 000000000..cffe0cfaa --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/trce/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/trce.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/tsim/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/tsim/regkeys new file mode 100644 index 000000000..52a3e8bb0 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/tsim/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/tsim.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys new file mode 100644 index 000000000..2d5cd6a1f --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/vhpcomp.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys new file mode 100644 index 000000000..9a5c2fab9 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/vlogcomp.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys new file mode 100644 index 000000000..c3f895c39 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/xpwr.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xreport/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xreport/regkeys new file mode 100644 index 000000000..e69de29bb diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xst/regkeys b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xst/regkeys new file mode 100644 index 000000000..5b1ae90bb --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xst/regkeys @@ -0,0 +1,3 @@ +ClientMessageOutputFile +_xmsgs/xst.xmsgs +s diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/version b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/version new file mode 100644 index 000000000..eec4d2283 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/version @@ -0,0 +1,10 @@ +REPOSITORY_VERSION +1.1 +REGISTRY_VERSION +1.1 +OBJSTORE_VERSION +1.3 +ISE_VERSION_CREATED_WITH +11.1 +ISE_VERSION_LAST_SAVED_WITH +11.1 diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/xmsgprops.lst b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/xmsgprops.lst new file mode 100644 index 000000000..e69de29bb diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/libgen.opt b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/libgen.opt new file mode 100644 index 000000000..55880074d --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/libgen.opt @@ -0,0 +1 @@ + -p virtex5 -msg __xps/ise/xmsgprops.lst diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/platgen.opt b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/platgen.opt new file mode 100644 index 000000000..58d810347 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/platgen.opt @@ -0,0 +1,2 @@ + -p xc5vfx70tff1136-1 -lang vhdl -msg __xps/ise/xmsgprops.lst + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/rtosdemo_compiler.opt b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/rtosdemo_compiler.opt new file mode 100644 index 000000000..f81b922b4 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/rtosdemo_compiler.opt @@ -0,0 +1,20 @@ +ppc440_0 +RTOSDEMO_SOURCES = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c +RTOSDEMO_HEADERS = +RTOSDEMO_CC = powerpc-eabi-gcc +RTOSDEMO_CC_SIZE = powerpc-eabi-size +RTOSDEMO_CC_OPT = -O0 +RTOSDEMO_CFLAGS = -D GCC_PPC440 -mregnames +RTOSDEMO_CC_SEARCH = # -B +RTOSDEMO_LIBPATH = -L./ppc440_0/lib/ # -L +RTOSDEMO_INCLUDES = -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop +RTOSDEMO_LFLAGS = # -l +RTOSDEMO_LINKER_SCRIPT = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld +RTOSDEMO_CC_DEBUG_FLAG = -g +RTOSDEMO_CC_PROFILE_FLAG = # -pg +RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi +RTOSDEMO_CC_INFERRED_FLAGS= -mfpu=sp_full -mcpu=440 +RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR= +RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE= +RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE= + $(RTOSDEMO_CC_INFERRED_FLAGS) \ diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/simgen.opt b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/simgen.opt new file mode 100644 index 000000000..d15e8cc45 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/simgen.opt @@ -0,0 +1 @@ + -p virtex5 -lang vhdl $(PPC440_0_BOOTLOOP) -msg __xps/ise/xmsgprops.lst -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/ diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/system.filters b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/system.filters new file mode 100644 index 000000000..a1a9109c9 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/system.filters @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/system.gui b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/system.gui new file mode 100644 index 000000000..82e9658fb --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/system.gui @@ -0,0 +1,103 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/xplorer.opt b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/xplorer.opt new file mode 100644 index 000000000..53ea0c72f --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/xplorer.opt @@ -0,0 +1 @@ + -device xc5vfx70tff1136-1 data/system.ucf 7 0 diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/xpsxflow.opt b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/xpsxflow.opt new file mode 100644 index 000000000..b8fbf7ab1 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/xpsxflow.opt @@ -0,0 +1 @@ + -device xc5vfx70tff1136-1 data/system.ucf 0 diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/blockdiagram/svg10.dtd b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/blockdiagram/svg10.dtd new file mode 100644 index 000000000..110f5ced5 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/blockdiagram/svg10.dtd @@ -0,0 +1,1704 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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#000088; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + tspan.iogrp_label_super { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + baseline-shift:super; + font-family: Arial Courier san-serif; + } + + text.p2pbus_label { + fill: #000000; + stroke: none; + font-size: 10pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + writing-mode: tb; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.multip_label { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + writing-mode: tb; + font-family: Verdana Arial Helvetica sans-serif; + } + + + + text.bc_iplabel { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Courier Arial Helvetica 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font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + + } + + text.buslabel { + fill: #CC3333; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.iplabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: 800; + text-anchor: middle; + font-family: Courier Arial Helvetica sans-serif; + } + + text.iptype { + fill: #AA0017; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.ipclass { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: normal; + font-weight: bold; + text-anchor: start; + font-family: Times Arial Helvetica sans-serif; + } + + text.procclass { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + plb_v46_0 + + + + + + + + + + xps_ethernetlite + Ethernet_MAC + + + SPLB + + + + + xps_gpio + LEDs_8Bit + + + SPLB + + + + + xps_gpio + LEDs_Positions + + + SPLB + + + + + xps_gpio + Push_Buttons_5Bit + + + SPLB + + + + + xps_gpio + DIP_Switches_8Bit + + + SPLB + + + + + xps_iic + IIC_EEPROM + + + SPLB + + + + + xps_intc + xps_intc_0 + + + SPLB + + + 0 + + + + + xps_mch_emc + SRAM + + + SPLB + + + + + xps_sysace + SysACE_CompactFlash + + + SPLB + + + + + xps_uartlite + RS232_Uart_1 + + + SPLB + + + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clock_generator + clock_generator_0 + + + + + + + + + plbv46_pcie + PCIe_Bridge + + + SPLB + + + MPLB + + + + + ppc440mc_ddr2 + DDR2_SDRAM + + + PPC4 + + + + + apu_fpu_virtex5 + ppc440_0_apu_fpu_virtex5 + + + SFCB2 + + + + + jtagppc_cntlr + jtagppc_cntlr_inst + + + JTAG + + + + + proc_sys_reset + proc_sys_reset_0 + + + RESE + + + + + ppc440_virtex5 + ppc440_0 + + + MPLB + + + SPLB0 + + + PPC4 + + + MFCB + + + JTAG + + + RESE + + + + 0 + + + + + + + + + + SLAVES OF plb_v46_0 + + PROCESSOR + + + + + bram_block + xps_bram_if_cntlr_1_bram + + PORTA + + + + + xps_bram_if_cntlr + xps_bram_if_cntlr_1 + + + SPLB + + PORTA + + + + + + + + + + + + + ppc440_0_SPLB0 + + + + + + + + ppc440_0_PPC440MC + + + + + + + + ppc_reset_bus + + + + + + + + + + + + + + + ppc440_0_fcb_v20 + + + + + + + + ppc440_0_jtagppc_bus + + + + + + + + + + + + + + + + + + x + + + + + + x + + + + + y + x + + + + + KEY + + SYMBOLS + + bus interface + + shared bus + Bus connections + + master or initiator + + slave or target + + master slave + + monitor + External Ports + + monitor + + output + + inout + Interrupts + + interrupt + controller + + interrupted + processor + + interrupt + source + x = controller ID + y = priority + + COLORS + Bus Standards + + DCR + + FCB + + FSL + + LMB + + OPB + + PLB + + SOCM + + Xilinx P2P + + USER P2P + + + + + SPECS + + EDK VERSION + 11.1 + + ARCH + virtex5 + + PART + xc5vfx70tff1136-1 + + GENERATED + Tue Jun 23 13:32:12 2009 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IP + + + + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/data/system.ucf b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/data/system.ucf new file mode 100644 index 000000000..fd1b9bdd6 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/data/system.ucf @@ -0,0 +1,495 @@ +Net fpga_0_RS232_Uart_1_RX_pin LOC = AG15 | IOSTANDARD=LVCMOS33; +Net fpga_0_RS232_Uart_1_TX_pin LOC = AG20 | IOSTANDARD=LVCMOS33; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> LOC = AE24 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> LOC = AD24 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> LOC = AD25 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> LOC = G16 | IOSTANDARD=LVCMOS25 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> LOC = AD26 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> LOC = G15 | IOSTANDARD=LVCMOS25 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> LOC = L18 | IOSTANDARD=LVCMOS25 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> LOC = H18 | IOSTANDARD=LVCMOS25 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=E8 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=AF23 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=AG12 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=AG23 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=AF13 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<0> LOC = AJ6 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<1> LOC = AJ7 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<2> LOC = V8 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<3> LOC = AK7 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<4> LOC = U8 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<0> LOC=U25 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<1> LOC=AG27 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<2> LOC=AF25 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<3> LOC=AF26 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<4> LOC=AE27 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<5> LOC=AE26 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<6> LOC=AC25 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<7> LOC=AC24 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2; +Net fpga_0_IIC_EEPROM_Sda_pin LOC=F8 | SLEW = SLOW | DRIVE = 6 | IOSTANDARD=LVCMOS33; +Net fpga_0_IIC_EEPROM_Scl_pin LOC=F9 | SLEW = SLOW | DRIVE = 6 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<30> LOC=K12 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<29> LOC=K13 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<28> LOC=H23 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<27> LOC=G23 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<26> LOC=H12 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<25> LOC=J12 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<24> LOC=K22 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<23> LOC=K23 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<22> LOC=K14 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<21> LOC=L14 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<20> LOC=H22 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<19> LOC=G22 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<18> LOC=J15 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<17> LOC=K16 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<16> LOC=K21 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<15> LOC=J22 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<14> LOC=L16 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<13> LOC=L15 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<12> LOC=L20 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<11> LOC=L21 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<10> LOC=AE23 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<9> LOC=AE22 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<8> LOC=AE12 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<7> LOC=AE13 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_CEN_pin LOC=J10 | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_OEN_pin LOC=B12 | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_WEN_pin LOC=AF20 | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=J11 | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=K11 | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=D10 | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=D11 | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=H8 | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=AG22 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=AH22 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=AH12 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=AG13 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=AH20 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=AH19 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=AH14 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=AH13 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=AF15 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=AE16 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=AE21 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=AD20 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=AF16 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=AE17 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=AE19 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=AD19 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=J9 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=K8 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=K9 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=B13 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=C13 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=G11 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=G12 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=M8 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=L8 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=F11 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=E11 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=M10 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=L9 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=E12 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=E13 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=N10 | PULLDOWN | IOSTANDARD=LVDCI_33; +Net fpga_0_SRAM_ZBT_CLK_OUT_pin LOC=G8 | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33; +Net fpga_0_SRAM_ZBT_CLK_FB_pin LOC=AG21 | IOSTANDARD=LVCMOS33; +Net fpga_0_PCIe_Bridge_RXN_pin LOC=AF1 | IOSTANDARD = LVDS_25; +Net fpga_0_PCIe_Bridge_RXP_pin LOC=AE1 | IOSTANDARD = LVDS_25; +Net fpga_0_PCIe_Bridge_TXN_pin LOC=AE2 | IOSTANDARD = LVDS_25; +Net fpga_0_PCIe_Bridge_TXP_pin LOC=AD2 | IOSTANDARD = LVDS_25; +Net "pcie_bridge/*SPLB_Clk" TNM_NET = "SPLB_Clk"; +Net "pcie_bridge/*Bridge_Clk" TNM_NET = "Bridge_Clk"; + +## Timing constraints between clock-domain boundaries +# +TIMESPEC "TS_PLB_PCIe" = FROM "SPLB_Clk" TO "Bridge_Clk" 8 ns datapathonly; +TIMESPEC "TS_PCIe_PLB" = FROM "Bridge_Clk" TO "SPLB_Clk" 8 ns datapathonly; + +Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=K17 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=H17 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=E34 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=E32 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=A33 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=B33 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=C33 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=C32 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=B32 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=E33 | IOSTANDARD = LVCMOS25; +Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC=J14 | IOSTANDARD = LVCMOS25 | TIG; +Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=AJ10 | IOSTANDARD = LVDCI_33; +Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=AH10 | IOSTANDARD = LVDCI_33; +Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=AH9 | IOSTANDARD = LVDCI_33; +Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=AE11 | IOSTANDARD = LVDCI_33; +Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=AF11 | IOSTANDARD = LVDCI_33; +Net fpga_0_Ethernet_MAC_MDINT_pin LOC=H20 | IOSTANDARD = LVCMOS25 | TIG; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<0> LOC=AF30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<1> LOC=AK31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<2> LOC=AF31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<3> LOC=AD30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<4> LOC=AJ30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<5> LOC=AF29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<6> LOC=AD29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<7> LOC=AE29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<8> LOC=AH27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<9> LOC=AF28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<10> LOC=AH28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<11> LOC=AA28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<12> LOC=AG25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<13> LOC=AJ26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<14> LOC=AG28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<15> LOC=AB28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<16> LOC=AC28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<17> LOC=AB25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<18> LOC=AC27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<19> LOC=AA26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<20> LOC=AB26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<21> LOC=AA24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<22> LOC=AB27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<23> LOC=AA25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<24> LOC=AC29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<25> LOC=AB30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<26> LOC=W31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<27> LOC=V30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<28> LOC=AC30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<29> LOC=W29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<30> LOC=V27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<31> LOC=W27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<32> LOC=V29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<33> LOC=Y27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<34> LOC=Y26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<35> LOC=W24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<36> LOC=V28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<37> LOC=W25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<38> LOC=W26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<39> LOC=V24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<40> LOC=R24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<41> LOC=P25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<42> LOC=N24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<43> LOC=P26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<44> LOC=T24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<45> LOC=N25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<46> LOC=P27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<47> LOC=N28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<48> LOC=M28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<49> LOC=L28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<50> LOC=F25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<51> LOC=H25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<52> LOC=K27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<53> LOC=K28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<54> LOC=H24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<55> LOC=G26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<56> LOC=G25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<57> LOC=M26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<58> LOC=J24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<59> LOC=L26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<60> LOC=J27 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<61> LOC=M25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<62> LOC=L25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<63> LOC=L24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<0> LOC=AA29 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<1> LOC=AK28 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<2> LOC=AK26 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<3> LOC=AB31 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<4> LOC=Y28 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<5> LOC=E26 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<6> LOC=H28 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<7> LOC=G27 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<0> LOC=AA30 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<1> LOC=AK27 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<2> LOC=AJ27 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<3> LOC=AA31 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<4> LOC=Y29 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<5> LOC=E27 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<6> LOC=G28 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<7> LOC=H27 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<0> LOC=L30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<1> LOC=M30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<2> LOC=N29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<3> LOC=P29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<4> LOC=K31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<5> LOC=L31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<6> LOC=P31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<7> LOC=P30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<8> LOC=M31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<9> LOC=R28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<10> LOC=J31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<11> LOC=R29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_A_pin<12> LOC=T31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_BA_pin<0> LOC=G31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_BA_pin<1> LOC=J30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin LOC=H30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin LOC=E31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_WE_N_pin LOC=K29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_CS_N_pin LOC=L29 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin<0> LOC=F31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin<1> LOC=F30 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_CKE_pin LOC=T28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<0> LOC=AJ31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<1> LOC=AE28 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<2> LOC=Y24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<3> LOC=Y31 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<4> LOC=V25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<5> LOC=P24 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<6> LOC=F26 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<7> LOC=J25 | IOSTANDARD = SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_CK_pin<0> LOC=AK29 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_CK_pin<1> LOC=E28 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_CK_N_pin<0> LOC=AJ29 | IOSTANDARD = DIFF_SSTL18_II; +Net fpga_0_DDR2_SDRAM_DDR2_CK_N_pin<1> LOC=F28 | IOSTANDARD = DIFF_SSTL18_II; +############################################################################ +# +# PPC440MC_DDR2 BRAM Location Constraints +# +############################################################################ + +##------------------------------------------------------------------------------ +## MIG 2.0 Constraints +##------------------------------------------------------------------------------ +########################################################################### +## Define multicycle paths - these paths may take longer because additional +## time allowed for logic to settle in calibration/initialization FSM +########################################################################### + +NET "DDR2_SDRAM*/mc_mibclk" TNM = FFS "TNM_CLK0"; +NET "DDR2_SDRAM*/mi_mcclk90" TNM = FFS "TNM_CLK90"; + +NET "DDR2_SDRAM*/mc_mibclk" TNM_NET = "mc_clk"; +TIMESPEC "TS_MC_CLK" = PERIOD "mc_clk" 5.000 ns; + + +## MUX Select for either rising/falling CLK0 for 2nd stage read capture +INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL"; +TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO "TNM_CLK0" +"TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i" * 4; + +## Calibration/Initialization complete status flag (for PHY logic only) +INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL"; +TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO + "TNM_CLK0" +"TS_MC_CLK" * 4; + +TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO + "TNM_CLK90" "TS_MC_CLK" * 4; + +## Select (address) bits for SRL32 shift registers used in stage3/stage4 +## calibration +INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY"; +TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO "TNM_CLK0" +"TS_MC_CLK" * 4; + +INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY"; +TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO "TNM_CLK0" +"TS_MC_CLK" * 4; + +INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly" + TNM = "TNM_CAL_RDEN_DLY"; +TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO "TNM_CLK0" +"TS_MC_CLK" * 4; + +## MUX select for read data - optional delay on data to account for byte skews +INST "*/usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX"; +TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO "TNM_CLK0" +"TS_MC_CLK" * 4; + +########################################################################### +## LOC placment of DQS-squelch related IDDR and IDELAY elements +## Each circuit can be located at any of the following locations: +## 1. Ununsed "N"-side of DQS diff pair I/O +## 2. DM data mask (output only, input side is free for use) +## 3. Any output-only site +########################################################################### + +INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y96"; +INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y96"; +INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y58"; +INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y58"; +INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y62"; +INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y62"; +INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y100"; +INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y100"; +INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y102"; +INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y102"; +INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y256"; +INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y256"; +INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y260"; +INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y260"; +INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y262"; +INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y262"; + +########################################################################### +## DQS Squelch-related timing constraints +########################################################################### + +########################################################################### +## Half-cycle path constraint from IDDR to CE pin for all DQ IDDRs +## for DQS Read Postamble Glitch Squelch circuit +########################################################################### +## Max delay from output of IDDR to CE input of DQ IDDRs = tRPST + some slack +## where slack account for rise-time of DQS on board. For now assume slack = +## 0.400ns (based on initial SPICE simulations, assumes use of ODT), so +## time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz +INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR"; +INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS"; +TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 1.9 ns; + +########################################################################### +## LOC and timing constraints for flop driving DQS CE enable signal +## from fabric logic. Even though the absolute delay on this path is +## calibrated out (when synchronizing this output to DQS), the delay +## should still be kept as low as possible to reduce post-calibration +## voltage/temp variations - these are roughly proportional to the +## absolute delay of the path +########################################################################### + +INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff" LOC = SLICE_X0Y48; +INST "*/u_phy_calib/gen_gate[1].u_en_dqs_ff" LOC = SLICE_X0Y29; +INST "*/u_phy_calib/gen_gate[2].u_en_dqs_ff" LOC = SLICE_X0Y31; +INST "*/u_phy_calib/gen_gate[3].u_en_dqs_ff" LOC = SLICE_X0Y50; +INST "*/u_phy_calib/gen_gate[4].u_en_dqs_ff" LOC = SLICE_X0Y51; +INST "*/u_phy_calib/gen_gate[5].u_en_dqs_ff" LOC = SLICE_X0Y128; +INST "*/u_phy_calib/gen_gate[6].u_en_dqs_ff" LOC = SLICE_X0Y130; +INST "*/u_phy_calib/gen_gate[7].u_en_dqs_ff" LOC = SLICE_X0Y131; + +########################################################################### +## Control for DQS gate - from fabric flop. Prevent runaway delay - +## two parts to this path: (1) from fabric flop to IDELAY, (2) from +## IDELAY to asynchronous reset of IDDR that drives the DQ CEs +## A single number is used for all speed grades - value based on 333MHz. +## This can be relaxed for lower frequencies. +########################################################################### + +NET "*/u_phy_io/en_dqs*" MAXDELAY = 600 ps; +NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps; + +########################################################################### + +INST "*/gen_dq[0].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42; +INST "*/gen_dq[1].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y43; +INST "*/gen_dq[2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y45; +INST "*/gen_dq[3].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46; +INST "*/gen_dq[4].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y41; +INST "*/gen_dq[5].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42; +INST "*/gen_dq[6].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44; +INST "*/gen_dq[7].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44; +INST "*/gen_dq[8].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28; +INST "*/gen_dq[9].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y32; +INST "*/gen_dq[10].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33; +INST "*/gen_dq[11].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34; +INST "*/gen_dq[12].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y26; +INST "*/gen_dq[13].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28; +INST "*/gen_dq[14].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33; +INST "*/gen_dq[15].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34; +INST "*/gen_dq[16].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y35; +INST "*/gen_dq[17].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36; +INST "*/gen_dq[18].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38; +INST "*/gen_dq[19].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39; +INST "*/gen_dq[20].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36; +INST "*/gen_dq[21].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y37; +INST "*/gen_dq[22].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38; +INST "*/gen_dq[23].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39; +INST "*/gen_dq[24].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46; +INST "*/gen_dq[25].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49; +INST "*/gen_dq[26].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y53; +INST "*/gen_dq[27].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y55; +INST "*/gen_dq[28].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49; +INST "*/gen_dq[29].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52; +INST "*/gen_dq[30].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54; +INST "*/gen_dq[31].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56; +INST "*/gen_dq[32].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52; +INST "*/gen_dq[33].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56; +INST "*/gen_dq[34].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58; +INST "*/gen_dq[35].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59; +INST "*/gen_dq[36].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54; +INST "*/gen_dq[37].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y57; +INST "*/gen_dq[38].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58; +INST "*/gen_dq[39].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59; +INST "*/gen_dq[40].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120; +INST "*/gen_dq[41].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121; +INST "*/gen_dq[42].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y122; +INST "*/gen_dq[43].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123; +INST "*/gen_dq[44].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120; +INST "*/gen_dq[45].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121; +INST "*/gen_dq[46].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123; +INST "*/gen_dq[47].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124; +INST "*/gen_dq[48].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124; +INST "*/gen_dq[49].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126; +INST "*/gen_dq[50].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y132; +INST "*/gen_dq[51].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133; +INST "*/gen_dq[52].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y125; +INST "*/gen_dq[53].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126; +INST "*/gen_dq[54].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133; +INST "*/gen_dq[55].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134; +INST "*/gen_dq[56].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134; +INST "*/gen_dq[57].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136; +INST "*/gen_dq[58].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y137; +INST "*/gen_dq[59].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138; +INST "*/gen_dq[60].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y135; +INST "*/gen_dq[61].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136; +INST "*/gen_dq[62].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138; +INST "*/gen_dq[63].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y139; + + +INST "DDR2_SDRAM/*/*u_rdf" LOC = RAMB36_X0Y19; +INST "DDR2_SDRAM/*/*u_rdf1" LOC = RAMB36_X0Y18; +INST "DDR2_SDRAM/*/*gen_wdf[0]*u_wdf" LOC = RAMB36_X0Y17; +INST "DDR2_SDRAM/*/*gen_wdf[1]*u_wdf" LOC = RAMB36_X0Y16; + + +############################################################################### + +# Prevent unrelated logic from being packed into any slices used + +# by read data capture RPM's - if unrelated logic gets packed into + +# these slices, it could cause the DIRT strings that define the + +# IDDR -> fabric flop routing to become unroutable during PAR stage + +# (unrelated logic may require routing resources required by the + +# DIRT strings - MAP does not currently take into account DIRT + +# strings when placing logic + +############################################################################### + +AREA_GROUP "DDR_CAPTURE_FFS" GROUP = CLOSED; + + + +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=G5 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=N7 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=N5 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=P5 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=R6 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=M6 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=L6 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AH17 | IOSTANDARD = LVCMOS33 | PERIOD = 30000 ps; +Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=M7 | IOSTANDARD = LVCMOS33 | TIG; +Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=M5 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=N8 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=R9 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=P9 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=T8 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=J7 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=H7 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=R7 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=U7 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=P7 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=P6 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=R8 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=L5 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=L4 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=K6 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=J5 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=T6 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=K7 | IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=J6 | IOSTANDARD = LVCMOS33; +Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin; +TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz; +Net fpga_0_clk_1_sys_clk_pin LOC = AH15 | IOSTANDARD=LVCMOS33; +Net fpga_0_rst_1_sys_rst_pin TIG; +Net fpga_0_rst_1_sys_rst_pin LOC = E9 | IOSTANDARD=LVCMOS33 | PULLUP; +Net fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin LOC=AF4 | IOSTANDARD = LVDS_25; +Net fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin LOC=AF3 | IOSTANDARD = LVDS_25; diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/etc/bitgen.ut b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/etc/bitgen.ut new file mode 100644 index 000000000..9bdebfcf7 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/etc/bitgen.ut @@ -0,0 +1,14 @@ +-g TdoPin:PULLNONE +-g DriveDone:No +-g StartUpClk:JTAGCLK +-g DONE_cycle:4 +-g GTS_cycle:5 +-g TckPin:PULLUP +-g TdiPin:PULLUP +-g TmsPin:PULLUP +-g DonePipe:No +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:NONE +-g Persist:No + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/etc/download.cmd b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/etc/download.cmd new file mode 100644 index 000000000..f46037346 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/etc/download.cmd @@ -0,0 +1,6 @@ +setMode -bscan +setCable -p auto +identify +assignfile -p 5 -file implementation/download.bit +program -p 5 +quit diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/etc/fast_runtime.opt b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/etc/fast_runtime.opt new file mode 100644 index 000000000..52396f17f --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/etc/fast_runtime.opt @@ -0,0 +1,83 @@ +FLOWTYPE = FPGA; +############################################################### +## Filename: fast_runtime.opt +## +## Option File For Xilinx FPGA Implementation Flow for Fast +## Runtime. +## +## Version: 4.1.1 +############################################################### +# +# Options for Translator +# +# Type "ngdbuild -h" for a detailed list of ngdbuild command line options +# +Program ngdbuild +-p ; # Partname to use - picked from xflow commandline +-nt timestamp; # NGO File generation. Regenerate only when + # source netlist is newer than existing + # NGO file (default) +-bm .bmm # Block RAM memory map file +; # User design - pick from xflow command line +-uc .ucf; # ucf constraints +.ngd; # Name of NGD file. Filebase same as design filebase +End Program ngdbuild + +# +# Options for Mapper +# +# Type "map -h " for a detailed list of map command line options +# +Program map +-o _map.ncd; # Output Mapped ncd file +-w; # Overwrite output files. +-pr b; # Pack internal FF/latches into IOBs +#-fp .mfp; # Floorplan file +-ol high; +-timing; +.ngd; # Input NGD file +.pcf; # Physical constraints file +END Program map + +# +# Options for Post Map Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_map_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o _map.twr; # Output trace report file +-xml _map.twx; # Output XML version of the timing report +#-tsi _map.tsi; # Produce Timing Specification Interaction report +_map.ncd; # Input mapped ncd +.pcf; # Physical constraints file +END Program post_map_trce + +# +# Options for Place and Route +# +# Type "par -h" for a detailed list of par command line options +# +Program par +-w; # Overwrite existing placed and routed ncd +-ol high; # Overall effort level +_map.ncd; # Input mapped NCD file +.ncd; # Output placed and routed NCD +.pcf; # Input physical constraints file +END Program par + +# +# Options for Post Par Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_par_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o .twr; # Output trace report file +-xml .twx; # Output XML version of the timing report +#-tsi .tsi; # Produce Timing Specification Interaction report +.ncd; # Input placed and routed ncd +.pcf; # Physical constraints file +END Program post_par_trce + + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/revup/system_mhs.11.1 b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/revup/system_mhs.11.1 new file mode 100644 index 000000000..597527ed7 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/revup/system_mhs.11.1 @@ -0,0 +1,474 @@ + +# ############################################################################## +# Created by Base System Builder Wizard for Xilinx EDK 11.1 Build EDK_L.29.1 +# Sat Jun 13 13:14:11 2009 +# Target Board: Xilinx Virtex 5 ML507 Evaluation Platform Rev A +# Family: virtex5 +# Device: xc5vfx70t +# Package: ff1136 +# Speed Grade: -1 +# Processor number: 1 +# Processor 1: ppc440_0 +# Processor clock frequency: 125.0 +# Bus clock frequency: 125.0 +# Debug Interface: FPGA JTAG +# ############################################################################## + PARAMETER VERSION = 2.1.0 + + + PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I + PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O + PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7] + PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO_pin, DIR = IO, VEC = [0:4] + PORT fpga_0_Push_Buttons_5Bit_GPIO_IO_pin = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin, DIR = IO, VEC = [0:4] + PORT fpga_0_DIP_Switches_8Bit_GPIO_IO_pin = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7] + PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda_pin, DIR = IO + PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl_pin, DIR = IO + PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat, DIR = O, VEC = [7:30] + PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN_pin, DIR = O + PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN_pin, DIR = O + PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN_pin, DIR = O + PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN_pin, DIR = O, VEC = [0:3] + PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN_pin, DIR = O + PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ_pin, DIR = IO, VEC = [0:31] + PORT fpga_0_SRAM_ZBT_CLK_OUT_pin = SRAM_CLK_OUT_s, DIR = O + PORT fpga_0_SRAM_ZBT_CLK_FB_pin = SRAM_CLK_FB_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000 + PORT fpga_0_PCIe_Bridge_RXN_pin = fpga_0_PCIe_Bridge_RXN_pin, DIR = I + PORT fpga_0_PCIe_Bridge_RXP_pin = fpga_0_PCIe_Bridge_RXP_pin, DIR = I + PORT fpga_0_PCIe_Bridge_TXN_pin = fpga_0_PCIe_Bridge_TXN_pin, DIR = O + PORT fpga_0_PCIe_Bridge_TXP_pin = fpga_0_PCIe_Bridge_TXP_pin, DIR = O + PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk_pin, DIR = I + PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk_pin, DIR = I + PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs_pin, DIR = I + PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv_pin, DIR = I + PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data_pin, DIR = I, VEC = [3:0] + PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col_pin, DIR = I + PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er_pin, DIR = I + PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n_pin, DIR = O + PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en_pin, DIR = O + PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data_pin, DIR = O, VEC = [3:0] + PORT fpga_0_Ethernet_MAC_MDINT_pin = fpga_0_Ethernet_MAC_MDINT_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM + PORT fpga_0_DDR2_SDRAM_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_DDR2_DQ_pin, DIR = IO, VEC = [63:0] + PORT fpga_0_DDR2_SDRAM_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_pin, DIR = IO, VEC = [7:0] + PORT fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin, DIR = IO, VEC = [7:0] + PORT fpga_0_DDR2_SDRAM_DDR2_A_pin = fpga_0_DDR2_SDRAM_DDR2_A_pin, DIR = O, VEC = [12:0] + PORT fpga_0_DDR2_SDRAM_DDR2_BA_pin = fpga_0_DDR2_SDRAM_DDR2_BA_pin, DIR = O, VEC = [1:0] + PORT fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin, DIR = O + PORT fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin, DIR = O + PORT fpga_0_DDR2_SDRAM_DDR2_WE_N_pin = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin, DIR = O + PORT fpga_0_DDR2_SDRAM_DDR2_CS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin, DIR = O + PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT_pin, DIR = O, VEC = [1:0] + PORT fpga_0_DDR2_SDRAM_DDR2_CKE_pin = fpga_0_DDR2_SDRAM_DDR2_CKE_pin, DIR = O + PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM_pin, DIR = O, VEC = [7:0] + PORT fpga_0_DDR2_SDRAM_DDR2_CK_pin = fpga_0_DDR2_SDRAM_DDR2_CK_pin, DIR = O, VEC = [1:0] + PORT fpga_0_DDR2_SDRAM_DDR2_CK_N_pin = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin, DIR = O, VEC = [1:0] + PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin, DIR = O, VEC = [6:0] + PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin, DIR = I + PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin, DIR = I + PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin, DIR = O + PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin, DIR = O + PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin, DIR = O + PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin, DIR = IO, VEC = [15:0] + PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 + PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0 + PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK + PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK + + +BEGIN ppc440_virtex5 + PARAMETER INSTANCE = ppc440_0 + PARAMETER C_IDCR_BASEADDR = 0b0000000000 + PARAMETER C_IDCR_HIGHADDR = 0b0011111111 + PARAMETER C_APU_CONTROL = 0b00000010000000001 + PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x003FFE00 + PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00C00000 + PARAMETER C_PPC440MC_CONTROL = 0xF810008F + PARAMETER C_SPLB0_USE_MPLB_ADDR = 1 + PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 1 + PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0 + PARAMETER HW_VER = 1.01.a + PARAMETER C_SPLB0_RNG0_MPLB_BASEADDR = 0x80000000 + PARAMETER C_SPLB0_RNG0_MPLB_HIGHADDR = 0xffffffff + PARAMETER C_SPLB0_RNG_MC_BASEADDR = 0x00000000 + PARAMETER C_SPLB0_RNG_MC_HIGHADDR = 0x0fffffff + BUS_INTERFACE MPLB = plb_v46_0 + BUS_INTERFACE SPLB0 = ppc440_0_SPLB0 + BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC + BUS_INTERFACE MFCB = ppc440_0_fcb_v20 + BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus + BUS_INTERFACE RESETPPC = ppc_reset_bus + PORT CPMC440CLK = clk_125_0000MHzPLL0 + PORT CPMINTERCONNECTCLK = clk_125_0000MHzPLL0 + PORT CPMINTERCONNECTCLKNTO1 = net_vcc + PORT EICC440EXTIRQ = ppc440_0_EICC440EXTIRQ + PORT CPMMCCLK = clk_125_0000MHzPLL0_ADJUST + PORT CPMPPCMPLBCLK = clk_125_0000MHzPLL0_ADJUST + PORT CPMPPCS0PLBCLK = clk_125_0000MHzPLL0_ADJUST +END + +BEGIN plb_v46 + PARAMETER INSTANCE = plb_v46_0 + PARAMETER C_DCR_INTFCE = 0 + PARAMETER C_FAMILY = virtex5 + PARAMETER HW_VER = 1.04.a + PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST + PORT SYS_Rst = sys_bus_reset +END + +BEGIN xps_bram_if_cntlr + PARAMETER INSTANCE = xps_bram_if_cntlr_1 + PARAMETER C_SPLB_NATIVE_DWIDTH = 64 + PARAMETER C_SPLB_SUPPORT_BURSTS = 1 + PARAMETER C_SPLB_P2P = 0 + PARAMETER C_FAMILY = virtex5 + PARAMETER HW_VER = 1.00.b + PARAMETER C_BASEADDR = 0xffffe000 + PARAMETER C_HIGHADDR = 0xffffffff + BUS_INTERFACE SPLB = plb_v46_0 + BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port +END + +BEGIN bram_block + PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram + PARAMETER C_FAMILY = virtex5 + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port +END + +BEGIN xps_uartlite + PARAMETER INSTANCE = RS232_Uart_1 + PARAMETER C_FAMILY = virtex5 + PARAMETER C_BAUDRATE = 9600 + PARAMETER C_DATA_BITS = 8 + PARAMETER C_USE_PARITY = 0 + PARAMETER C_ODD_PARITY = 0 + PARAMETER HW_VER = 1.01.a + PARAMETER C_BASEADDR = 0x84000000 + PARAMETER C_HIGHADDR = 0x8400ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT RX = fpga_0_RS232_Uart_1_RX_pin + PORT TX = fpga_0_RS232_Uart_1_TX_pin + PORT Interrupt = RS232_Uart_1_Interrupt +END + +BEGIN xps_gpio + PARAMETER INSTANCE = LEDs_8Bit + PARAMETER C_FAMILY = virtex5 + PARAMETER C_ALL_INPUTS = 0 + PARAMETER C_GPIO_WIDTH = 8 + PARAMETER C_INTERRUPT_PRESENT = 0 + PARAMETER C_IS_DUAL = 0 + PARAMETER HW_VER = 2.00.a + PARAMETER C_BASEADDR = 0x81440000 + PARAMETER C_HIGHADDR = 0x8144ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO_pin +END + +BEGIN xps_gpio + PARAMETER INSTANCE = LEDs_Positions + PARAMETER C_FAMILY = virtex5 + PARAMETER C_ALL_INPUTS = 0 + PARAMETER C_GPIO_WIDTH = 5 + PARAMETER C_INTERRUPT_PRESENT = 0 + PARAMETER C_IS_DUAL = 0 + PARAMETER HW_VER = 2.00.a + PARAMETER C_BASEADDR = 0x81420000 + PARAMETER C_HIGHADDR = 0x8142ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO_pin +END + +BEGIN xps_gpio + PARAMETER INSTANCE = Push_Buttons_5Bit + PARAMETER C_FAMILY = virtex5 + PARAMETER C_ALL_INPUTS = 1 + PARAMETER C_GPIO_WIDTH = 5 + PARAMETER C_INTERRUPT_PRESENT = 0 + PARAMETER C_IS_DUAL = 0 + PARAMETER HW_VER = 2.00.a + PARAMETER C_BASEADDR = 0x81400000 + PARAMETER C_HIGHADDR = 0x8140ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT GPIO_IO = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin +END + +BEGIN xps_gpio + PARAMETER INSTANCE = DIP_Switches_8Bit + PARAMETER C_FAMILY = virtex5 + PARAMETER C_ALL_INPUTS = 1 + PARAMETER C_GPIO_WIDTH = 8 + PARAMETER C_INTERRUPT_PRESENT = 0 + PARAMETER C_IS_DUAL = 0 + PARAMETER HW_VER = 2.00.a + PARAMETER C_BASEADDR = 0x81460000 + PARAMETER C_HIGHADDR = 0x8146ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT GPIO_IO = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin +END + +BEGIN xps_iic + PARAMETER INSTANCE = IIC_EEPROM + PARAMETER C_IIC_FREQ = 100000 + PARAMETER C_TEN_BIT_ADR = 0 + PARAMETER C_FAMILY = virtex5 + PARAMETER HW_VER = 2.01.a + PARAMETER C_BASEADDR = 0x81600000 + PARAMETER C_HIGHADDR = 0x8160ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT Sda = fpga_0_IIC_EEPROM_Sda_pin + PORT Scl = fpga_0_IIC_EEPROM_Scl_pin +END + +BEGIN xps_mch_emc + PARAMETER INSTANCE = SRAM + PARAMETER C_FAMILY = virtex5 + PARAMETER C_NUM_BANKS_MEM = 1 + PARAMETER C_NUM_CHANNELS = 0 + PARAMETER C_MEM0_WIDTH = 32 + PARAMETER C_MAX_MEM_WIDTH = 32 + PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0 + PARAMETER C_SYNCH_MEM_0 = 1 + PARAMETER C_TCEDV_PS_MEM_0 = 0 + PARAMETER C_TAVDV_PS_MEM_0 = 0 + PARAMETER C_THZCE_PS_MEM_0 = 0 + PARAMETER C_THZOE_PS_MEM_0 = 0 + PARAMETER C_TWC_PS_MEM_0 = 0 + PARAMETER C_TWP_PS_MEM_0 = 0 + PARAMETER C_TLZWE_PS_MEM_0 = 0 + PARAMETER HW_VER = 3.00.a + PARAMETER C_MEM0_BASEADDR = 0xf8000000 + PARAMETER C_MEM0_HIGHADDR = 0xf80fffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT RdClk = clk_125_0000MHzPLL0_ADJUST + PORT Mem_A = 0b0000000 & fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat & 0b0 + PORT Mem_CEN = fpga_0_SRAM_Mem_CEN_pin + PORT Mem_OEN = fpga_0_SRAM_Mem_OEN_pin + PORT Mem_WEN = fpga_0_SRAM_Mem_WEN_pin + PORT Mem_BEN = fpga_0_SRAM_Mem_BEN_pin + PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN_pin + PORT Mem_DQ = fpga_0_SRAM_Mem_DQ_pin +END + +BEGIN plbv46_pcie + PARAMETER INSTANCE = PCIe_Bridge + PARAMETER C_FAMILY = virtex5 + PARAMETER C_IPIFBAR_NUM = 2 + PARAMETER C_PCIBAR_NUM = 1 + PARAMETER C_DEVICE_ID = 0x0505 + PARAMETER C_VENDOR_ID = 0x10EE + PARAMETER C_CLASS_CODE = 0x058000 + PARAMETER C_REV_ID = 0x00 + PARAMETER C_SUBSYSTEM_ID = 0x0000 + PARAMETER C_SUBSYSTEM_VENDOR_ID = 0x0000 + PARAMETER C_COMP_TIMEOUT = 1 + PARAMETER C_IPIFBAR2PCIBAR_0 = 0x00000000 + PARAMETER C_IPIFBAR2PCIBAR_1 = 0x00000000 + PARAMETER C_PCIBAR2IPIFBAR_0 = 0xf8000000 + PARAMETER C_PCIBAR2IPIFBAR_1 = 0x00000000 + PARAMETER C_PCIBAR_LEN_0 = 20 + PARAMETER C_PCIBAR_LEN_1 = 28 + PARAMETER C_BOARD = ml507 + PARAMETER HW_VER = 3.00.b + PARAMETER C_BASEADDR = 0x85c00000 + PARAMETER C_HIGHADDR = 0x85c0ffff + PARAMETER C_IPIFBAR_0 = 0xc0000000 + PARAMETER C_IPIFBAR_HIGHADDR_0 = 0xdfffffff + PARAMETER C_IPIFBAR_1 = 0xe0000000 + PARAMETER C_IPIFBAR_HIGHADDR_1 = 0xefffffff + BUS_INTERFACE SPLB = plb_v46_0 + BUS_INTERFACE MPLB = ppc440_0_SPLB0 + PORT PERSTN = net_vcc + PORT REFCLK = PCIe_Diff_Clk + PORT RXN = fpga_0_PCIe_Bridge_RXN_pin + PORT RXP = fpga_0_PCIe_Bridge_RXP_pin + PORT TXN = fpga_0_PCIe_Bridge_TXN_pin + PORT TXP = fpga_0_PCIe_Bridge_TXP_pin + PORT MSI_request = net_gnd +END + +BEGIN plb_v46 + PARAMETER INSTANCE = ppc440_0_SPLB0 + PARAMETER C_FAMILY = virtex5 + PARAMETER HW_VER = 1.04.a + PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST + PORT SYS_Rst = sys_bus_reset +END + +BEGIN xps_ethernetlite + PARAMETER INSTANCE = Ethernet_MAC + PARAMETER C_FAMILY = virtex5 + PARAMETER HW_VER = 2.01.a + PARAMETER C_BASEADDR = 0x81000000 + PARAMETER C_HIGHADDR = 0x8100ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk_pin + PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk_pin + PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs_pin + PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv_pin + PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data_pin + PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col_pin + PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er_pin + PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n_pin + PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en_pin + PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data_pin +END + +BEGIN ppc440mc_ddr2 + PARAMETER INSTANCE = DDR2_SDRAM + PARAMETER C_DDR_BAWIDTH = 2 + PARAMETER C_NUM_CLK_PAIRS = 2 + PARAMETER C_DDR_DWIDTH = 64 + PARAMETER C_DDR_CAWIDTH = 10 + PARAMETER C_NUM_RANKS_MEM = 1 + PARAMETER C_CS_BITS = 0 + PARAMETER C_DDR_DM_WIDTH = 8 + PARAMETER C_DQ_BITS = 8 + PARAMETER C_DDR2_ODT_WIDTH = 2 + PARAMETER C_DDR2_ADDT_LAT = 0 + PARAMETER C_INCLUDE_ECC_SUPPORT = 0 + PARAMETER C_DDR2_ODT_SETTING = 1 + PARAMETER C_DQS_BITS = 3 + PARAMETER C_DDR_DQS_WIDTH = 8 + PARAMETER C_DDR_RAWIDTH = 13 + PARAMETER C_DDR_BURST_LENGTH = 4 + PARAMETER C_DDR_CAS_LAT = 4 + PARAMETER C_REG_DIMM = 0 + PARAMETER C_MIB_MC_CLOCK_RATIO = 1 + PARAMETER C_DDR_TREFI = 3900 + PARAMETER C_DDR_TRAS = 40000 + PARAMETER C_DDR_TRCD = 15000 + PARAMETER C_DDR_TRFC = 75000 + PARAMETER C_DDR_TRP = 15000 + PARAMETER C_DDR_TRTP = 7500 + PARAMETER C_DDR_TWR = 15000 + PARAMETER C_DDR_TWTR = 7500 + PARAMETER C_MC_MIBCLK_PERIOD_PS = 8000 + PARAMETER C_IDEL_HIGH_PERF = TRUE + PARAMETER C_NUM_IDELAYCTRL = 3 + PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1 + PARAMETER C_DQS_IO_COL = 0b000000000000000000 + PARAMETER C_DQ_IO_MS = 0b000000000111010100111101000011110001111000101110110000111100000110111100 + PARAMETER HW_VER = 2.00.a + PARAMETER C_MEM_BASEADDR = 0x00000000 + PARAMETER C_MEM_HIGHADDR = 0x0fffffff + BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC + PORT mc_mibclk = clk_125_0000MHzPLL0_ADJUST + PORT mi_mcclk90 = clk_125_0000MHz90PLL0_ADJUST + PORT mi_mcreset = sys_bus_reset + PORT mi_mcclkdiv2 = clk_62_5000MHzPLL0_ADJUST + PORT mi_mcclk_200 = clk_200_0000MHz + PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ_pin + PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS_pin + PORT DDR2_DQS_N = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin + PORT DDR2_A = fpga_0_DDR2_SDRAM_DDR2_A_pin + PORT DDR2_BA = fpga_0_DDR2_SDRAM_DDR2_BA_pin + PORT DDR2_RAS_N = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin + PORT DDR2_CAS_N = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin + PORT DDR2_WE_N = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin + PORT DDR2_CS_N = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin + PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT_pin + PORT DDR2_CKE = fpga_0_DDR2_SDRAM_DDR2_CKE_pin + PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM_pin + PORT DDR2_CK = fpga_0_DDR2_SDRAM_DDR2_CK_pin + PORT DDR2_CK_N = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin +END + +BEGIN xps_sysace + PARAMETER INSTANCE = SysACE_CompactFlash + PARAMETER C_MEM_WIDTH = 16 + PARAMETER C_FAMILY = virtex5 + PARAMETER HW_VER = 1.01.a + PARAMETER C_BASEADDR = 0x83600000 + PARAMETER C_HIGHADDR = 0x8360ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin + PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin + PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin + PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin + PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin + PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin + PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin +END + +BEGIN fcb_v20 + PARAMETER INSTANCE = ppc440_0_fcb_v20 + PARAMETER HW_VER = 1.00.a + PORT FCB_CLK = clk_125_0000MHzPLL0_ADJUST + PORT SYS_RST = sys_bus_reset +END + +BEGIN apu_fpu_virtex5 + PARAMETER INSTANCE = ppc440_0_apu_fpu_virtex5 + PARAMETER C_DOUBLE_PRECISION = 0 + PARAMETER HW_VER = 1.01.a + BUS_INTERFACE SFCB2 = ppc440_0_fcb_v20 +END + +BEGIN clock_generator + PARAMETER INSTANCE = clock_generator_0 + PARAMETER C_CLKIN_FREQ = 100000000 + PARAMETER C_CLKFBIN_FREQ = 125000000 + PARAMETER C_CLKOUT0_FREQ = 125000000 + PARAMETER C_CLKOUT0_PHASE = 90 + PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST + PARAMETER C_CLKOUT0_BUF = TRUE + PARAMETER C_CLKOUT1_FREQ = 125000000 + PARAMETER C_CLKOUT1_PHASE = 0 + PARAMETER C_CLKOUT1_GROUP = PLL0 + PARAMETER C_CLKOUT1_BUF = TRUE + PARAMETER C_CLKOUT2_FREQ = 125000000 + PARAMETER C_CLKOUT2_PHASE = 0 + PARAMETER C_CLKOUT2_GROUP = PLL0_ADJUST + PARAMETER C_CLKOUT2_BUF = TRUE + PARAMETER C_CLKOUT3_FREQ = 200000000 + PARAMETER C_CLKOUT3_PHASE = 0 + PARAMETER C_CLKOUT3_GROUP = NONE + PARAMETER C_CLKOUT3_BUF = TRUE + PARAMETER C_CLKOUT4_FREQ = 62500000 + PARAMETER C_CLKOUT4_PHASE = 0 + PARAMETER C_CLKOUT4_GROUP = PLL0_ADJUST + PARAMETER C_CLKOUT4_BUF = TRUE + PARAMETER C_CLKFBOUT_FREQ = 125000000 + PARAMETER C_CLKFBOUT_BUF = TRUE + PARAMETER HW_VER = 3.00.a + PORT CLKIN = dcm_clk_s + PORT CLKFBIN = SRAM_CLK_FB_s + PORT CLKOUT0 = clk_125_0000MHz90PLL0_ADJUST + PORT CLKOUT1 = clk_125_0000MHzPLL0 + PORT CLKOUT2 = clk_125_0000MHzPLL0_ADJUST + PORT CLKOUT3 = clk_200_0000MHz + PORT CLKOUT4 = clk_62_5000MHzPLL0_ADJUST + PORT CLKFBOUT = SRAM_CLK_OUT_s + PORT RST = net_gnd + PORT LOCKED = Dcm_all_locked +END + +BEGIN jtagppc_cntlr + PARAMETER INSTANCE = jtagppc_cntlr_inst + PARAMETER HW_VER = 2.01.c + BUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_bus +END + +BEGIN proc_sys_reset + PARAMETER INSTANCE = proc_sys_reset_0 + PARAMETER C_EXT_RESET_HIGH = 0 + PARAMETER HW_VER = 2.00.a + BUS_INTERFACE RESETPPC0 = ppc_reset_bus + PORT Slowest_sync_clk = clk_125_0000MHzPLL0_ADJUST + PORT Ext_Reset_In = sys_rst_s + PORT Dcm_locked = Dcm_all_locked + PORT Bus_Struct_Reset = sys_bus_reset + PORT Peripheral_Reset = sys_periph_reset +END + +BEGIN xps_intc + PARAMETER INSTANCE = xps_intc_0 + PARAMETER HW_VER = 2.00.a + PARAMETER C_BASEADDR = 0x81800000 + PARAMETER C_HIGHADDR = 0x8180ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT Intr = fpga_0_Ethernet_MAC_MDINT_pin&RS232_Uart_1_Interrupt + PORT Irq = ppc440_0_EICC440EXTIRQ +END + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/revup/system_mss.11.1 b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/revup/system_mss.11.1 new file mode 100644 index 000000000..aa363ea29 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/revup/system_mss.11.1 @@ -0,0 +1,131 @@ + + PARAMETER VERSION = 2.2.0 + + +BEGIN OS + PARAMETER OS_NAME = standalone + PARAMETER OS_VER = 2.00.a + PARAMETER PROC_INSTANCE = ppc440_0 + PARAMETER STDIN = RS232_Uart_1 + PARAMETER STDOUT = RS232_Uart_1 +END + + +BEGIN PROCESSOR + PARAMETER DRIVER_NAME = cpu_ppc440 + PARAMETER DRIVER_VER = 1.00.b + PARAMETER HW_INSTANCE = ppc440_0 + PARAMETER COMPILER = powerpc-eabi-gcc + PARAMETER ARCHIVER = powerpc-eabi-ar +END + + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1_bram +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = uartlite + PARAMETER DRIVER_VER = 1.14.a + PARAMETER HW_INSTANCE = RS232_Uart_1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.13.a + PARAMETER HW_INSTANCE = LEDs_8Bit +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.13.a + PARAMETER HW_INSTANCE = LEDs_Positions +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.13.a + PARAMETER HW_INSTANCE = Push_Buttons_5Bit +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.13.a + PARAMETER HW_INSTANCE = DIP_Switches_8Bit +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = iic + PARAMETER DRIVER_VER = 1.14.a + PARAMETER HW_INSTANCE = IIC_EEPROM +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = emc + PARAMETER DRIVER_VER = 2.00.a + PARAMETER HW_INSTANCE = SRAM +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = pcie + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = PCIe_Bridge +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = emaclite + PARAMETER DRIVER_VER = 1.14.a + PARAMETER HW_INSTANCE = Ethernet_MAC +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = memcon + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = DDR2_SDRAM +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = sysace + PARAMETER DRIVER_VER = 1.12.a + PARAMETER HW_INSTANCE = SysACE_CompactFlash +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = apu_fpu_virtex5 + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = ppc440_0_apu_fpu_virtex5 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = clock_generator_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = jtagppc_cntlr_inst +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = proc_sys_reset_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = intc + PARAMETER DRIVER_VER = 1.11.a + PARAMETER HW_INSTANCE = xps_intc_0 +END + + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/revup/system_xmp.11.1 b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/revup/system_xmp.11.1 new file mode 100644 index 000000000..8f5b60051 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/revup/system_xmp.11.1 @@ -0,0 +1,69 @@ +#Please do not modify this file by hand +XmpVersion: 11.1 +VerMgmt: 11.1 +IntStyle: default +MHS File: system.mhs +MSS File: system.mss +Architecture: virtex5 +Device: xc5vfx70t +Package: ff1136 +SpeedGrade: -1 +UserCmd1: +UserCmd1Type: 0 +UserCmd2: +UserCmd2Type: 0 +GenSimTB: 0 +SdkExportBmmBit: 1 +SdkExportDir: SDK/SDK_Export +InsertNoPads: 0 +WarnForEAArch: 1 +HdlLang: VHDL +SimModel: BEHAVIORAL +UcfFile: data/system.ucf +EnableParTimingError: 1 +ShowLicenseDialog: 1 +Processor: ppc440_0 +BootLoop: 1 +XmdStub: 0 +SwProj: RTOSDemo +Processor: ppc440_0 +Executable: RTOSDemo/executable.elf +Source: RTOSDemo/../../Common/Minimal/BlockQ.c +Source: RTOSDemo/../../Common/Minimal/blocktim.c +Source: RTOSDemo/../../Common/Minimal/comtest.c +Source: RTOSDemo/../../Common/Minimal/countsem.c +Source: RTOSDemo/../../Common/Minimal/death.c +Source: RTOSDemo/../../Common/Minimal/dynamic.c +Source: RTOSDemo/../../Common/Minimal/flash.c +Source: RTOSDemo/../../Common/Minimal/GenQTest.c +Source: RTOSDemo/../../Common/Minimal/integer.c +Source: RTOSDemo/../../Common/Minimal/QPeek.c +Source: RTOSDemo/../../Common/Minimal/recmutex.c +Source: RTOSDemo/../../Common/Minimal/semtest.c +Source: RTOSDemo/../../../Source/tasks.c +Source: RTOSDemo/../../../Source/list.c +Source: RTOSDemo/../../../Source/queue.c +Source: RTOSDemo/../../../Source/croutine.c +Source: RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S +Source: RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c +Source: RTOSDemo/../../../Source/portable/MemMang/heap_2.c +Source: RTOSDemo/flop/flop-reg-test.c +Source: RTOSDemo/flop/flop.c +Source: RTOSDemo/partest/partest.c +Source: RTOSDemo/serial/serial.c +Source: RTOSDemo/main.c +DefaultInit: EXECUTABLE +InitBram: 0 +Active: 1 +CompilerOptLevel: 0 +GlobPtrOpt: 0 +DebugSym: 1 +ProfileFlag: 0 +SearchIncl: ../../Source/include ../../Source/portable/GCC/PPC440_Xilinx ../Common/include ./RTOSDemo ./RTOSDemo/flop +ProgStart: +StackSize: +HeapSize: +LinkerScript: RTOSDemo/RTOSDemo_linker_script.ld +ProgCCFlags: -D GCC_PPC440 -mregnames +CompileInXps: 1 +NonXpsApp: 0 diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.bsb b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.bsb new file mode 100644 index 000000000..19ffa7ee7 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.bsb @@ -0,0 +1 @@ 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\ No newline at end of file diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.log b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.log new file mode 100644 index 000000000..6c00f76e6 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.log @@ -0,0 +1,99 @@ +No logfile was found. + +WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'! + +WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'! + +Generating Block Diagram to Buffer + +Generated Block Diagram SVG + +The project file (XMP) has changed on disk. + +WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'! + +WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'! + +WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'! + +WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'! + +At Local date and time: Tue Jun 30 18:34:41 2009 + make -f system.make hwclean started... + +rm -f implementation/system.ngc +rm -f platgen.log +rm -f __xps/ise/_xmsgs/platgen.xmsgs +rm -f implementation/system.bmm +rm -f implementation/system.bit +rm -f implementation/system.ncd +rm -f implementation/system_bd.bmm +rm -f implementation/system_map.ncd +rm -f __xps/system_routed +rm -rf implementation synthesis xst hdl +rm -rf xst.srp system.srp +rm -f __xps/ise/_xmsgs/bitinit.xmsgs + + +Done! + +At Local date and time: Tue Jun 30 18:34:46 2009 + make -f system.make bitsclean started... + +rm -f implementation/system.bit +rm -f implementation/system.ncd +rm -f implementation/system_bd.bmm +rm -f implementation/system_map.ncd +rm -f __xps/system_routed + + +Done! + +At Local date and time: Tue Jun 30 18:34:52 2009 + make -f system.make netlistclean started... + +rm -f implementation/system.ngc +rm -f platgen.log +rm -f __xps/ise/_xmsgs/platgen.xmsgs +rm -f implementation/system.bmm + + +Done! + +At Local date and time: Tue Jun 30 18:34:57 2009 + make -f system.make libsclean started... + +rm -rf ppc440_0/ +rm -f libgen.log +rm -f __xps/ise/_xmsgs/libgen.xmsgs + + +Done! + +At Local date and time: Tue Jun 30 18:35:02 2009 + make -f system.make programclean started... + +rm -f RTOSDemo/executable.elf + + +Done! + +At Local date and time: Tue Jun 30 18:35:08 2009 + make -f system.make swclean started... + +rm -rf ppc440_0/ +rm -f libgen.log +rm -f __xps/ise/_xmsgs/libgen.xmsgs +rm -f RTOSDemo/executable.elf + + +Done! + +Writing filter settings.... + +Done writing filter settings to: + C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters + +Done writing Tab View settings to: + C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.make b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.make new file mode 100644 index 000000000..1d8de4e4b --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.make @@ -0,0 +1,277 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.xmp +# +# WARNING : This file will be re-generated every time a command +# to run a make target is invoked. So, any changes made to this +# file manually, will be lost when make is invoked next. +################################################################# + +# Name of the Microprocessor system +# The hardware specification of the system is in file : +# C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs +# The software specification of the system is in file : +# C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mss + +include system_incl.make + +################################################################# +# PHONY TARGETS +################################################################# +.PHONY: dummy +.PHONY: netlistclean +.PHONY: bitsclean +.PHONY: simclean +.PHONY: exporttosdk + +################################################################# +# EXTERNAL TARGETS +################################################################# +all: + @echo "Makefile to build a Microprocessor system :" + @echo "Run make with any of the following targets" + @echo " " + @echo " netlist : Generates the netlist for the given MHS " + @echo " bits : Runs Implementation tools to generate the bitstream" + @echo " exporttosdk: Export files to SDK" + @echo " " + @echo " libs : Configures the sw libraries for this system" + @echo " program : Compiles the program sources for all the processor instances" + @echo " " + @echo " init_bram: Initializes bitstream with BRAM data" + @echo " ace : Generate ace file from bitstream and elf" + @echo " download : Downloads the bitstream onto the board" + @echo " " + @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode" + @echo " simmodel : Generates HDL simulation models for chosen simulation mode" + @echo " behavioral_model : Generates behavioral HDL models with BRAM initialization" + @echo " structural_model : Generates structural simulation HDL models with BRAM initialization" + @echo " timing : Generates timing simulation HDL models with BRAM initialization" + @echo " " + @echo " netlistclean: Deletes netlist" + @echo " bitsclean: Deletes bit, ncd, bmm files" + @echo " hwclean : Deletes implementation dir" + @echo " libsclean: Deletes sw libraries" + @echo " programclean: Deletes compiled ELF files" + @echo " swclean : Deletes sw libraries and ELF files" + @echo " simclean : Deletes simulation dir" + @echo " clean : Deletes all generated files/directories" + @echo " " + @echo " make : (Default)" + @echo " Creates a Microprocessor system using default initializations" + @echo " specified for each processor in MSS file" + + +bits: $(SYSTEM_BIT) + +ace: $(SYSTEM_ACE) + +exporttosdk: $(SYSTEM_HW_HANDOFF_DEP) + +netlist: $(POSTSYN_NETLIST) + +libs: $(LIBRARIES) + +program: $(ALL_USER_ELF_FILES) + +download: $(DOWNLOAD_BIT) dummy + @echo "*********************************************" + @echo "Downloading Bitstream onto the target board" + @echo "*********************************************" + impact -batch etc/download.cmd + +init_bram: $(DOWNLOAD_BIT) + +sim: $(DEFAULT_SIM_SCRIPT) + cd simulation/behavioral; \ + $(SIM_CMD) & + +simmodel: $(DEFAULT_SIM_SCRIPT) + +behavioral_model: $(BEHAVIORAL_SIM_SCRIPT) + +structural_model: $(STRUCTURAL_SIM_SCRIPT) + +clean: hwclean libsclean programclean simclean + rm -f _impact.cmd + +hwclean: netlistclean bitsclean + rm -rf implementation synthesis xst hdl + rm -rf xst.srp $(SYSTEM).srp + rm -f __xps/ise/_xmsgs/bitinit.xmsgs + +netlistclean: + rm -f $(POSTSYN_NETLIST) + rm -f platgen.log + rm -f __xps/ise/_xmsgs/platgen.xmsgs + rm -f $(BMM_FILE) + +bitsclean: + rm -f $(SYSTEM_BIT) + rm -f implementation/$(SYSTEM).ncd + rm -f implementation/$(SYSTEM)_bd.bmm + rm -f implementation/$(SYSTEM)_map.ncd + rm -f __xps/$(SYSTEM)_routed + +simclean: + rm -rf simulation/behavioral + rm -f simgen.log + rm -f __xps/ise/_xmsgs/simgen.xmsgs + +swclean: libsclean programclean + @echo "" + +libsclean: $(LIBSCLEAN_TARGETS) + rm -f libgen.log + rm -f __xps/ise/_xmsgs/libgen.xmsgs + +programclean: $(PROGRAMCLEAN_TARGETS) + +################################################################# +# SOFTWARE PLATFORM FLOW +################################################################# + + +$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt + @echo "*********************************************" + @echo "Creating software libraries..." + @echo "*********************************************" + libgen $(LIBGEN_OPTIONS) $(MSSFILE) + + +ppc440_0_libsclean: + rm -rf ppc440_0/ + +################################################################# +# SOFTWARE APPLICATION RTOSDEMO +################################################################# + +RTOSDemo_program: $(RTOSDEMO_OUTPUT) + +$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \ + $(LIBRARIES) __xps/rtosdemo_compiler.opt + @mkdir -p $(RTOSDEMO_OUTPUT_DIR) + $(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \ + $(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \ + $(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS) + $(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT) + @echo "" + +RTOSDemo_programclean: + rm -f $(RTOSDEMO_OUTPUT) + +################################################################# +# BOOTLOOP ELF FILES +################################################################# + + + +$(PPC440_0_BOOTLOOP): $(PPC440_BOOTLOOP) + @mkdir -p $(BOOTLOOP_DIR) + cp -f $(PPC440_BOOTLOOP) $(PPC440_0_BOOTLOOP) + +################################################################# +# HARDWARE IMPLEMENTATION FLOW +################################################################# + + +$(BMM_FILE) \ +$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ + $(CORE_STATE_DEVELOPMENT_FILES) + @echo "****************************************************" + @echo "Creating system netlist for hardware specification.." + @echo "****************************************************" + platgen $(PLATGEN_OPTIONS) $(MHSFILE) + +$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES) + @echo "Running synthesis..." + bash -c "cd synthesis; ./synthesis.sh" + +__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY) + @echo "*********************************************" + @echo "Running Xilinx Implementation tools.." + @echo "*********************************************" + @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf + @cp -f etc/fast_runtime.opt implementation/xflow.opt + xflow -wd implementation -p $(DEVICE) -implement xflow.opt -ise ../__xps/ise/$(SYSTEM).ise $(SYSTEM).ngc + touch __xps/$(SYSTEM)_routed + +$(SYSTEM_BIT): __xps/$(SYSTEM)_routed $(BITGEN_UT_FILE) + xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par + @echo "*********************************************" + @echo "Running Bitgen.." + @echo "*********************************************" + @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut + cd implementation; bitgen -w -f bitgen.ut $(SYSTEM); cd .. + +$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt + @cp -f implementation/$(SYSTEM)_bd.bmm . + @echo "*********************************************" + @echo "Initializing BRAM contents of the bitstream" + @echo "*********************************************" + bitinit -p $(DEVICE) $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \ + -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT) + @rm -f $(SYSTEM)_bd.bmm + +$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT) + @echo "*********************************************" + @echo "Creating system ace file" + @echo "*********************************************" + xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -target ppc_hw -ace $(SYSTEM_ACE) + +################################################################# +# EXPORT_TO_SDK FLOW +################################################################# + + +$(SYSTEM_HW_HANDOFF): $(MHSFILE) __xps/platgen.opt + mkdir -p $(SDK_EXPORT_DIR) + psf2Edward.exe -inp $(SYSTEM).xmp -xml $(SDK_EXPORT_DIR)/$(SYSTEM).xml $(SEARCHPATHOPT) + xdsgen.exe -inp $(SYSTEM).xmp -report $(SDK_EXPORT_DIR)/$(SYSTEM).html $(SEARCHPATHOPT) -make_docs_local + +$(SYSTEM_HW_HANDOFF_BIT): $(SYSTEM_BIT) + @rm -rf $(SYSTEM_HW_HANDOFF_BIT) + @cp -f $(SYSTEM_BIT) $(SDK_EXPORT_DIR)/ + +$(SYSTEM_HW_HANDOFF_BMM): implementation/$(SYSTEM)_bd.bmm + @rm -rf $(SYSTEM_HW_HANDOFF_BMM) + @cp -f implementation/$(SYSTEM)_bd.bmm $(SDK_EXPORT_DIR)/ + +################################################################# +# SIMULATION FLOW +################################################################# + + +################## BEHAVIORAL SIMULATION ################## + +$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \ + $(BRAMINIT_ELF_FILES) + @echo "*********************************************" + @echo "Creating behavioral simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE) + +################## STRUCTURAL SIMULATION ################## + +$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \ + $(BRAMINIT_ELF_FILES) + @echo "*********************************************" + @echo "Creating structural simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE) + + +################## TIMING SIMULATION ################## + +implementation/$(SYSTEM).ncd: __xps/$(SYSTEM)_routed + +$(TIMING_SIM_SCRIPT): implementation/$(SYSTEM).ncd __xps/simgen.opt \ + $(BRAMINIT_ELF_FILES) + @echo "*********************************************" + @echo "Creating timing simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE) + +dummy: + @echo "" + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.mhs b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.mhs new file mode 100644 index 000000000..8431bfdde --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.mhs @@ -0,0 +1,474 @@ + +# ############################################################################## +# Created by Base System Builder Wizard for Xilinx EDK 11.1 Build EDK_L.29.1 +# Sat Jun 13 13:14:11 2009 +# Target Board: Xilinx Virtex 5 ML507 Evaluation Platform Rev A +# Family: virtex5 +# Device: xc5vfx70t +# Package: ff1136 +# Speed Grade: -1 +# Processor number: 1 +# Processor 1: ppc440_0 +# Processor clock frequency: 125.0 +# Bus clock frequency: 125.0 +# Debug Interface: FPGA JTAG +# ############################################################################## + PARAMETER VERSION = 2.1.0 + + + PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I + PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O + PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7] + PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO_pin, DIR = IO, VEC = [0:4] + PORT fpga_0_Push_Buttons_5Bit_GPIO_IO_pin = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin, DIR = IO, VEC = [0:4] + PORT fpga_0_DIP_Switches_8Bit_GPIO_IO_pin = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7] + PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda_pin, DIR = IO + PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl_pin, DIR = IO + PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat, DIR = O, VEC = [7:30] + PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN_pin, DIR = O + PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN_pin, DIR = O + PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN_pin, DIR = O + PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN_pin, DIR = O, VEC = [0:3] + PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN_pin, DIR = O + PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ_pin, DIR = IO, VEC = [0:31] + PORT fpga_0_SRAM_ZBT_CLK_OUT_pin = SRAM_CLK_OUT_s, DIR = O + PORT fpga_0_SRAM_ZBT_CLK_FB_pin = SRAM_CLK_FB_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000 + PORT fpga_0_PCIe_Bridge_RXN_pin = fpga_0_PCIe_Bridge_RXN_pin, DIR = I + PORT fpga_0_PCIe_Bridge_RXP_pin = fpga_0_PCIe_Bridge_RXP_pin, DIR = I + PORT fpga_0_PCIe_Bridge_TXN_pin = fpga_0_PCIe_Bridge_TXN_pin, DIR = O + PORT fpga_0_PCIe_Bridge_TXP_pin = fpga_0_PCIe_Bridge_TXP_pin, DIR = O + PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk_pin, DIR = I + PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk_pin, DIR = I + PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs_pin, DIR = I + PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv_pin, DIR = I + PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data_pin, DIR = I, VEC = [3:0] + PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col_pin, DIR = I + PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er_pin, DIR = I + PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n_pin, DIR = O + PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en_pin, DIR = O + PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data_pin, DIR = O, VEC = [3:0] + PORT fpga_0_Ethernet_MAC_MDINT_pin = fpga_0_Ethernet_MAC_MDINT_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM + PORT fpga_0_DDR2_SDRAM_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_DDR2_DQ_pin, DIR = IO, VEC = [63:0] + PORT fpga_0_DDR2_SDRAM_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_pin, DIR = IO, VEC = [7:0] + PORT fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin, DIR = IO, VEC = [7:0] + PORT fpga_0_DDR2_SDRAM_DDR2_A_pin = fpga_0_DDR2_SDRAM_DDR2_A_pin, DIR = O, VEC = [12:0] + PORT fpga_0_DDR2_SDRAM_DDR2_BA_pin = fpga_0_DDR2_SDRAM_DDR2_BA_pin, DIR = O, VEC = [1:0] + PORT fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin, DIR = O + PORT fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin, DIR = O + PORT fpga_0_DDR2_SDRAM_DDR2_WE_N_pin = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin, DIR = O + PORT fpga_0_DDR2_SDRAM_DDR2_CS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin, DIR = O + PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT_pin, DIR = O, VEC = [1:0] + PORT fpga_0_DDR2_SDRAM_DDR2_CKE_pin = fpga_0_DDR2_SDRAM_DDR2_CKE_pin, DIR = O + PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM_pin, DIR = O, VEC = [7:0] + PORT fpga_0_DDR2_SDRAM_DDR2_CK_pin = fpga_0_DDR2_SDRAM_DDR2_CK_pin, DIR = O, VEC = [1:0] + PORT fpga_0_DDR2_SDRAM_DDR2_CK_N_pin = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin, DIR = O, VEC = [1:0] + PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin, DIR = O, VEC = [6:0] + PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin, DIR = I + PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin, DIR = I + PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin, DIR = O + PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin, DIR = O + PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin, DIR = O + PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin, DIR = IO, VEC = [15:0] + PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 + PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0 + PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK + PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK + + +BEGIN ppc440_virtex5 + PARAMETER INSTANCE = ppc440_0 + PARAMETER C_IDCR_BASEADDR = 0b0000000000 + PARAMETER C_IDCR_HIGHADDR = 0b0011111111 + PARAMETER C_APU_CONTROL = 0b00000010000000001 + PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x003FFE00 + PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00C00000 + PARAMETER C_PPC440MC_CONTROL = 0xF810008F + PARAMETER C_SPLB0_USE_MPLB_ADDR = 1 + PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 1 + PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0 + PARAMETER HW_VER = 1.01.a + PARAMETER C_SPLB0_RNG0_MPLB_BASEADDR = 0x80000000 + PARAMETER C_SPLB0_RNG0_MPLB_HIGHADDR = 0xffffffff + PARAMETER C_SPLB0_RNG_MC_BASEADDR = 0x00000000 + PARAMETER C_SPLB0_RNG_MC_HIGHADDR = 0x0fffffff + BUS_INTERFACE MPLB = plb_v46_0 + BUS_INTERFACE SPLB0 = ppc440_0_SPLB0 + BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC + BUS_INTERFACE MFCB = ppc440_0_fcb_v20 + BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus + BUS_INTERFACE RESETPPC = ppc_reset_bus + PORT CPMC440CLK = clk_125_0000MHzPLL0 + PORT CPMINTERCONNECTCLK = clk_125_0000MHzPLL0 + PORT CPMINTERCONNECTCLKNTO1 = net_vcc + PORT EICC440EXTIRQ = ppc440_0_EICC440EXTIRQ + PORT CPMMCCLK = clk_125_0000MHzPLL0_ADJUST + PORT CPMPPCMPLBCLK = clk_125_0000MHzPLL0_ADJUST + PORT CPMPPCS0PLBCLK = clk_125_0000MHzPLL0_ADJUST +END + +BEGIN plb_v46 + PARAMETER INSTANCE = plb_v46_0 + PARAMETER C_DCR_INTFCE = 0 + PARAMETER C_FAMILY = virtex5 + PARAMETER HW_VER = 1.04.a + PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST + PORT SYS_Rst = sys_bus_reset +END + +BEGIN xps_bram_if_cntlr + PARAMETER INSTANCE = xps_bram_if_cntlr_1 + PARAMETER C_SPLB_NATIVE_DWIDTH = 64 + PARAMETER C_SPLB_SUPPORT_BURSTS = 1 + PARAMETER C_SPLB_P2P = 0 + PARAMETER C_FAMILY = virtex5 + PARAMETER HW_VER = 1.00.b + PARAMETER C_BASEADDR = 0xffffe000 + PARAMETER C_HIGHADDR = 0xffffffff + BUS_INTERFACE SPLB = plb_v46_0 + BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port +END + +BEGIN bram_block + PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram + PARAMETER C_FAMILY = virtex5 + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port +END + +BEGIN xps_uartlite + PARAMETER INSTANCE = RS232_Uart_1 + PARAMETER C_FAMILY = virtex5 + PARAMETER C_BAUDRATE = 9600 + PARAMETER C_DATA_BITS = 8 + PARAMETER C_USE_PARITY = 0 + PARAMETER C_ODD_PARITY = 0 + PARAMETER HW_VER = 1.01.a + PARAMETER C_BASEADDR = 0x84000000 + PARAMETER C_HIGHADDR = 0x8400ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT RX = fpga_0_RS232_Uart_1_RX_pin + PORT TX = fpga_0_RS232_Uart_1_TX_pin + PORT Interrupt = RS232_Uart_1_Interrupt +END + +BEGIN xps_gpio + PARAMETER INSTANCE = LEDs_8Bit + PARAMETER C_FAMILY = virtex5 + PARAMETER C_ALL_INPUTS = 0 + PARAMETER C_GPIO_WIDTH = 8 + PARAMETER C_INTERRUPT_PRESENT = 0 + PARAMETER C_IS_DUAL = 0 + PARAMETER HW_VER = 2.00.a + PARAMETER C_BASEADDR = 0x81440000 + PARAMETER C_HIGHADDR = 0x8144ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO_pin +END + +BEGIN xps_gpio + PARAMETER INSTANCE = LEDs_Positions + PARAMETER C_FAMILY = virtex5 + PARAMETER C_ALL_INPUTS = 0 + PARAMETER C_GPIO_WIDTH = 5 + PARAMETER C_INTERRUPT_PRESENT = 0 + PARAMETER C_IS_DUAL = 0 + PARAMETER HW_VER = 2.00.a + PARAMETER C_BASEADDR = 0x81420000 + PARAMETER C_HIGHADDR = 0x8142ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO_pin +END + +BEGIN xps_gpio + PARAMETER INSTANCE = Push_Buttons_5Bit + PARAMETER C_FAMILY = virtex5 + PARAMETER C_ALL_INPUTS = 1 + PARAMETER C_GPIO_WIDTH = 5 + PARAMETER C_INTERRUPT_PRESENT = 0 + PARAMETER C_IS_DUAL = 0 + PARAMETER HW_VER = 2.00.a + PARAMETER C_BASEADDR = 0x81400000 + PARAMETER C_HIGHADDR = 0x8140ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT GPIO_IO = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin +END + +BEGIN xps_gpio + PARAMETER INSTANCE = DIP_Switches_8Bit + PARAMETER C_FAMILY = virtex5 + PARAMETER C_ALL_INPUTS = 1 + PARAMETER C_GPIO_WIDTH = 8 + PARAMETER C_INTERRUPT_PRESENT = 0 + PARAMETER C_IS_DUAL = 0 + PARAMETER HW_VER = 2.00.a + PARAMETER C_BASEADDR = 0x81460000 + PARAMETER C_HIGHADDR = 0x8146ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT GPIO_IO = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin +END + +BEGIN xps_iic + PARAMETER INSTANCE = IIC_EEPROM + PARAMETER C_IIC_FREQ = 100000 + PARAMETER C_TEN_BIT_ADR = 0 + PARAMETER C_FAMILY = virtex5 + PARAMETER HW_VER = 2.01.a + PARAMETER C_BASEADDR = 0x81600000 + PARAMETER C_HIGHADDR = 0x8160ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT Sda = fpga_0_IIC_EEPROM_Sda_pin + PORT Scl = fpga_0_IIC_EEPROM_Scl_pin +END + +BEGIN xps_mch_emc + PARAMETER INSTANCE = SRAM + PARAMETER C_FAMILY = virtex5 + PARAMETER C_NUM_BANKS_MEM = 1 + PARAMETER C_NUM_CHANNELS = 0 + PARAMETER C_MEM0_WIDTH = 32 + PARAMETER C_MAX_MEM_WIDTH = 32 + PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0 + PARAMETER C_SYNCH_MEM_0 = 1 + PARAMETER C_TCEDV_PS_MEM_0 = 0 + PARAMETER C_TAVDV_PS_MEM_0 = 0 + PARAMETER C_THZCE_PS_MEM_0 = 0 + PARAMETER C_THZOE_PS_MEM_0 = 0 + PARAMETER C_TWC_PS_MEM_0 = 0 + PARAMETER C_TWP_PS_MEM_0 = 0 + PARAMETER C_TLZWE_PS_MEM_0 = 0 + PARAMETER HW_VER = 3.00.a + PARAMETER C_MEM0_BASEADDR = 0xf8000000 + PARAMETER C_MEM0_HIGHADDR = 0xf80fffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT RdClk = clk_125_0000MHzPLL0_ADJUST + PORT Mem_A = 0b0000000 & fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat & 0b0 + PORT Mem_CEN = fpga_0_SRAM_Mem_CEN_pin + PORT Mem_OEN = fpga_0_SRAM_Mem_OEN_pin + PORT Mem_WEN = fpga_0_SRAM_Mem_WEN_pin + PORT Mem_BEN = fpga_0_SRAM_Mem_BEN_pin + PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN_pin + PORT Mem_DQ = fpga_0_SRAM_Mem_DQ_pin +END + +BEGIN plbv46_pcie + PARAMETER INSTANCE = PCIe_Bridge + PARAMETER C_FAMILY = virtex5 + PARAMETER C_IPIFBAR_NUM = 2 + PARAMETER C_PCIBAR_NUM = 1 + PARAMETER C_DEVICE_ID = 0x0505 + PARAMETER C_VENDOR_ID = 0x10EE + PARAMETER C_CLASS_CODE = 0x058000 + PARAMETER C_REV_ID = 0x00 + PARAMETER C_SUBSYSTEM_ID = 0x0000 + PARAMETER C_SUBSYSTEM_VENDOR_ID = 0x0000 + PARAMETER C_COMP_TIMEOUT = 1 + PARAMETER C_IPIFBAR2PCIBAR_0 = 0x00000000 + PARAMETER C_IPIFBAR2PCIBAR_1 = 0x00000000 + PARAMETER C_PCIBAR2IPIFBAR_0 = 0xf8000000 + PARAMETER C_PCIBAR2IPIFBAR_1 = 0x00000000 + PARAMETER C_PCIBAR_LEN_0 = 20 + PARAMETER C_PCIBAR_LEN_1 = 28 + PARAMETER C_BOARD = ml507 + PARAMETER HW_VER = 3.00.b + PARAMETER C_BASEADDR = 0x85c00000 + PARAMETER C_HIGHADDR = 0x85c0ffff + PARAMETER C_IPIFBAR_0 = 0xc0000000 + PARAMETER C_IPIFBAR_HIGHADDR_0 = 0xdfffffff + PARAMETER C_IPIFBAR_1 = 0xe0000000 + PARAMETER C_IPIFBAR_HIGHADDR_1 = 0xefffffff + BUS_INTERFACE SPLB = plb_v46_0 + BUS_INTERFACE MPLB = ppc440_0_SPLB0 + PORT PERSTN = net_vcc + PORT REFCLK = PCIe_Diff_Clk + PORT RXN = fpga_0_PCIe_Bridge_RXN_pin + PORT RXP = fpga_0_PCIe_Bridge_RXP_pin + PORT TXN = fpga_0_PCIe_Bridge_TXN_pin + PORT TXP = fpga_0_PCIe_Bridge_TXP_pin + PORT MSI_request = net_gnd +END + +BEGIN plb_v46 + PARAMETER INSTANCE = ppc440_0_SPLB0 + PARAMETER C_FAMILY = virtex5 + PARAMETER HW_VER = 1.04.a + PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST + PORT SYS_Rst = sys_bus_reset +END + +BEGIN xps_ethernetlite + PARAMETER INSTANCE = Ethernet_MAC + PARAMETER C_FAMILY = virtex5 + PARAMETER HW_VER = 2.01.a + PARAMETER C_BASEADDR = 0x81000000 + PARAMETER C_HIGHADDR = 0x8100ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk_pin + PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk_pin + PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs_pin + PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv_pin + PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data_pin + PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col_pin + PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er_pin + PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n_pin + PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en_pin + PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data_pin +END + +BEGIN ppc440mc_ddr2 + PARAMETER INSTANCE = DDR2_SDRAM + PARAMETER C_DDR_BAWIDTH = 2 + PARAMETER C_NUM_CLK_PAIRS = 2 + PARAMETER C_DDR_DWIDTH = 64 + PARAMETER C_DDR_CAWIDTH = 10 + PARAMETER C_NUM_RANKS_MEM = 1 + PARAMETER C_CS_BITS = 0 + PARAMETER C_DDR_DM_WIDTH = 8 + PARAMETER C_DQ_BITS = 8 + PARAMETER C_DDR2_ODT_WIDTH = 2 + PARAMETER C_DDR2_ADDT_LAT = 0 + PARAMETER C_INCLUDE_ECC_SUPPORT = 0 + PARAMETER C_DDR2_ODT_SETTING = 1 + PARAMETER C_DQS_BITS = 3 + PARAMETER C_DDR_DQS_WIDTH = 8 + PARAMETER C_DDR_RAWIDTH = 13 + PARAMETER C_DDR_BURST_LENGTH = 4 + PARAMETER C_DDR_CAS_LAT = 4 + PARAMETER C_REG_DIMM = 0 + PARAMETER C_MIB_MC_CLOCK_RATIO = 1 + PARAMETER C_DDR_TREFI = 3900 + PARAMETER C_DDR_TRAS = 40000 + PARAMETER C_DDR_TRCD = 15000 + PARAMETER C_DDR_TRFC = 75000 + PARAMETER C_DDR_TRP = 15000 + PARAMETER C_DDR_TRTP = 7500 + PARAMETER C_DDR_TWR = 15000 + PARAMETER C_DDR_TWTR = 7500 + PARAMETER C_MC_MIBCLK_PERIOD_PS = 8000 + PARAMETER C_IDEL_HIGH_PERF = TRUE + PARAMETER C_NUM_IDELAYCTRL = 3 + PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1 + PARAMETER C_DQS_IO_COL = 0b000000000000000000 + PARAMETER C_DQ_IO_MS = 0b000000000111010100111101000011110001111000101110110000111100000110111100 + PARAMETER HW_VER = 2.00.b + PARAMETER C_MEM_BASEADDR = 0x00000000 + PARAMETER C_MEM_HIGHADDR = 0x0fffffff + BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC + PORT mc_mibclk = clk_125_0000MHzPLL0_ADJUST + PORT mi_mcclk90 = clk_125_0000MHz90PLL0_ADJUST + PORT mi_mcreset = sys_bus_reset + PORT mi_mcclkdiv2 = clk_62_5000MHzPLL0_ADJUST + PORT mi_mcclk_200 = clk_200_0000MHz + PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ_pin + PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS_pin + PORT DDR2_DQS_N = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin + PORT DDR2_A = fpga_0_DDR2_SDRAM_DDR2_A_pin + PORT DDR2_BA = fpga_0_DDR2_SDRAM_DDR2_BA_pin + PORT DDR2_RAS_N = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin + PORT DDR2_CAS_N = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin + PORT DDR2_WE_N = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin + PORT DDR2_CS_N = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin + PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT_pin + PORT DDR2_CKE = fpga_0_DDR2_SDRAM_DDR2_CKE_pin + PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM_pin + PORT DDR2_CK = fpga_0_DDR2_SDRAM_DDR2_CK_pin + PORT DDR2_CK_N = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin +END + +BEGIN xps_sysace + PARAMETER INSTANCE = SysACE_CompactFlash + PARAMETER C_MEM_WIDTH = 16 + PARAMETER C_FAMILY = virtex5 + PARAMETER HW_VER = 1.01.a + PARAMETER C_BASEADDR = 0x83600000 + PARAMETER C_HIGHADDR = 0x8360ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin + PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin + PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin + PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin + PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin + PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin + PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin +END + +BEGIN fcb_v20 + PARAMETER INSTANCE = ppc440_0_fcb_v20 + PARAMETER HW_VER = 1.00.a + PORT FCB_CLK = clk_125_0000MHzPLL0_ADJUST + PORT SYS_RST = sys_bus_reset +END + +BEGIN apu_fpu_virtex5 + PARAMETER INSTANCE = ppc440_0_apu_fpu_virtex5 + PARAMETER C_DOUBLE_PRECISION = 0 + PARAMETER HW_VER = 1.01.a + BUS_INTERFACE SFCB2 = ppc440_0_fcb_v20 +END + +BEGIN clock_generator + PARAMETER INSTANCE = clock_generator_0 + PARAMETER C_CLKIN_FREQ = 100000000 + PARAMETER C_CLKFBIN_FREQ = 125000000 + PARAMETER C_CLKOUT0_FREQ = 125000000 + PARAMETER C_CLKOUT0_PHASE = 90 + PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST + PARAMETER C_CLKOUT0_BUF = TRUE + PARAMETER C_CLKOUT1_FREQ = 125000000 + PARAMETER C_CLKOUT1_PHASE = 0 + PARAMETER C_CLKOUT1_GROUP = PLL0 + PARAMETER C_CLKOUT1_BUF = TRUE + PARAMETER C_CLKOUT2_FREQ = 125000000 + PARAMETER C_CLKOUT2_PHASE = 0 + PARAMETER C_CLKOUT2_GROUP = PLL0_ADJUST + PARAMETER C_CLKOUT2_BUF = TRUE + PARAMETER C_CLKOUT3_FREQ = 200000000 + PARAMETER C_CLKOUT3_PHASE = 0 + PARAMETER C_CLKOUT3_GROUP = NONE + PARAMETER C_CLKOUT3_BUF = TRUE + PARAMETER C_CLKOUT4_FREQ = 62500000 + PARAMETER C_CLKOUT4_PHASE = 0 + PARAMETER C_CLKOUT4_GROUP = PLL0_ADJUST + PARAMETER C_CLKOUT4_BUF = TRUE + PARAMETER C_CLKFBOUT_FREQ = 125000000 + PARAMETER C_CLKFBOUT_BUF = TRUE + PARAMETER HW_VER = 3.01.a + PORT CLKIN = dcm_clk_s + PORT CLKFBIN = SRAM_CLK_FB_s + PORT CLKOUT0 = clk_125_0000MHz90PLL0_ADJUST + PORT CLKOUT1 = clk_125_0000MHzPLL0 + PORT CLKOUT2 = clk_125_0000MHzPLL0_ADJUST + PORT CLKOUT3 = clk_200_0000MHz + PORT CLKOUT4 = clk_62_5000MHzPLL0_ADJUST + PORT CLKFBOUT = SRAM_CLK_OUT_s + PORT RST = net_gnd + PORT LOCKED = Dcm_all_locked +END + +BEGIN jtagppc_cntlr + PARAMETER INSTANCE = jtagppc_cntlr_inst + PARAMETER HW_VER = 2.01.c + BUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_bus +END + +BEGIN proc_sys_reset + PARAMETER INSTANCE = proc_sys_reset_0 + PARAMETER C_EXT_RESET_HIGH = 0 + PARAMETER HW_VER = 2.00.a + BUS_INTERFACE RESETPPC0 = ppc_reset_bus + PORT Slowest_sync_clk = clk_125_0000MHzPLL0_ADJUST + PORT Ext_Reset_In = sys_rst_s + PORT Dcm_locked = Dcm_all_locked + PORT Bus_Struct_Reset = sys_bus_reset + PORT Peripheral_Reset = sys_periph_reset +END + +BEGIN xps_intc + PARAMETER INSTANCE = xps_intc_0 + PARAMETER HW_VER = 2.00.a + PARAMETER C_BASEADDR = 0x81800000 + PARAMETER C_HIGHADDR = 0x8180ffff + BUS_INTERFACE SPLB = plb_v46_0 + PORT Intr = fpga_0_Ethernet_MAC_MDINT_pin&RS232_Uart_1_Interrupt + PORT Irq = ppc440_0_EICC440EXTIRQ +END + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.mss b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.mss new file mode 100644 index 000000000..ce5c2f78b --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.mss @@ -0,0 +1,131 @@ + + PARAMETER VERSION = 2.2.0 + + +BEGIN OS + PARAMETER OS_NAME = standalone + PARAMETER OS_VER = 2.00.a + PARAMETER PROC_INSTANCE = ppc440_0 + PARAMETER STDIN = RS232_Uart_1 + PARAMETER STDOUT = RS232_Uart_1 +END + + +BEGIN PROCESSOR + PARAMETER DRIVER_NAME = cpu_ppc440 + PARAMETER DRIVER_VER = 1.01.a + PARAMETER HW_INSTANCE = ppc440_0 + PARAMETER COMPILER = powerpc-eabi-gcc + PARAMETER ARCHIVER = powerpc-eabi-ar +END + + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1_bram +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = uartlite + PARAMETER DRIVER_VER = 1.14.a + PARAMETER HW_INSTANCE = RS232_Uart_1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.13.a + PARAMETER HW_INSTANCE = LEDs_8Bit +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.13.a + PARAMETER HW_INSTANCE = LEDs_Positions +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.13.a + PARAMETER HW_INSTANCE = Push_Buttons_5Bit +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.13.a + PARAMETER HW_INSTANCE = DIP_Switches_8Bit +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = iic + PARAMETER DRIVER_VER = 1.15.a + PARAMETER HW_INSTANCE = IIC_EEPROM +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = emc + PARAMETER DRIVER_VER = 2.00.a + PARAMETER HW_INSTANCE = SRAM +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = pcie + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = PCIe_Bridge +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = emaclite + PARAMETER DRIVER_VER = 1.14.a + PARAMETER HW_INSTANCE = Ethernet_MAC +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = memcon + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = DDR2_SDRAM +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = sysace + PARAMETER DRIVER_VER = 1.12.a + PARAMETER HW_INSTANCE = SysACE_CompactFlash +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = apu_fpu_virtex5 + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = ppc440_0_apu_fpu_virtex5 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = clock_generator_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = jtagppc_cntlr_inst +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = proc_sys_reset_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = intc + PARAMETER DRIVER_VER = 1.11.a + PARAMETER HW_INSTANCE = xps_intc_0 +END + + diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.xmp b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.xmp new file mode 100644 index 000000000..177a41c14 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.xmp @@ -0,0 +1,69 @@ +#Please do not modify this file by hand +XmpVersion: 11.2 +VerMgmt: 11.2 +IntStyle: default +MHS File: system.mhs +MSS File: system.mss +Architecture: virtex5 +Device: xc5vfx70t +Package: ff1136 +SpeedGrade: -1 +UserCmd1: +UserCmd1Type: 0 +UserCmd2: +UserCmd2Type: 0 +GenSimTB: 0 +SdkExportBmmBit: 1 +SdkExportDir: SDK/SDK_Export +InsertNoPads: 0 +WarnForEAArch: 1 +HdlLang: VHDL +SimModel: BEHAVIORAL +UcfFile: data/system.ucf +EnableParTimingError: 1 +ShowLicenseDialog: 1 +Processor: ppc440_0 +BootLoop: 1 +XmdStub: 0 +SwProj: RTOSDemo +Processor: ppc440_0 +Executable: RTOSDemo/executable.elf +Source: RTOSDemo/../../Common/Minimal/BlockQ.c +Source: RTOSDemo/../../Common/Minimal/blocktim.c +Source: RTOSDemo/../../Common/Minimal/comtest.c +Source: RTOSDemo/../../Common/Minimal/countsem.c +Source: RTOSDemo/../../Common/Minimal/death.c +Source: RTOSDemo/../../Common/Minimal/dynamic.c +Source: RTOSDemo/../../Common/Minimal/flash.c +Source: RTOSDemo/../../Common/Minimal/GenQTest.c +Source: RTOSDemo/../../Common/Minimal/integer.c +Source: RTOSDemo/../../Common/Minimal/QPeek.c +Source: RTOSDemo/../../Common/Minimal/recmutex.c +Source: RTOSDemo/../../Common/Minimal/semtest.c +Source: RTOSDemo/../../../Source/tasks.c +Source: RTOSDemo/../../../Source/list.c +Source: RTOSDemo/../../../Source/queue.c +Source: RTOSDemo/../../../Source/croutine.c +Source: RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S +Source: RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c +Source: RTOSDemo/../../../Source/portable/MemMang/heap_2.c +Source: RTOSDemo/flop/flop-reg-test.c +Source: RTOSDemo/flop/flop.c +Source: RTOSDemo/partest/partest.c +Source: RTOSDemo/serial/serial.c +Source: RTOSDemo/main.c +DefaultInit: EXECUTABLE +InitBram: 0 +Active: 1 +CompilerOptLevel: 0 +GlobPtrOpt: 0 +DebugSym: 1 +ProfileFlag: 0 +SearchIncl: ../../Source/include ../../Source/portable/GCC/PPC440_Xilinx ../Common/include ./RTOSDemo ./RTOSDemo/flop +ProgStart: +StackSize: +HeapSize: +LinkerScript: RTOSDemo/RTOSDemo_linker_script.ld +ProgCCFlags: -D GCC_PPC440 -mregnames +CompileInXps: 1 +NonXpsApp: 0 diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system_incl.make b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system_incl.make new file mode 100644 index 000000000..71c6546a0 --- /dev/null +++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system_incl.make @@ -0,0 +1,153 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.xmp +# +# WARNING : This file will be re-generated every time a command +# to run a make target is invoked. So, any changes made to this +# file manually, will be lost when make is invoked next. +################################################################# + +XILINX_EDK_DIR = /cygdrive/c/devtools/Xilinx/11.1/EDK +NON_CYG_XILINX_EDK_DIR = C:/devtools/Xilinx/11.1/EDK + +SYSTEM = system + +MHSFILE = system.mhs + +MSSFILE = system.mss + +FPGA_ARCH = virtex5 + +DEVICE = xc5vfx70tff1136-1 + +LANGUAGE = vhdl + +SEARCHPATHOPT = + +SUBMODULE_OPT = + +PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) -msg __xps/ise/xmsgprops.lst + +LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst + +OBSERVE_PAR_OPTIONS = -error yes + +RTOSDEMO_OUTPUT_DIR = RTOSDemo +RTOSDEMO_OUTPUT = $(RTOSDEMO_OUTPUT_DIR)/executable.elf + +MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf +PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf +PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf +BOOTLOOP_DIR = bootloops + +PPC440_0_BOOTLOOP = $(BOOTLOOP_DIR)/ppc440_0.elf + +BRAMINIT_ELF_FILES = $(PPC440_0_BOOTLOOP) +BRAMINIT_ELF_FILE_ARGS = -pe ppc440_0 $(PPC440_0_BOOTLOOP) + +ALL_USER_ELF_FILES = $(RTOSDEMO_OUTPUT) + +SIM_CMD = vsim + +BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.do + +STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.do + +TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do + +DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT) + +MIX_LANG_SIM_OPT = -mixed yes + +SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/ + + +LIBRARIES = \ + ppc440_0/lib/libxil.a + +LIBSCLEAN_TARGETS = ppc440_0_libsclean + +PROGRAMCLEAN_TARGETS = RTOSDemo_programclean + +CORE_STATE_DEVELOPMENT_FILES = + +WRAPPER_NGC_FILES = implementation/ppc440_0_wrapper.ngc \ +implementation/plb_v46_0_wrapper.ngc \ +implementation/xps_bram_if_cntlr_1_wrapper.ngc \ +implementation/xps_bram_if_cntlr_1_bram_wrapper.ngc \ +implementation/rs232_uart_1_wrapper.ngc \ +implementation/leds_8bit_wrapper.ngc \ +implementation/leds_positions_wrapper.ngc \ +implementation/push_buttons_5bit_wrapper.ngc \ +implementation/dip_switches_8bit_wrapper.ngc \ +implementation/iic_eeprom_wrapper.ngc \ +implementation/sram_wrapper.ngc \ +implementation/pcie_bridge_wrapper.ngc \ +implementation/ppc440_0_splb0_wrapper.ngc \ +implementation/ethernet_mac_wrapper.ngc \ +implementation/ddr2_sdram_wrapper.ngc \ +implementation/sysace_compactflash_wrapper.ngc \ +implementation/ppc440_0_fcb_v20_wrapper.ngc \ +implementation/ppc440_0_apu_fpu_virtex5_wrapper.ngc \ +implementation/clock_generator_0_wrapper.ngc \ +implementation/jtagppc_cntlr_inst_wrapper.ngc \ +implementation/proc_sys_reset_0_wrapper.ngc \ +implementation/xps_intc_0_wrapper.ngc + +POSTSYN_NETLIST = implementation/$(SYSTEM).ngc + +SYSTEM_BIT = implementation/$(SYSTEM).bit + +DOWNLOAD_BIT = implementation/download.bit + +SYSTEM_ACE = implementation/$(SYSTEM).ace + +UCF_FILE = data/system.ucf + +BMM_FILE = implementation/$(SYSTEM).bmm + +BITGEN_UT_FILE = etc/bitgen.ut + +XFLOW_OPT_FILE = etc/fast_runtime.opt +XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE) + +XPLORER_DEPENDENCY = __xps/xplorer.opt +XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7 + +FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(XFLOW_DEPENDENCY) + +SDK_EXPORT_DIR = SDK/SDK_Export/hw +SYSTEM_HW_HANDOFF = $(SDK_EXPORT_DIR)/$(SYSTEM).xml +SYSTEM_HW_HANDOFF_BIT = $(SDK_EXPORT_DIR)/$(SYSTEM).bit +SYSTEM_HW_HANDOFF_BMM = $(SDK_EXPORT_DIR)/$(SYSTEM)_bd.bmm +SYSTEM_HW_HANDOFF_DEP = $(SYSTEM_HW_HANDOFF) $(SYSTEM_HW_HANDOFF_BIT) $(SYSTEM_HW_HANDOFF_BMM) + +################################################################# +# SOFTWARE APPLICATION RTOSDEMO +################################################################# + +RTOSDEMO_SOURCES = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c + +RTOSDEMO_HEADERS = + +RTOSDEMO_CC = powerpc-eabi-gcc +RTOSDEMO_CC_SIZE = powerpc-eabi-size +RTOSDEMO_CC_OPT = -O0 +RTOSDEMO_CFLAGS = -D GCC_PPC440 -mregnames +RTOSDEMO_CC_SEARCH = # -B +RTOSDEMO_LIBPATH = -L./ppc440_0/lib/ # -L +RTOSDEMO_INCLUDES = -I./ppc440_0/include/ -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop +RTOSDEMO_LFLAGS = # -l +RTOSDEMO_LINKER_SCRIPT = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld +RTOSDEMO_LINKER_SCRIPT_FLAG = -Wl,-T -Wl,$(RTOSDEMO_LINKER_SCRIPT) +RTOSDEMO_CC_DEBUG_FLAG = -g +RTOSDEMO_CC_PROFILE_FLAG = # -pg +RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi +RTOSDEMO_CC_INFERRED_FLAGS= -mfpu=sp_full -mcpu=440 +RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR= +RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE= +RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE= +RTOSDEMO_OTHER_CC_FLAGS= $(RTOSDEMO_CC_GLOBPTR_FLAG) \ + $(RTOSDEMO_CC_START_ADDR_FLAG) $(RTOSDEMO_CC_STACK_SIZE_FLAG) $(RTOSDEMO_CC_HEAP_SIZE_FLAG) \ + $(RTOSDEMO_CC_INFERRED_FLAGS) \ + $(RTOSDEMO_LINKER_SCRIPT_FLAG) $(RTOSDEMO_CC_DEBUG_FLAG) $(RTOSDEMO_CC_PROFILE_FLAG)