Add some missing volatiles to __asm statements in the CA9 GCC port.

This commit is contained in:
Richard Barry 2014-05-19 13:14:02 +00:00
parent 0bb794301a
commit b215310e63
3 changed files with 52 additions and 52 deletions

View File

@ -410,8 +410,8 @@ void FreeRTOS_Tick_Handler( void )
updated. */ updated. */
portCPU_IRQ_DISABLE(); portCPU_IRQ_DISABLE();
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
__asm( "dsb \n" __asm volatile ( "dsb \n"
"isb \n" ); "isb \n" );
portCPU_IRQ_ENABLE(); portCPU_IRQ_ENABLE();
/* Increment the RTOS tick. */ /* Increment the RTOS tick. */
@ -435,7 +435,7 @@ uint32_t ulInitialFPSCR = 0;
ulPortTaskHasFPUContext = pdTRUE; ulPortTaskHasFPUContext = pdTRUE;
/* Initialise the floating point status register. */ /* Initialise the floating point status register. */
__asm( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) ); __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@ -464,8 +464,8 @@ uint32_t ulReturn;
{ {
ulReturn = pdFALSE; ulReturn = pdFALSE;
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
__asm( "dsb \n" __asm volatile ( "dsb \n"
"isb \n" ); "isb \n" );
} }
portCPU_IRQ_ENABLE(); portCPU_IRQ_ENABLE();

View File

@ -119,7 +119,7 @@ extern uint32_t ulPortYieldRequired; \
} }
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
#define portYIELD() __asm( "SWI 0" ); #define portYIELD() __asm volatile ( "SWI 0" );
/*----------------------------------------------------------- /*-----------------------------------------------------------