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Add PIC32MEC14xx port and demo application.

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This commit is contained in:
Richard Barry 2015-09-12 20:47:59 +00:00
parent f19497c3d6
commit a29dc8d6c6
103 changed files with 49682 additions and 6 deletions
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2
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/BasicSocketCommandServer/BasicSocketCommandServer.c
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/*
FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

2
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.c
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/*
FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

2
FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.h
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/*
FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

2
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/BasicSocketCommandServer/BasicSocketCommandServer.c
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/*
FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

2
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.c
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/*
FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

2
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.h
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/*
FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

113
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/Makefile Normal file
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#
# There exist several targets which are by default empty and which can be
# used for execution of your targets. These targets are usually executed
# before and after some main targets. They are:
#
# .build-pre: called before 'build' target
# .build-post: called after 'build' target
# .clean-pre: called before 'clean' target
# .clean-post: called after 'clean' target
# .clobber-pre: called before 'clobber' target
# .clobber-post: called after 'clobber' target
# .all-pre: called before 'all' target
# .all-post: called after 'all' target
# .help-pre: called before 'help' target
# .help-post: called after 'help' target
#
# Targets beginning with '.' are not intended to be called on their own.
#
# Main targets can be executed directly, and they are:
#
# build build a specific configuration
# clean remove built files from a configuration
# clobber remove all built files
# all build all configurations
# help print help mesage
#
# Targets .build-impl, .clean-impl, .clobber-impl, .all-impl, and
# .help-impl are implemented in nbproject/makefile-impl.mk.
#
# Available make variables:
#
# CND_BASEDIR base directory for relative paths
# CND_DISTDIR default top distribution directory (build artifacts)
# CND_BUILDDIR default top build directory (object files, ...)
# CONF name of current configuration
# CND_ARTIFACT_DIR_${CONF} directory of build artifact (current configuration)
# CND_ARTIFACT_NAME_${CONF} name of build artifact (current configuration)
# CND_ARTIFACT_PATH_${CONF} path to build artifact (current configuration)
# CND_PACKAGE_DIR_${CONF} directory of package (current configuration)
# CND_PACKAGE_NAME_${CONF} name of package (current configuration)
# CND_PACKAGE_PATH_${CONF} path to package (current configuration)
#
# NOCDDL
# Environment
MKDIR=mkdir
CP=cp
CCADMIN=CCadmin
RANLIB=ranlib
# build
build: .build-post
.build-pre:
# Add your pre 'build' code here...
.build-post: .build-impl
# Add your post 'build' code here...
# clean
clean: .clean-post
.clean-pre:
# Add your pre 'clean' code here...
# WARNING: the IDE does not call this target since it takes a long time to
# simply run make. Instead, the IDE removes the configuration directories
# under build and dist directly without calling make.
# This target is left here so people can do a clean when running a clean
# outside the IDE.
.clean-post: .clean-impl
# Add your post 'clean' code here...
# clobber
clobber: .clobber-post
.clobber-pre:
# Add your pre 'clobber' code here...
.clobber-post: .clobber-impl
# Add your post 'clobber' code here...
# all
all: .all-post
.all-pre:
# Add your pre 'all' code here...
.all-post: .all-impl
# Add your post 'all' code here...
# help
help: .help-post
.help-pre:
# Add your pre 'help' code here...
.help-post: .help-impl
# Add your post 'help' code here...
# include project implementation makefile
include nbproject/Makefile-impl.mk
# include project make variables
include nbproject/Makefile-variables.mk

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FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/disassembly/listing.disasm Normal file
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FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-default.mk Normal file
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9
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-genesis.properties Normal file
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#
#Sat Sep 12 19:52:29 BST 2015
default.com-microchip-mplab-nbide-toolchainXC32-XC32LanguageToolchain.md5=a29d9df60dd9a7849837c8f5ca17a004
default.languagetoolchain.dir=C\:\\DevTools\\Microchip\\xc32\\v1.33\\bin
configurations-xml=1488628682f58c9c6bf4eb01175324a8
com-microchip-mplab-nbide-embedded-makeproject-MakeProject.md5=47805b5596804b87cda41e61096929be
default.languagetoolchain.version=1.33
host.platform=windows
conf.ids=default

69
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-impl.mk Normal file
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#
# Generated Makefile - do not edit!
#
# Edit the Makefile in the project folder instead (../Makefile). Each target
# has a pre- and a post- target defined where you can add customization code.
#
# This makefile implements macros and targets common to all configurations.
#
# NOCDDL
# Building and Cleaning subprojects are done by default, but can be controlled with the SUB
# macro. If SUB=no, subprojects will not be built or cleaned. The following macro
# statements set BUILD_SUB-CONF and CLEAN_SUB-CONF to .build-reqprojects-conf
# and .clean-reqprojects-conf unless SUB has the value 'no'
SUB_no=NO
SUBPROJECTS=${SUB_${SUB}}
BUILD_SUBPROJECTS_=.build-subprojects
BUILD_SUBPROJECTS_NO=
BUILD_SUBPROJECTS=${BUILD_SUBPROJECTS_${SUBPROJECTS}}
CLEAN_SUBPROJECTS_=.clean-subprojects
CLEAN_SUBPROJECTS_NO=
CLEAN_SUBPROJECTS=${CLEAN_SUBPROJECTS_${SUBPROJECTS}}
# Project Name
PROJECTNAME=PIC32MEC14xx_RTOSDemo.X
# Active Configuration
DEFAULTCONF=default
CONF=${DEFAULTCONF}
# All Configurations
ALLCONFS=default
# build
.build-impl: .build-pre
${MAKE} -f nbproject/Makefile-${CONF}.mk SUBPROJECTS=${SUBPROJECTS} .build-conf
# clean
.clean-impl: .clean-pre
${MAKE} -f nbproject/Makefile-${CONF}.mk SUBPROJECTS=${SUBPROJECTS} .clean-conf
# clobber
.clobber-impl: .clobber-pre .depcheck-impl
${MAKE} SUBPROJECTS=${SUBPROJECTS} CONF=default clean
# all
.all-impl: .all-pre .depcheck-impl
${MAKE} SUBPROJECTS=${SUBPROJECTS} CONF=default build
# dependency checking support
.depcheck-impl:
# @echo "# This code depends on make tool being used" >.dep.inc
# @if [ -n "${MAKE_VERSION}" ]; then \
# echo "DEPFILES=\$$(wildcard \$$(addsuffix .d, \$${OBJECTFILES}))" >>.dep.inc; \
# echo "ifneq (\$${DEPFILES},)" >>.dep.inc; \
# echo "include \$${DEPFILES}" >>.dep.inc; \
# echo "endif" >>.dep.inc; \
# else \
# echo ".KEEP_STATE:" >>.dep.inc; \
# echo ".KEEP_STATE_FILE:.make.state.\$${CONF}" >>.dep.inc; \
# fi

37
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-local-default.mk Normal file
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#
# Generated Makefile - do not edit!
#
#
# This file contains information about the location of compilers and other tools.
# If you commmit this file into your revision control server, you will be able to
# to checkout the project and build it from the command line with make. However,
# if more than one person works on the same project, then this file might show
# conflicts since different users are bound to have compilers in different places.
# In that case you might choose to not commit this file and let MPLAB X recreate this file
# for each user. The disadvantage of not commiting this file is that you must run MPLAB X at
# least once so the file gets created and the project can be built. Finally, you can also
# avoid using this file at all if you are only building from the command line with make.
# You can invoke make with the values of the macros:
# $ makeMP_CC="/opt/microchip/mplabc30/v3.30c/bin/pic30-gcc" ...
#
SHELL=cmd.exe
PATH_TO_IDE_BIN=C:/DevTools/Microchip/MPLABX/v3.05/mplab_ide/mplab_ide/modules/../../bin/
# Adding MPLAB X bin directory to path.
PATH:=C:/DevTools/Microchip/MPLABX/v3.05/mplab_ide/mplab_ide/modules/../../bin/:$(PATH)
# Path to java used to run MPLAB X when this makefile was created
MP_JAVA_PATH="C:\DevTools\Microchip\MPLABX\v3.05\sys\java\jre1.7.0_67/bin/"
OS_CURRENT="$(shell uname -s)"
MP_CC="C:\DevTools\Microchip\xc32\v1.33\bin\xc32-gcc.exe"
MP_CPPC="C:\DevTools\Microchip\xc32\v1.33\bin\xc32-g++.exe"
# MP_BC is not defined
MP_AS="C:\DevTools\Microchip\xc32\v1.33\bin\xc32-as.exe"
MP_LD="C:\DevTools\Microchip\xc32\v1.33\bin\xc32-ld.exe"
MP_AR="C:\DevTools\Microchip\xc32\v1.33\bin\xc32-ar.exe"
DEP_GEN=${MP_JAVA_PATH}java -jar "C:/DevTools/Microchip/MPLABX/v3.05/mplab_ide/mplab_ide/modules/../../bin/extractobjectdependencies.jar"
MP_CC_DIR="C:\DevTools\Microchip\xc32\v1.33\bin"
MP_CPPC_DIR="C:\DevTools\Microchip\xc32\v1.33\bin"
# MP_BC_DIR is not defined
MP_AS_DIR="C:\DevTools\Microchip\xc32\v1.33\bin"
MP_LD_DIR="C:\DevTools\Microchip\xc32\v1.33\bin"
MP_AR_DIR="C:\DevTools\Microchip\xc32\v1.33\bin"
# MP_BC_DIR is not defined

13
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-variables.mk Normal file
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#
# Generated - do not edit!
#
# NOCDDL
#
CND_BASEDIR=`pwd`
# default configuration
CND_ARTIFACT_DIR_default=dist/default/production
CND_ARTIFACT_NAME_default=PIC32MEC14xx_RTOSDemo.X.production.hex
CND_ARTIFACT_PATH_default=dist/default/production/PIC32MEC14xx_RTOSDemo.X.production.hex
CND_PACKAGE_DIR_default=${CND_DISTDIR}/default/package
CND_PACKAGE_NAME_default=pic32mec14xxrtosdemo.x.tar
CND_PACKAGE_PATH_default=${CND_DISTDIR}/default/package/pic32mec14xxrtosdemo.x.tar

73
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Package-default.bash Normal file
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#!/bin/bash -x
#
# Generated - do not edit!
#
# Macros
TOP=`pwd`
CND_CONF=default
CND_DISTDIR=dist
TMPDIR=build/${CND_CONF}/${IMAGE_TYPE}/tmp-packaging
TMPDIRNAME=tmp-packaging
OUTPUT_PATH=dist/${CND_CONF}/${IMAGE_TYPE}/PIC32MEC14xx_RTOSDemo.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
OUTPUT_BASENAME=PIC32MEC14xx_RTOSDemo.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
PACKAGE_TOP_DIR=pic32mec14xxrtosdemo.x/
# Functions
function checkReturnCode
{
rc=$?
if [ $rc != 0 ]
then
exit $rc
fi
}
function makeDirectory
# $1 directory path
# $2 permission (optional)
{
mkdir -p "$1"
checkReturnCode
if [ "$2" != "" ]
then
chmod $2 "$1"
checkReturnCode
fi
}
function copyFileToTmpDir
# $1 from-file path
# $2 to-file path
# $3 permission
{
cp "$1" "$2"
checkReturnCode
if [ "$3" != "" ]
then
chmod $3 "$2"
checkReturnCode
fi
}
# Setup
cd "${TOP}"
mkdir -p ${CND_DISTDIR}/${CND_CONF}/package
rm -rf ${TMPDIR}
mkdir -p ${TMPDIR}
# Copy files and create directories and links
cd "${TOP}"
makeDirectory ${TMPDIR}/pic32mec14xxrtosdemo.x/bin
copyFileToTmpDir "${OUTPUT_PATH}" "${TMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755
# Generate tar file
cd "${TOP}"
rm -f ${CND_DISTDIR}/${CND_CONF}/package/pic32mec14xxrtosdemo.x.tar
cd ${TMPDIR}
tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/package/pic32mec14xxrtosdemo.x.tar *
checkReturnCode
# Cleanup
cd "${TOP}"
rm -rf ${TMPDIR}

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FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/configurations.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<configurationDescriptor version="62">
<logicalFolder name="root" displayName="root" projectFiles="true">
<logicalFolder name="HeaderFiles"
displayName="Header Files"
projectFiles="true">
<logicalFolder name="kernel" displayName="FreeRTOS Source" projectFiles="true">
<logicalFolder name="include" displayName="include" projectFiles="true">
<itemPath>../../../Source/include/FreeRTOS.h</itemPath>
<itemPath>../../../Source/include/StackMacros.h</itemPath>
<itemPath>../../../Source/include/croutine.h</itemPath>
<itemPath>../../../Source/include/event_groups.h</itemPath>
<itemPath>../../../Source/include/list.h</itemPath>
<itemPath>../../../Source/include/mpu_wrappers.h</itemPath>
<itemPath>../../../Source/include/portable.h</itemPath>
<itemPath>../../../Source/include/projdefs.h</itemPath>
<itemPath>../../../Source/include/queue.h</itemPath>
<itemPath>../../../Source/include/semphr.h</itemPath>
<itemPath>../../../Source/include/task.h</itemPath>
<itemPath>../../../Source/include/timers.h</itemPath>
</logicalFolder>
<logicalFolder name="portable" displayName="portable" projectFiles="true">
<logicalFolder name="MPLAB" displayName="MPLAB" projectFiles="true">
<logicalFolder name="MEC14XX" displayName="MEC14XX" projectFiles="true">
<itemPath>../../../Source/portable/MPLAB/PIC32MEC14xx/ISR_Support.h</itemPath>
<itemPath>../../../Source/portable/MPLAB/PIC32MEC14xx/portmacro.h</itemPath>
</logicalFolder>
</logicalFolder>
</logicalFolder>
</logicalFolder>
<logicalFolder name="incs" displayName="incs" projectFiles="true">
<logicalFolder name="crypto" displayName="crypto" projectFiles="true">
<itemPath>../src/incs/crypto/aes.h</itemPath>
<itemPath>../src/incs/crypto/crypto.h</itemPath>
<itemPath>../src/incs/crypto/error.h</itemPath>
<itemPath>../src/incs/crypto/logging.h</itemPath>
<itemPath>../src/incs/crypto/memory.h</itemPath>
<itemPath>../src/incs/crypto/misc.h</itemPath>
<itemPath>../src/incs/crypto/port.h</itemPath>
<itemPath>../src/incs/crypto/settings.h</itemPath>
<itemPath>../src/incs/crypto/sha256.h</itemPath>
<itemPath>../src/incs/crypto/types.h</itemPath>
<itemPath>../src/incs/crypto/version.h</itemPath>
<itemPath>../src/incs/crypto/visibility.h</itemPath>
</logicalFolder>
<logicalFolder name="MEC14xx" displayName="MEC14xx" projectFiles="true">
<itemPath>../src/include/MEC14xx/mec14xx.h</itemPath>
<itemPath>../src/include/MEC14xx/mec14xx_bbled.h</itemPath>
<itemPath>../src/include/MEC14xx/mec14xx_girqm.h</itemPath>
<itemPath>../src/include/MEC14xx/mec14xx_girqs.h</itemPath>
<itemPath>../src/include/MEC14xx/mec14xx_gpio.h</itemPath>
<itemPath>../src/include/MEC14xx/mec14xx_jtvic.h</itemPath>
<itemPath>../src/include/MEC14xx/mec14xx_pcr.h</itemPath>
<itemPath>../src/include/MEC14xx/mec14xx_system.h</itemPath>
<itemPath>../src/include/MEC14xx/mec14xx_tfdp.h</itemPath>
<itemPath>../src/include/MEC14xx/mec14xx_timers.h</itemPath>
<itemPath>../src/include/MEC14xx/mec14xx_trace_func.h</itemPath>
<itemPath>../src/include/MEC14xx/mec14xx_trace_inline.h</itemPath>
</logicalFolder>
<itemPath>../src/incs/apptasks.h</itemPath>
<itemPath>../src/incs/dbg_dump.h</itemPath>
<itemPath>../src/incs/mipscpu.h</itemPath>
<itemPath>../src/incs/system_config.h</itemPath>
<itemPath>../src/include/appcfg.h</itemPath>
<itemPath>../src/include/platform.h</itemPath>
</logicalFolder>
<itemPath>../src/FreeRTOSConfig.h</itemPath>
</logicalFolder>
<logicalFolder name="LinkerScript"
displayName="Linker Files"
projectFiles="true">
<itemPath>../linkfile/custom_pMEC1404.ld</itemPath>
</logicalFolder>
<logicalFolder name="SourceFiles"
displayName="Source Files"
projectFiles="true">
<logicalFolder name="src" displayName="src" projectFiles="true">
<logicalFolder name="f3" displayName="Blinky_Demo" projectFiles="true">
<itemPath>../src/Blinky_Demo/main_blinky.c</itemPath>
</logicalFolder>
<logicalFolder name="f2" displayName="FreeRTOS Source" projectFiles="true">
<logicalFolder name="f1" displayName="portable" projectFiles="true">
<logicalFolder name="f1" displayName="MemMang" projectFiles="true">
<itemPath>../../../Source/portable/MemMang/heap_2.c</itemPath>
</logicalFolder>
<logicalFolder name="f2" displayName="MPLAB" projectFiles="true">
<logicalFolder name="f1" displayName="PIC32MEC14xx" projectFiles="true">
<itemPath>../../../Source/portable/MPLAB/PIC32MEC14xx/port.c</itemPath>
<itemPath>../../../Source/portable/MPLAB/PIC32MEC14xx/port_asm.S</itemPath>
</logicalFolder>
</logicalFolder>
</logicalFolder>
<itemPath>../../../Source/event_groups.c</itemPath>
<itemPath>../../../Source/list.c</itemPath>
<itemPath>../../../Source/queue.c</itemPath>
<itemPath>../../../Source/tasks.c</itemPath>
<itemPath>../../../Source/timers.c</itemPath>
</logicalFolder>
<logicalFolder name="f4" displayName="Full_Demo" projectFiles="true">
<logicalFolder name="f1" displayName="Standard_Demo_Tasks" projectFiles="true">
<itemPath>../../Common/Minimal/blocktim.c</itemPath>
<itemPath>../../Common/Minimal/countsem.c</itemPath>
<itemPath>../../Common/Minimal/dynamic.c</itemPath>
<itemPath>../../Common/Minimal/EventGroupsDemo.c</itemPath>
<itemPath>../../Common/Minimal/GenQTest.c</itemPath>
<itemPath>../../Common/Minimal/IntQueue.c</itemPath>
<itemPath>../../Common/Minimal/IntSemTest.c</itemPath>
<itemPath>../../Common/Minimal/recmutex.c</itemPath>
<itemPath>../../Common/Minimal/semtest.c</itemPath>
<itemPath>../../Common/Minimal/TaskNotify.c</itemPath>
<itemPath>../../Common/Minimal/TimerDemo.c</itemPath>
</logicalFolder>
<itemPath>../src/Full_Demo/IntQueueTimer.c</itemPath>
<itemPath>../src/Full_Demo/IntQueueTimer.h</itemPath>
<itemPath>../src/Full_Demo/IntQueueTimer_isr.S</itemPath>
<itemPath>../src/Full_Demo/main_full.c</itemPath>
<itemPath>../src/Full_Demo/timertest.c</itemPath>
<itemPath>../src/Full_Demo/RegisterTestTasks.S</itemPath>
</logicalFolder>
<logicalFolder name="MEC14xx" displayName="MEC14xx" projectFiles="true">
<logicalFolder name="exceptions" displayName="exceptions" projectFiles="true">
<logicalFolder name="MPLAB" displayName="MPLAB" projectFiles="true">
<itemPath>../src/MEC14xx/exceptions/MPLAB/general_exception.c</itemPath>
<itemPath>../src/MEC14xx/exceptions/MPLAB/general_exception_ctx.S</itemPath>
</logicalFolder>
</logicalFolder>
<logicalFolder name="interrupts" displayName="interrupts" projectFiles="true">
<itemPath>../src/MEC14xx/interrupts/girq08.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq09.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq10.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq11.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq12.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq13.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq14.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq15.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq16.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq17.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq18.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq19.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq20.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq21.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq22.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq23.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq24.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq25.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq26.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girqs.c</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq08d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq09d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq10d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq11d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq12d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq13d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq14d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq15d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq16d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq17d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq18d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq19d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq20d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq21d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq22d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq23d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq24d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq25d.S</itemPath>
<itemPath>../src/MEC14xx/interrupts/girq26d.S</itemPath>
</logicalFolder>
<logicalFolder name="startup" displayName="startup" projectFiles="true">
<logicalFolder name="MPLAB" displayName="MPLAB" projectFiles="true">
<itemPath>../src/MEC14xx/startup/MPLAB/default-on-bootstrap.c</itemPath>
<itemPath>../src/MEC14xx/startup/MPLAB/on_reset.c</itemPath>
<itemPath>../src/MEC14xx/startup/MPLAB/crt0.S</itemPath>
<itemPath>../src/MEC14xx/startup/MPLAB/crti.S</itemPath>
<itemPath>../src/MEC14xx/startup/MPLAB/crtn.S</itemPath>
</logicalFolder>
</logicalFolder>
<itemPath>../src/MEC14xx/mec14xx_bbled.c</itemPath>
<itemPath>../src/MEC14xx/mec14xx_gpio.c</itemPath>
<itemPath>../src/MEC14xx/mec14xx_jtvic.c</itemPath>
<itemPath>../src/MEC14xx/mec14xx_system.c</itemPath>
<itemPath>../src/MEC14xx/mec14xx_tfdp.c</itemPath>
<itemPath>../src/MEC14xx/mec14xx_timers.c</itemPath>
</logicalFolder>
<itemPath>../src/main.c</itemPath>
</logicalFolder>
</logicalFolder>
<logicalFolder name="ExternalFiles"
displayName="Important Files"
projectFiles="false">
<itemPath>Makefile</itemPath>
</logicalFolder>
</logicalFolder>
<sourceRootList>
<Elem>../linkfile</Elem>
<Elem>../src</Elem>
<Elem>../../../Source</Elem>
<Elem>../../Common/Minimal</Elem>
</sourceRootList>
<projectmakefile>Makefile</projectmakefile>
<confs>
<conf name="default" type="2">
<toolsSet>
<developmentServer>localhost</developmentServer>
<targetDevice>MEC1404</targetDevice>
<targetHeader></targetHeader>
<targetPluginBoard></targetPluginBoard>
<platformTool>ICD3PlatformTool</platformTool>
<languageToolchain>XC32</languageToolchain>
<languageToolchainVersion>1.33</languageToolchainVersion>
<platform>3</platform>
</toolsSet>
<compileType>
<linkerTool>
<linkerLibItems>
</linkerLibItems>
</linkerTool>
<archiverTool>
</archiverTool>
<loading>
<useAlternateLoadableFile>false</useAlternateLoadableFile>
<parseOnProdLoad>true</parseOnProdLoad>
<alternateLoadableFile></alternateLoadableFile>
</loading>
</compileType>
<makeCustomizationType>
<makeCustomizationPreStepEnabled>false</makeCustomizationPreStepEnabled>
<makeCustomizationPreStep></makeCustomizationPreStep>
<makeCustomizationPostStepEnabled>false</makeCustomizationPostStepEnabled>
<makeCustomizationPostStep></makeCustomizationPostStep>
<makeCustomizationPutChecksumInUserID>false</makeCustomizationPutChecksumInUserID>
<makeCustomizationEnableLongLines>false</makeCustomizationEnableLongLines>
<makeCustomizationNormalizeHexFile>false</makeCustomizationNormalizeHexFile>
</makeCustomizationType>
<C32>
<property key="additional-warnings" value="false"/>
<property key="enable-app-io" value="false"/>
<property key="enable-omit-frame-pointer" value="false"/>
<property key="enable-symbols" value="true"/>
<property key="enable-unroll-loops" value="false"/>
<property key="exclude-floating-point" value="false"/>
<property key="extra-include-directories"
value="..\src;..\src\include;..\..\..\Source\include;..\..\..\Source\portable\MPLAB\PIC32MEC14xx;..\src\MEC14xx;..\..\Common\include;..\src\Full_Demo"/>
<property key="generate-16-bit-code" value="false"/>
<property key="generate-micro-compressed-code" value="true"/>
<property key="isolate-each-function" value="true"/>
<property key="make-warnings-into-errors" value="false"/>
<property key="optimization-level" value="-O3"/>
<property key="place-data-into-section" value="false"/>
<property key="post-instruction-scheduling" value="default"/>
<property key="pre-instruction-scheduling" value="default"/>
<property key="preprocessor-macros" value=""/>
<property key="strict-ansi" value="false"/>
<property key="support-ansi" value="false"/>
<property key="use-cci" value="false"/>
<property key="use-iar" value="false"/>
<property key="use-indirect-calls" value="false"/>
<appendMe value="-D__DEBUG -Wall -Wextra"/>
</C32>
<C32-AR>
<property key="additional-options-chop-files" value="false"/>
</C32-AR>
<C32-AS>
<property key="assembler-symbols" value=""/>
<property key="enable-symbols" value="true"/>
<property key="exclude-floating-point-library" value="false"/>
<property key="expand-macros" value="false"/>
<property key="extra-include-directories-for-assembler" value=""/>
<property key="extra-include-directories-for-preprocessor"
value="..\src;..\src\include;..\src\MEC14xx;..\..\..\Source\include;..\..\..\Source\portable\MPLAB\PIC32MEC14xx"/>
<property key="false-conditionals" value="false"/>
<property key="keep-locals" value="false"/>
<property key="list-assembly" value="false"/>
<property key="list-source" value="false"/>
<property key="list-symbols" value="false"/>
<property key="oXC32asm-list-to-file" value="false"/>
<property key="omit-debug-dirs" value="false"/>
<property key="omit-forms" value="false"/>
<property key="preprocessor-macros" value=""/>
<property key="warning-level" value=""/>
</C32-AS>
<C32-LD>
<property key="additional-options-use-response-files" value="false"/>
<property key="enable-check-sections" value="false"/>
<property key="exclude-floating-point-library" value="false"/>
<property key="exclude-standard-libraries" value="false"/>
<property key="extra-lib-directories" value=""/>
<property key="fill-flash-options-addr" value=""/>
<property key="fill-flash-options-const" value=""/>
<property key="fill-flash-options-how" value="0"/>
<property key="fill-flash-options-inc-const" value="1"/>
<property key="fill-flash-options-increment" value=""/>
<property key="fill-flash-options-seq" value=""/>
<property key="fill-flash-options-what" value="0"/>
<property key="generate-16-bit-code" value="false"/>
<property key="generate-cross-reference-file" value="false"/>
<property key="generate-micro-compressed-code" value="true"/>
<property key="heap-size" value=""/>
<property key="input-libraries" value=""/>
<property key="linker-symbols" value=""/>
<property key="map-file" value="${DISTDIR}/${PROJECTNAME}.${IMAGE_TYPE}.map"/>
<property key="no-startup-files" value="true"/>
<property key="oXC32ld-extra-opts" value=""/>
<property key="optimization-level" value=""/>
<property key="preprocessor-macros" value=""/>
<property key="remove-unused-sections" value="false"/>
<property key="report-memory-usage" value="true"/>
<property key="stack-size" value="2048"/>
<property key="symbol-stripping" value=""/>
<property key="trace-symbols" value=""/>
<property key="warn-section-align" value="false"/>
<appendMe value="--verbose"/>
</C32-LD>
<C32CPP>
<property key="additional-warnings" value="false"/>
<property key="check-new" value="false"/>
<property key="eh-specs" value="false"/>
<property key="enable-app-io" value="false"/>
<property key="enable-omit-frame-pointer" value="false"/>
<property key="enable-symbols" value="true"/>
<property key="enable-unroll-loops" value="false"/>
<property key="exceptions" value="false"/>
<property key="exclude-floating-point" value="false"/>
<property key="extra-include-directories"
value="..\src\incs;..\..\..\Source\include;..\..\..\Source\portable\MPLAB\PIC32MEC14xx"/>
<property key="generate-16-bit-code" value="false"/>
<property key="generate-micro-compressed-code" value="true"/>
<property key="isolate-each-function" value="true"/>
<property key="make-warnings-into-errors" value="false"/>
<property key="optimization-level" value=""/>
<property key="place-data-into-section" value="false"/>
<property key="post-instruction-scheduling" value="default"/>
<property key="pre-instruction-scheduling" value="default"/>
<property key="preprocessor-macros" value=""/>
<property key="rtti" value="false"/>
<property key="strict-ansi" value="false"/>
<property key="use-cci" value="false"/>
<property key="use-iar" value="false"/>
<property key="use-indirect-calls" value="false"/>
</C32CPP>
<C32Global>
<property key="common-include-directories" value=""/>
<property key="gp-relative-option" value=""/>
<property key="legacy-libc" value="false"/>
<property key="relaxed-math" value="false"/>
<property key="save-temps" value="false"/>
<property key="wpo-lto" value="false"/>
</C32Global>
<ICD3PlatformTool>
<property key="AutoSelectMemRanges" value="auto"/>
<property key="SecureSegment.SegmentProgramming" value="FullChipProgramming"/>
<property key="ToolFirmwareFilePath"
value="Press to browse for a specific firmware version"/>
<property key="ToolFirmwareOption.UseLatestFirmware" value="true"/>
<property key="debugoptions.useswbreakpoints" value="false"/>
<property key="hwtoolclock.frcindebug" value="false"/>
<property key="memories.aux" value="false"/>
<property key="memories.bootflash" value="false"/>
<property key="memories.configurationmemory" value="true"/>
<property key="memories.configurationmemory2" value="true"/>
<property key="memories.dataflash" value="true"/>
<property key="memories.eeprom" value="true"/>
<property key="memories.flashdata" value="true"/>
<property key="memories.id" value="true"/>
<property key="memories.programmemory" value="true"/>
<property key="memories.programmemory.end" value="0x1fd17fff"/>
<property key="memories.programmemory.partition2" value="true"/>
<property key="memories.programmemory.partition2.end"
value="${memories.programmemory.partition2.end.value}"/>
<property key="memories.programmemory.partition2.start"
value="${memories.programmemory.partition2.start.value}"/>
<property key="memories.programmemory.start" value="0x1fd00000"/>
<property key="poweroptions.powerenable" value="false"/>
<property key="programoptions.donoteraseauxmem" value="false"/>
<property key="programoptions.eraseb4program" value="true"/>
<property key="programoptions.preservedataflash" value="false"/>
<property key="programoptions.preserveeeprom" value="false"/>
<property key="programoptions.preserveprogramrange" value="false"/>
<property key="programoptions.preserveprogramrange.end" value="0x1fd17fff"/>
<property key="programoptions.preserveprogramrange.start" value="0x1fd00000"/>
<property key="programoptions.preserveuserid" value="false"/>
<property key="programoptions.programcalmem" value="false"/>
<property key="programoptions.programuserotp" value="false"/>
<property key="programoptions.testmodeentrymethod" value="VPPFirst"/>
<property key="programoptions.usehighvoltageonmclr" value="false"/>
<property key="programoptions.uselvpprogramming" value="false"/>
<property key="voltagevalue" value="3.25"/>
</ICD3PlatformTool>
<RealICEPlatformTool>
<property key="AutoSelectMemRanges" value="auto"/>
<property key="RIExTrigs.Five" value="OFF"/>
<property key="RIExTrigs.Four" value="OFF"/>
<property key="RIExTrigs.One" value="OFF"/>
<property key="RIExTrigs.Seven" value="OFF"/>
<property key="RIExTrigs.Six" value="OFF"/>
<property key="RIExTrigs.Three" value="OFF"/>
<property key="RIExTrigs.Two" value="OFF"/>
<property key="RIExTrigs.Zero" value="OFF"/>
<property key="SecureSegment.SegmentProgramming" value="FullChipProgramming"/>
<property key="ToolFirmwareFilePath"
value="Press to browse for a specific firmware version"/>
<property key="ToolFirmwareOption.UseLatestFirmware" value="true"/>
<property key="debugoptions.useswbreakpoints" value="false"/>
<property key="hwtoolclock.frcindebug" value="false"/>
<property key="hwtoolclock.instructionspeed" value="4"/>
<property key="hwtoolclock.units" value="mips"/>
<property key="memories.aux" value="false"/>
<property key="memories.bootflash" value="true"/>
<property key="memories.configurationmemory" value="true"/>
<property key="memories.configurationmemory2" value="true"/>
<property key="memories.dataflash" value="true"/>
<property key="memories.eeprom" value="true"/>
<property key="memories.flashdata" value="true"/>
<property key="memories.id" value="true"/>
<property key="memories.programmemory" value="true"/>
<property key="memories.programmemory.end" value="0x1fd17fff"/>
<property key="memories.programmemory.partition2" value="true"/>
<property key="memories.programmemory.partition2.end"
value="${memories.programmemory.partition2.end.value}"/>
<property key="memories.programmemory.partition2.start"
value="${memories.programmemory.partition2.start.value}"/>
<property key="memories.programmemory.start" value="0x1fd00000"/>
<property key="poweroptions.powerenable" value="false"/>
<property key="programoptions.donoteraseauxmem" value="false"/>
<property key="programoptions.eraseb4program" value="true"/>
<property key="programoptions.preservedataflash" value="false"/>
<property key="programoptions.preserveeeprom" value="false"/>
<property key="programoptions.preserveprogramrange" value="false"/>
<property key="programoptions.preserveprogramrange.end" value="0x1fd17fff"/>
<property key="programoptions.preserveprogramrange.start" value="0x1fd00000"/>
<property key="programoptions.preserveuserid" value="false"/>
<property key="programoptions.programcalmem" value="false"/>
<property key="programoptions.programuserotp" value="false"/>
<property key="programoptions.usehighvoltageonmclr" value="false"/>
<property key="programoptions.uselvpprogramming" value="false"/>
<property key="voltagevalue" value="3.25"/>
</RealICEPlatformTool>
<Simulator>
<property key="codecoverage.enabled" value="Disable"/>
<property key="codecoverage.enableoutputtofile" value="false"/>
<property key="codecoverage.outputfile" value=""/>
<property key="oscillator.auxfrequency" value="120"/>
<property key="oscillator.auxfrequencyunit" value="Mega"/>
<property key="oscillator.frequency" value="1"/>
<property key="oscillator.frequencyunit" value="Mega"/>
<property key="oscillator.rcfrequency" value="250"/>
<property key="oscillator.rcfrequencyunit" value="Kilo"/>
<property key="performancedata.show" value="false"/>
<property key="periphADC1.altscl" value="false"/>
<property key="periphADC1.minTacq" value=""/>
<property key="periphADC1.tacqunits" value="microseconds"/>
<property key="periphADC2.altscl" value="false"/>
<property key="periphADC2.minTacq" value=""/>
<property key="periphADC2.tacqunits" value="microseconds"/>
<property key="periphComp1.gte" value="gt"/>
<property key="periphComp2.gte" value="gt"/>
<property key="periphComp3.gte" value="gt"/>
<property key="periphComp4.gte" value="gt"/>
<property key="periphComp5.gte" value="gt"/>
<property key="periphComp6.gte" value="gt"/>
<property key="uart10io.output" value="window"/>
<property key="uart10io.outputfile" value=""/>
<property key="uart10io.uartioenabled" value="false"/>
<property key="uart1io.output" value="window"/>
<property key="uart1io.outputfile" value=""/>
<property key="uart1io.uartioenabled" value="false"/>
<property key="uart2io.output" value="window"/>
<property key="uart2io.outputfile" value=""/>
<property key="uart2io.uartioenabled" value="false"/>
<property key="uart3io.output" value="window"/>
<property key="uart3io.outputfile" value=""/>
<property key="uart3io.uartioenabled" value="false"/>
<property key="uart4io.output" value="window"/>
<property key="uart4io.outputfile" value=""/>
<property key="uart4io.uartioenabled" value="false"/>
<property key="uart5io.output" value="window"/>
<property key="uart5io.outputfile" value=""/>
<property key="uart5io.uartioenabled" value="false"/>
<property key="uart6io.output" value="window"/>
<property key="uart6io.outputfile" value=""/>
<property key="uart6io.uartioenabled" value="false"/>
<property key="uart7io.output" value="window"/>
<property key="uart7io.outputfile" value=""/>
<property key="uart7io.uartioenabled" value="false"/>
<property key="uart8io.output" value="window"/>
<property key="uart8io.outputfile" value=""/>
<property key="uart8io.uartioenabled" value="false"/>
<property key="uart9io.output" value="window"/>
<property key="uart9io.outputfile" value=""/>
<property key="uart9io.uartioenabled" value="false"/>
<property key="warningmessagebreakoptions.W0001_CORE_BITREV_MODULO_EN"
value="report"/>
<property key="warningmessagebreakoptions.W0002_CORE_SECURE_MEMORYACCESS"
value="report"/>
<property key="warningmessagebreakoptions.W0003_CORE_SW_RESET" value="report"/>
<property key="warningmessagebreakoptions.W0004_CORE_WDT_RESET" value="report"/>
<property key="warningmessagebreakoptions.W0005_CORE_IOPUW_RESET"
value="report"/>
<property key="warningmessagebreakoptions.W0006_CORE_CODE_GUARD_PFC_RESET"
value="report"/>
<property key="warningmessagebreakoptions.W0007_CORE_DO_LOOP_STACK_UNDERFLOW"
value="report"/>
<property key="warningmessagebreakoptions.W0008_CORE_DO_LOOP_STACK_OVERFLOW"
value="report"/>
<property key="warningmessagebreakoptions.W0009_CORE_NESTED_DO_LOOP_RANGE"
value="report"/>
<property key="warningmessagebreakoptions.W0010_CORE_SIM32_ODD_WORDACCESS"
value="report"/>
<property key="warningmessagebreakoptions.W0011_CORE_SIM32_UNIMPLEMENTED_RAMACCESS"
value="report"/>
<property key="warningmessagebreakoptions.W0012_CORE_STACK_OVERFLOW_RESET"
value="report"/>
<property key="warningmessagebreakoptions.W0013_CORE_STACK_UNDERFLOW_RESET"
value="report"/>
<property key="warningmessagebreakoptions.W0014_CORE_STACK_OVERFLOW"
value="report"/>
<property key="warningmessagebreakoptions.W0015_CORE_STACK_UNDERFLOW"
value="report"/>
<property key="warningmessagebreakoptions.W0101_SIM_UPDATE_FAILED"
value="report"/>
<property key="warningmessagebreakoptions.W0102_SIM_PERIPH_MISSING"
value="report"/>
<property key="warningmessagebreakoptions.W0103_SIM_PERIPH_FAILED"
value="report"/>
<property key="warningmessagebreakoptions.W0104_SIM_FAILED_TO_INIT_TOOL"
value="report"/>
<property key="warningmessagebreakoptions.W0201_ADC_NO_STIMULUS_FILE"
value="report"/>
<property key="warningmessagebreakoptions.W0202_ADC_GO_DONE_BIT" value="report"/>
<property key="warningmessagebreakoptions.W0203_ADC_MINIMUM_2_TAD"
value="report"/>
<property key="warningmessagebreakoptions.W0204_ADC_TAD_TOO_SMALL"
value="report"/>
<property key="warningmessagebreakoptions.W0205_ADC_UNEXPECTED_TRANSITION"
value="report"/>
<property key="warningmessagebreakoptions.W0206_ADC_SAMP_TIME_TOO_SHORT"
value="report"/>
<property key="warningmessagebreakoptions.W0207_ADC_NO_PINS_SCANNED"
value="report"/>
<property key="warningmessagebreakoptions.W0208_ADC_UNSUPPORTED_CLOCK_SOURCE"
value="report"/>
<property key="warningmessagebreakoptions.W0209_ADC_ANALOG_CHANNEL_DIGITAL"
value="report"/>
<property key="warningmessagebreakoptions.W0210_ADC_ANALOG_CHANNEL_OUTPUT"
value="report"/>
<property key="warningmessagebreakoptions.W0211_ADC_PIN_INVALID_CHANNEL"
value="report"/>
<property key="warningmessagebreakoptions.W0212_ADC_BAND_GAP_NOT_SUPPORTED"
value="report"/>
<property key="warningmessagebreakoptions.W0213_ADC_RESERVED_SSRC"
value="report"/>
<property key="warningmessagebreakoptions.W0214_ADC_POSITIVE_INPUT_DIGITAL"
value="report"/>
<property key="warningmessagebreakoptions.W0215_ADC_POSITIVE_INPUT_OUTPUT"
value="report"/>
<property key="warningmessagebreakoptions.W0216_ADC_NEGATIVE_INPUT_DIGITAL"
value="report"/>
<property key="warningmessagebreakoptions.W0217_ADC_NEGATIVE_INPUT_OUTPUT"
value="report"/>
<property key="warningmessagebreakoptions.W0218_ADC_REFERENCE_HIGH_DIGITAL"
value="report"/>
<property key="warningmessagebreakoptions.W0219_ADC_REFERENCE_HIGH_OUTPUT"
value="report"/>
<property key="warningmessagebreakoptions.W0220_ADC_REFERENCE_LOW_DIGITAL"
value="report"/>
<property key="warningmessagebreakoptions.W0221_ADC_REFERENCE_LOW_OUTPUT"
value="report"/>
<property key="warningmessagebreakoptions.W0222_ADC_OVERFLOW" value="report"/>
<property key="warningmessagebreakoptions.W0223_ADC_UNDERFLOW" value="report"/>
<property key="warningmessagebreakoptions.W0224_ADC_CTMU_NOT_SUPPORTED"
value="report"/>
<property key="warningmessagebreakoptions.W0225_ADC_INVALID_CH0S"
value="report"/>
<property key="warningmessagebreakoptions.W0226_ADC_VBAT_NOT_SUPPORTED"
value="report"/>
<property key="warningmessagebreakoptions.W0227_ADC_INVALID_ADCS"
value="report"/>
<property key="warningmessagebreakoptions.W1201_DATAFLASH_MEM_OUTSIDE_RANGE"
value="report"/>
<property key="warningmessagebreakoptions.W1202_DATAFLASH_ERASE_WHILE_LOCKED"
value="report"/>
<property key="warningmessagebreakoptions.W1203_DATAFLASH_WRITE_WHILE_LOCKED"
value="report"/>
<property key="warningmessagebreakoptions.W1401_DMA_PERIPH_NOT_AVAIL"
value="report"/>
<property key="warningmessagebreakoptions.W1402_DMA_INVALID_IRQ" value="report"/>
<property key="warningmessagebreakoptions.W1403_DMA_INVALID_SFR" value="report"/>
<property key="warningmessagebreakoptions.W1404_DMA_INVALID_DMA_ADDR"
value="report"/>
<property key="warningmessagebreakoptions.W1405_DMA_IRQ_DIR_MISMATCH"
value="report"/>
<property key="warningmessagebreakoptions.W2001_INPUTCAPTURE_TMR3_UNAVAILABLE"
value="report"/>
<property key="warningmessagebreakoptions.W2002_INPUTCAPTURE_CAPTURE_EMPTY"
value="report"/>
<property key="warningmessagebreakoptions.W9001_TMR_GATE_AND_EXTCLOCK_ENABLED"
value="report"/>
<property key="warningmessagebreakoptions.W9002_TMR_NO_PIN_AVAILABLE"
value="report"/>
<property key="warningmessagebreakoptions.W9003_TMR_INVALID_CLOCK_SOURCE"
value="report"/>
<property key="warningmessagebreakoptions.W9201_UART_TX_OVERFLOW"
value="report"/>
<property key="warningmessagebreakoptions.W9202_UART_TX_CAPTUREFILE"
value="report"/>
<property key="warningmessagebreakoptions.W9203_UART_TX_INVALIDINTERRUPTMODE"
value="report"/>
<property key="warningmessagebreakoptions.W9204_UART_RX_EMPTY_QUEUE"
value="report"/>
<property key="warningmessagebreakoptions.W9205_UART_TX_BADFILE" value="report"/>
<property key="warningmessagebreakoptions.W9801_SCL_BAD_SUBTYPE_INDICATION"
value="report"/>
<property key="warningmessagebreakoptions.W9802_SCL_FILE_NOT_FOUND"
value="report"/>
<property key="warningmessagebreakoptions.W9803_SCL_FAILED_TO_READ_FILE"
value="report"/>
<property key="warningmessagebreakoptions.W9804_SCL_UNRECOGNIZED_LABEL"
value="report"/>
<property key="warningmessagebreakoptions.W9805_SCL_UNRECOGNIZED_VAR"
value="report"/>
<property key="warningmessagebreakoptions.displaywarningmessagesoption"
value=""/>
<property key="warningmessagebreakoptions.warningmessages" value="holdstate"/>
</Simulator>
</conf>
</confs>
</configurationDescriptor>

25
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/private/SuppressibleMessageMemo.properties Normal file
View File

@ -0,0 +1,25 @@
#
#Tue Aug 25 11:11:09 BST 2015
mdbDebugger/MEMORY_VIEW_LAST_HW_BP_RESOURCE_WARN=false
pkobskde/CHECK_4_HIGH_VOLTAGE_VPP=false
pk3/DEVID_MISMATCH=false
mdbDebugger/NO_HW_COMBINER_RESOURCES_WARNING=false
mdbDebugger/NO_HW_BP_RESOURCES_WARN=false
icd3/CAL_WARNING=false
mdbDebugger/MEMORY_VIEW_NO_HW_BP_RESOURCES_WARN=false
pk3/CHECK_CLOCK=false
mdbDebugger/LAST_HW_BP_RESOURCE_WARN=false
pk3/CHECK_4_HIGH_VOLTAGE_VPP=false
icd3/DEVID_MISMATCH=true
realice/DEVID_MISMATCH=true
realice/CHECK_CLOCK=false
pkoblicdbgr/DEVID_MISMATCH=false
pkoblicdbgr/CHECK_CLOCK=false
pkobskde/DEVID_MISMATCH=false
icd3/CHECK_CLOCK=false
realice/CHECK_4_HIGH_VOLTAGE_VPP=false
pkoblicdbgr/CHECK_4_HIGH_VOLTAGE_VPP=false
pk3/CAL_WARNING=false
icd3/CHECK_4_HIGH_VOLTAGE_VPP=false
pkobskde/CHECK_CLOCK=false
realice/CAL_WARNING=false

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<?xml version="1.0" encoding="UTF-8"?>
<configurationDescriptor version="62">
<projectmakefile>Makefile</projectmakefile>
<defaultConf>0</defaultConf>
<confs>
<conf name="default" type="2">
<platformToolSN>:=MPLABComm-USB-Microchip:=&lt;vid>04D8:=&lt;pid>9009:=&lt;rev>0100:=&lt;man>Microchip Technology, Inc. (www.microchip.com):=&lt;prod>MPLAB ICD3 tm (www.microchip.com):=&lt;sn>JIT112942201:=&lt;drv>x:=&lt;xpt>b:=end</platformToolSN>
<languageToolchainDir>C:\DevTools\Microchip\xc32\v1.33\bin</languageToolchainDir>
<mdbdebugger version="1">
<placeholder1>place holder 1</placeholder1>
<placeholder2>place holder 2</placeholder2>
</mdbdebugger>
<runprofile version="6">
<args></args>
<rundir></rundir>
<buildfirst>true</buildfirst>
<console-type>0</console-type>
<terminal-type>0</terminal-type>
<remove-instrumentation>0</remove-instrumentation>
<environment>
</environment>
</runprofile>
</conf>
</confs>
</configurationDescriptor>

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<editor-bookmarks xmlns="http://www.netbeans.org/ns/editor-bookmarks/2" lastBookmarkId="0"/>
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<group>
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<file>file:/C:/Users/m91145/Documents/OS%20IDE%20Specialist%20Team/FreeRTOS%20MEC%20Port/FreeRTOS/Source/tasks.c</file>
<file>file:/C:/Users/m91145/Documents/OS%20IDE%20Specialist%20Team/FreeRTOS%20MEC%20Port/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/timertest.c</file>
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<file>file:/C:/Users/m91145/Documents/OS%20IDE%20Specialist%20Team/FreeRTOS%20MEC%20Port/FreeRTOS/Demo/Common/Minimal/IntQueue.c</file>
<file>file:/C:/Users/m91145/Documents/OS%20IDE%20Specialist%20Team/FreeRTOS%20MEC%20Port/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer.c</file>
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<?xml version="1.0" encoding="UTF-8"?>
<project xmlns="http://www.netbeans.org/ns/project/1">
<type>com.microchip.mplab.nbide.embedded.makeproject</type>
<configuration>
<data xmlns="http://www.netbeans.org/ns/make-project/1">
<name>PIC32MEC14xx_RTOSDemo</name>
<creation-uuid>ae050a6a-b5b0-45c7-b21f-96b074d910a4</creation-uuid>
<make-project-type>0</make-project-type>
<c-extensions>c</c-extensions>
<cpp-extensions/>
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BIN
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/spiimage/PIC32MEC14xx_RTOSDemo_SPI_16M.bin Normal file
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FreeRTOS/Demo/PIC32MEC14xx_MPLAB/linkfile/custom_pMEC1404.ld Normal file
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/*--------------------------------------------------------------------------
* MPLAB XC Compiler - MEC1404 linker script
* Build date : Jul 14 2014
*
* This software is developed by Microchip Technology Inc. and its
* subsidiaries ("Microchip").
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* 3. Microchip's name may not be used to endorse or promote products
* derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*-------------------------------------------------------------------------*/
/* Default linker script, for normal executables */
OUTPUT_FORMAT("elf32-tradlittlemips")
OUTPUT_ARCH(pic32mx)
ENTRY(_reset)
/*
* Provide for a minimum stack and heap size
* - _min_stack_size - represents the minimum space that must be made
* available for the stack. Can be overridden from
* the command line using the linker's --defsym option.
* - _min_heap_size - represents the minimum space that must be made
* available for the heap. Must be specified on
* the command line using the linker's --defsym option.
*/
EXTERN (_min_stack_size _min_heap_size)
PROVIDE(_min_stack_size = 0x400) ;
PROVIDE(_min_heap_size = 0x400) ;
/*************************************************************************
* Processor-specific object file. Contains SFR definitions.
*************************************************************************/
INPUT("processor.o")
/*************************************************************************
* For interrupt vector handling
*************************************************************************/
PROVIDE(_vector_spacing = 0x00000001);
PROVIDE(_ebase_address = 0xBFD00000);
/*************************************************************************
* Memory Address Equates
* _RESET_ADDR -- Reset Vector
* _GEN_EXCPT_ADDR -- General Exception Vector
*************************************************************************/
_RESET_ADDR = 0xBFD00000;
_GEN_EXCPT_ADDR = _ebase_address + 0x180;
/*************************************************************************
* Memory Regions
*
* Memory regions without attributes cannot be used for orphaned sections.
* Only sections specifically assigned to these regions can be allocated
* into these regions.
*************************************************************************/
MEMORY
{
rom (rx) : ORIGIN = 0xBFC00000, LENGTH = 0x10000
kseg0_program_mem (rx) : ORIGIN = 0xBFD00000, LENGTH = 0x18000
sfrs : ORIGIN = 0xBFBFEFF0, LENGTH = 0x100000
kseg1_data_mem (rwx) : ORIGIN = 0xBFD18000, LENGTH = 0x8000
}
SECTIONS
{
.reset _RESET_ADDR :
{
KEEP(*(.reset))
} > kseg0_program_mem
.app_excpt _GEN_EXCPT_ADDR :
{
KEEP(*(.gen_handler))
} > kseg0_program_mem
/* MEC14x4 JTVIC has 19 aggregated interrupt sources in its
* power-on-reset configuration. MEC14xx data sheet uses nomenclature
* GIRQ00 - GIRQ18.
* MEC14x4 M14K core was built to support EIC Mode 2 only. The JTVIC
* supplies a 17-bit offset to the M14K core. The M14K combines this
* 17-bit offset with EBASE to produce the final vector location.
* Similar to the PIC32MZ EVIC, the JTVIC has a register for each
* GIRQx containing the 17-bit value supplied to the M14K core.
* This means ISR's can be located anywhere above EBASE except for
* the fixed location of the General Exception at EBASE + 0x180.
* To avoid overhead of XC32 .vector_N long jumps we will program
* the address of the C ISR directly into the JTVIC. All ISR's
* can be in .text
* C ISR's must also be marked with the interrupt(XXX_IPL) attribute
* so the compiler knows about priority, etc.
*/
.vectors _ebase_address + 0x200 :
{
/*
KEEP (*(.vector_0))
KEEP (*(.vector_1))
KEEP (*(.vector_2))
KEEP (*(.vector_3))
KEEP (*(.vector_4))
KEEP (*(.vector_5))
KEEP (*(.vector_6))
KEEP (*(.vector_7))
KEEP (*(.vector_8))
KEEP (*(.vector_9))
KEEP (*(.vector_10))
KEEP (*(.vector_11))
KEEP (*(.vector_12))
KEEP (*(.vector_13))
KEEP (*(.vector_14))
KEEP (*(.vector_15))
KEEP (*(.vector_16))
KEEP (*(.vector_17))
KEEP (*(.vector_18))
*/
KEEP (SORT_BY_NAME(*)(.girqs.*))
KEEP (*(.vec_default))
} > kseg0_program_mem
/* The startup code is in the .reset.startup section.
* SRAM Application startup code does NOT need to be
* located at the beginning of CODE SRAM. A processor/chip
* reset will go to the BootROM reset/startup code and
* begin the BootROM SPI application load sequence.
* Upon a successful SPI load and verification, BootROM
* will jump into the Application. We expect the jump address
* to be .startup(reset handler) of the application because
* .startup runs the XC32 startup code and calls C main.
* Since application .startup is never entered on a real HW
* reset/nmi/soft-reset it can be located anywhere in SRAM
* CODE space.
*/
.startup :
{
KEEP(*(.startup))
KEEP(*(.reset.startup))
} > kseg0_program_mem
/* Code Sections - Note that input sections *(.text) and *(.text.*)
* are not mapped here. The best-fit allocator locates them,
* so that .text may flow around absolute sections as needed.
*/
.text :
{
*(.stub .gnu.linkonce.t.*)
KEEP (*(.text.*personality*))
*(.mips16.fn.*)
*(.mips16.call.*)
*(.gnu.warning)
. = ALIGN(4) ;
} >kseg0_program_mem
/* Global-namespace object initialization */
.init :
{
KEEP (*crti.o(.init))
KEEP (*crtbegin.o(.init))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))
KEEP (*crtend.o(.init))
KEEP (*crtn.o(.init))
. = ALIGN(4) ;
} >kseg0_program_mem
.fini :
{
KEEP (*(.fini))
. = ALIGN(4) ;
} >kseg0_program_mem
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4) ;
} >kseg0_program_mem
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4) ;
} >kseg0_program_mem
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4) ;
} >kseg0_program_mem
.ctors :
{
/* XC32 uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
. = ALIGN(4) ;
} >kseg0_program_mem
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
. = ALIGN(4) ;
} >kseg0_program_mem
/* Read-only sections */
.rodata :
{
*( .gnu.linkonce.r.*)
*(.rodata1)
. = ALIGN(4) ;
} >kseg0_program_mem
/*
* Small initialized constant global and static data can be placed in the
* .sdata2 section. This is different from .sdata, which contains small
* initialized non-constant global and static data.
*/
.sdata2 ALIGN(4) :
{
*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
. = ALIGN(4) ;
} >kseg0_program_mem
/*
* Uninitialized constant global and static data (i.e., variables which will
* always be zero). Again, this is different from .sbss, which contains
* small non-initialized, non-constant global and static data.
*/
.sbss2 ALIGN(4) :
{
*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
. = ALIGN(4) ;
} >kseg0_program_mem
.eh_frame_hdr :
{
*(.eh_frame_hdr)
} >kseg0_program_mem
. = ALIGN(4) ;
.eh_frame : ONLY_IF_RO
{
KEEP (*(.eh_frame))
} >kseg0_program_mem
. = ALIGN(4) ;
.gcc_except_table : ONLY_IF_RO
{
*(.gcc_except_table .gcc_except_table.*)
} >kseg0_program_mem
. = ALIGN(4) ;
.persist :
{
_persist_begin = .;
*(.persist .persist.*)
*(.pbss .pbss.*)
. = ALIGN(4) ;
_persist_end = .;
} >kseg1_data_mem
.jcr :
{
KEEP (*(.jcr))
. = ALIGN(4) ;
} >kseg1_data_mem
.eh_frame : ONLY_IF_RW
{
KEEP (*(.eh_frame))
} >kseg1_data_mem
. = ALIGN(4) ;
.gcc_except_table : ONLY_IF_RW
{
*(.gcc_except_table .gcc_except_table.*)
} >kseg1_data_mem
. = ALIGN(4) ;
/* Persistent data - Use the new C 'persistent' attribute instead. */
/*
.persist :
{
_persist_begin = .;
*(.persist .persist.*)
*(.pbss .pbss.*)
. = ALIGN(4) ;
_persist_end = .;
} >kseg1_data_mem
*/
/*
* Note that input sections named .data* are not mapped here.
* The best-fit allocator locates them, so that they may flow
* around absolute sections as needed.
*/
.data :
{
*( .gnu.linkonce.d.*)
SORT(CONSTRUCTORS)
*(.data1)
. = ALIGN(4) ;
} >kseg1_data_mem
. = .;
_gp = ALIGN(16) + 0x7ff0;
.got ALIGN(4) :
{
*(.got.plt) *(.got)
. = ALIGN(4) ;
} >kseg1_data_mem /* AT>kseg0_program_mem */
/*
* Note that 'small' data sections are still mapped in the linker
* script. This ensures that they are grouped together for
* gp-relative addressing. Absolute sections are allocated after
* the 'small' data sections so small data cannot flow around them.
*/
/*
* We want the small data sections together, so single-instruction offsets
* can access them all, and initialized data all before uninitialized, so
* we can shorten the on-disk segment size.
*/
.sdata ALIGN(4) :
{
_sdata_begin = . ;
*(.sdata .sdata.* .gnu.linkonce.s.*)
. = ALIGN(4) ;
_sdata_end = . ;
} >kseg1_data_mem
.lit8 :
{
*(.lit8)
} >kseg1_data_mem
.lit4 :
{
*(.lit4)
} >kseg1_data_mem
. = ALIGN (4) ;
_data_end = . ;
_bss_begin = . ;
.sbss ALIGN(4) :
{
_sbss_begin = . ;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
_sbss_end = . ;
. = ALIGN(4) ;
} >kseg1_data_mem
/*
* Align here to ensure that the .bss section occupies space up to
* _end. Align after .bss to ensure correct alignment even if the
* .bss section disappears because there are no input sections.
*
* Note that input sections named .bss* are no longer mapped here.
* The best-fit allocator locates them, so that they may flow
* around absolute sections as needed.
*
*/
.bss :
{
*(.dynbss)
*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(. != 0 ? 4 : 1);
} >kseg1_data_mem
. = ALIGN(4) ;
_end = . ;
_bss_end = . ;
/*
* The heap and stack are best-fit allocated by the linker after other
* data and bss sections have been allocated.
*/
/* MCHP - disable best-fit allocation of stack & heap */
.heap ALIGN(16) :
{
_heap_bottom = .;
. += _min_heap_size;
_heap_top = .;
} >kseg1_data_mem
.stack ALIGN(16) :
{
_stack_bottom = .;
. += _min_stack_size;
. = ALIGN(16);
_stack_top = .;
} >kseg1_data_mem
PROVIDE( _heap = _heap_bottom );
PROVIDE( _stack = _stack_top );
PROVIDE( _stack_start = _stack_bottom );
/*
* RAM functions go at the end of our stack and heap allocation.
* Alignment of 2K required by the boundary register (BMXDKPBA).
*
* RAM functions are now allocated by the linker. The linker generates
* _ramfunc_begin and _bmxdkpba_address symbols depending on the
* location of RAM functions.
*/
_bmxdudba_address = LENGTH(kseg1_data_mem) ;
_bmxdupba_address = LENGTH(kseg1_data_mem) ;
/* The .pdr section belongs in the absolute section */
/DISCARD/ : { *(.pdr) }
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
.mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }
.mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }
.mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }
.mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }
.mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }
.mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }
.gcc_compiled_long32 : { KEEP(*(.gcc_compiled_long32)) }
.gcc_compiled_long64 : { KEEP(*(.gcc_compiled_long64)) }
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections used by MPLAB X for source-level debugging.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
/DISCARD/ : { *(.rel.dyn) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) }
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) *(.discard) }
}

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FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/Blinky_Demo/main_blinky.c Normal file
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/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky style
* project, and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
* in main.c. This file implements the simply blinky style version.
*
* NOTE 2: This file only contains the source code that is specific to the
* basic demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
******************************************************************************
*
* main_blinky() creates one queue, two tasks, and one software timer. It then
* starts the scheduler.
*
* The Blinky Software Timer:
* This demonstrates an auto-reload software timer. The timer callback function
* does nothing but toggle an LED.
*
* The Queue Send Task:
* The queue send task is implemented by prvQueueSendTask() in main_blinky.c.
* prvQueueSendTask() repeatedly blocks for 200 milliseconds before sending the
* value 100 to the queue that was created in main_blinky().
*
* The Queue Receive Task:
* The queue receive task is implemented by prvQueueReceiveTask() in
* main_blinky.c. prvQueueReceiveTask() repeatedly blocks on attempts to read
* from the queue that was created in main_blinky(), toggling an LED each time
* data is received. The queue send task sends data to the queue every 200
* milliseconds, so the LED will toggle every 200 milliseconds.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "timers.h"
/* Priorities at which the tasks are created. */
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* The rate at which data is sent to the queue. The 200ms value is converted
to ticks using the portTICK_PERIOD_MS constant. */
#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )
/* The number of items the queue can hold. This is 1 as the receive task
will remove items as they are added, meaning the send task should always find
the queue empty. */
#define mainQUEUE_LENGTH ( 1 )
/* Values passed to the two tasks just to check the task parameter
functionality. */
#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )
#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )
/* The period of the blinky software timer. The period is specified in ms and
converted to ticks using the portTICK_PERIOD_MS constant. */
#define mainBLINKY_TIMER_PERIOD ( 50 / portTICK_PERIOD_MS )
/* The LED used by the communicating tasks and the blinky timer respectively. */
#define mainTASKS_LED ( 0 )
#define mainTIMER_LED ( 1 )
/* Misc. */
#define mainDONT_BLOCK ( 0 )
/*-----------------------------------------------------------*/
/*
* The tasks as described in the comments at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
/*
* The callback function for the blinky software timer, as described at the top
* of this file.
*/
static void prvBlinkyTimerCallback( TimerHandle_t xTimer );
/*
* Called by main() to create the simply blinky style application if
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
*/
void main_blinky( void );
/*
* LED toggle function that uses a critical section to ensure thread safety.
*/
extern void vToggleLED( uint8_t ucLED );
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
static QueueHandle_t xQueue = NULL;
/*-----------------------------------------------------------*/
void main_blinky( void )
{
TimerHandle_t xTimer;
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
configASSERT( xQueue );
if( xQueue != NULL )
{
/* Create the two tasks as described in the comments at the top of this
file. */
xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
"Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */
mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
NULL ); /* The task handle is not required, so NULL is passed. */
xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Create the blinky software timer as described at the top of this file. */
xTimer = xTimerCreate( "Blinky", /* A text name, purely to help debugging. */
( mainBLINKY_TIMER_PERIOD ),/* The timer period. */
pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
( void * ) 0, /* The ID is not used, so can be set to anything. */
prvBlinkyTimerCallback ); /* The callback function that inspects the status of all the other tasks. */
configASSERT( xTimer );
if( xTimer != NULL )
{
xTimerStart( xTimer, mainDONT_BLOCK );
}
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was insufficient FreeRTOS heap memory available for the idle and/or
timer tasks to be created. See the memory management section on the
FreeRTOS web site for more details. http://www.freertos.org/a00111.html */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvQueueSendTask( void *pvParameters )
{
TickType_t xNextWakeTime;
const unsigned long ulValueToSend = 100UL;
/* Remove compiler warnings in the case that configASSERT() is not defined. */
( void ) pvParameters;
/* Check the task parameter is as expected. */
configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again.
The block time is specified in ticks, the constant used converts ticks
to ms. While in the Blocked state this task will not consume any CPU
time. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle the LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xQueueSend( xQueue, &ulValueToSend, 0U );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
unsigned long ulReceivedValue;
/* Remove compiler warnings in the case where configASSERT() is not defined. */
( void ) pvParameters;
/* Check the task parameter is as expected. */
configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but
is it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == 100UL )
{
vToggleLED( mainTASKS_LED );
ulReceivedValue = 0U;
}
}
}
/*-----------------------------------------------------------*/
static void prvBlinkyTimerCallback( TimerHandle_t xTimer )
{
/* Avoid compiler warnings. */
( void ) xTimer;
/* This function is called when the blinky software time expires. All the
function does is toggle the LED. LED mainTIMER_LED should therefore toggle
with the period set by mainBLINKY_TIMER_PERIOD. */
vToggleLED( mainTIMER_LED );
}
/*-----------------------------------------------------------*/

184
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/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#ifdef __XC32__
#include <xc.h>
#endif
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
/* The MEC14xx controller allows interrupts to be aggregated into a single
* signal which triggers a single interrupt with a fixed priority for all
* interrupt levels. Alternatively the signals can be disaggregated into unique
* interrupt events which can be vectored via a dispatch table to unique
* handlers for each interrupt source. This mechanism allows, for instance, a
* single interrupt handler for a large number of IO pins yet unique handlers
* for timers and other signals.
*
* When operating in disaggregated mode certain restrictions apply. The
* interrupt event and status registers are shared between timers due to their
* proximity in the memory map. Similarly the software interrupt control
* registers are shared with other interrupt sources. The JTVIC maps interrupt
* levels into MIPs core interrupt levels consequently JTVIC priorities of 0, 1,
* 3, and 4 map to the MIPs core values of 1, 3, 5, and 7. The parameter
* configTIMERS_DISAGGREGATED_ISRS is used to control if the timers in register
* GIRQ23 are operating in disaggregated mode. Similarly
* configCPU_DISAGGREGATED_ISRS controls the mode for GIRQ24.
*
* Note:
* Disaggregated mode is the more natural manner in which to operate the ISRs
* and currently only this mode has been tested with the demo application. If
* you wish to use aggregated mode then an alternative interrupt handler scheme
* will need to be used that marshals all interrupts from a single GIRQ through
* a common handler function that tests which interrupt occurred and dispatches
* to the relevant handlers.
*/
#define configTIMERS_DISAGGREGATED_ISRS 1
#define configCPU_DISAGGREGATED_ISRS 1
#define configUSE_PREEMPTION 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#define configUSE_QUEUE_SETS 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#define configCPU_CLOCK_HZ ( 48000000UL )
#define configPERIPHERAL_CLOCK_HZ ( 48000000UL )
#define configMAX_PRIORITIES ( 5UL )
#define configMINIMAL_STACK_SIZE ( 190 )
/* MEC14xx JTVIC HW implements 4 priority levels. */
#define configISR_STACK_SIZE ( 4 * configMINIMAL_STACK_SIZE )
#define configTOTAL_HEAP_SIZE ( ( size_t ) 22800 )
#define configMAX_TASK_NAME_LEN ( 8 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configCHECK_FOR_STACK_OVERFLOW 3
#define configQUEUE_REGISTRY_SIZE 0
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configGENERATE_RUN_TIME_STATS 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_uxTaskGetStackHighWaterMark 1
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTimerPendFunctionCall 1
/* The priority at which the tick interrupt runs.
* Use interrupt controller priority 1 */
#define configKERNEL_INTERRUPT_PRIORITY 0x01
/* The maximum interrupt priority from which FreeRTOS.org API functions can
be called. Only API functions that end in ...FromISR() can be used within
interrupts. This describes the interrupt in a numeric range from 1 to 7 however
only values 1, 3, 5, and 7 are valid */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 0x03
/* Prevent C specific syntax being included in assembly files. */
#ifndef __LANGUAGE_ASSEMBLY
extern void vAssertCalled( const char * pcFile, unsigned long ulLine );
#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ )
#endif
#endif /* FREERTOS_CONFIG_H */

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/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/* FreeRTOS includes. */
#include "FreeRTOS.h"
/* Standard demo includes. */
#include "IntQueueTimer.h"
#include "IntQueue.h"
/* Microchip includes. */
#include "MEC14xx/mec14xx_timers.h"
#include "MEC14xx/mec14xx_jtvic.h"
#include "MEC14xx/mec14xx.h"
/* The frequency of the two timers is offset so the time between the timers
expiring is not always the same. */
#define timerINTERRUPT0_FREQUENCY ( 2000UL )
#define timerINTERRUPT1_FREQUENCY ( 2221UL )
/* MEC14xx JTVIC external interrupt controller is mapped to M14K closely-coupled
peripheral space. */
#define portMMCR_JTVIC_GIRQ23_PRIA *((volatile uint32_t *)(0xBFFFC3F0ul))
/*-----------------------------------------------------------*/
/* These are the C handlers called from the asm wrappers. */
void vT0InterruptHandler( void );
void vT1InterruptHandler( void );
/*-----------------------------------------------------------*/
void vInitialiseTimerForIntQueueTest( void )
{
/* Timer RT is used for the tick interrupt, timer 3 is used for the high
frequency interrupt test. This file therefore uses timers 0 and 1. */
uint32_t ulPreload = ( unsigned short ) ( ( configPERIPHERAL_CLOCK_HZ / ( unsigned long ) timerINTERRUPT0_FREQUENCY ) );
btmr_sleep_en( BTMR0_ID, 0 );
btmr_init( BTMR0_ID, BTMR_COUNT_DOWN + BTMR_AUTO_RESTART + BTMR_INT_EN, 0, ulPreload, ulPreload );
btmr_start( BTMR0_ID );
jtvic_clr_source( MEC14xx_GIRQ23_ID, 0 );
portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 0 );
portMMCR_JTVIC_GIRQ23_PRIA |= ( ( portIPL_TO_CODE( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) << 0 );
jtvic_en_source( MEC14xx_GIRQ23_ID, 0, pdTRUE );
ulPreload = ( unsigned short ) ( ( configPERIPHERAL_CLOCK_HZ / ( unsigned long ) timerINTERRUPT1_FREQUENCY ) );
btmr_sleep_en( BTMR1_ID, 0 );
btmr_init( BTMR1_ID, BTMR_COUNT_DOWN + BTMR_AUTO_RESTART + BTMR_INT_EN, 0, ulPreload, ulPreload );
btmr_start( BTMR1_ID );
jtvic_clr_source( MEC14xx_GIRQ23_ID, 1 );
portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 4 );
portMMCR_JTVIC_GIRQ23_PRIA |= ( ( portIPL_TO_CODE( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) << 4 );
jtvic_en_source( MEC14xx_GIRQ23_ID, 1, pdTRUE );
}
/*-----------------------------------------------------------*/
void vT0InterruptHandler( void )
{
/* Disable all interrupts because the source bit is shared with a bit used
by the other timer and the high frequency timer test. */
__asm volatile( "di" );
/* Clear the timer interrupt. */
jtvic_clr_source( MEC14xx_GIRQ23_ID, 0 );
__asm volatile( "ei" );
portEND_SWITCHING_ISR( xFirstTimerHandler() );
}
/*-----------------------------------------------------------*/
void vT1InterruptHandler( void )
{
/* Disable all interrupts because the source bit is shared with a bit used
by the other timer and the high frequency timer test. */
__asm volatile( "di" );
/* Clear the timer interrupt. */
jtvic_clr_source( MEC14xx_GIRQ23_ID, 1 );
__asm volatile( "ei" );
portEND_SWITCHING_ISR( xSecondTimerHandler() );
}

78
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/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef INT_QUEUE_TIMER_H
#define INT_QUEUE_TIMER_H
void vInitialiseTimerForIntQueueTest( void );
portBASE_TYPE xTimer0Handler( void );
portBASE_TYPE xTimer1Handler( void );
#endif

123
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer_isr.S Normal file
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/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#include <xc.h>
#include <sys/asm.h>
#include "ISR_Support.h"
#define portEXC_CODE_MASK ( 0x1f << 2 )
.extern vT0InterruptHandler
.extern vT1InterruptHandler
.global vT0InterruptWrapper
.global vT1InterruptWrapper
/******************************************************************/
.set micromips
.set noreorder
.set noat
.ent vT0InterruptWrapper
.global girq23_b0
girq23_b0:
vT0InterruptWrapper:
portSAVE_CONTEXT
jal vT0InterruptHandler
nop
portRESTORE_CONTEXT
.end vT0InterruptWrapper
/******************************************************************/
.set micromips
.set noreorder
.set noat
.ent vT1InterruptWrapper
.global girq23_b1
girq23_b1:
vT1InterruptWrapper:
portSAVE_CONTEXT
jal vT1InterruptHandler
nop
portRESTORE_CONTEXT
.end vT1InterruptWrapper

257
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/RegisterTestTasks.S Normal file
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/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#include <xc.h>
#include <sys/asm.h>
.global vRegTest1
.global vRegTest2
/* Reg test macro helper. Test a register for a known value branching to
error_loop if not correct otherwise continuing on */
.macro portREG_TEST work_reg, test_reg, test_value
.set micromips
.set noreorder
.set noat
/* Check each register maintains the value assigned to it for the lifetime
of the task. */
addiu \work_reg, $0, 0x00
addiu \work_reg, \test_reg, -\test_value
beq \work_reg, $0, 1f
nop
/* The register value was not that expected. Jump to the error loop so the
cycle counter stops incrementing. */
b error_loop
nop
1:
.endm
.set micromips
.set noreorder
.set noat
.ent error_loop
/* Reg test tasks call the error loop when they find an error. Sitting in the
tight error loop prevents them incrementing their ulRegTestnCycles counter, and
so allows the check softwate timer to know an error has been found. */
error_loop:
b error_loop
nop
.end error_loop
.set micromips
.set noreorder
.set noat
.ent vRegTest1
vRegTest1:
/* Fill the registers with known values. */
addiu $1, $0, 0x11
addiu $2, $0, 0x12
addiu $3, $0, 0x13
/* $4 contains the address of the loop counter - don't mess with $4. */
addiu $5, $0, 0x15
addiu $6, $0, 0x16
addiu $7, $0, 0x17
addiu $8, $0, 0x18
addiu $9, $0, 0x19
addiu $10, $0, 0x110
addiu $11, $0, 0x111
addiu $12, $0, 0x112
addiu $13, $0, 0x113
addiu $14, $0, 0x114
addiu $15, $0, 0x115
addiu $16, $0, 0x116
addiu $17, $0, 0x117
addiu $18, $0, 0x118
addiu $19, $0, 0x119
addiu $20, $0, 0x120
addiu $21, $0, 0x121
addiu $23, $0, 0x123
addiu $24, $0, 0x124
addiu $25, $0, 0x125
addiu $30, $0, 0x130
addiu $22, $0, 0x131
vRegTest1Loop:
portREG_TEST $22, $1, 0x11
portREG_TEST $22, $2, 0x12
portREG_TEST $22, $3, 0x13
portREG_TEST $22, $5, 0x15
portREG_TEST $22, $6, 0x16
portREG_TEST $22, $7, 0x17
portREG_TEST $22, $8, 0x18
portREG_TEST $22, $9, 0x19
portREG_TEST $22, $10, 0x110
portREG_TEST $22, $11, 0x111
portREG_TEST $22, $12, 0x112
portREG_TEST $22, $13, 0x113
portREG_TEST $22, $14, 0x114
portREG_TEST $22, $15, 0x115
portREG_TEST $22, $16, 0x116
portREG_TEST $22, $17, 0x117
portREG_TEST $22, $18, 0x118
portREG_TEST $22, $19, 0x119
portREG_TEST $22, $20, 0x120
portREG_TEST $22, $21, 0x121
portREG_TEST $22, $23, 0x123
portREG_TEST $22, $24, 0x124
portREG_TEST $22, $25, 0x125
portREG_TEST $22, $30, 0x130
/* No errors detected. Increment the loop count so the check timer knows
this task is still running without error, then loop back to do it all
again. The address of the loop counter is in $4. */
lw $22, 0( $4 )
addiu $22, $22, 0x01
sw $22, 0( $4 )
b vRegTest1Loop
nop
.end vRegTest1
.set micromips
.set noreorder
.set noat
.ent vRegTest2
vRegTest2:
addiu $1, $0, 0x21
addiu $2, $0, 0x22
addiu $3, $0, 0x23
/* $4 contains the address of the loop counter - don't mess with $4. */
addiu $5, $0, 0x25
addiu $6, $0, 0x26
addiu $7, $0, 0x27
addiu $8, $0, 0x28
addiu $9, $0, 0x29
addiu $10, $0, 0x210
addiu $11, $0, 0x211
addiu $12, $0, 0x212
addiu $13, $0, 0x213
addiu $14, $0, 0x214
addiu $15, $0, 0x215
addiu $16, $0, 0x216
addiu $17, $0, 0x217
addiu $18, $0, 0x218
addiu $19, $0, 0x219
addiu $20, $0, 0x220
addiu $21, $0, 0x221
addiu $23, $0, 0x223
addiu $24, $0, 0x224
addiu $25, $0, 0x225
addiu $30, $0, 0x230
addiu $22, $0, 0x231
vRegTest2Loop:
portREG_TEST $22, $1, 0x21
portREG_TEST $22, $2, 0x22
portREG_TEST $22, $3, 0x23
portREG_TEST $22, $5, 0x25
portREG_TEST $22, $6, 0x26
portREG_TEST $22, $7, 0x27
portREG_TEST $22, $8, 0x28
portREG_TEST $22, $9, 0x29
portREG_TEST $22, $10, 0x210
portREG_TEST $22, $11, 0x211
portREG_TEST $22, $12, 0x212
portREG_TEST $22, $13, 0x213
portREG_TEST $22, $14, 0x214
portREG_TEST $22, $15, 0x215
portREG_TEST $22, $16, 0x216
portREG_TEST $22, $17, 0x217
portREG_TEST $22, $18, 0x218
portREG_TEST $22, $19, 0x219
portREG_TEST $22, $20, 0x220
portREG_TEST $22, $21, 0x221
portREG_TEST $22, $23, 0x223
portREG_TEST $22, $24, 0x224
portREG_TEST $22, $25, 0x225
portREG_TEST $22, $30, 0x230
/* No errors detected. Increment the loop count so the check timer knows
this task is still running without error, then loop back to do it all
again. The address of the loop counter is in $4. */
lw $22, 0( $4 )
addiu $22, $22, 0x01
sw $22, 0( $4 )
b vRegTest2Loop
nop
.end vRegTest2

378
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/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky style
* project, and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
* in main.c. This file implements the comprehensive test and demo version.
*
* NOTE 2: This file only contains the source code that is specific to the
* full demo. Generic functions, such as FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
******************************************************************************
*
* main_full() creates all the demo application tasks and software timers, then
* starts the scheduler. The WEB documentation provides more details of the
* standard demo application tasks. In addition to the standard demo tasks, the
* following tasks and tests are also defined:
*
* "Register test" tasks - These tasks are used in part to test the kernel port.
* They set each processor register to a known value, then check that the
* register still contains that value. Each of the tasks sets the registers
* to different values, and will get swapping in and out between setting and
* then subsequently checking the register values. Discovery of an incorrect
* value would be indicative of an error in the task switching mechanism.
*
* "High Frequency Timer Test" - The high frequency timer is created to test
* the interrupt nesting method. The standard demo interrupt nesting test tasks
* are created with priorities at or below configMAX_SYSCALL_INTERRUPT_PRIORITY
* because they use interrupt safe FreeRTOS API functions. The high frequency
* time is created with a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY,
* so cannot us the same API functions.
*
* "Check" timer - The check software timer period is initially set to three
* seconds. The callback function associated with the check software timer
* checks that all the standard demo tasks, and the register check tasks, are
* not only still executing, but are executing without reporting any errors. If
* the check software timer discovers that a task has either stalled, or
* reported an error, then it changes its own execution period from the initial
* three seconds, to just 200ms. The check software timer also toggle LED
* mainCHECK_LED; If mainCHECK_LED toggles every 3 seconds, no errors have
* been detected. If mainCHECK_LED toggles every 200ms then an error has been
* detected in at least one task.
*
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
#include "timers.h"
/* Demo application includes. */
#include "blocktim.h"
#include "semtest.h"
#include "GenQTest.h"
#include "IntQueue.h"
#include "countsem.h"
/*-----------------------------------------------------------*/
/* The period after which the check timer will expire, in ms, provided no errors
have been reported by any of the standard demo tasks. ms are converted to the
equivalent in ticks using the portTICK_PERIOD_MS constant. */
#define mainCHECK_TIMER_PERIOD_MS pdMS_TO_TICKS( 3000UL )
/* The period at which the check timer will expire, in ms, if an error has been
reported in one of the standard demo tasks. ms are converted to the equivalent
in ticks using the portTICK_PERIOD_MS constant. */
#define mainERROR_CHECK_TIMER_PERIOD_MS pdMS_TO_TICKS( 200UL )
/* The priorities of the various demo application tasks. */
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )
/* The LED controlled by the 'check' software timer. */
#define mainCHECK_LED ( 2 )
/* Misc. */
#define mainDONT_BLOCK ( 0 )
/* The frequency at which the "high frequency interrupt" interrupt will
occur. */
#define mainTEST_INTERRUPT_FREQUENCY ( 20000 )
/*-----------------------------------------------------------*/
/*
* The check timer callback function, as described at the top of this file.
*/
static void prvCheckTimerCallback( TimerHandle_t xTimer );
/*
* It is important to ensure the high frequency timer test does not start before
* the kernel. It is therefore started from inside a software timer callback
* function, which will not execute until the timer service/daemon task is
* executing. A one-shot timer is used, so the callback function will only
* execute once (unless it is manually reset/restarted).
*/
static void prvSetupHighFrequencyTimerTest( TimerHandle_t xTimer );
/*
* Tasks that test the context switch mechanism by filling the processor
* registers with known values, then checking that the values contained
* within the registers is as expected. The tasks are likely to get swapped
* in and out between setting the register values and checking the register
* values.
*/
static void prvRegTestTask1( void *pvParameters );
static void prvRegTestTask2( void *pvParameters );
/*
* LED toggle function that uses a critical section to ensure thread safety.
*/
extern void vToggleLED( uint8_t ucLED );
/*-----------------------------------------------------------*/
/* Variables incremented by prvRegTestTask1() and prvRegTestTask2() respectively
on each iteration of their function. These are used to detect errors in the
reg test tasks. */
volatile unsigned long ulRegTest1Cycles = 0, ulRegTest2Cycles = 0;
/*-----------------------------------------------------------*/
/*
* Create the demo tasks then start the scheduler.
*/
int main_full( void )
{
TimerHandle_t xTimer = NULL;
/* Create all the other standard demo tasks. */
vCreateBlockTimeTasks();
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );
vStartInterruptQueueTasks();
vStartCountingSemaphoreTasks();
/* Create the tasks defined within this file. */
xTaskCreate( prvRegTestTask1, /* The function that implements the task. */
"Reg1", /* Text name for the task to assist debugger - not used by FreeRTOS itself. */
configMINIMAL_STACK_SIZE, /* The stack size to allocate for the task - specified in words not bytes. */
NULL, /* The parameter to pass into the task - not used in this case so set to NULL. */
tskIDLE_PRIORITY, /* The priority to assign to the task. */
NULL ); /* Used to obtain a handle to the task being created - not used in this case so set to NULL. */
xTaskCreate( prvRegTestTask2, "Reg2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
/* Create the software timer that performs the 'check' functionality, as
described at the top of this file. */
xTimer = xTimerCreate( "CheckTimer",/* A text name, purely to help debugging. */
( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */
pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
( void * ) 0, /* The ID is not used, so can be set to anything. */
prvCheckTimerCallback ); /* The callback function that inspects the status of all the other tasks. */
if( xTimer != NULL )
{
xTimerStart( xTimer, mainDONT_BLOCK );
}
/* A software timer is also used to start the high frequency timer test.
This is to ensure the test does not start before the kernel. This time a
one shot software timer is used. */
xTimer = xTimerCreate( "HighHzTimerSetup", 1, pdFALSE, ( void * ) 0, prvSetupHighFrequencyTimerTest );
if( xTimer != NULL )
{
xTimerStart( xTimer, mainDONT_BLOCK );
}
/* Finally start the scheduler. */
vTaskStartScheduler();
/* If all is well, the scheduler will now be running, and the following line
will never be reached. If the following line does execute, then there was
insufficient FreeRTOS heap memory available for the idle and/or timer tasks
to be created. See the memory management section on the FreeRTOS web site
for more details. http://www.freertos.org/a00111.html */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvRegTestTask1( void *pvParameters )
{
extern void vRegTest1( volatile unsigned long * );
/* Avoid compiler warnings. */
( void ) pvParameters;
/* Pass the address of the RegTest1 loop counter into the test function,
which is necessarily implemented in assembler. */
vRegTest1( &ulRegTest1Cycles );
/* vRegTest1 should never exit! */
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
static void prvRegTestTask2( void *pvParameters )
{
extern void vRegTest2( volatile unsigned long * );
/* Avoid compiler warnings. */
( void ) pvParameters;
/* Pass the address of the RegTest2 loop counter into the test function,
which is necessarily implemented in assembler. */
vRegTest2( &ulRegTest2Cycles );
/* vRegTest1 should never exit! */
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
static void prvCheckTimerCallback( TimerHandle_t xTimer )
{
static long lChangedTimerPeriodAlready = pdFALSE;
static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0, ulLastHighFrequencyTimerInterrupts = 0;
static const unsigned long ulExpectedHighFrequencyInterrupts = ( ( mainTEST_INTERRUPT_FREQUENCY / 1000UL ) * mainCHECK_TIMER_PERIOD_MS ) - 10; /* 10 allows for a margin of error. */
unsigned long ulErrorOccurred = pdFALSE;
/* The count of the high frequency timer interrupts. */
extern unsigned long ulHighFrequencyTimerInterrupts;
/* Avoid compiler warnings. */
( void ) xTimer;
/* Check that the register test 1 task is still running. */
if( ulLastRegTest1Value == ulRegTest1Cycles )
{
ulErrorOccurred |= ( 0x01UL << 1UL );
}
ulLastRegTest1Value = ulRegTest1Cycles;
/* Check that the register test 2 task is still running. */
if( ulLastRegTest2Value == ulRegTest2Cycles )
{
ulErrorOccurred |= ( 0x01UL << 2UL );
}
ulLastRegTest2Value = ulRegTest2Cycles;
/* Have any of the standard demo tasks detected an error in their
operation? */
if( xAreGenericQueueTasksStillRunning() != pdTRUE )
{
ulErrorOccurred |= ( 0x01UL << 3UL );
}
else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
{
ulErrorOccurred |= ( 0x01UL << 4UL );
}
else if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorOccurred |= ( 0x01UL << 5UL );
}
else if( xAreIntQueueTasksStillRunning() != pdTRUE )
{
ulErrorOccurred |= ( 0x01UL << 6UL );
}
else if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorOccurred |= ( 0x01UL << 7UL );
}
/* Ensure the expected number of high frequency interrupts have occurred. */
if( ulLastHighFrequencyTimerInterrupts != 0 )
{
if( ( ulHighFrequencyTimerInterrupts - ulLastHighFrequencyTimerInterrupts ) < ulExpectedHighFrequencyInterrupts )
{
ulErrorOccurred |= ( 0x01UL << 8UL );
}
}
ulLastHighFrequencyTimerInterrupts = ulHighFrequencyTimerInterrupts;
if( ulErrorOccurred != pdFALSE )
{
/* An error occurred. Increase the frequency at which the check timer
toggles its LED to give visual feedback of the potential error
condition. */
if( lChangedTimerPeriodAlready == pdFALSE )
{
lChangedTimerPeriodAlready = pdTRUE;
/* This call to xTimerChangePeriod() uses a zero block time.
Functions called from inside of a timer callback function must
*never* attempt to block as to do so could impact other software
timers. */
xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );
}
}
vToggleLED( mainCHECK_LED );
}
/*-----------------------------------------------------------*/
static void prvSetupHighFrequencyTimerTest( TimerHandle_t xTimer )
{
void vSetupTimerTest( unsigned short usFrequencyHz );
/* Prevent compiler warnings */
(void) xTimer;
/* Setup the high frequency, high priority, timer test. It is setup in this
software timer callback to ensure it does not start before the kernel does.
This is a one shot timer - so the setup routine will only be executed once. */
vSetupTimerTest( mainTEST_INTERRUPT_FREQUENCY );
}
/*-----------------------------------------------------------*/

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/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/* High speed timer test as described in main.c. */
/* System port includes */
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
/* Scheduler includes. */
#include "FreeRTOS.h"
/* The priority of the high speed timer interrupt. */
#define timerTEST_INT_PRIORITY ( 7 )
/* MEC14xx Timer 3 Timer MMCR's */
#define portMMCR_TMR3_COUNT *((volatile uint32_t *)(0xA0000C60ul))
#define portMMCR_TMR3_PRELOAD *((volatile uint32_t *)(0xA0000C64ul))
#define portMMCR_TMR3_STATUS *((volatile uint32_t *)(0xA0000C68ul))
#define portMMCR_TMR3_INTEN *((volatile uint32_t *)(0xA0000C6Cul))
#define portMMCR_TMR3_CONTROL *((volatile uint32_t *)(0xA0000C70ul))
/* MEC14xx JTVIC external interrupt controller
* is mapped to M14K closely-coupled peripheral space.
*/
#define portGIRQ23_TMR3_TIMER_BITPOS (3)
#define portGIRQ23_TMR3_TIMER_MASK (1ul << (portGIRQ23_TMR3_TIMER_BITPOS))
#define portMMCR_JTVIC_GIRQ23_SRC *((volatile uint32_t *)(0xBFFFC0F0ul))
#define portMMCR_JTVIC_GIRQ23_SETEN *((volatile uint32_t *)(0xBFFFC0F4ul))
#define portMMCR_JTVIC_GIRQ23_PRIA *((volatile uint32_t *)(0xBFFFC3F0ul))
/*-----------------------------------------------------------*/
/* Incremented every 20,000 interrupts, so should count in seconds. */
unsigned long ulHighFrequencyTimerInterrupts = 0;
/*-----------------------------------------------------------*/
void vSetupTimerTest( unsigned short usFrequencyHz )
{
/* Timer 3 is going to interrupt at usFrequencyHz Hz. */
const uint32_t ulPreload = ( unsigned short ) ( ( configPERIPHERAL_CLOCK_HZ / ( unsigned long ) usFrequencyHz ) - 1 );
/* Timer 3 is used to generate interrupts above the kernel and max syscall
interrupt priorities. No system library calls are used here as they are not
guaranteed to be re-entrant. */
portMMCR_TMR3_CONTROL = 1ul;
portMMCR_TMR3_PRELOAD = ulPreload;
portMMCR_TMR3_COUNT = ulPreload;
portMMCR_TMR3_INTEN = 0x0001ul;
portMMCR_TMR3_STATUS = 0x0001ul;
/* Enable Timer 3, and set for auto restart, counting down. */
portMMCR_TMR3_CONTROL |= 0x0008;
portMMCR_TMR3_CONTROL |= 0x0020;
/* Configure interrupts from the Timer 3. */
portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_TMR3_TIMER_MASK );
portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 12 );
portMMCR_JTVIC_GIRQ23_PRIA |= ( ( portIPL_TO_CODE( timerTEST_INT_PRIORITY ) ) << 12 );
portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_TMR3_TIMER_MASK );
}
/*-----------------------------------------------------------*/
/* Interrupt handler for Timer 3 interrupts, no library functions are used
here as they may not be re-entrant. */
void __attribute__((interrupt, nomips16)) girq23_b3( void )
{
ulHighFrequencyTimerInterrupts++;
/* The interrupt flag registered is shared with the lower priority timer
interrupts and the RTOS timer so disable interrupts here. This is not
strictly necessary since this is the highest priority interrupt. */
__asm volatile( "di" );
/* Clear the timer interrupt. */
portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_TMR3_TIMER_MASK;
__asm volatile( "ei" );
}

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/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef TIMER_TEST_H
#define TIMER_TEST_H
/* Setup the high frequency timer interrupt. */
void vSetupTimerTest( unsigned short usFrequencyHz );
#endif /* TIMER_TEST_H */

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file general_exception.c
*MEC14xx General Exception Handler
*/
/** @defgroup MEC14xx Exceptions
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_trace_inline.h"
typedef struct gen_except_capture
{
uint32_t stack_ptr;
uint32_t cp0_status;
uint32_t cp0_cause;
uint32_t cp0_epc;
uint32_t cp0_error_epc;
uint32_t cp0_nexc;
uint32_t cp0_nepc;
uint32_t cp0_badvaddr;
uint32_t ahb_err;
} GEN_EXCEPT_CAPTURE;
GEN_EXCEPT_CAPTURE gexc_cap;
void
__attribute__((nomips16, noreturn)) _general_exception_handler (void)
{
/*
* MEC14xx Application General Exception handler
*/
uint32_t e;
/* Get current Stack Pointer. Note: this is not SP at
* exception. XC32 wraps _general_exception_handler in
* assembly code which saves state resulting is a
* modified SP. Wrapper allocates 88 bytes for context
* save. Original SP = SPcurrent + 88.
*/
__asm__ __volatile (
"move %0,$sp \n\t"
"nop \n\t"
:"=r" (e)
::);
gexc_cap.stack_ptr = e;
gexc_cap.cp0_status = _CP0_GET_STATUS();
gexc_cap.cp0_cause = _CP0_GET_CAUSE();
gexc_cap.cp0_epc = _CP0_GET_EPC();
gexc_cap.cp0_error_epc = _CP0_GET_ERROREPC();
gexc_cap.cp0_nexc = _CP0_GET_NESTEDEXC();
gexc_cap.cp0_nepc = _CP0_GET_NESTEDEPC();
gexc_cap.cp0_badvaddr = _CP0_GET_BADVADDR();
trace0(0, AP3GENEXCEPT, 0, "Application General Exception Handler (BEV=0)");
TRACE11(601, AP3GENEXCEPT, 0, "Current SP = 0x%08x",gexc_cap.stack_ptr);
TRACE11(602, AP3GENEXCEPT, 0, "CP0 STATUS = 0x%08x",gexc_cap.cp0_status);
TRACE11(603, AP3GENEXCEPT, 0, "CP0 CAUSE = 0x%08x",gexc_cap.cp0_cause);
TRACE11(604, AP3GENEXCEPT, 0, "CP0 EPC = 0x%08x",gexc_cap.cp0_epc);
TRACE11(605, AP3GENEXCEPT, 0, "CP0 ERROREPC = 0x%08x",gexc_cap.cp0_error_epc);
TRACE11(606, AP3GENEXCEPT, 0, "CP0 NEXC = 0x%08x",gexc_cap.cp0_nexc);
TRACE11(607, AP3GENEXCEPT, 0, "CP0 NEPC = 0x%08x",gexc_cap.cp0_nepc);
TRACE11(608, AP3GENEXCEPT, 0, "CP0 BADVADDR = 0x%08x",gexc_cap.cp0_badvaddr);
for (;;) {
__asm__ __volatile ("%(ssnop%)" : :);
}
}
/* end general_exception.c */
/** @}
*/

128
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/*********************************************************************
*
* General Exception
*
*********************************************************************
* Filename: general-exception.S
*
* Processor: PIC32
*
* Compiler: MPLAB XC32 v1.00
* MPLAB X IDE
* Company: Microchip Technology Inc.
*
* Software License Agreement
*
* This software is developed by Microchip Technology Inc. and its
* subsidiaries ("Microchip").
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Microchip's name may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************/
#include <xc.h>
#ifdef __LIBBUILD__
.file 1 "general-exception.S"
.loc 1 0
#endif
###################
# Default general exception handler
###################
.extern _general_exception_handler
.section .text.general_exception, code
.set noreorder
.set noat
.set nomips16
.globl _general_exception_context
.ent _general_exception_context
_general_exception_context:
# Save off the non-callee saved registers that may get mucked with
addiu sp, sp, -88
sw $1, 4(sp)
sw v0, 8(sp)
sw v1, 12(sp)
sw a0, 16(sp)
sw a1, 20(sp)
sw a2, 24(sp)
sw a3, 28(sp)
sw t0, 32(sp)
sw t1, 36(sp)
sw t2, 40(sp)
sw t3, 44(sp)
sw t4, 48(sp)
sw t5, 52(sp)
sw t6, 56(sp)
sw t7, 60(sp)
sw t8, 64(sp)
sw t9, 68(sp)
sw ra, 72(sp)
mflo t0
sw t0, 76(sp)
mfhi t0
sw t0, 80(sp)
la k0,_general_exception_handler
nop
# Pass Cause and Status to the handler function
mfc0 a0, _CP0_CAUSE
mfc0 a1, _CP0_STATUS
jalr k0
nop
lw t0, 80(sp)
mthi t0
lw t0, 76(sp)
mtlo t0
lw $1, 4(sp)
lw v0, 8(sp)
lw v1, 12(sp)
lw a0, 16(sp)
lw a1, 20(sp)
lw a2, 24(sp)
lw a3, 28(sp)
lw t0, 32(sp)
lw t1, 36(sp)
lw t2, 40(sp)
lw t3, 44(sp)
lw t4, 48(sp)
lw t5, 52(sp)
lw t6, 56(sp)
lw t7, 60(sp)
lw t8, 64(sp)
lw t9, 68(sp)
lw ra, 72(sp)
addiu sp, sp, 88
ehb
eret
.end _general_exception_context

224
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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq08.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ08_DISAGG == 0
/*
* Aggregated mode handler, must handle all enabled
* GIRQ08 sources.
*/
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq08_isr( void )
{
JTVIC_GROUP_EN_CLR->w = (1ul<<0);
}
#else
/*
* Disaggregated GIRQ08 subhandlers, one for each
* source. Called by assembly language wrapper.
*/
void __attribute__((weak, interrupt, nomips16))
girq08_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 6);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 7);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 8);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 9);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b10(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 10);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b11(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 11);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b12(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 12);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b13(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 13);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b14(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 14);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b15(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 15);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b16(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 16);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b17(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 17);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b18(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 18);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b19(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 19);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b20(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 20);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b21(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 21);
}
void __attribute__((weak, interrupt, nomips16))
girq08_b22(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 22);
}
#endif
/* end girq08.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ08 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq08_b0
.extern girq08_b1
.extern girq08_b2
.extern girq08_b3
.extern girq08_b4
.extern girq08_b5
.extern girq08_b6
.extern girq08_b7
.extern girq08_b8
.extern girq08_b9
.extern girq08_b10
.extern girq08_b11
.extern girq08_b12
.extern girq08_b13
.extern girq08_b14
.extern girq08_b15
.extern girq08_b16
.extern girq08_b17
.extern girq08_b18
.extern girq08_b19
.extern girq08_b20
.extern girq08_b21
.extern girq08_b22
#if GIRQ08_DISAGG != 0
/*
* Disaggregated girq08v
* Program address of this version of girq23v into JTVIC GIRQ08
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq08_isr,code
#else
.section .girqs.girq08_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.global girq08_isr
.ent girq08_isr
.align 2
girq08_isr:
J girq08_b0
NOP
.align 2
J girq08_b1
NOP
.align 2
J girq08_b2
NOP
.align 2
J girq08_b3
NOP
.align 2
J girq08_b4
NOP
.align 2
J girq08_b5
NOP
.align 2
J girq08_b6
NOP
.align 2
J girq08_b7
NOP
.align 2
J girq08_b8
NOP
.align 2
J girq08_b9
NOP
.align 2
J girq08_b10
NOP
.align 2
J girq08_b11
NOP
.align 2
J girq08_b12
NOP
.align 2
J girq08_b13
NOP
.align 2
J girq08_b14
NOP
.align 2
J girq08_b15
NOP
.align 2
J girq08_b16
NOP
.align 2
J girq08_b17
NOP
.align 2
J girq08_b18
NOP
.align 2
J girq08_b19
NOP
.align 2
J girq08_b20
NOP
.align 2
J girq08_b21
NOP
.align 2
J girq08_b22
NOP
.end girq08_isr
/******************************************************************/
#endif

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq09.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ09_DISAGG == 0
/*
* Aggregated mode handler, must handle all enabled
* GIRQ08 sources.
*/
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq09_isr( void )
{
JTVIC_GROUP_EN_CLR->w = (1ul<<1);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq09_b0(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 0);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 0);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b1(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 1);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 1);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b2(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 2);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 2);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b3(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 3);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 3);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b4(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 4);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 4);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b5(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 5);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 5);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b6(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 6);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 6);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b7(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 7);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 7);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b8(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 8);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 8);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b9(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 9);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 9);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b10(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 10);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 10);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b11(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 11);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 11);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b12(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 12);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 12);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b13(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 13);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 13);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b14(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 14);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 14);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b15(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 15);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 15);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b16(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 16);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 16);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b17(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 17);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 17);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b18(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 18);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 18);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b19(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 19);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 19);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b20(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 20);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 20);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b21(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 21);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 21);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b22(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 22);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 22);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b23(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 23);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 23);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b24(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 24);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 24);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b25(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 25);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 25);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b26(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 26);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 26);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b27(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 27);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 27);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b28(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 28);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 28);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b29(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 29);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 29);
}
void __attribute__((weak, interrupt, nomips16))
girq09_b30(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 30);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 30);
}
#endif
/* end girq09.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ09 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq09_b0
.extern girq09_b1
.extern girq09_b2
.extern girq09_b3
.extern girq09_b4
.extern girq09_b5
.extern girq09_b6
.extern girq09_b7
.extern girq09_b8
.extern girq09_b9
.extern girq09_b10
.extern girq09_b11
.extern girq09_b12
.extern girq09_b13
.extern girq09_b14
.extern girq09_b15
.extern girq09_b16
.extern girq09_b17
.extern girq09_b18
.extern girq09_b19
.extern girq09_b20
.extern girq09_b21
.extern girq09_b22
.extern girq09_b23
.extern girq09_b24
.extern girq09_b25
.extern girq09_b26
.extern girq09_b27
.extern girq09_b28
.extern girq09_b29
.extern girq09_b30
#if GIRQ09_DISAGG != 0
/*
* Disaggregated girq09v
* Program address of this version of girq23v into JTVIC GIRQ09
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq09_isr, code
#else
.section .girqs.girq09_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.global girq09_isr
.ent girq09_isr
.align 2
girq09_isr:
J girq09_b0
NOP
.align 2
J girq09_b1
NOP
.align 2
J girq09_b2
NOP
.align 2
J girq09_b3
NOP
.align 2
J girq09_b4
NOP
.align 2
J girq09_b5
NOP
.align 2
J girq09_b6
NOP
.align 2
J girq09_b7
NOP
.align 2
J girq09_b8
NOP
.align 2
J girq09_b9
NOP
.align 2
J girq09_b10
NOP
.align 2
J girq09_b11
NOP
.align 2
J girq09_b12
NOP
.align 2
J girq09_b13
NOP
.align 2
J girq09_b14
NOP
.align 2
J girq09_b15
NOP
.align 2
J girq09_b16
NOP
.align 2
J girq09_b17
NOP
.align 2
J girq09_b18
NOP
.align 2
J girq09_b19
NOP
.align 2
J girq09_b20
NOP
.align 2
J girq09_b21
NOP
.align 2
J girq09_b22
NOP
.align 2
J girq09_b23
NOP
.align 2
J girq09_b24
NOP
.align 2
J girq09_b25
NOP
.align 2
J girq09_b26
NOP
.align 2
J girq09_b27
NOP
.align 2
J girq09_b28
NOP
.align 2
J girq09_b29
NOP
.align 2
J girq09_b30
NOP
.end girq09_isr
#endif
/******************************************************************/

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq10.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ10_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq10_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<2);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq10_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 0, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 1, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 2, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 3, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 4, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 5, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 6, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 7, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 8, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 9, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b10(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 10, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b11(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 11, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b12(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 12, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b13(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 13, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b14(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 14, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b15(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 15, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b16(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 16, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b17(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 17, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b18(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 18, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b19(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 19, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b20(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 20, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b21(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 21, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b22(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 22, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq10_b23(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 23, JTVIC_CLR_SRC);
}
#endif
/* end girq10.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ10 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq10_b0
.extern girq10_b1
.extern girq10_b2
.extern girq10_b3
.extern girq10_b4
.extern girq10_b5
.extern girq10_b6
.extern girq10_b7
.extern girq10_b8
.extern girq10_b9
.extern girq10_b10
.extern girq10_b11
.extern girq10_b12
.extern girq10_b13
.extern girq10_b14
.extern girq10_b15
.extern girq10_b16
.extern girq10_b17
.extern girq10_b18
.extern girq10_b19
.extern girq10_b20
.extern girq10_b21
.extern girq10_b22
.extern girq10_b23
#if GIRQ10_DISAGG != 0
/*
* Disaggregated girq10_isr
* Program address of this version of girq23_isr into JTVIC GIRQ09
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq10_isr, code
#else
.section .girqs.girq10_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq10_isr
.global girq10_isr
.align 2
girq10_isr:
J girq10_b0
NOP
.align 2
J girq10_b1
NOP
.align 2
J girq10_b2
NOP
.align 2
J girq10_b3
NOP
.align 2
J girq10_b4
NOP
.align 2
J girq10_b5
NOP
.align 2
J girq10_b6
NOP
.align 2
J girq10_b7
NOP
.align 2
J girq10_b8
NOP
.align 2
J girq10_b9
NOP
.align 2
J girq10_b10
NOP
.align 2
J girq10_b11
NOP
.align 2
J girq10_b12
NOP
.align 2
J girq10_b13
NOP
.align 2
J girq10_b14
NOP
.align 2
J girq10_b15
NOP
.align 2
J girq10_b16
NOP
.align 2
J girq10_b17
NOP
.align 2
J girq10_b18
NOP
.align 2
J girq10_b19
NOP
.align 2
J girq10_b20
NOP
.align 2
J girq10_b21
NOP
.align 2
J girq10_b22
NOP
.align 2
J girq10_b23
NOP
.end girq10_isr
#endif
/******************************************************************/

238
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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq11.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ11_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq11_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<3);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq11_b0(void)
{
return;
}
void __attribute__((weak, interrupt, nomips16))
girq11_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 1, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 2, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 3, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 4, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 5, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 6, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 7, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 8, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 9, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b10(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 10, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b11(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 11, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b12(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 12, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b13(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 13, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b14(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 14, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b15(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 15, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b16(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 16, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b17(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 17, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b18(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 18, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b19(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 19, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b20(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 20, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b21(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 21, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b22(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 22, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b23(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 23, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b24(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 24, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b25(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 25, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b26(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 26, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b27(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 27, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b28(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 28, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b29(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 29, JTVIC_CLR_SRC);
}
void __attribute__((weak, interrupt, nomips16))
girq11_b30(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 30, JTVIC_CLR_SRC);
}
#endif
/* end girq11.c */
/** @}
*/

211
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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ11 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq11_b0
.extern girq11_b1
.extern girq11_b2
.extern girq11_b3
.extern girq11_b4
.extern girq11_b5
.extern girq11_b6
.extern girq11_b7
.extern girq11_b8
.extern girq11_b9
.extern girq11_b10
.extern girq11_b11
.extern girq11_b12
.extern girq11_b13
.extern girq11_b14
.extern girq11_b15
.extern girq11_b16
.extern girq11_b17
.extern girq11_b18
.extern girq11_b19
.extern girq11_b20
.extern girq11_b21
.extern girq11_b22
.extern girq11_b23
.extern girq11_b24
.extern girq11_b25
.extern girq11_b26
.extern girq11_b27
.extern girq11_b28
.extern girq11_b30
#if GIRQ11_DISAGG != 0
/*
* Disaggregated girq11_isr
* Program address of this version of girq23v into JTVIC GIRQ11
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq11_isr, code
#else
.section .girqs.girq11_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq11_isr
.global girq11_isr
.align 2
girq11_isr:
#if 1
J girq11_b0
NOP
.align 2
J girq11_b1
NOP
.align 2
J girq11_b2
NOP
.align 2
J girq11_b3
NOP
.align 2
J girq11_b4
NOP
.align 2
J girq11_b5
NOP
.align 2
J girq11_b6
NOP
.align 2
J girq11_b7
NOP
.align 2
J girq11_b8
NOP
.align 2
J girq11_b9
NOP
.align 2
J girq11_b10
NOP
.align 2
J girq11_b11
NOP
.align 2
J girq11_b12
NOP
.align 2
J girq11_b13
NOP
.align 2
J girq11_b14
NOP
.align 2
J girq11_b15
NOP
.align 2
J girq11_b16
NOP
.align 2
J girq11_b17
NOP
.align 2
J girq11_b18
NOP
.align 2
J girq11_b19
NOP
.align 2
J girq11_b20
NOP
.align 2
J girq11_b21
NOP
.align 2
J girq11_b22
NOP
.align 2
J girq11_b23
NOP
.align 2
J girq11_b24
NOP
.align 2
J girq11_b25
NOP
.align 2
J girq11_b26
NOP
.align 2
J girq11_b27
NOP
.align 2
J girq11_b28
NOP
.align 2
J girq11_b29
NOP
.align 2
J girq11_b30
NOP
.end girq11_isr
#else
gen_jump_table 11,0,30
#endif
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq12.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ12_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq12_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<4);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq12_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq12_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq12_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 2);
}
#endif
/* end girq12.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ12 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq12_b0
.extern girq12_b1
.extern girq12_b2
#if GIRQ12_DISAGG != 0
/*
* Disaggregated girq12_isr
* Program address of this version of girq23v into JTVIC GIRQ12
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq12_isr, code
#else
.section .girqs.girq12_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq12_isr
.global girq12_isr
.align 2
girq12_isr:
J girq12_b0
NOP
.align 2
J girq12_b1
NOP
.align 2
J girq12_b2
NOP
.end girq12_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq13.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ13_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq13_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<5);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq13_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq13_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq13_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq13_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq13_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq13_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq13_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 6);
}
#endif
/* end girq13.c */
/** @}
*/

88
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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ13 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq13_b0
.extern girq13_b1
.extern girq13_b2
.extern girq13_b3
.extern girq13_b4
.extern girq13_b5
.extern girq13_b6
#if GIRQ13_DISAGG != 0
/*
* Disaggregated girq13_isr
* Program address of this version of girq23v into JTVIC GIRQ13
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq13_isr, code
#else
.section .girqs.girq13_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq13_isr
.global girq13_isr
.align 2
girq13_isr:
J girq13_b0
NOP
.align 2
J girq13_b1
NOP
.align 2
J girq13_b2
NOP
.align 2
J girq13_b3
NOP
.align 2
J girq13_b4
NOP
.align 2
J girq13_b5
NOP
.align 2
J girq13_b6
NOP
.end girq13_isr
#endif
/******************************************************************/

88
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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq14.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ14_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq14_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<6);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq14_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq14_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq14_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq14_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq14_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq14_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 5);
}
#endif
/* end girq14.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ14 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq14_b0
.extern girq14_b1
.extern girq14_b2
.extern girq14_b3
.extern girq14_b4
.extern girq14_b5
#if GIRQ14_DISAGG != 0
/*
* Disaggregated girq14_isr
* Program address of this version of girq14_isr into JTVIC GIRQ14
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq14_isr, code
#else
.section .girqs.girq14_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq14_isr
.global girq14_isr
.align 2
girq14_isr:
J girq14_b0
NOP
.align 2
J girq14_b1
NOP
.align 2
J girq14_b2
NOP
.align 2
J girq14_b3
NOP
.align 2
J girq14_b4
NOP
.align 2
J girq14_b5
NOP
.end girq14_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq15.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ15_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq15_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<7);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq15_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 6);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 7);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 8);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 9);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b10(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 10);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b11(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 11);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b12(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 12);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b13(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 13);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b14(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 14);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b15(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 15);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b16(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 16);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b17(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 17);
}
void __attribute__((weak, interrupt, nomips16))
girq15_b18(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 18);
}
#endif
/* end girq15.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ15 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq15_b0
.extern girq15_b1
.extern girq15_b2
.extern girq15_b3
.extern girq15_b4
.extern girq15_b5
.extern girq15_b6
.extern girq15_b7
.extern girq15_b8
.extern girq15_b9
.extern girq15_b10
.extern girq15_b11
.extern girq15_b12
.extern girq15_b13
.extern girq15_b14
.extern girq15_b15
.extern girq15_b16
.extern girq15_b17
.extern girq15_b18
#if GIRQ15_DISAGG != 0
/*
* Disaggregated girq15_isr
* Program address of this version of girq15_isr into JTVIC GIRQ15
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq15_isr, code
#else
.section .girqs.girq15_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq15_isr
.global girq15_isr
.align 2
girq15_isr:
J girq15_b0
NOP
.align 2
J girq15_b1
NOP
.align 2
J girq15_b2
NOP
.align 2
J girq15_b3
NOP
.align 2
J girq15_b4
NOP
.align 2
J girq15_b5
NOP
.align 2
J girq15_b6
NOP
.align 2
J girq15_b7
NOP
.align 2
J girq15_b8
NOP
.align 2
J girq15_b9
NOP
.align 2
J girq15_b10
NOP
.align 2
J girq15_b11
NOP
.align 2
J girq15_b12
NOP
.align 2
J girq15_b13
NOP
.align 2
J girq15_b14
NOP
.align 2
J girq15_b15
NOP
.align 2
J girq15_b16
NOP
.align 2
J girq15_b17
NOP
.align 2
J girq15_b18
NOP
.end girq15_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq16.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ16_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq16_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<8);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq16_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 6);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 7);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 8);
}
void __attribute__((weak, interrupt, nomips16))
girq16_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 9);
}
#endif
/* end girq16.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ16 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq16_b0
.extern girq16_b1
.extern girq16_b2
.extern girq16_b3
.extern girq16_b4
.extern girq16_b5
.extern girq16_b6
.extern girq16_b7
.extern girq16_b8
.extern girq16_b9
#if GIRQ16_DISAGG != 0
/*
* Disaggregated girq16_isr
* Program address of this version of girq16_isr into JTVIC GIRQ16
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq16_isr, code
#else
.section .girqs.girq16_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq16_isr
.global girq16_isr
.align 2
girq16_isr:
J girq16_b0
NOP
.align 2
J girq16_b1
NOP
.align 2
J girq16_b2
NOP
.align 2
J girq16_b3
NOP
.align 2
J girq16_b4
NOP
.align 2
J girq16_b5
NOP
.align 2
J girq16_b6
NOP
.align 2
J girq16_b7
NOP
.align 2
J girq16_b8
NOP
.align 2
J girq16_b9
NOP
.end girq16_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq17.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ17_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq17_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<9);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq17_b0(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 0);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 0);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b1(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 1);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 1);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b2(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 2);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 2);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b3(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 3);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 3);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b4(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 4);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 4);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b5(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 5);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 5);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b6(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 6);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 6);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b7(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 7);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 7);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b8(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 8);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 8);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b9(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 9);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 9);
}
void __attribute__((weak, interrupt, nomips16))
girq17_b10(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 10);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 10);
}
#endif
/* end girq17.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ17 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq17_b0
.extern girq17_b1
.extern girq17_b2
.extern girq17_b3
.extern girq17_b4
.extern girq17_b5
.extern girq17_b6
.extern girq17_b7
.extern girq17_b8
.extern girq17_b9
.extern girq17_b10
#if GIRQ17_DISAGG != 0
/*
* Disaggregated girq17_isr
* Program address of this version of girq17_isr into JTVIC GIRQ17
* Aggregator Control register with bit[0] = 1.
*/
.insn
#ifdef __XC32
.section .girqs.girq17_isr, code
#else
.section .girqs.girq17_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq17_isr
.global girq17_isr
.align 2
girq17_isr:
J girq17_b0
NOP
.align 2
J girq17_b1
NOP
.align 2
J girq17_b2
NOP
.align 2
J girq17_b3
NOP
.align 2
J girq17_b4
NOP
.align 2
J girq17_b5
NOP
.align 2
J girq17_b6
NOP
.align 2
J girq17_b7
NOP
.align 2
J girq17_b8
NOP
.align 2
J girq17_b9
NOP
.align 2
J girq17_b10
NOP
.end girq17_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq18.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ18_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq18_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<10);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq18_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ18_ID, 0);
}
#endif
/* end girq18.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ18 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq18_b0
#if GIRQ18_DISAGG != 0
/*
* Disaggregated girq18_isr
* Program address of this version of girq18_isr into JTVIC GIRQ18
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
/*
* NOTE: GIRQ18 has only one source, no need for indirect jumps.
*/
.insn
#ifdef __XC32
.section .girqs.girq18_isr, code
#else
.section .girqs.girq18_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq18_isr
.global girq18_isr
.align 2
girq18_isr:
J girq18_b0
g18b0b:
NOP
g18end:
.end girq18_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq19.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ19_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq19_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<11);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq19_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 6);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 7);
}
void __attribute__((weak, interrupt, nomips16))
girq19_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 8);
}
#endif
/* end girq19.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ19 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq19_b0
.extern girq19_b1
.extern girq19_b2
.extern girq19_b3
.extern girq19_b4
.extern girq19_b5
.extern girq19_b6
.extern girq19_b7
.extern girq19_b8
#if GIRQ19_DISAGG != 0
/*
* Disaggregated girq19_isr
* Program address of this version of girq19_isr into JTVIC GIRQ19
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq19_isr, code
#else
.section .girqs.girq19_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq19_isr
.global girq19_isr
.align 2
girq19_isr:
J girq19_b0
g19b0b:
NOP
.align 2
g19b1a:
J girq19_b1
g19b1b:
NOP
.align 2
g19b2a:
J girq19_b2
g19b2b:
NOP
.align 2
g19b3a:
J girq19_b3
g19b3b:
NOP
.align 2
g19b4a:
J girq19_b4
g19b4b:
NOP
.align 2
g19b5a:
J girq19_b5
g19b5b:
NOP
.align 2
g19b6a:
J girq19_b6
g19b6b:
NOP
.align 2
g19b7a:
J girq19_b7
g19b7b:
NOP
.align 2
g19b8a:
J girq19_b8
g19b8b:
NOP
g19end:
.end girq19_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq20.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ20_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq20_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<12);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq20_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq20_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq20_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq20_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq20_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq20_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 5);
}
#endif
/* end girq20.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ20 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq20_b0
.extern girq20_b1
.extern girq20_b2
.extern girq20_b3
.extern girq20_b4
.extern girq20_b5
#if GIRQ20_DISAGG != 0
/*
* Disaggregated girq20_isr
* Program address of this version of girq20_isr into JTVIC GIRQ20
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq20_isr, code
#else
.section .girqs.girq20_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq20_isr
.global girq20_isr
.align 2
girq20_isr:
J girq20_b0
g20b0b:
NOP
.align 2
g20b1a:
J girq20_b1
g20b1b:
NOP
.align 2
g20b2a:
J girq20_b2
g20b2b:
NOP
.align 2
g20b3a:
J girq20_b3
g20b3b:
NOP
.align 2
g20b4a:
J girq20_b4
g20b4b:
NOP
.align 2
g20b5a:
J girq20_b5
g20b5b:
NOP
g20end:
.end girq20_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq21.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ21_DISAGG == 0
/*
* GIRQ21 is a wake peripheral logic only interrupt.
* It's purpose is to allow the peripheral logic such as SMBus or LPC to
* wake an service HW event without waking the EC.
* This handler is superfluous.
*/
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq21_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<13);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq21_b0(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<13);
}
#endif
/* end girq21.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ21 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq21_b0
#if GIRQ21_DISAGG != 0
/*
* Disaggregated girq21_isr
* Program address of this version of girq21_isr into JTVIC GIRQ21
* Aggregator Control register with bit[0] = 1.
* NOTE: GIRQ21 has no sources, it is a wake only and actually
* does not send an interrupt message to the M14K.
*
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq21_isr, code
#else
.section .girqs.girq21_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq21_isr
.global girq21_isr
.align 2
girq21_isr:
J girq21_b0
g21b0b:
NOP
g21end:
.end girq21_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq22.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ22_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq22_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<14);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq22_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 6);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 7);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 8);
}
void __attribute__((weak, interrupt, nomips16))
girq22_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 9);
}
#endif
/* end girq22.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ22 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq22_b0
.extern girq22_b1
.extern girq22_b2
.extern girq22_b3
.extern girq22_b4
.extern girq22_b5
.extern girq22_b6
.extern girq22_b7
.extern girq22_b8
.extern girq22_b9
#if GIRQ22_DISAGG != 0
/*
* Disaggregated girq22_isr
* Program address of this version of girq22_isr into JTVIC GIRQ22
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq22_isr, code
#else
.section .girqs.girq22_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq22_isr
.global girq22_isr
.align 2
girq22_isr:
J girq22_b0
g22b0b:
NOP
.align 2
g22b1a:
J girq22_b1
g22b1b:
NOP
.align 2
g22b2a:
J girq22_b2
g22b2b:
NOP
.align 2
g22b3a:
J girq22_b3
g22b3b:
NOP
.align 2
g22b4a:
J girq22_b4
g22b4b:
NOP
.align 2
g22b5a:
J girq22_b5
g22b5b:
NOP
.align 2
g22b6a:
J girq22_b6
g22b6b:
NOP
.align 2
g22b7a:
J girq22_b7
g22b7b:
NOP
.align 2
g22b8a:
J girq22_b8
g22b8b:
NOP
.align 2
g22b9a:
J girq22_b9
g22b9b:
NOP
g22end:
.end girq22_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq23.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_bbled.h"
#include "MEC14xx/mec14xx_trace_func.h"
typedef void (* GIRQ23_FPVU8)(uint8_t);
#if GIRQ23_DISAGG == 0
/*
* FreeRTOS ISR for HW timer used as RTOS tick.
* Implemented in MEC14xx FreeRTOS porting layer, port_asm.S
* It save/restores CPU context and clears HW timer interrupt
* status in JTVIC. On each timer tick it checks if any task
* requires service. If yes then it triggers the PendSV low
* priority software interrupt.
* Issue:
* When aggregated girq23_isr save CPU context but this context
* is not the same as a FreeRTOS context save. If the RTOS timer
* is active then girq23_isr would call vPortTickInterruptHandler
* which uses FreeRTOS portSAVE_CONTEXT macro to save RTOS + CPU
* context. At this point you have two context saves on the stack.
* There is a problem:
* vPortTickInterruptHandler does not return but exits using
* portRESTORE_CONTEXT. This means the context save performed
* by aggregated girq23_isr is left on the stack. Eventually
* a stack overflow will occur.
*
* Solutions:
* 1. vPortTickInterruptHandler must be modified to handle scan
* GIRQ23 Result bits and all the respective handler. All
* other GIRQ23 source are called as hook functions.
*
* 2. Do not use vPortTickInterruptHandler.
* Modify girq23_isr here to use FreeRTOS portSAVE_CONTEXT
* and portRESTORE_CONTEXT macros.
* If RTOS timer is active interrupt then call vPortIncrementTick
* as vPortTickInterruptHandler does.
* For all other GIRQ23 sources call the respective handlers.
*
* NOTE: for both of the above solutions a we must either:
* A. Service one source only resulting in GIRQ23 firing multiple
* times if more than one source is active.
* B. Service all active sources with RTOS Timer checked first.
*
* We will implement 1A with a single hook for all other sources.
*
*/
extern void vPortIncrementTick(void);
void girq23_dflt_handler(uint8_t inum)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].EN_CLR = (1ul << inum);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << inum);
}
void __attribute__((weak)) rtos_tmr_handler(uint8_t inum)
{
(void) inum;
JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 4);
}
const GIRQ23_FPVU8 girq23_htable[GIRQ23_NUM_SOURCES] =
{
girq23_dflt_handler, /* btmr0_handler, */
girq23_dflt_handler, /* btmr1_handler, */
girq23_dflt_handler, /* btmr2_handler, */
girq23_dflt_handler, /* btmr3_handler, */
vPortIncrementTick,
girq23_dflt_handler, /* hib_tmr_handler, */
girq23_dflt_handler, /* week_tmr_handler, */
girq23_dflt_handler, /* week_tmr_handler, */
girq23_dflt_handler, /* week_tmr_handler, */
girq23_dflt_handler, /* week_tmr_handler, */
girq23_dflt_handler, /* week_tmr_handler, */
girq23_dflt_handler, /* vci_handler, */
girq23_dflt_handler, /* vci_handler, */
girq23_dflt_handler, /* vci_handler, */
};
/* Called by FreeRTOS vPortTickInterruptHandler(girq23_isr)
* after saving FreeRTOS context
*/
void girq23_handler(void)
{
uint32_t d;
uint8_t bitpos;
d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].RESULT & (GIRQ23_SRC_MASK);
while ( 0 != d )
{
bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);
(girq23_htable[bitpos])(bitpos);
d &= ~(1ul << bitpos);
}
}
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq23_isr(void)
{
uint32_t d;
uint8_t bitpos;
d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].RESULT & (GIRQ23_SRC_MASK);
while ( 0 != d )
{
bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);
(girq23_htable[bitpos])(bitpos);
d &= ~(1ul << bitpos);
}
}
#else
/* 16-bit Basic Timer 0 */
void __attribute__((weak, interrupt, nomips16))
girq23_b0(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 0);
}
/* 16-bit Basic Timer 1 */
void __attribute__((weak, interrupt, nomips16))
girq23_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 1, TRUE);
}
/* 16-bit Basic Timer 2 */
void __attribute__((weak, interrupt, nomips16))
girq23_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 2, TRUE);
}
/* 16-bit Basic Timer 3 */
void __attribute__((weak, interrupt, nomips16))
girq23_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 3, TRUE);
}
/* RTOS Timer */
void __attribute__((weak, interrupt, nomips16))
girq23_b4(void)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 4);
}
/* Hibernation Timer */
void __attribute__((weak, interrupt, nomips16))
girq23_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 5, TRUE);
}
/* Week Alarm */
void __attribute__((weak, interrupt, nomips16))
girq23_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 6, TRUE);
}
/* Sub-Week Alarm */
void __attribute__((weak, interrupt, nomips16))
girq23_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 7, TRUE);
}
/* Week Alarm One Second */
void __attribute__((weak, interrupt, nomips16))
girq23_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 8, TRUE);
}
/* Week Alarm Sub Second */
void __attribute__((weak, interrupt, nomips16))
girq23_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 9, TRUE);
}
/* Week Alarm System Power Present Pin */
void __attribute__((weak, interrupt, nomips16))
girq23_b10(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 10, TRUE);
}
/* VCI OVRD Input */
void __attribute__((weak, interrupt, nomips16))
girq23_b11(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 11, TRUE);
}
/* VCI IN0 */
void __attribute__((weak, interrupt, nomips16))
girq23_b12(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 12, TRUE);
}
/* VCI IN1 */
void __attribute__((weak, interrupt, nomips16))
girq23_b13(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 13, TRUE);
}
#endif
/* end girq23.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/***************************************************************
* MEC14xx GIRQ23 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq23_b0
.extern girq23_b1
.extern girq23_b2
.extern girq23_b3
.extern girq23_b4
.extern girq23_b5
.extern girq23_b6
.extern girq23_b7
.extern girq23_b8
.extern girq23_b9
.extern girq23_b10
.extern girq23_b11
.extern girq23_b12
.extern girq23_b13
#if GIRQ23_DISAGG != 0
/*
* FreeRTOS Handler for MEC14xx RTOS Timer
* implemented in the porting layer.
*/
.extern vPortTickInterruptHandler
/*
* Disaggregated girq23_isr
* Program address of this version of girq23_isr into JTVIC GIRQ23
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq23_isr, code
#else
.section .girqs.girq23_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq23_isr
.global girq23_isr
.align 2
girq23_isr:
J girq23_b0
g23b0b:
NOP
.align 2
g23b1a:
J girq23_b1
g23b1b:
NOP
.align 2
g23b2a:
J girq23_b2
g23b2b:
NOP
.align 2
g23b3a:
J girq23_b3
g23b3b:
NOP
.align 2
g23b4a:
J girq23_b4
g23b4b:
NOP
.align 2
g23b5a:
J girq23_b5
g23b5b:
NOP
.align 2
g23b6a:
J girq23_b6
g23b6b:
NOP
.align 2
g23b7a:
J girq23_b7
g23b7b:
NOP
.align 2
g23b8a:
J girq23_b8
g23b8b:
NOP
.align 2
g23b9a:
J girq23_b9
g23b9b:
NOP
.align 2
g23b10a:
J girq23_b10
g23b10b:
NOP
.align 2
g23b11a:
J girq23_b11
g23b11b:
NOP
.align 2
g23b12a:
J girq23_b12
g23b12b:
NOP
.align 2
g23b13a:
J girq23_b13
g23b13b:
NOP
g23end:
.end girq23_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq24.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_bbled.h"
#include "MEC14xx/mec14xx_trace_func.h"
typedef void (* GIRQ24_FPVU8)(uint8_t);
/* MIPS M14K internal counter is connected to GIRQ24 bit[0]
* It is a simple counter which fires an interrupt when its
* count value is equal to a match value.
*
*/
#if GIRQ24_DISAGG == 0
void girq24_dflt_handler(uint8_t inum)
{
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].EN_CLR = (1ul << inum);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << inum);
}
void __attribute__((weak)) m14k_counter_handler(uint8_t inum)
{
uint32_t r;
(void) inum;
r = _CP0_GET_COUNT();
r += (M14K_TIMER_COMPARE);
/* Write of CP0.Compare clears status in M14K */
_CP0_SET_COUNT(r);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 0);
}
/*
* TODO - FreeRTOS M14K Software Interrupt 0 handler
* is vPortYieldISR in port_asm.S
* vPortYieldISR was designed to be entered directly by the
* CPU not via a higher level ISR handler.
* One work-around is to modify vPortYieldISR to do the work
* of girq24_handler below. It must determine which GIRQ24 source
* was active: M14K counter, SoftIRQ0, or SoftIRQ1.
*/
void __attribute__((weak)) m14k_soft_irq0(uint8_t inum)
{
(void) inum;
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 1);
}
void __attribute__((weak)) m14k_soft_irq1(uint8_t inum)
{
(void) inum;
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 2);
}
void girq24_b_0_2( void )
{
uint32_t d;
d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].RESULT & (GIRQ24_SRC_MASK);
if ( d & (1ul << 0) )
{
m14k_counter_handler(0);
}
if ( d & (1ul << 2) )
{
m14k_soft_irq1(2);
}
}
const GIRQ24_FPVU8 girq24_htable[GIRQ24_NUM_SOURCES] =
{
m14k_counter_handler, /* m14k_counter_handler, */
m14k_soft_irq0, /* m14k_soft_irq0, */
m14k_soft_irq1, /* m14k_soft_irq1 */
};
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq24_isr(void)
{
uint32_t d;
uint8_t bitpos;
d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].RESULT & (GIRQ24_SRC_MASK);
while ( 0 != d )
{
bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);
(girq24_htable[bitpos])(bitpos);
d &= ~(1ul << bitpos);
}
}
#else
void __attribute__((weak, interrupt, nomips16))
girq24_b0(void)
{
uint32_t r;
r = _CP0_GET_COUNT();
r += (M14K_TIMER_COMPARE);
_CP0_SET_COUNT(r);
JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 0);
}
void __attribute__((weak, interrupt, nomips16))
girq24_b1(void)
{
_CP0_BIC_CAUSE(0x100ul);
jtvic_clr_source(MEC14xx_GIRQ24_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq24_b2(void)
{
_CP0_BIC_CAUSE(0x200ul);
jtvic_clr_source(MEC14xx_GIRQ24_ID, 2);
}
#endif
/* end girq24.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ24 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq24_b0
.extern girq24_b1
.extern girq24_b2
#if GIRQ24_DISAGG != 0
/*
* FreeRTOS Handler for MIPS M14K Software Interrupt 0
* implemented in the porting layer.
*/
.extern vPortYieldISR
/*
* Disaggregated girq24_isr
* Program address of this version of girq24_isr into JTVIC GIRQ24
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq24_isr, code
#else
.section .girqs.girq24_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq24_isr
.global girq24_isr
.align 2
girq24_isr:
J girq24_b0
g24b0b:
NOP
.align 2
g24b1a:
J vPortYieldISR /* girq24_b1 */
g24b1b:
NOP
.align 2
g24b2a:
J girq24_b2
g24b2b:
NOP
g24end:
.end girq24_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2013 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq25.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ25_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq25_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<15);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq25_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 6);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 7);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 8);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 9);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b10(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 10);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b11(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 11);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b12(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 12);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b13(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 13);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b14(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 14);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b15(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 15);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b16(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 16);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b17(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 17);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b18(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 18);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b19(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 19);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b20(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 20);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b21(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 21);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b22(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 22);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b23(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 23);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b24(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 24);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b25(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 25);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b26(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 26);
}
void __attribute__((weak, interrupt, nomips16))
girq25_b27(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 27);
}
#endif
/* end girq25.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ25 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq25_b0
.extern girq25_b1
.extern girq25_b2
.extern girq25_b3
.extern girq25_b4
.extern girq25_b5
.extern girq25_b6
.extern girq25_b7
.extern girq25_b8
.extern girq25_b9
.extern girq25_b10
.extern girq25_b11
.extern girq25_b12
.extern girq25_b13
.extern girq25_b14
.extern girq25_b15
.extern girq25_b16
.extern girq25_b17
.extern girq25_b18
.extern girq25_b19
.extern girq25_b20
.extern girq25_b21
.extern girq25_b22
.extern girq25_b23
.extern girq25_b24
.extern girq25_b25
.extern girq25_b26
.extern girq25_b27
#if GIRQ25_DISAGG != 0
/*
* Disaggregated girq25_isr
* Program address of this version of girq25_isr into JTVIC GIRQ25
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq25_isr, code
#else
.section .girqs.girq25_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq25_isr
.global girq25_isr
.align 2
girq25_isr:
J girq25_b0
g25b0b:
NOP
.align 2
g25b1a:
J girq25_b1
g25b1b:
NOP
.align 2
g25b2a:
J girq25_b2
g25b2b:
NOP
.align 2
g25b3a:
J girq25_b3
g25b3b:
NOP
.align 2
g25b4a:
J girq25_b4
g25b4b:
NOP
.align 2
g25b5a:
J girq25_b5
g25b5b:
NOP
.align 2
g25b6a:
J girq25_b6
g25b6b:
NOP
.align 2
g25b7a:
J girq25_b7
g25b7b:
NOP
.align 2
g25b8a:
J girq25_b8
g25b8b:
NOP
.align 2
g25b9a:
J girq25_b9
g25b9b:
NOP
.align 2
g25b10a:
J girq25_b10
g25b10b:
NOP
.align 2
g25b11a:
J girq25_b11
g25b11b:
NOP
.align 2
g25b12a:
J girq25_b12
g25b12b:
NOP
.align 2
g25b13a:
J girq25_b13
g25b13b:
NOP
.align 2
g25b14a:
J girq25_b14
g25b14b:
NOP
.align 2
g25b15a:
J girq25_b15
g25b15b:
NOP
.align 2
g25b16a:
J girq25_b16
g25b16b:
NOP
.align 2
g25b17a:
J girq25_b17
g25b17b:
NOP
.align 2
g25b18a:
J girq25_b18
g25b18b:
NOP
.align 2
g25b19a:
J girq25_b19
g25b19b:
NOP
.align 2
g25b20a:
J girq25_b20
g25b20b:
NOP
.align 2
g25b21a:
J girq25_b21
g25b21b:
NOP
.align 2
g25b22a:
J girq25_b22
g25b22b:
NOP
.align 2
g25b23a:
J girq25_b23
g25b23b:
NOP
.align 2
g25b24a:
J girq25_b24
g25b24b:
NOP
.align 2
g25b25a:
J girq25_b25
g25b25b:
NOP
.align 2
g25b26a:
J girq25_b26
g25b26b:
NOP
.align 2
g25b27a:
J girq25_b27
g25b27b:
NOP
g25end:
.end girq25_isr
#endif
/******************************************************************/

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/*****************************************************************************
* (c) 2013 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girq26.c
*Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
*/
/** @defgroup MEC14xx ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#if GIRQ26_DISAGG == 0
void __attribute__((weak, interrupt, nomips16, section(".girqs")))
girq26_isr(void)
{
JTVIC_GROUP_EN_CLR->w = (1ul<<16);
}
#else
void __attribute__((weak, interrupt, nomips16))
girq26_b0(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 0);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b1(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 1);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b2(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 2);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b3(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 3);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b4(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 4);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b5(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 5);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b6(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 6);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b7(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 7);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b8(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 8);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b9(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 9);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b10(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 10);
}
void __attribute__((weak, interrupt, nomips16))
girq26_b11(void)
{
jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 11);
}
#endif
/* end girq26.c */
/** @}
*/

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/*
Copyright (C) 2014 Microchip Inc.
All rights reserved
1 tab == 4 spaces!
*/
#ifdef __XC32
#include <xc.h>
#include <sys/asm.h>
#else
#include "Regs.S"
#endif
#include "MEC14xx/mec14xx_girqm.h"
/******************************************************************/
/***************************************************************
* MEC14xx GIRQ26 Disaggregated Vector Jump table
*
***************************************************************/
.extern girq26_b0
.extern girq26_b1
.extern girq26_b2
.extern girq26_b3
.extern girq26_b4
.extern girq26_b5
.extern girq26_b6
.extern girq26_b7
.extern girq26_b8
.extern girq26_b9
.extern girq26_b10
.extern girq26_b11
#if GIRQ26_DISAGG != 0
/*
* Disaggregated girq26_isr
* Program address of this version of girq26_isr into JTVIC GIRQ26
* Aggregator Control register with bit[0] = 1.
*/
/*
* NOTE: All the additional labels surrounding every instruction are
* there to force GCC OBJDUMP to disassemble microMIPS correctly.
*/
.insn
#ifdef __XC32
.section .girqs.girq26_isr, code
#else
.section .girqs.girq26_isr,"x"
#endif
.set nomips16
.set micromips
.set noreorder
.set noat
.ent girq26_isr
.global girq26_isr
.align 2
girq26_isr:
J girq26_b0
g26b0b:
NOP
.align 2
g26b1a:
J girq26_b1
g26b1b:
NOP
.align 2
g26b2a:
J girq26_b2
g26b2b:
NOP
.align 2
g26b3a:
J girq26_b3
g26b3b:
NOP
.align 2
g26b4a:
J girq26_b4
g26b4b:
NOP
.align 2
g26b5a:
J girq26_b5
g26b5b:
NOP
.align 2
g26b6a:
J girq26_b6
g26b6b:
NOP
.align 2
g26b7a:
J girq26_b7
g26b7b:
NOP
.align 2
g26b8a:
J girq26_b8
g26b8b:
NOP
.align 2
g26b9a:
J girq26_b9
g26b9b:
NOP
.align 2
g26b10a:
J girq26_b10
g26b10b:
NOP
.align 2
g26b11a:
J girq26_b11
g26b11b:
NOP
g26end:
.end girq26_isr
#endif
/******************************************************************/

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file girqs.c
*MEC14xx JTVIC default configuration table
*/
/** @defgroup MEC140x ISR
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_girqm.h"
#include "MEC14xx/mec14xx_girqs.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
/*
* Interrupt Service Routine prototypes for each GIRQn
*/
/*
* Table for initializing MEC14xx JTVIC.
* Each GIRQn handler's address must be programmed into
* respective JTVIC register.
*/
const JTVIC_CFG dflt_ih_table[MEC14xx_NUM_JTVIC_INTS] = {
{
(uint32_t)girq08_isr,
{
(GIRQ08_PRI_A),
(GIRQ08_PRI_B),
(GIRQ08_PRI_C),
(GIRQ08_PRI_D)
}
},
{
(uint32_t)girq09_isr,
{
(GIRQ09_PRI_A),
(GIRQ09_PRI_B),
(GIRQ09_PRI_C),
(GIRQ09_PRI_D)
}
},
{
(uint32_t)girq10_isr,
{
(GIRQ10_PRI_A),
(GIRQ10_PRI_B),
(GIRQ10_PRI_C),
(GIRQ10_PRI_D)
}
},
{
(uint32_t)girq11_isr,
{
GIRQ11_PRI_A,
GIRQ11_PRI_B,
GIRQ11_PRI_C,
GIRQ11_PRI_D
}
},
{
(uint32_t)girq12_isr,
{
GIRQ12_PRI_A,
GIRQ12_PRI_B,
GIRQ12_PRI_C,
GIRQ12_PRI_D
}
},
{
(uint32_t)girq13_isr,
{
GIRQ13_PRI_A,
GIRQ13_PRI_B,
GIRQ13_PRI_C,
GIRQ13_PRI_D
}
},
{
(uint32_t)girq14_isr,
{
GIRQ14_PRI_A,
GIRQ14_PRI_B,
GIRQ14_PRI_C,
GIRQ14_PRI_D
}
},
{
(uint32_t)girq15_isr,
{
GIRQ15_PRI_A,
GIRQ15_PRI_B,
GIRQ15_PRI_C,
GIRQ15_PRI_D
}
},
{
(uint32_t)girq16_isr,
{
GIRQ16_PRI_A,
GIRQ16_PRI_B,
GIRQ16_PRI_C,
GIRQ16_PRI_D
}
},
{
(uint32_t)girq17_isr,
{
GIRQ17_PRI_A,
GIRQ17_PRI_B,
GIRQ17_PRI_C,
GIRQ17_PRI_D
}
},
{
(uint32_t)girq18_isr,
{
GIRQ18_PRI_A,
GIRQ18_PRI_B,
GIRQ18_PRI_C,
GIRQ18_PRI_D
}
},
{
(uint32_t)girq19_isr,
{
GIRQ19_PRI_A,
GIRQ19_PRI_B,
GIRQ19_PRI_C,
GIRQ19_PRI_D
}
},
{
(uint32_t)girq20_isr,
{
GIRQ20_PRI_A,
GIRQ20_PRI_B,
GIRQ20_PRI_C,
GIRQ20_PRI_D
}
},
{
(uint32_t)girq21_isr,
{
GIRQ21_PRI_A,
GIRQ21_PRI_B,
GIRQ21_PRI_C,
GIRQ21_PRI_D
}
},
{
(uint32_t)girq22_isr,
{
GIRQ22_PRI_A,
GIRQ22_PRI_B,
GIRQ22_PRI_C,
GIRQ22_PRI_D
}
},
{
(uint32_t)girq23_isr,
{
GIRQ23_PRI_A,
GIRQ23_PRI_B,
GIRQ23_PRI_C,
GIRQ23_PRI_D
}
},
{
(uint32_t)girq24_isr,
{
GIRQ24_PRI_A,
GIRQ24_PRI_B,
GIRQ24_PRI_C,
GIRQ24_PRI_D
}
},
{
(uint32_t)girq25_isr,
{
GIRQ25_PRI_A,
GIRQ25_PRI_B,
GIRQ25_PRI_C,
GIRQ25_PRI_D
}
},
{
(uint32_t)girq26_isr,
{
GIRQ26_PRI_A,
GIRQ26_PRI_B,
GIRQ26_PRI_C,
GIRQ26_PRI_D
}
}
};
/* end girqs.c */
/** @}
*/

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_bbled.c
*MEC14xx Breating-Blinking LED definitions
*/
/** @defgroup MEC14xx Peripherals BBLED
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_pcr.h"
#include "MEC14xx/mec14xx_bbled.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_bbled.h"
#ifdef __cplusplus
extern "C" {
#endif
static uint32_t led_addr(uint8_t led_id)
{
if (led_id < (LED_ID_MAX) )
{
return ((LED0_BASE) + (led_id << 8));
}
else
{
return (LED0_BASE);
}
}
#ifdef LED_ENABLE_VALID_CHECK
static uint8_t led_is_valid(uint8_t led_id)
{
if (led_id < (LED_ID_MAX)) {
return true;
}
return false;
}
#else
static uint8_t led_is_valid(uint8_t led_id) { ( void ) led_id; return (MEC14XX_TRUE); }
#endif
/**
@brief MEC1404 LED are alternate functions of GPIO pins.
@note -
LED0 is GPIO157 Function 1
LED1 is GPIO156 Function 1
LED2 is GPIO104 Function 1
*/
static const uint8_t led_pcr_slp2_bitpos[LED_ID_MAX] = {
(PCR_EC2_LED0_SLP_BITPOS),
(PCR_EC2_LED1_SLP_BITPOS),
(PCR_EC2_LED2_SLP_BITPOS)
};
static const uint16_t led_gpio_tbl[LED_ID_MAX] = {
(((uint16_t)(GPIO_FUNC_1)<<8) + (uint16_t)GPIO_0157_ID),
(((uint16_t)(GPIO_FUNC_1)<<8) + (uint16_t)GPIO_0156_ID),
(((uint16_t)(GPIO_FUNC_1)<<8) + (uint16_t)GPIO_0104_ID)
};
/**
* led_sleep_en - Enable/Disable gating of clocks on idle to the
* BBLED block
*
*
* @param uint8_t sleep_en (1=Enable sleep on idle), (0=No sleep
* on idle).
* @param uint8_t LED ID (0-3)
* @note if LED ID > 3 no action taken.
*/
void led_sleep_en(uint8_t led_id, uint8_t sleep_en)
{
uint32_t slp_mask;
uint32_t laddr;
slp_mask = 0ul;
if ( led_is_valid(led_id) ) {
slp_mask = (1ul << led_pcr_slp2_bitpos[led_id]);
if ( sleep_en ) {
PCR->EC_SLEEP_EN2 |= slp_mask;
laddr = led_addr(led_id);
((BBLED_TypeDef *)laddr)->CONFIG &= ~(0x03ul);
} else {
PCR->EC_SLEEP_EN2 &= ~(slp_mask);
}
}
}
/**
* led_reset - Reset the specified LED hardware block.
*
* @author sworley
*
* @param led_id 0-based LED ID
* @note Sets the LED's soft reset bit and waits for hardware to
* clear it. Will wait up to 0x10000 times.
*/
void led_reset(uint8_t led_id)
{
uint32_t p;
uint32_t cnt;
p = led_addr(led_id);
((BBLED_TypeDef *)p)->CONFIG = (LED_CFG_RESET);
cnt = 0x100000UL;
while ( ((BBLED_TypeDef *)p)->CONFIG & (LED_CFG_RESET) ) {
if ( cnt != 0UL ) {
cnt--;
} else {
break;
}
}
}
uint8_t led_get_gpio_num(uint8_t led_id)
{
return led_gpio_tbl[(led_id & ((LED_ID_MAX)-1u))];
}
/**
* led_init - Initialize the specified LED
*
* @author sworley
*
* @param led_id 0-based LED ID
* @note Configures the LED's GPIO pin for LED function and then
* peforms a soft reset of the LED hardware.
*/
void led_init(uint8_t led_id)
{
uint16_t ledi;
if ( led_id < LED_ID_MAX )
{
/* bits[7:0] = GPIO_ID, bits[15:8] = GPIO Function */
ledi = led_gpio_tbl[led_id];
GPIOPropertySet((ledi & 0xFF), GPIO_PROP_MUX_SEL, (ledi >> 8) & 0xFF);
led_reset(ledi & 0xFF);
}
}
/**
* led_mode_blink - Enable LED hardware blink
*
* @author sworley
*
* @param led_id 0-based LED ID
* @param duty_cycle duty cycle (0x80 = 50%)
* @param prescale sets the blink frequency
* @note Blink frequency is (32768 * 255)/(prescale + 1) Hz
*/
void led_mode_blink(uint8_t led_id,
uint8_t duty_cycle,
uint16_t prescale)
{
uint32_t pLed;
pLed = 0UL;
if (led_is_valid(led_id)) {
pLed = led_addr(led_id);
((BBLED_TypeDef *)pLed)->CONFIG = LED_CFG_CNTL_BLINK;
((BBLED_TypeDef *)pLed)->LIMIT = (uint32_t)duty_cycle;
((BBLED_TypeDef *)pLed)->DELAY = (uint32_t)prescale;
((BBLED_TypeDef *)pLed)->CONFIG |= (LED_CFG_EN_UPDATE);
}
}
/**
* led_out_toggle - Toggle the LED output pin.
*
* @author sworley
*
* @param led_id 0-based LED ID.
*/
void led_out_toggle(uint8_t led_id)
{
uint32_t p;
if (led_is_valid(led_id)) {
p = led_addr(led_id);
if (((BBLED_TypeDef *)p)->CONFIG & LED_CFG_CNTL_MASK) {
((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_LO;
} else {
((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_HI;
}
}
}
/**
* led_out_high - Set the LED block to drive the pin High
*
* @author sworley
*
* @param led_id 0-based LED ID
* @note The LED controller will drive the pin High. Depending
* upon the external circuit the LED may be in ON or OFF
* state.
*/
void led_out_high(uint8_t led_id)
{
uint32_t p;
if (led_is_valid(led_id)) {
p = led_addr(led_id);
((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_HI;
}
}
/**
* led_out_low - Set the LED block to drive the pin Low
*
* @author sworley
*
* @param led_id 0-based LED ID
* @note The LED controller will drive the pin Low. Depending
* upon the external circuit the LED may be in ON or OFF
* state.
*/
void led_out_low(uint8_t led_id)
{
uint32_t p;
if (led_is_valid(led_id)) {
p = led_addr(led_id);
((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_LO;
}
}
#ifdef __cplusplus
}
#endif
/* end mec14xx_bbled.h */
/** @}
*/

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/*****************************************************************************
* © 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_gpio.c
*MEC14xx GPIO hardware access
*/
/** @defgroup MEC14xx Peripherals GPIO
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_gpio.h"
static uint32_t gpio_has_drv_str ( enum gpio_id_t gpio_id );
#ifdef ENABLE_GPIO_PIN_VALIDATION
static const uint32_t gpio_port_bitmaps[NUM_GPIO_PORTS] =
{
(GPIO_PORT_A_BITMAP),
(GPIO_PORT_B_BITMAP),
(GPIO_PORT_C_BITMAP),
(GPIO_PORT_D_BITMAP)
};
#endif
//
// Drive Strength Register bitmap
//
static const uint32_t gpio_drv_str_bitmap[NUM_GPIO_PORTS] =
{
(GPIO_PORT_A_DRVSTR_BITMAP),
(GPIO_PORT_B_DRVSTR_BITMAP),
(GPIO_PORT_C_DRVSTR_BITMAP),
(GPIO_PORT_D_DRVSTR_BITMAP)
};
struct gpio_cfg
{
uint16_t bit_mask;
uint8_t bit_pos;
};
static const struct gpio_cfg gpio_cfg_tbl[GPIO_PROP_MAX] =
{
{ 0x0003u, 0x00u },
{ 0x000Cu, 0x02u },
{ 0x00F0u, 0x04u },
{ 0x0100u, 0x08u },
{ 0x0200u, 0x09u },
{ 0x0400u, 0x0Au },
{ 0x0800u, 0x0Bu },
{ 0x3000u, 0x0Cu },
{ 0x3FFFu, 0x00u }
};
static uint32_t gpio_pin_ctrl_addr(enum gpio_id_t gpio_id)
{
return ((uint32_t)(GPIO_BASE) + (uint32_t)(gpio_id << 2));
}
#ifdef ENABLE_GPIO_PIN_VALIDATION
/**
* gpio_is_valid - local helper checks if GPIO pin is
* implemented in this hardware.
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
*
* @return uint8_t Non-zero(GPIO Pin implemented), 0(not
* implemented).
*/
static uint8_t gpio_is_valid ( enum gpio_id_t gpio_id )
{
uint16_t gp_bank;
gp_bank = 0;
if ( (uint16_t)gpio_id < (uint16_t)(MAX_GPIO_ID) )
{
gp_bank = (uint16_t)gpio_id >> 5;
if ( gpio_port_bitmaps[gp_bank] & (1 << (gpio_id & 0x001Fu)) )
{
return true;
}
}
return false;
}
#else
static uint32_t gpio_is_valid(enum gpio_id_t gpio_id) { return true; }
#endif
static uint8_t gpio_bank_num(enum gpio_id_t gpio_id)
{
return (uint8_t)(gpio_id) >> 5;
}
static uint8_t gpio_pin_num(enum gpio_id_t gpio_id)
{
return (uint8_t)(gpio_id) & 0x1Fu;
}
/**
* gpio_has_drv_str - Local helper to check if GPIO pin has
* associated drive strength register.
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
*
* @return uint32_t 0(No Drive Strength), Non-zero(Physical
* address of Drive Strength Register).
*/
static uint32_t gpio_has_drv_str ( enum gpio_id_t gpio_id )
{
uint32_t bank, bitpos, addr;
addr = 0ul;
if ( gpio_id < MAX_GPIO_ID )
{
bank = gpio_bank_num(gpio_id);
bitpos = gpio_pin_num(gpio_id);
if ( gpio_drv_str_bitmap[bank] & (1ul << bitpos) )
{
addr = (GPIO_PCTRL2_BASE) + ((uint32_t)(gpio_id) << 2);
if ( gpio_id > GPIO_0077_ID )
{
addr -= 0x20ul;
}
}
}
return addr;
}
uint16_t GPIOGetConfig(enum gpio_id_t gpio_id)
{
if (gpio_is_valid(gpio_id)) {
return *((volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id));
} else {
return 0u;
}
}
void GPIOSetConfig(enum gpio_id_t gpio_id, uint16_t config)
{
volatile uint16_t * p;
if (gpio_is_valid(gpio_id)) {
p = (volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id);
*p = config;
}
}
void GPIOConfigAndOr(enum gpio_id_t gpio_id, uint16_t and_mask, uint16_t or_mask)
{
volatile uint16_t * p;
if (gpio_is_valid(gpio_id)) {
p = (volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id);
*p = (*p & and_mask) | or_mask;
}
}
uint32_t GPIOGetControl(enum gpio_id_t gpio_id)
{
if (gpio_is_valid(gpio_id)) {
return *((volatile uint32_t *)gpio_pin_ctrl_addr(gpio_id));
} else {
return 0xFFFFFFFFul;
}
}
void GPIOSetControl(enum gpio_id_t gpio_id, uint32_t ctrl_val)
{
volatile uint32_t * p;
if (gpio_is_valid(gpio_id)) {
p = (volatile uint32_t *)gpio_pin_ctrl_addr(gpio_id);
*p = ctrl_val;
}
}
void GPIOControlAndOr(enum gpio_id_t gpio_id, uint32_t and_mask, uint32_t or_mask)
{
volatile uint32_t * p;
if (gpio_is_valid(gpio_id)) {
p = (volatile uint32_t *)gpio_pin_ctrl_addr(gpio_id);
*p = (*p & and_mask) | or_mask;
}
}
/**
* GPIOPropertySet - Program specified GPIO Pin configuration
* item.
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
* @param gpio_prop enumerated GPIO Property(configuration item)
* @param prop_val new property value
*/
void GPIOPropertySet ( enum gpio_id_t gpio_id,
enum gpio_prop_t gpio_prop,
uint16_t prop_val
)
{
volatile uint16_t * p;
uint16_t gp_cfg;
gp_cfg = 0u;
if ( gpio_is_valid(gpio_id) && ((uint16_t)gpio_prop < (uint16_t)GPIO_PROP_MAX) )
{
p = (volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id);
gp_cfg = *p;
gp_cfg &= ~(gpio_cfg_tbl[gpio_prop].bit_mask);
gp_cfg |= (prop_val << gpio_cfg_tbl[gpio_prop].bit_pos) &
gpio_cfg_tbl[gpio_prop].bit_mask;
*p = gp_cfg;
}
}
/**
* GPIOGetSlewRate - Return GPIO Pin Slew Rate
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
*
* @return uint8_t GPIO Pin Slew Rate: 0(Slow) or 1(Fast)
*/
uint8_t GPIOGetSlewRate( enum gpio_id_t gpio_id )
{
uint32_t addr;
uint8_t slew;
addr = gpio_has_drv_str(gpio_id);
if ( 0ul != addr )
{
slew = ((*(volatile uint8_t *)addr) >> GPIO_DRV_SLEW_BITPOS) & 0x01u;
}
else
{
slew = 0u;
}
return slew;
}
/**
* GPIOSetSlewRate - Program GPIO Pin's Slew Rate
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
* @param slew_rate new slew rate: 0(Slow), Non-zero(Fast)
*/
void GPIOSetSlewRate ( enum gpio_id_t gpio_id,
enum gpio_slew_rate_t slew_rate )
{
uint32_t addr;
addr = gpio_has_drv_str(gpio_id );
if ( addr )
{
*(volatile uint8_t *)addr = (*(volatile uint8_t *)addr &
~(GPIO_DRV_SLEW_MASK)) |
((slew_rate << (GPIO_DRV_SLEW_BITPOS)) & (GPIO_DRV_SLEW_MASK));
}
}
/**
* GPIOGetDriveStr - Get GPIO Pin's Drive Strength
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
*
* @return uint8_t Pin Drive Strength: 0=2mA, 1=4mA, 2=8mA,
* 3=12mA.
*/
uint8_t GPIOGetDriveStr ( enum gpio_id_t gpio_id )
{
uint32_t addr;
addr = gpio_has_drv_str(gpio_id );
if ( addr )
{
return ((*(volatile uint8_t *)addr) >> GPIO_DRV_STR_BITPOS) & (GPIO_DRV_STR_MASK);
}
else
{
return 0u;
}
}
/**
* GPIOSetDriveStr - Program GPIO Pin's Drive Strength
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
* @param drv_str enumerated drive strength: 0=2mA, 1=4mA,
* 2=8mA, 3=12mA
*/
void GPIOSetDriveStr ( enum gpio_id_t gpio_id,
enum gpio_drv_str_t drv_str )
{
uint32_t addr;
uint8_t r8;
addr = gpio_has_drv_str(gpio_id);
if ( addr )
{
r8 = *(volatile uint8_t *)addr & ~(GPIO_DRV_STR_MASK);
r8 += ((drv_str << GPIO_DRV_STR_BITPOS) & GPIO_DRV_STR_MASK);
*(volatile uint8_t *)addr = r8;
}
}
/**
* GPIOGetDriveStrAndSlew - Return combined value representing
* Drive Strength and Slew Rate.
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
*
* @return uint8_t bit[0] = Slew Rate, bits[3:1]=0(Reserved),
* bits[5:4]=Drive Strength, bits[7:6]=0(Reserved)
*/
uint8_t GPIOGetDriveStrAndSlew ( enum gpio_id_t gpio_id )
{
uint32_t addr;
addr = gpio_has_drv_str(gpio_id );
if ( addr )
{
return (*(volatile uint8_t *)addr);
}
else
{
return 0u;
}
}
/**
* GPIOSetDriveStrAndSlew - Program GPIO Pin's drive strength
* and slew rate.
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
* @param drv_and_slew bit[0] = Slew Rate, bits[3:1]=0(Reserved),
* bits[5:4]=Drive Strength, bits[7:6]=0(Reserved)
*/
void GPIOSetDriveStrAndSlew ( enum gpio_id_t gpio_id,
uint8_t drv_and_slew )
{
uint32_t addr;
uint8_t r8;
addr = gpio_has_drv_str(gpio_id);
if ( addr )
{
r8 = *(volatile uint8_t *)addr & ~(GPIO_DRV_SLEW_MASK + GPIO_DRV_STR_MASK);
r8 |= (drv_and_slew & (GPIO_DRV_SLEW_MASK + GPIO_DRV_STR_MASK));
*(volatile uint8_t *)addr = r8;
}
}
/**
* GPIOSetOutput - Program GPIO Pin's output state using Pin
* configuration register (not parallel output register).
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID
* @param gpio_state pin state: actual pin state at pad will
* depend upon GPIO Output invert
* configuration.
* @note peforms a byte wide write to byte offset 2 of the GPIO
* Pin's 32-bit configuration register. No
* read-modify-write.
*/
void GPIOSetOutput ( enum gpio_id_t gpio_id,
uint8_t gpio_state
)
{
volatile uint8_t * p;
if ( gpio_is_valid(gpio_id) )
{
p = (volatile uint8_t *)(gpio_pin_ctrl_addr(gpio_id) + 2ul);
if (gpio_state) {
*p = 0x01u;
} else {
*p = 0u;
}
}
}
void GPIOToggleOutput ( enum gpio_id_t gpio_id )
{
volatile uint8_t * p;
if ( gpio_is_valid(gpio_id) )
{
p = (volatile uint8_t *)(gpio_pin_ctrl_addr(gpio_id) + 2ul);
*p ^= 0x01u;
}
}
/**
* GPIOReadPin - Read GPIO Pin's Pad Input from configuration
* register.
*
* @author sworley
*
* @param gpio_id 0-based GPIO ID.
*
* @return uint8_t 0 or 1 depending upon the state of the GPIO
* pad.
* @note performs a byte read of offset 3 of the GPIO Pin's
* 32-bit configuration register.
*/
uint8_t GPIOReadPin( enum gpio_id_t gpio_id )
{
if ( gpio_is_valid(gpio_id) )
{
return *((volatile uint8_t *)(gpio_pin_ctrl_addr(gpio_id) + 3ul));
}
else
{
return 0u;
}
}
/** GPIOPinLock - Lock specified GPIO's control register.
* @param enum gpio_id_t zero based GPIO ID
* @note Lock bit is only cleared on POR. Lock registers
* are in reverse order, first register is at top address.
* GPIO_LOCK_BASE defined to top(first) register address.
* */
void GPIOPinLock(enum gpio_id_t gpio_id)
{
uint32_t addr;
uint8_t bank, bitpos;
if (gpio_is_valid(gpio_id)) {
bank = gpio_bank_num(gpio_id); // 0 - 4
bitpos = gpio_pin_num(gpio_id); // 0 - 31
addr = (uint32_t)(GPIO_LOCK_BASE) - (bank << 2);
*(volatile uint32_t *)addr |= (1ul << bitpos);
}
}
/* end mec14xx_gpio.c */
/** @}
*/

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/*****************************************************************************
* © 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_jtvic.c
*MEC14xx JTVIC
*/
/** @defgroup MEC14xx Peripherals JTVIC
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_jtvic.h"
void jtvic_init(const JTVIC_CFG *ih_table, uint32_t disagg_bitmap, uint32_t cflags)
{
uint32_t d;
uint8_t i, j, pidx;
JTVIC_CTRL->w = (1ul << 0); // Soft-Reset
d = 0ul;
if ( cflags & (1ul << 0) )
{
d = (1ul << 8);
}
JTVIC_CTRL->w = d; // HW does not automatically clear Soft-Reset
for (i = 0u; i < (MEC14xx_NUM_JTVIC_INTS); i++) {
pidx = i << 2;
for (j = 0u; j < 4u; j++) {
JTVIC_PRI->REG32[pidx+j] = (uint32_t)(ih_table[i].pri[j]);
}
d = ih_table[i].isr_addr & ~(1ul << 0);
if (disagg_bitmap & (1ul << i)) {
d |= (1ul << 0); // dis-aggregate this GIRQ
}
JTVIC_ACTRL->REG32[i] = d;
}
JTVIC_GROUP_EN_SET->w = 0xFFFFFFFFul; // Enable GIRQ08 - GIRQ18 (all)
}
/* Clear JTVIC GIRQn source bit
*
*/
void jtvic_clr_source(uint8_t girq_num, uint8_t bit_num)
{
if (girq_num < (MEC14xx_NUM_JTVIC_INTS))
{
bit_num &= 0x1Fu;
JTVIC_GIRQ->REGS[girq_num].SOURCE = (1ul << bit_num);
}
}
/* Disable GIRQn source with optional clearing of source.
* girq_num = [0, 18], 0=GIRQ08, 1=GIRQ09, ..., 18=GIRQ26
* bit_num = [0, 31]
*/
void jtvic_dis_clr_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src)
{
if (girq_num < (MEC14xx_NUM_JTVIC_INTS))
{
bit_num &= 0x1Fu;
JTVIC_GIRQ->REGS[girq_num].EN_CLR = (1ul << bit_num);
if ( 0 != clr_src )
{
JTVIC_GIRQ->REGS[girq_num].SOURCE = (1ul << bit_num);
}
}
}
/* Enable with optional source clear before enable.
* girq_num = [0, 18], 0=GIRQ08, 1=GIRQ09, ..., 18=GIRQ26
* bit_num = [0, 31]
*/
void jtvic_en_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src)
{
if (girq_num < (MEC14xx_NUM_JTVIC_INTS))
{
bit_num &= 0x1Fu;
if ( 0 != clr_src )
{
JTVIC_GIRQ->REGS[girq_num].SOURCE = (1ul << bit_num);
}
JTVIC_GIRQ->REGS[girq_num].EN_SET = (1ul << bit_num);
}
}
/* end mec14xx_jtvic.c */
/** @}
*/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_system.c
*MEC14xx system functions
*/
/** @defgroup MEC14xx System
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_system.h"
#include "MEC14xx/mec14xx_jtvic.h"
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
PCR->PROC_CLOCK_CNTRL = (PCR_CLOCK_DIVIDER);
}
/*---------------------------------------------------------------------------*/
uint32_t sys_code_sram_base(void)
{
#if MEC14XX_DEVID == MEC1418_DEVID
return (uint32_t)(MEC1418_ICODE_PSRAM_BASE);
#else
return (uint32_t)(MEC1404_ICODE_PSRAM_BASE);
#endif
}
/*---------------------------------------------------------------------------*/
uint8_t sys_valid_sram_addr(void * const p)
{
uint32_t base;
base = sys_code_sram_base();
if ((uint32_t)p >= base) {
if ((uint32_t)p < (MEC14XX_DCODE_VSRAM_LIMIT)) {
return 1u;
}
}
return 0u;
}
/*---------------------------------------------------------------------------*/
uint8_t sys_valid_sram_range(void * const p, const uint32_t byte_len)
{
uint32_t base;
base = sys_code_sram_base();
if ((uint32_t)p >= base) {
if (((uint32_t)p + byte_len) < (MEC14XX_DCODE_VSRAM_LIMIT)) {
return 1u;
}
}
return 0u;
}
/*---------------------------------------------------------------------------*/
void sys_cpu_en_timer(uint32_t counts, uint8_t ien)
{
/* Disable Counter by setting DC bit to 1 in CP0.Cause */
_CP0_BIS_CAUSE(_CP0_CAUSE_DC_MASK);
_CP0_SET_COUNT(counts);
if (ien) {
jtvic_en_source(MEC14xx_GIRQ24_ID, 0, 0);
} else {
jtvic_dis_clr_source(MEC14xx_GIRQ24_ID, 0, 1);
}
/* Enable Counter */
_CP0_BIC_CAUSE(_CP0_CAUSE_DC_MASK);
}
/*---------------------------------------------------------------------------*/
uint32_t cpu_microsecond_count(void)
{
return _CP0_GET_COUNT();
}
/*---------------------------------------------------------------------------*/
/*
* Assumes M14K CPU is running at clock divide by 1 (48MHz)
* 1us = 48 counts.
* NOTE: We need to find out from DE what the pipeline rate is.
* M14K counter ticks at pipeline rate.
*/
uint32_t cpu_microsecond_interval(uint32_t start_count)
{
uint32_t curr_count;
curr_count = _CP0_GET_COUNT();
if (curr_count >= start_count) {
return ((curr_count - start_count) >> 4)/ 3ul;
} else {
return (((0xFFFFFFFFul - start_count) + curr_count) >> 4) / 3ul;
}
}
/*---------------------------------------------------------------------------*/
/* end mec14xx_system.c */
/** @}
*/

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/*****************************************************************************
* © 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_tfdp.c
*MEC14xx Trace FIFO Data Port hardware access
*/
/** @defgroup MEC14xx Peripherals TFDP
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_pcr.h"
#include "MEC14xx/mec14xx_gpio.h"
#include "MEC14xx/mec14xx_trace_func.h"
#ifdef ENABLE_TFDP_TRACE
#undef TFDP_PIN_1
#undef TFDP_PIN_2
#define TFDP_PIN_1 (GPIO_0116_ID) // Func1 PullUp enabled
#define TFDP_PIN_2 (GPIO_0117_ID) // Func1 PullUp enabled
static void tfdp_xmit_header(uint16_t nbr)
{
TFDP->DATA = TFDP_FRAME_START;
TFDP_DELAY();
TFDP->DATA = (uint8_t)nbr;
TFDP_DELAY();
TFDP->DATA = (uint8_t)(nbr >> 8);
TFDP_DELAY();
}
static void tfdp_xmit_hword(uint16_t hword)
{
TFDP->DATA = (uint8_t)hword;
TFDP_DELAY();
TFDP->DATA = (uint8_t)(hword >> 8);
TFDP_DELAY();
}
static void tfdp_xmit_word(uint32_t word)
{
uint8_t i;
for (i = 0u; i < 4; i++) {
TFDP->DATA = (uint8_t)word;
word >>= 8;
TFDP_DELAY();
}
}
/**
* tfdp_sleep_en - Gate clocks On/Off to TFDP block when idle
*
* @author C21969 (2/4/2014)
*
* @param sleep_en (1=Gate clocks when idle), (0=Do not gate
* clocks when idle)
*/
void tfdp_sleep_en(uint8_t sleep_en)
{
if ( sleep_en ) {
PCR->EC_SLEEP_EN |= (PCR_EC_TFDP_SLP_CLK);
} else {
PCR->EC_SLEEP_EN &= ~(PCR_EC_TFDP_SLP_CLK);
}
}
/**
* tfdp_enable - Init Trace FIFO Data Port
* @param boolean true=enable TFDP, false=disable TFDP
* @param boolean true=change TFDP pin configuration.
* If TFDP is enabled then GPIO103/104 set to Alt. Func. 1
* Else GPIO103/104 set to GPIO input, internal PU enabled.
* @note -
*/
void tfdp_enable(uint8_t en, uint8_t pin_cfg)
{
uint32_t delay;
if (en) {
if (pin_cfg) {
// Input with AltOut=1 to drive high when switched to output
GPIO_CTRL->REG[TFDP_PIN_1].w = (1ul << 16);
GPIO_CTRL->REG[TFDP_PIN_2].w = (1ul << 16);
delay = 128;
while ( delay-- )
{
CPU_NOP();
}
// GPIO Output enabled (drive based on above settings)
GPIO_CTRL->REG[TFDP_PIN_1].w |= (1ul << 9);
GPIO_CTRL->REG[TFDP_PIN_2].w |= (1ul << 9);
delay = 128;
while ( delay-- )
{
CPU_NOP();
}
// Switch to Function 1 (TFDP mode b[13:12]=01b)
GPIO_CTRL->REG[TFDP_PIN_1].w = (1ul << 16) + (1ul << 12);
GPIO_CTRL->REG[TFDP_PIN_2].w = (1ul << 16) + (1ul << 12);
}
/* b[0]=1(Enable)
* b[1]=0(Shift data out on rising edge)
* b[3:2]=00b TFDP shift clocks = AHB_CLK/2
* b[6:4]=000b 1 clock inter-packet delay
*/
TFDP->CONTROL = 0x01u;
}
else
{
TFDP->CONTROL = 0x00u;
if (pin_cfg)
{ /* Set to POR value (tri-stated input) */
GPIO_CTRL->REG[TFDP_PIN_1].w = 0;
GPIO_CTRL->REG[TFDP_PIN_2].w = 0;
}
}
} // end tfdp_enable()
/**
* TFDPTrace0 - TRACE0: transmit 16-bit trace number lsb first
* over TFDP.
*
* @author sworley
*
* @param nbr 16-bit trace number
* @param b unused
*
* @return uint8_t always TRUE
* @note Function implements critical section.
* Uses tool kit __disable_irq()/__enable_irq() pair which may use
* priviledged Cortex-Mx instructions.
*/
void TFDPTrace0 ( uint16_t nbr, uint8_t b )
{
#ifdef ENABLE_TRACE_MASK_IRQ
uint32_t isave;
isave = mips32r2_dis_intr();
#endif
(void)b;
tfdp_xmit_header(nbr);
#ifdef ENABLE_TRACE_MASK_IRQ
mips32r2_restore_intr(isave);
#endif
}
/**
* TRDPTrace1 - TRACE1: transmit 16-bit trace number lsb first
* and 16-bit data lsb first over TFDP.
*
* @author sworley
*
* @param nbr 16-bit trace number
* @param b unused
* @param uint32_t p1 16-bit data1 in b[15:0]
*
* @return uint8_t always TRUE
* @note Function implements critical section.
* Uses tool kit __disable_irq()/__enable_irq() pair which may use
* priviledged Cortex-Mx instructions.
*/
void TFDPTrace1 ( uint16_t nbr, uint8_t b, uint32_t p1 )
{
#ifdef ENABLE_TRACE_MASK_IRQ
uint32_t isave;
isave = mips32r2_dis_intr();
#endif
(void)b;
tfdp_xmit_header(nbr);
tfdp_xmit_hword(p1);
#ifdef ENABLE_TRACE_MASK_IRQ
mips32r2_restore_intr(isave);
#endif
}
/**
* TFDPTrace2 - TRACE2: transmit 16-bit trace number lsb first
* and two 16-bit data parameters lsb first over TFDP.
*
* @author sworley
*
* @param nbr trace number
* @param b unused
* @param uint32_t p1 16-bit data1 in b[15:0]
* @param uint32_t p2 16-bit data2 in b[15:0]
*
* @return uint8_t always TRUE
* @note Uses tool kit functions to save/disable/restore
* interrupts for critical section. These may use
* priviledged instructions.
*/
void TFDPTrace2 ( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2 )
{
#ifdef ENABLE_TRACE_MASK_IRQ
uint32_t isave;
isave = mips32r2_dis_intr();
#endif
(void)b;
tfdp_xmit_header(nbr);
tfdp_xmit_hword(p1);
tfdp_xmit_hword(p2);
#ifdef ENABLE_TRACE_MASK_IRQ
mips32r2_restore_intr(isave);
#endif
}
/**
* TFDPTrace3 - TRACE3: transmit 16-bit trace number lsb first
* and three 16-bit data parameters lsb first over TFDP.
*
* @author sworley
*
* @param nbr trace number
* @param b unused
* @param uint32_t p1 16-bit data1 in b[15:0]
* @param uint32_t p2 16-bit data2 in b[15:0]
* @param uint32_t p3 16-bit data3 in b[15:0]
*
* @return uint8_t always TRUE
* @note Uses tool kit functions to save/disable/restore
* interrupts for critical section. These may use
* priviledged instructions.
*/
void TFDPTrace3 ( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2, uint32_t p3)
{
#ifdef ENABLE_TRACE_MASK_IRQ
uint32_t isave;
isave = mips32r2_dis_intr();
#endif
(void)b;
tfdp_xmit_header(nbr);
tfdp_xmit_hword(p1);
tfdp_xmit_hword(p2);
tfdp_xmit_hword(p3);
#ifdef ENABLE_TRACE_MASK_IRQ
if ( isave & (1ul<<0) )
{
mips32r2_en_intr();
}
#endif
}
/**
* TFDPTrace4 - TRACE3: transmit 16-bit trace number lsb first
* and four 16-bit data parameters lsb first over TFDP.
*
* @author sworley
*
* @param nbr trace number
* @param b unused
* @param uint32_t p1 16-bit data1 in b[15:0]
* @param uint32_t p2 16-bit data2 in b[15:0]
* @param uint32_t p3 16-bit data3 in b[15:0]
* @param uint32_t p4 16-bit data4 in b[15:0]
*
* @return uint8_t always TRUE
* @note Uses tool kit functions to save/disable/restore
* interrupts for critical section. These may use
* priviledged instructions.
*/
void TFDPTrace4 ( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4)
{
#ifdef ENABLE_TRACE_MASK_IRQ
uint32_t isave;
isave = mips32r2_dis_intr();
#endif
(void)b;
tfdp_xmit_header(nbr);
tfdp_xmit_hword(p1);
tfdp_xmit_hword(p2);
tfdp_xmit_hword(p3);
tfdp_xmit_hword(p4);
#ifdef ENABLE_TRACE_MASK_IRQ
if ( isave & (1ul<<0) )
{
mips32r2_en_intr();
}
#endif
}
/**
* TFDPTrace11 - Transmit one 32-bit data item over TFDP
*
* @param nbr trace number
* @param b unused
* @param uint32_t p1 32-bit data to be transmitted
*
*/
void TFDPTrace11( uint16_t nbr, uint8_t b, uint32_t p1)
{
#ifdef ENABLE_TRACE_MASK_IRQ
uint32_t isave;
isave = mips32r2_dis_intr();
#endif
(void)b;
tfdp_xmit_header(nbr);
tfdp_xmit_word(p1);
#ifdef ENABLE_TRACE_MASK_IRQ
if ( isave & (1ul<<0) )
{
mips32r2_en_intr();
}
#endif
}
/**
* TFDPTrace12 - Transmit two 32-bit data items over TFDP
*
* @param nbr trace number
* @param b unused
* @param uint32_t p1 32-bit data1 to be transmitted
* @param uint32_t p2 32-bit data2 to be transmitted
*
*/
void TFDPTrace12( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2 )
{
#ifdef ENABLE_TRACE_MASK_IRQ
uint32_t isave;
isave = mips32r2_dis_intr();
#endif
(void)b;
tfdp_xmit_header(nbr);
tfdp_xmit_word(p1);
tfdp_xmit_word(p2);
#ifdef ENABLE_TRACE_MASK_IRQ
if ( isave & (1ul<<0) )
{
mips32r2_en_intr();
}
#endif
}
#endif // #ifdef ENABLE_TFDP_TRACE
/* end mec14xx_tfdp.c */
/** @}
*/

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/*****************************************************************************
* © 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_timers.c
*MEC14xx Timers
*/
/** @defgroup MEC14xx Peripherals Timers
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_pcr.h"
#include "MEC14xx/mec14xx_timers.h"
// pairs of bytes (sleep reg, bit position)
// sleep reg = 0 for EC_SLEEP_EN or 1 for EC_SLEEP_EN2
//
struct btmr_sleep_info_s {
uint8_t slp_reg;
uint8_t bit_pos;
};
static const struct btmr_sleep_info_s btmr_slp_info[BTMR_MAX_INSTANCE] = {
{ 0, PCR_EC_TIMER0_SLP_BITPOS },
{ 0, PCR_EC_TIMER1_SLP_BITPOS },
{ 1, PCR_EC2_TIMER2_SLP_BITPOS },
{ 1, PCR_EC2_TIMER3_SLP_BITPOS }
};
#ifdef MEC14XX_BTIMER_CHECK_ID
/**
* tmr_valid - Local helper that checks if logical Timer ID is
* valid.
*
* @author sworley
*
* @param tmr_id 0-based Timer ID
*
* @return uint8_t Non-zero(VALID), 0(Invalid)
*/
static uint8_t btmr_valid(uint8_t tmr_id)
{
if ( tmr_id < (BTMR_ID_MAX ) ) {
return true;
}
return false;
}
#else
/**
* @brief - This version of tmr_valid skips checking always
* returning TRUE. Compiler may optimize it out.
*
*/
static uint8_t btmr_valid(uint8_t tmr_id)
{
(void) tmr_id;
return true;
}
#endif
uint32_t btmr_get_hw_addr(uint8_t btmr_id)
{
return (uint32_t)(BTMR0_BASE) +
((uint32_t)(btmr_id) << (BTMR_INSTANCE_BITPOS));
}
/**
* btmr_sleep_en - Enable/Disable clock gating on idle of a
* timer
*
* @author sworley (8/16/2013)
*
* @param tmr_id zero based timer ID.
* @param pwr_on boolean true=ON, false=OFF
*/
void btmr_sleep_en(uint8_t tmr_id, uint8_t sleep_en)
{
uint32_t sleep_mask;
uint32_t volatile * p;
sleep_mask = 0ul;
if ( btmr_valid(tmr_id) ) {
if (btmr_slp_info[tmr_id].slp_reg) {
p = (uint32_t volatile *)&(PCR->EC_SLEEP_EN2);
} else {
p = (uint32_t volatile *)&(PCR->EC_SLEEP_EN);
}
sleep_mask = (1ul << btmr_slp_info[tmr_id].bit_pos);
if (sleep_en) {
*p |= (sleep_mask);
} else {
*p &= ~(sleep_mask);
}
}
}
/**
* btmr_reset - Peform soft reset of specified timer.
*
* @author sworley
*
* @param tmr_id 0-based Timer ID
* @note Soft reset set all registers to POR values.
* Spins 256 times waiting on hardware to clear reset bit.
*/
void btmr_reset(uint8_t tmr_id)
{
BTMR_TypeDef * p;
uint32_t wait_cnt;
if (btmr_valid(tmr_id)) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
p->CONTROL = (BTMR_CNTL_SOFT_RESET);
wait_cnt = 256ul;
do {
if ( 0ul == (p->CONTROL & BTMR_CNTL_SOFT_RESET) ) {
break;
}
}
while ( wait_cnt-- );
}
}
/**
* btmr_init - Initialize specified timer
* @param zero based timer ID
* @param tmr_cntl b[15:0] = timer configuration flags.
* @param initial_count
* @param preload_count
* @note performs a soft reset of the timer before
* configuration.
*/
void btmr_init(uint8_t tmr_id,
uint16_t tmr_cntl,
uint16_t prescaler,
uint32_t initial_count,
uint32_t preload_count)
{
BTMR_TypeDef * pTMR;
pTMR = NULL;
if (btmr_valid(tmr_id)) {
btmr_reset(tmr_id);
pTMR = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
// Ungate timer clocks and program prescale
pTMR->CONTROL = ((uint32_t)prescaler << 16) + (BTMR_CNTL_ENABLE);
// Program Preload & initial counter value
pTMR->PRELOAD = preload_count;
pTMR->COUNT = initial_count;
// Program control register, interrupt enable, and clear status
if (tmr_cntl & BTMR_COUNT_UP) {
pTMR->CONTROL |= BTMR_CNTL_COUNT_UP;
}
if (tmr_cntl & BTMR_AUTO_RESTART) {
pTMR->CONTROL |= BTMR_CNTL_AUTO_RESTART;
}
if (tmr_cntl & BTMR_INT_EN) {
pTMR->INTEN = 0x01u; // enable first
pTMR->STATUS = 0x01u; // clear status
}
}
}
/**
* btmr_ien - Enable specified timer's interrupt.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
* @param ien Non-zero enable interrupt in timer block, 0
* disable.
* @note Write 0 or 1 to timer's INTEN register.
*/
void btmr_ien(uint8_t tmr_id, uint8_t ien)
{
BTMR_TypeDef * p;
if (btmr_valid(tmr_id)) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
if (ien) {
p->INTEN = (BTMR_INTEN);
} else {
p->INTEN = (BTMR_INTDIS);
}
}
}
/**
* tmr_get_clr_ists - Read Timer interrupt status and clear if
* set.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
*
* @return uint8_t true (Timer interrupt status set) else false.
* @note If timer interrupt status is set then clear it before
* returning.
*/
uint8_t btmr_get_clr_ists(uint8_t tmr_id)
{
BTMR_TypeDef * p;
uint8_t rc;
rc = (MEC14XX_FALSE);
if (btmr_valid(tmr_id)) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
if ( p->STATUS ) {
p->STATUS = (BTMR_STATUS_ACTIVE);
rc = true;
}
}
return rc;
}
/**
* btmr_reload - Force timer to reload counter from preload
* register.
*
* @param tmr_id zero based timer ID.
* @note Hardware will only reload counter if timer is running.
*/
void btmr_reload(uint8_t tmr_id)
{
BTMR_TypeDef * p;
if ( btmr_valid(tmr_id) ) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
if (p->CONTROL & BTMR_CNTL_START) {
p->CONTROL |= BTMR_CNTL_RELOAD;
}
}
}
/**
* btmr_set_count - Program timer's counter register.
*
* @author sworley
*
* @param tmr_id zero based timer ID
* @param count new counter value
* @note Timer hardware may implement a 16-bit or 32-bit
* hardware counter. If the timer is 16-bit only the lower
* 16-bits of the count paramter are used.
*/
void btmr_set_count(uint8_t tmr_id, uint32_t count)
{
BTMR_TypeDef * p;
if (btmr_valid(tmr_id)) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
p->COUNT = count;
}
}
/**
* btmr_count - Return current value of timer's count register.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
*
* @return uint32_t timer count may be 32 or 16 bits depending
* upon the hardware. On MEC1322 Timers 0-3 are 16-bit
* and Timers 4-5 are 32-bit.
*/
uint32_t btmr_count(uint8_t tmr_id)
{
BTMR_TypeDef * p;
uint32_t cnt;
cnt = 0ul;
if ( btmr_valid(tmr_id) ) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
cnt = (uint32_t)(p->COUNT);
}
return cnt;
}
/**
* btmr_start - Start timer counting.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
*/
void btmr_start(uint8_t btmr_id)
{
BTMR_TypeDef * p;
if ( btmr_valid(btmr_id) ) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(btmr_id);
p->CONTROL |= BTMR_CNTL_START;
}
}
/**
* btmr_stop - Stop timer.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
* @note When a stopped timer is started again it will reload
* the count register from preload value.
*/
void btmr_stop(uint8_t tmr_id)
{
BTMR_TypeDef * p;
if (btmr_valid(tmr_id)) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
p->CONTROL &= ~(BTMR_CNTL_START);
}
}
/**
* btmr_is_stopped - Return state of timer's START bit.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
*
* @return uint8_t false(timer not started), true(timer started)
*/
uint8_t btmr_is_stopped(uint8_t tmr_id)
{
BTMR_TypeDef * p;
uint8_t rc;
rc = (MEC14XX_TRUE);
if (btmr_valid(tmr_id)) {
rc = (MEC14XX_FALSE);
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
if ((p->CONTROL & BTMR_CNTL_START) == 0) {
rc = (MEC14XX_TRUE);
}
}
return rc;
}
/**
* btmr_halt - Halt timer counting with no reload on unhalt.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
* @note A halted timer will not reload the count register when
* unhalted, it will continue counting from the current
* count value.
*/
void btmr_halt(uint8_t tmr_id)
{
BTMR_TypeDef * p;
if ( btmr_valid(tmr_id) ) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
p->CONTROL |= (BTMR_CNTL_HALT);
}
}
/**
* btmr_unhalt - Unhalt timer counting.
*
* @author sworley
*
* @param tmr_id zero based timer ID.
*/
void btmr_unhalt(uint8_t tmr_id)
{
BTMR_TypeDef * p;
if ( btmr_valid(tmr_id) ) {
p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);
p->CONTROL &= ~(BTMR_CNTL_HALT);
}
}
/* end mec14xx_timers.c */
/** @}
*/

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/*********************************************************************
*
* C Runtime Startup
*
*********************************************************************
* Filename: crt0.S
*
* Processor: PIC32
*
* Compiler: MPLAB XC32
* MPLAB X IDE
* Company: Microchip Technology Inc.
*
* Software License Agreement
*
* This software is developed by Microchip Technology Inc. and its
* subsidiaries ("Microchip").
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Microchip's name may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************/
#include <xc.h>
#include <cp0defs.h>
/* MEC14xx */
#define PIC32_SRS_SET_COUNT 1
#define INIT_SSX
#undef INIT_MMU_MZ_FIXED
#undef INIT_L1_CACHE
/* MEC14xx fill stack with sentinel value */
#define EN_STACK_FILL */
#if (__XC32_VERSION > 1000) && !defined(CPP_INIT)
#define CPP_INIT
#endif
#if !defined(PIC32_SRS_SET_COUNT)
# warning PIC32_SRS_SET_COUNT not defined on build line
# define PIC32_SRS_SET_COUNT 2
#endif
#if !defined(STACK_FILL_VALUE)
# define STACK_FILL_VALUE 0xDEADBEEFul
#endif
/* This file contains 32-bit assembly code */
.set nomips16
##################################################################
# Entry point of the entire application
##################################################################
.section .reset,code,keep
.align 2
.set noreorder
.ent _reset
############################
# Begin ISA switching code #
############################
#if defined(__PIC32_HAS_MICROMIPS) || defined(__mips_micromips)
#if defined (__mips_micromips)
.set micromips
#endif
_reset:
.word 0x10000003 /* MIPS32: branch to 0xBFC00010 from here */
/* MicroMIPS: ADDI32 $0, $0, 0x0007 (nop) */
/* DO NOT change the relative branch */
.word 0x00000000 /* NOP */
__reset_micromips_isa:
.set micromips
jal _startup
nop
.align 2
/* Device not in proper ISA mode */
.set nomicromips
__reset_switch_isa:
jal _startup
nop
#else
_reset:
jal _startup
nop
#endif /* __PIC32_HAS_MICROMIPS */
.align 2
.end _reset
.globl _reset
.size _reset, .-_reset
.section .reset.startup,code,keep
.align 2
.set noreorder
#if defined (__mips_micromips)
.set micromips
#else
.set nomicromips
#endif
############################
# End ISA switching code #
############################
##################################################################
# Startup code
##################################################################
.align 2
.set noreorder
.ent _startup
_startup:
##################################################################
# New - Set BEV=1 for the cases where M14K instruction pointer
# is changed to force ROM to run again. CP0.BEV must be 1 to
# safely write CP0.EBASE
##################################################################
mfc0 k0, _CP0_STATUS
lui k1, 0x0040
or k0, k0, k1 # CP0.STATUS.BEV(bit[22]) = 1
mtc0 k0, _CP0_STATUS
ehb
##################################################################
# Initialize Stack Pointer
# _stack is initialized by the linker script to point to the
# starting location of the stack in DRM
##################################################################
la sp,_stack
##################################################################
# Initialize Global Pointer
# _gp is initialized by the linker script to point to "middle"
# of the small variables region
##################################################################
la gp,_gp
#if (PIC32_SRS_SET_COUNT == 2)
##################################################################
# Initialize Global Pointer in Shadow Set
# The SRSCtl's PSS field must be set to the shadow set in which
# to initialize the global pointer. Since we have only a
# single shadow set (besides the normal), we will initialize
# SRSCtl<PSS> to SRSCtl<HSS>. We then write the global pointer
# to the previous shadow set to ensure that on interrupt, the
# global pointer has been initialized.
##################################################################
mfc0 t1,_CP0_SRSCTL # Read SRSCtl register
add t3,t1,zero # Save off current SRSCtl
ext t2,t1,26,4 # to obtain HSS field
ins t1,t2,6,4 # Put HSS field
mtc0 t1,_CP0_SRSCTL # into SRSCtl<PSS>
ehb # Clear hazard before using new SRSCTL
wrpgpr gp,gp # Set global pointer in PSS
mtc0 t3,_CP0_SRSCTL # Restore SRSCtl
ehb
#elif (PIC32_SRS_SET_COUNT > 2)
##################################################################
# Initialize Global Pointer in Shadow Set(s)
# The SRSCtl PSS field must be set to the shadow set in which
# to initialize the global pointer. We will initialize
# SRSCtl<PSS> to the number of reg sets and work down to set zero.
# We write the global pointer to the previous shadow set to
# ensure that on interrupt, the global pointer has been
# initialized.
##################################################################
mfc0 t1,_CP0_SRSCTL # Read SRSCtl register
add t3,t1,zero # Save off current SRSCtl
li t2,(PIC32_SRS_SET_COUNT-1)
1: ins t1,t2,6,4 # Put next shadow set field
mtc0 t1,_CP0_SRSCTL # into SRSCtl<PSS>
ehb # Clear hazard before using new SRSCTL
wrpgpr gp,gp # Set global pointer in PSS
addiu t2,t2,-1 # Next lower shadow set
# Loop for all sets
bne t2,$0,1b # Down to zero (normal GPR set)
nop
mtc0 t3,_CP0_SRSCTL # Restore SRSCtl
ehb
#endif /* (PIC32_SRS_SET_COUNT > 2) */
##################################################################
# Call the "on reset" procedure
##################################################################
la t0,_on_reset
jalr t0
nop
#if defined(INIT_MMU_MZ_FIXED)
##################################################################
# Initialize TLB for fixed mapping to EBI and SQI
##################################################################
.extern __pic32_tlb_init_ebi_sqi
la t0,__pic32_tlb_init_ebi_sqi
jalr t0
nop
#endif
#if defined(INIT_L1_CACHE)
##################################################################
# Initialize L1 cache register
##################################################################
.extern __pic32_init_cache
la t0,__pic32_init_cache
jalr t0
nop
#endif
#if defined(EN_STACK_FILL)
##################################################################
# Fill stack
# TODO - handle different stack lengths:
# mulitple of 4, 8, 16, or 32
##################################################################
la t0,_stack_start
la t1,_stack
b _stack_check
_stack_init:
sw zero,0x0(t0)
sw zero,0x4(t0)
sw zero,0x8(t0)
sw zero,0xc(t0)
addu t0,16
_stack_check:
bltu t0,t1,_stack_init
nop
#endif
##################################################################
# Clear uninitialized data sections
##################################################################
la t0,_bss_begin
la t1,_bss_end
b _bss_check
nop
_bss_init:
sw zero,0x0(t0)
sw zero,0x4(t0)
sw zero,0x8(t0)
sw zero,0xc(t0)
addu t0,16
_bss_check:
bltu t0,t1,_bss_init
nop
##################################################################
# Initialize data using the linker-generated .dinit table
##################################################################
.equiv FMT_CLEAR,0
.equiv FMT_COPY,1
_dinit_init:
la t0,_dinit_addr
#define SRC t0
#define DST t1
#define LEN t2
#define FMT t3
0: lw DST,0(SRC)
beqz DST,9f
addu SRC,4
lw LEN,0(SRC)
addu SRC,4
lw FMT,0(SRC)
beq FMT,$0,_dinit_clear
addu SRC,4
_dinit_copy:
lbu t4,0(SRC)
subu LEN,1
addu SRC,1
sb t4,0(DST)
bne LEN,$0,_dinit_copy
addu DST,1
b _dinit_end
nop
_dinit_clear:
sb $0,(DST)
subu LEN,1
bne LEN,$0,_dinit_clear
addu DST,1
_dinit_end:
addu SRC,3
addiu LEN,$0,0xFFFFFFFC
and SRC,LEN,SRC
lw DST,0(SRC)
bne DST,$0,0b
nop
9:
##################################################################
# If there are no RAM functions, skip the next section --
# initializing bus matrix registers.
##################################################################
la t1,_ramfunc_begin
beqz t1,_ramfunc_done
nop
#if defined(INIT_SSX)
/* No initialization required */
#else /* Use BMX */
##################################################################
# Initialize bus matrix registers if RAM functions exist in the
# application
##################################################################
la t1,_bmxdkpba_address
la t2,BMXDKPBA
sw t1,0(t2)
la t1,_bmxdudba_address
la t2,BMXDUDBA
sw t1,0(t2)
la t1,_bmxdupba_address
la t2,BMXDUPBA
sw t1,0(t2)
#endif /* INIT_SSX */
_ramfunc_done:
##################################################################
# Initialize CP0 registers
##################################################################
# Initialize Count register
##################################################################
mtc0 zero,_CP0_COUNT
##################################################################
# Initialize Compare register
##################################################################
li t2,-1
mtc0 t2,_CP0_COMPARE
##################################################################
# Initialize EBase register
##################################################################
la t1,_ebase_address
mtc0 t1,_CP0_EBASE
##################################################################
# Initialize IntCtl register
##################################################################
la t1,_vector_spacing
li t2,0 # Clear t2 and
ins t2,t1,5,5 # shift value to VS field
mtc0 t2,_CP0_INTCTL
##################################################################
# Initialize CAUSE registers
# - Enable counting of Count register <DC = 0>
# - Use special exception vector <IV = 1>
# - Clear pending software interrupts <IP1:IP0 = 0>
##################################################################
li t1,0x00800000
mtc0 t1,_CP0_CAUSE
##################################################################
# Initialize STATUS register
# - Access to Coprocessor 0 not allowed in user mode <CU0 = 0>
# - User mode uses configured endianness <RE = 0>
# - Preserve Bootstrap Exception vectors <BEV>
# - Preserve soft reset <SR> and non-maskable interrupt <NMI>
# - CorExtend enabled based on whether CorExtend User Defined
# Instructions have been implemented <CEE = Config<UDI>>
# - Disable any pending interrups <IM7..IM2 = 0, IM1..IM0 = 0>
# - Disable hardware interrupts <IPL7:IPL2 = 0>
# - Base mode is Kernel mode <UM = 0>
# - Error level is normal <ERL = 0>
# - Exception level is normal <EXL = 0>
# - Interrupts are disabled <IE = 0>
# - DSPr2 ASE is enabled for devices that support it <MX = 1>
##################################################################
mfc0 t0,_CP0_CONFIG
ext t1,t0,22,1 # Extract UDI from Config register
sll t1,t1,17 # Move UDI to Status.CEE location
mfc0 t0,_CP0_STATUS
and t0,t0,0x00580000 # Preserve SR, NMI, and BEV
#if defined(INIT_DSPR2)
li t2, 0x01000000 # Set the Status.MX bit to enable DSP
or t0,t2,t0
#endif
or t0,t1,t0 # Include Status.CEE (from UDI)
mtc0 t0,_CP0_STATUS
##################################################################
# Call the "on bootstrap" procedure
##################################################################
la t0,_on_bootstrap
jalr t0
nop
##################################################################
# Initialize Status<BEV> for normal exception vectors
##################################################################
mfc0 t0,_CP0_STATUS
and t0,t0,0xffbfffff # Clear BEV
mtc0 t0,_CP0_STATUS
##################################################################
# Call main. We do this via a thunk in the text section so that
# a normal jump and link can be used, enabling the startup code
# to work properly whether main is written in MIPS16 or MIPS32
# code. I.e., the linker will correctly adjust the JAL to JALX if
# necessary
##################################################################
and a0,a0,0
and a1,a1,0
la t0,_main_entry
jr t0
nop
.end _startup
##################################################################
# General Exception Vector Handler
# Jumps to _general_exception_context
##################################################################
.section .gen_handler,code
.set noreorder
.ent _gen_exception
_gen_exception:
0: la k0,_general_exception_context
jr k0
nop
.end _gen_exception
#if defined(INIT_MMU_MZ_FIXED)
##################################################################
# Simple TLB-Refill Exception Vector
# Jumps to _simple_tlb_refill_exception_context
##################################################################
.section .simple_tlb_refill_vector,code,keep
.set noreorder
.ent simple_tlb_refill_vector
simple_tlb_refill_vector:
la k0,_simple_tlb_refill_exception_context
jr k0
nop
.end simple_tlb_refill_vector
#endif
#if defined(INIT_L1_CACHE)
##################################################################
# Cache-Error Exception Vector Handler
# Jumps to _cache_err_exception_context
##################################################################
.section .cache_err_vector,code,keep
.set noreorder
.ent _cache_err_vector
_cache_err_vector:
la k0,_cache_err_exception_context
jr k0
nop
.end _cache_err_vector
#endif
.section .text.main_entry,code,keep
.ent _main_entry
_main_entry:
#if defined(CPP_INIT)
.weak _init
# call .init section to run constructors etc
lui a0,%hi(_init)
addiu sp,sp,-24
addiu a0,a0,%lo(_init)
beq a0,$0,2f
sw $31,20(sp) #,
jalr a0
nop
2:
#endif
and a0,a0,0
and a1,a1,0
##################################################################
# Call main
##################################################################
jal main
nop
#if defined(CALL_EXIT)
##################################################################
# Call exit()
##################################################################
jal exit
nop
#endif
##################################################################
# Just in case, go into infinite loop
# Call a software breakpoint only with -mdebugger compiler option
##################################################################
.weak __exception_handler_break
__crt0_exit:
1:
la v0,__exception_handler_break
beq v0,0,0f
nop
jalr v0
nop
0: b 1b
nop
.globl __crt0_exit
.end _main_entry
###############################################################
# launch_fw
###############################################################
.globl rom_launch_fw
.set nomips16
.set micromips
.ent rom_launch_fw
.type rom_launch_fw, @function
rom_launch_fw:
.set noreorder
.set nomacro
lfw1:
di
lfw2:
ehb
lfw3:
nop
# turn off core timer
lfw4:
mfc0 t0, _CP0_CAUSE
lfw5:
lui t1, 0xf7ff
lfw6:
ori t1, t1, 0xffff
lfw7:
and t0, t0, t1
lfw8:
mtc0 t0, _CP0_CAUSE
lfw9:
ehb
lfw10:
nop
lfw11:
mfc0 t0, _CP0_STATUS
lfw12:
lui t1, 0x0040
lfw13:
or t0, t0, t1 # BEV(bit[22]) = 1
lfw14:
mtc0 t0, _CP0_STATUS
lfw15:
ehb
lfw16:
nop
lfw17:
JR.HB a0
lfw18:
nop
0:
j 0b # should not get here
lfw19:
nop
.set macro
.set reorder
.end rom_launch_fw
.size rom_launch_fw, .-rom_launch_fw

68
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crti.S Normal file
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/*********************************************************************
*
* C Runtime Startup
*
*********************************************************************
* Filename: crti.s
*
* Processor: PIC32
*
* Compiler: MPLAB XC32
* MPLAB X IDE
* Company: Microchip Technology Inc.
*
* Software License Agreement
*
* This software is developed by Microchip Technology Inc. and its
* subsidiaries ("Microchip").
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Microchip's name may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************/
#ifdef __LIBBUILD__
# Replace the standard debugging information with a simple filename. This
# prevents the library build directory from showing up in MPLAB IDE. It
# also effectively disables source-line debugging.
.file 1 "libpic32/startup/crti.s"
.loc 1 0
#endif
/* 4 slots for argument spill area. 1 for cpreturn, 1 for stack.
Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */
.section .init, code
.globl _init
.type _init,@function
_init:
addu $sp,$sp,-32
sw $31,20($sp)
.section .fini, code
.globl _fini
.type _fini,@function
_fini:
addu $sp,$sp,-32
sw $31,20($sp)

62
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crtn.S Normal file
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/*********************************************************************
*
* C Runtime Startup
*
*********************************************************************
* Filename: crtn.s
*
* Processor: PIC32
*
* Compiler: MPLAB XC32
* MPLAB X IDE
* Company: Microchip Technology Inc.
*
* Software License Agreement
*
* This software is developed by Microchip Technology Inc. and its
* subsidiaries ("Microchip").
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Microchip's name may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************/
#ifdef __LIBBUILD__
# Replace the standard debugging information with a simple filename. This
# prevents the library build directory from showing up in MPLAB IDE. It
# also effectively disables source-line debugging.
.file 1 "libpic32/startup/crtn.s"
.loc 1 0
#endif
.section .init, code
lw $31,20($sp)
addu $sp,$sp,32
j $31
.section .fini, code
lw $31,20($sp)
addu $sp,$sp,32
j $31

43
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/default-on-bootstrap.c Normal file
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/*********************************************************************
*
* Default _on_bootstrap Implementation
*
*********************************************************************
* Filename: default-on-bootstrap.c
*
* Processor: PIC32
*
* Compiler: MPLAB C Compiler for PIC32 MCUs
* MPLAB IDE
* Company: Microchip Technology Inc.
*
* Software License Agreement
*
* The software supplied herewith by Microchip Technology Incorporated
* (the 'Company') for its PIC32/PIC24F Microcontroller is intended
* and supplied to you, the Company's customer, for use solely and
* exclusively on Microchip PIC32/PIC24F Microcontroller products.
* The software is owned by the Company and/or its supplier, and is
* protected under applicable copyright laws. All rights are reserved.
* Any use in violation of the foregoing restrictions may subject the
* user to criminal sanctions under applicable laws, as well as to
* civil liability for the breach of the terms and conditions of this
* license.
*
* THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
* TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,
* IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
********************************************************************/
/* This is a default definition of an _on_bootstrap() function.
* It does nothing and just goes returns. If the user
* application supplies a handler function, this function will not be
* referenced and thus not pulled in from the library.
*/
void
_on_bootstrap (void)
{
}

63
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/on_reset.c Normal file
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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file on_reset.c
*MEC14xx XC32 M14K Startup code _on_reset handler
*/
/** @defgroup MEC14xx Startup
* @{
*/
#include "appcfg.h"
#include "platform.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_pcr.h"
/*
* From linker command file
*/
extern uint32_t _ebase_address[];
/** _on_reset - Very early HW initialization.
* @note XC32 startup code has initialized SP & GP. No other
* C features have been initialized (before .bss clear and
* global data init.) NOTE: MIPS M14K is still in Boot-Strap
* mode and EBASE has not been programmed. Any exception or
* interrupts will vector to the BEV Exception handler!
*/
void
__attribute__((nomips16)) _on_reset (void)
{
/* Enable JTAG */
ECS_REG->JTAG_ENABLE |= 1u;
/* Disable WDT */
WDT->CONTROL = 0u;
/* Set CPU clock divider specified in appcfg.h */
PCR->PROC_CLOCK_CNTRL = ( PCR_CLOCK_DIVIDER );
__EHB();
CPU_NOP();
}

642
FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/include/MEC14xx/mec14xx.h Normal file
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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx.h
*MEC14xx master header
*/
/** @defgroup MEC14xx
*/
/**
* MEC14xx initial version
*/
#ifndef MEC14XX_DEFS_H
#define MEC14XX_DEFS_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup MEC14xx_Definitions
This file defines all structures and symbols for MEC14xx:
- registers and bitfields
- peripheral base address
- peripheral ID
- Peripheral definitions
@{
*/
/** MEC14xx Hardware memory maps.
* @note
* Common
*
* MEC1404
* 96KB CODE SRAM
* 32KB DATA SRAM
*
* Physical Virtual Length
* CODE SRAM 0x1FD0_0000 - 0x1FD1_7FFF 0xBFD0_0000 - 0xBFD1_7FFF 96KB (0x18000)
* DATA SRAM 0x1FD1_8000 - 0x1FD1_FFFF 0xBFD1_8000 - 0xBFD1_FFFF 32KB
* CPP Regs 0x1FFF_C000 - 0x1FFF_FFFF 0xBFFF_C000 - 0xBFFF_FFFF 16KB
*
* MEC1418
* 160KB CODE SRAM
* 32KB DATA SRAM
*
* Physical Virtual Length
* CODE SRAM 0x1FCF_0000 - 0x1FD1_7FFF 0xBFCF_0000 - 0xBFD1_7FFF 128KB (0x20000)
* DATA SRAM 0x1FD1_8000 - 0x1FD1_FFFF 0xBFD1_8000 - 0xBFD1_FFFF 32KB
* CPP Regs 0x1FFF_C000 - 0x1FFF_FFFF 0xBFFF_C000 - 0xBFFF_FFFF 16KB
*
*/
#define MEC14XX_TRUE (1ul)
#define MEC14XX_FALSE (0ul)
#define MEC14XX_ON (1ul)
#define MEC14XX_OFF (0ul)
#define MEC14XX_ENABLE (1ul)
#define MEC14XX_DISABLE (0ul)
#define MEC14XX_ROM_PBASE (0x1FC00000ul)
#define MEC14XX_ROM_PBLEN (1024ul * 64ul)
#define MEC14XX_ROM_PLIMIT ((MEC14XX_ROM_PBASE) + (MEC14XX_ROM_PBLEN))
#define MEC14XX_ROM_VBASE (0xBFC00000ul)
#define MEC14XX_ROM_VBLEN (1024ul * 64ul)
#define MEC14XX_ROM_VLIMIT ((MEC14XX_ROM_VBASE) + (MEC14XX_ROM_VBLEN))
/* MEC1404 */
#define MEC1404_ICODE_PSRAM_BASE (0x1FD00000ul)
#define MEC1404_ICODE_PSRAM_BLEN (1024ul * 96ul)
#define MEC1404_ICODE_PSRAM_LIMIT ((MEC1404_ICODE_PSRAM_SM_BASE)+(MEC1404_ICODE_PSRAM_SM_BLEN))
// Virtual
#define MEC1404_ICODE_VSRAM_BASE ((MEC1404_ICODE_PSRAM_BASE) | (0xA0000000ul))
#define MEC1404_ICODE_VSRAM_BLEN (MEC1404_ICODE_PSRAM_BLEN)
#define MEC1404_ICODE_VSRAM_LIMIT ((MEC1404_ICODE_PSRAM_LIMIT) | (0xA0000000ul))
/* MEC1418 */
#define MEC1418_ICODE_PSRAM_BASE (0x1FCF0000ul)
#define MEC1418_ICODE_PSRAM_BLEN (1024ul * 160ul)
#define MEC1418_ICODE_PSRAM_LIMIT ((MEC1418_ICODE_PSRAM_SM_BASE)+(MEC1418_ICODE_PSRAM_SM_BLEN))
// Virtual
#define MEC1418_ICODE_VSRAM_BASE ((MEC1418_ICODE_PSRAM_BASE) | (0xA0000000ul))
#define MEC1418_ICODE_VSRAM_BLEN (MEC1418_ICODE_PSRAM_BLEN)
#define MEC1418_ICODE_VSRAM_LIMIT ((MEC1418_ICODE_PSRAM_LIMIT) | (0xA0000000ul))
/* 32KB Data SRAM */
#define MEC14XX_DCODE_PSRAM_BASE (0x1FD18000ul)
#define MEC14XX_DCODE_PSRAM_BLEN (1024ul * 32ul)
#define MEC14XX_DCODE_PSRAM_LIMIT ((MEC14XX_DCODE_PSRAM_BASE)+(MEC14XX_DCODE_PSRAM_BLEN))
#define MEC14XX_DCODE_PSRAM_MASK ((MEC14XX_DCODE_PSRAM_BLEN) - 1ul)
#define MEC14XX_DCODE_VSRAM_BASE (0xBFD18000ul)
#define MEC14XX_DCODE_VSRAM_BLEN (1024ul * 32ul)
#define MEC14XX_DCODE_VSRAM_LIMIT ((MEC14XX_DCODE_VSRAM_BASE)+(MEC14XX_DCODE_VSRAM_BLEN))
#define MEC14XX_DCODE_VSRAM_MASK ((MEC14XX_DCODE_VSRAM_BLEN) - 1ul)
/* Closely Coupled Peripheral Region */
#define MEC14XX_CCP_PHYS_BASE (0x1FFFC000ul)
#define MEC14XX_CCP_BLEN (16ul * 1024ul)
#define MEC14XX_CCP_PHYS_LIMIT ((MEC14XX_CCP_PHYS_BASE) + (MEC14XX_CCP_BLEN))
#define MEC14XX_CCP_VIRT_BASE (0xBFFFC000ul)
#define MEC14XX_CCP_VIRT_LIMIT ((MEC14XX_CCP_VIRT_BASE) + (MEC14XX_CCP_BLEN))
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup MEC14xx_DEFS Device Definitions
Configuration of the MIPS microAptiv M14K Processor and Core Peripherals
@{
*/
// Memory Mapped Control Register on AHB (system bus)
#define MMCR_BASE (0xA0000000UL)
#define MMCR_MASK (0x000FFFFFUL)
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
#define MEC14xx_GIRQ08_ID (0)
#define MEC14xx_GIRQ09_ID (1)
#define MEC14xx_GIRQ10_ID (2)
#define MEC14xx_GIRQ11_ID (3)
#define MEC14xx_GIRQ12_ID (4)
#define MEC14xx_GIRQ13_ID (5)
#define MEC14xx_GIRQ14_ID (6)
#define MEC14xx_GIRQ15_ID (7)
#define MEC14xx_GIRQ16_ID (8)
#define MEC14xx_GIRQ17_ID (9)
#define MEC14xx_GIRQ18_ID (10)
#define MEC14xx_GIRQ19_ID (11)
#define MEC14xx_GIRQ20_ID (12)
#define MEC14xx_GIRQ21_ID (13)
#define MEC14xx_GIRQ22_ID (14)
#define MEC14xx_GIRQ23_ID (15)
#define MEC14xx_GIRQ24_ID (16)
#define MEC14xx_GIRQ25_ID (17)
#define MEC14xx_GIRQ26_ID (18)
#define MEC14xx_NUM_JTVIC_INTS (18+1)
// 4-bits per GIRQ source bit (only lower 2-bits used)
// 4 * 32 * 19 = 2432 bits -> 76 32-bit registers
#define MEC14xx_NUM_GIRQ_PRI_REGS ((MEC14xx_NUM_JTVIC_INTS) << 2)
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/*@}*/ /* end of group MEC14xx_DEFS */
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/** @addtogroup MEC14xx_Peripherals MEC14xx Peripherals
MEC14xx Device Specific Peripheral registers structures
@{
*/
/* Register Union */
typedef union
{
volatile uint32_t w;
volatile uint16_t h[2];
volatile uint8_t b[4];
} REG32_U;
typedef union
{
uint32_t w;
uint16_t hw[2];
uint8_t b[4];
} DATA32_U;
typedef struct buff8_s
{
uint32_t len;
uint8_t *pd;
} BUFF8_T;
typedef struct buff16_s
{
uint32_t len;
uint16_t *pd;
} BUFF16_T;
typedef struct buff32_s
{
uint32_t len;
uint32_t *pd;
} BUFF32_T;
#ifndef __IO
#define __IO volatile
#ifdef __cplusplus
#define __I volatile
#else
#define __I volatile const
#endif
#define __O volatile
#endif
/*---------!!!! M14K Closely Coupled Peripherals !!!!-----------------------*/
/*------------- Jump Table Interrupt Controller (JTVIC)------------------*/
/** @addtogroup JTVIC MEC14xx External Interrupt Controller (JTVIC)
@{
*/
typedef struct
{
__IO uint32_t SOURCE; /*!< Offset: 0x0000 Source RW1C */
__IO uint32_t EN_SET; /*!< Offset: 0x0004 Enable Set RW */
__IO uint32_t EN_CLR; /*!< Offset: 0x0008 Enable Clear RW */
__IO uint32_t RESULT; /*!< Offset: 0x000C Result RO */
} GIRQ_TypeDef;
typedef struct
{
__IO uint32_t REG32[MEC14xx_NUM_GIRQ_PRI_REGS];
uint8_t PAD[0x200ul - ((MEC14xx_NUM_GIRQ_PRI_REGS)<<2)];
} GIRQ_PRIORITY_TypeDef;
/*
* JTVIC GIRQ Sub-block size = 512 bytes (0x200)
* Pad structure to 512 bytes
*/
typedef struct
{
GIRQ_TypeDef REGS[MEC14xx_NUM_JTVIC_INTS];
uint8_t PAD[0x200ul-((MEC14xx_NUM_JTVIC_INTS)<<4)];
} JTVIC_GIRQ_REGS_TypeDef; // at CPP_BASE
/*
* JTVIC Aggregator Control Sub-block size = 256 bytes (0x100)
* Pad structure to 256 bytes
*/
typedef struct
{
__IO uint32_t REG32[MEC14xx_NUM_JTVIC_INTS];
uint8_t PAD[0x100ul-((MEC14xx_NUM_JTVIC_INTS)<<2)];
} JTVIC_AGG_CTRL_TypeDef; // at CCP_BASE+0x200
/*
* JTVIC Priority Sub-block size = 512 bytes (0x200)
* Pad structure to 512 bytes
*/
typedef struct
{
__IO uint32_t REG32[(MEC14xx_NUM_JTVIC_INTS)<<4];
uint8_t PAD[0x200ul-((MEC14xx_NUM_JTVIC_INTS)<<4)];
} JTVIC_PRIORITY_TypeDef; // at CPP_Base+0x300
typedef struct
{
GIRQ_TypeDef GIRQ[MEC14xx_NUM_JTVIC_INTS]; // CPP_BASE
uint8_t PADA[0x200ul-((MEC14xx_NUM_JTVIC_INTS)<<4)]; // 16 bytes/girq
__IO uint32_t AGG_CTRL[MEC14xx_NUM_JTVIC_INTS]; // CPP_BASE + 0x200
uint8_t PADB[0x100ul-((MEC14xx_NUM_JTVIC_INTS)<<2)]; // 4 bytes/girq
GIRQ_PRIORITY_TypeDef GIRQPRI[MEC14xx_NUM_GIRQ_PRI_REGS]; // CPP_BASE + 0x300
uint8_t PADC[0x200ul-((MEC14xx_NUM_JTVIC_INTS)<<4)]; // 16 bytes/girq
__IO uint32_t CONTROL; // CPP_BASE + 0x500
__IO uint32_t PENDING; // CPP_BASE + 0x504
__IO uint32_t GROUP_ENABLE_SET; // CPP_BASE + 0x508
__IO uint32_t GROUP_ENABLE_CLR; // CPP_BASE + 0x50c
__IO uint32_t GIRQ_ACTIVE; // CPP_BASE + 0x510
} JTVIC_TypeDef;
#define JTVIC_BASE (MEC14XX_CCP_VIRT_BASE)
#define JTVIC ((JTVIC_TypeDef *) JTVIC_BASE)
#define JTVIC_GIRQ ((JTVIC_GIRQ_REGS_TypeDef *)(JTVIC_BASE))
#define JTVIC_ACTRL ((JTVIC_AGG_CTRL_TypeDef *)(JTVIC_BASE + 0x200ul))
#define JTVIC_PRI ((GIRQ_PRIORITY_TypeDef *)(JTVIC_BASE + 0x300ul))
#define JTVIC_CTRL ((REG32_U *)(JTVIC_BASE + 0x500ul))
#define JTVIC_PEND ((REG32_U *)(JTVIC_BASE + 0x504ul))
#define JTVIC_GROUP_EN_SET ((REG32_U *)(JTVIC_BASE + 0x508ul))
#define JTVIC_GROUP_EN_CLR ((REG32_U *)(JTVIC_BASE + 0x50Cul))
#define JTVIC_GIRQ_ACTIVE ((REG32_U *)(JTVIC_BASE + 0x510ul))
/*@}*/ /* end of group JTVIC */
/*---------!!!! EC AHB Bus Segment !!!!---------------------------*/
/*------------- Watch Dog Timer (WDT) --------------------------*/
/** @addtogroup WDT MEC14xx Watch Dog Timer (WDT)
@{
*/
typedef struct
{
__IO uint16_t LOAD;
uint16_t RESERVEDA[1];
__IO uint8_t CONTROL;
uint8_t RESERVEDB[3];
__O uint8_t KICK;
uint8_t RESERVEDC[3];
__I uint16_t COUNT;
uint16_t RESERVEDD[1];
} WDT_TypeDef;
/*@}*/ /* end of group WDT */
/*------------- Basic Timer (TMR) -----------------------------*/
/** @addtogroup BTMR MEC14xx Basic Timer (TMR)
@{
*/
#define MEC14xx_NUM_BASIC_TIMERS (4)
typedef struct
{
__IO uint32_t COUNT; /*!< Offset: 0x0000 Timer Count Register */
__IO uint32_t PRELOAD; /*!< Offset: 0x0004 Timer Preload Register */
__IO uint8_t STATUS; /*!< Offset: 0x0008 Timer Status Register */
uint8_t RESERVEDC[3];
__IO uint8_t INTEN; /*!< Offset: 0x000C Timer Interrupt Enable Register */
uint8_t RESERVEDD[3];
__IO uint32_t CONTROL; /*!< Offset: 0x0010 Timer Control Register */
uint32_t RESERVEDE[3];
} BTMR_TypeDef;
typedef struct
{
BTMR_TypeDef BTimer[MEC14xx_NUM_BASIC_TIMERS];
} BTMRS_TypeDef;
/*@}*/ /* end of group BTMR */
/*------------- RTOS Timer (RTMR) -----------------------------*/
/** @addtogroup RTOS Timer (RTMR)
@{
*/
typedef struct
{
__IO uint32_t COUNT; /*!< Offset: 0x0000 Counter RO */
__IO uint32_t PRELOAD; /*!< Offset: 0x0004 Pre-Load */
__IO uint8_t CONTROL; /*!< Offset: 0x0008 Control */
uint8_t RESERVEDA[3];
} RTMR_TypeDef;
/*@}*/ /* end of group RTMR */
/*------------- Trace FIFO Data Port (TFDP) -----------------------------*/
/** @addtogroup TFDP Trace FIFO Data Port (TFDP)
@{
*/
typedef struct
{
__IO uint8_t DATA;
uint8_t RESERVEDA[3];
__IO uint8_t CONTROL;
uint8_t RESERVEDB[3];
} TFDP_TypeDef;
/*@}*/ /* end of group MEC14xx_TFDP */
/*------------- Breathing/Blinking LED (BBLED) -----------------------------*/
/** @addtogroup BBLED Breathing-Blinking LED (BBLED)
@{
*/
typedef struct
{
__IO uint32_t CONFIG;
__IO uint32_t LIMIT;
__IO uint32_t DELAY;
__IO uint32_t STEP;
__IO uint32_t INTERVAL;
} BBLED_TypeDef;
/*@}*/ /* end of group BBLED */
/*------------- VBAT Registers (VBATREGS) ---------------------------*/
/** @addtogroup PCR MEC14xx VBAT Register Block (VBATREGS)
@{
*/
typedef struct
{
__IO uint32_t POWER_FAIL_RESET; /*!< Offset: 0x0000 Power-Fail and Reset Status */
__IO uint32_t ATE_REG_CTRL; /*!< Offset: 0x0004 ATE Regulator Control Register */
__IO uint32_t CLOCK_ENABLE; /*!< Offset: 0x0008 Clock Enable */
uint32_t RESERVEDA[1];
__IO uint32_t ATE_TEST; /*!< Offset: 0x0010 ATE Test Register */
__IO uint32_t OSC_32K_TRIM; /*!< Offset: 0x0014 32KHz OSC trim */
__IO uint32_t VTR_ALT_CTRL; /*!< Offset: 0x0018 Alternate Function VTR Control */
__IO uint32_t OSC_TRIM_CTRL; /*!< Offset: 0x001C 32KHz Trim Control */
} VBATREGS_TypeDef;
/*@}*/ /* end of group VBATREGS */
/*------------- EC Subsystem (ECS) -----------------------------*/
/** @addtogroup ECS EC Subsystem (ECS)
@{
*/
typedef struct
{
__IO uint32_t JTAG_ENABLE; /*!< JTAG Enable */
} ECS_TypeDef;
/*@}*/ /* end of group MEC14xx_ECS */
/*----------!!!! Chip AHB Bus Segment !!!!-----------------------------*/
/*------------- Chip Power Control Reset (PCR) ------------------------*/
/** @addtogroup PCR MEC14xx Power Control Reset Block (PCR)
@{
*/
typedef struct
{
__IO uint32_t CHIP_SLEEP_EN; /*!< Offset: 0x0000 Chip sleep enable */
__IO uint32_t CHIP_CLOCK_REQ_STS; /*!< Offset: 0x0004 Chip Clocks required status */
__IO uint32_t EC_SLEEP_EN; /*!< Offset: 0x0008 EC Sleep enable */
__IO uint32_t EC_CLOCK_REQ_STS; /*!< Offset: 0x000C EC Clocks required status */
__IO uint32_t HOST_SLEEP_EN; /*!< Offset: 0x0010 Host Sleep enable */
__IO uint32_t HOST_CLOCK_REQ_STS; /*!< Offset: 0x0014 Host clocks required status */
__IO uint32_t SYSTEM_SLEEP_CNTRL; /*!< Offset: 0x0018 System Sleep control */
uint32_t RESERVEDA[1];
__IO uint32_t PROC_CLOCK_CNTRL; /*!< Offset: 0x0020 Processor clock control */
__IO uint32_t EC_SLEEP_EN2; /*!< Offset: 0x0024 EC Sleep Enable 2 */
__IO uint32_t EC_CLOCK_REQ_STS2; /*!< Offset: 0x0028 EC Clock Required 2 */
__IO uint32_t SLOW_CLOCK_CNTRL; /*!< Offset: 0x002C Slow clock control */
__IO uint32_t OSC_ID; /*!< Offset: 0x0030 Chip Oscillator ID, Read-Only */
__IO uint32_t CHIP_PWR_RST_STS; /*!< Offset: 0x0034 Chip Sub-system Power Reset Status */
__IO uint32_t CHIP_RESET_EN; /*!< Offset: 0x0038 Chip block resets */
__IO uint32_t HOST_RESET_EN; /*!< Offset: 0x003C Host block resets */
__IO uint32_t EC_RESET_EN; /*!< Offset: 0x0040 EC Block resets */
__IO uint32_t EC_RESET_EN2; /*!< Offset: 0x0044 EC Block resets 2 */
__IO uint32_t PWR_RST_CTRL; /*!< Offset: 0x0048 Power Reset Control */
} PCR_TypeDef;
/*@}*/ /* end of group PCR */
/*------------- General Purpose IO Pin Config (GPIO_CFG) -----------------------------*/
/** @addtogroup GPIO MEC14xx GPIO Pin Config (GPIO_CFG)
@{
*/
typedef struct
{
__IO uint16_t CONFIG;
__IO uint8_t ALT_OUT;
__I uint8_t PAD_IN;
} GPIO_CFG_TypeDef;
/*@}*/ /* end of group GPIO_CFG */
/*------------- General Purpose IO (GPIO) -----------------------------*/
/** @addtogroup GPIO MEC14xx GPIO (GPIO)
@{
*/
#define MEC14xx_NUM_GPIO_BANKS (4)
#define MEC14xx_NUM_GPIO_PINS ((MEC14xx_NUM_GPIO_BANKS) * 32)
typedef struct
{
GPIO_CFG_TypeDef PIN_CFG[MEC14xx_NUM_GPIO_PINS];
} GPIO_TypeDef;
typedef union
{
__IO uint32_t w;
GPIO_CFG_TypeDef s;
} GPIO_CTRL_REG_TypeDef;
typedef struct
{
GPIO_CTRL_REG_TypeDef REG[MEC14xx_NUM_GPIO_PINS];
} GPIO_CTRL_TypeDef;
typedef struct
{
__IO uint32_t PINS[MEC14xx_NUM_GPIO_BANKS];
} GPIO_PAROUT_TypeDef; /*!< Offset: 0x0280 GPIO Pins Parallel Output */
#define GPIO_PAR_000_037_IDX (0u)
#define GPIO_PAR_040_077_IDX (1u)
#define GPIO_PAR_100_137_IDX (2u)
#define GPIO_PAR_140_177_IDX (3u)
#define GPIO_LOCK_140_177_IDX (0u)
#define GPIO_LOCK_100_137_IDX (1u)
#define GPIO_LOCK_040_077_IDX (2u)
#define GPIO_LOCK_000_037_IDX (3u)
#define GPIO_LOCK_140_177_OFS ((GPIO_LOCK_140_177_IDX) << 2)
#define GPIO_LOCK_100_137_OFS ((GPIO_LOCK_100_137_IDX) << 2)
#define GPIO_LOCK_040_077_OFS ((GPIO_LOCK_040_077_IDX) << 2)
#define GPIO_LOCK_000_037_OFS ((GPIO_LOCK_000_037_IDX) << 2)
typedef struct
{
__IO uint32_t PINS[MEC14xx_NUM_GPIO_BANKS];
} GPIO_PARIN_TypeDef; /*!< Offset: 0x0300 GPIO Pins Parallel Input */
typedef struct
{
__IO uint32_t PINS[MEC14xx_NUM_GPIO_BANKS];
} GPIO_LOCK_Typedef; /*!< Offset: 0x03EC GPIO Pins Lock */
typedef struct
{
__IO uint32_t PINS[MEC14xx_NUM_GPIO_PINS];
} GPIO_DRVSTR_Typedef; /*!< Offset: 0x0500 GPIO Pins Lock */
/*@}*/ /* end of group GPIO */
/*@}*/ /* end of group MEC14xx_Peripherals */
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/** @addtogroup MEC14xx_MemoryMap MEC14xx Memory Mapping
@{
*/
/* Peripheral and SRAM base address */
#define MEC14xx_PERIPH_BASE (0xA0000000UL) /*!< (Peripheral) Base Address */
#define MEC14xx_SPB_PERIPH_BASE (0xA0080000UL) /*!< (Chip Subsystem SPB Peripheral) Base Address */
#define MEC14xx_HOST_PERIPH_BASE (0xA00F0000UL) /*!< (Host Peripheral) Base Address */
/* Peripheral memory map */
#define WDT_BASE ((MEC14xx_PERIPH_BASE) + 0x0400) /*!< (WDT ) Base */
#define BTMRS_BASE ((MEC14xx_PERIPH_BASE) + 0x0C00) /*!< (Basic Timers ) Base Address */
#define BTMR0_BASE ((MEC14xx_PERIPH_BASE) + 0x0C00) /*!< (Basic 16-bit timer 0 ) Base Address */
#define BTMR1_BASE ((MEC14xx_PERIPH_BASE) + 0x0C20) /*!< (Basic 16-bit timer 1 ) Base Address */
#define BTMR2_BASE ((MEC14xx_PERIPH_BASE) + 0x0C40) /*!< (Basic 16-bit timer 2 ) Base Address */
#define BTMR3_BASE ((MEC14xx_PERIPH_BASE) + 0x0C60) /*!< (Basic 16-bit timer 3 ) Base Address */
#define RTOS_TIMER_BASE ((MEC14xx_PERIPH_BASE) + 0x7400) /*!< (RTOS Timer) Base Address */
#define TFDP_BASE ((MEC14xx_PERIPH_BASE) + 0x8C00) /*!< (TFDP ) Base Address */
#define VBAT_REGS_BASE ((MEC14xx_PERIPH_BASE) + 0xA400) /*!< (PCR VBAT Regs ) Base Address */
#define VBAT_MEM_BASE ((MEC14xx_PERIPH_BASE) + 0xA800) /*!< (VBAT MEM ) Base Address */
#define LED0_BASE ((MEC14xx_PERIPH_BASE) + 0xB800) /*!< (LED0 ) Base Address */
#define LED1_BASE ((MEC14xx_PERIPH_BASE) + 0xB900) /*!< (LED1 ) Base Address */
#define LED2_BASE ((MEC14xx_PERIPH_BASE) + 0xBA00) /*!< (LED2 ) Base Address */
#define ECS_BASE ((MEC14xx_PERIPH_BASE) + 0xFC00) /*!< (ECS ) Base Address */
/* SPB Peripheral memory map */
#define PCR_BASE ((MEC14xx_SPB_PERIPH_BASE) + 0x0100) /*!< (PCR ) Base Address */
#define GPIO_BASE ((MEC14xx_SPB_PERIPH_BASE) + 0x1000) /*!< (GPIO ) Base Address */
#define GPIO_CTRL_BASE ((MEC14xx_SPB_PERIPH_BASE) + 0x1000)
#define GPIO_POUT_BASE ((MEC14xx_SPB_PERIPH_BASE) + 0x1280)
#define GPIO_PIN_BASE ((MEC14xx_SPB_PERIPH_BASE) + 0x1300)
#define GPIO_LOCK_BASE ((MEC14xx_SPB_PERIPH_BASE) + 0x13F0) /*!< (GPIO Lock Regis) Base Address */
#define GPIO_PCTRL2_BASE ((MEC14xx_SPB_PERIPH_BASE) + 0x1500) /*!< (GPIO Pin Ctrl 2) Base Address */
/*@}*/ /* end of group MEC14xx_MemoryMap */
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
/** @addtogroup MEC14xx_PeripheralDecl MEC14xx Peripheral Declaration
@{
*/
/* EC Bus Segment Devices */
#define WDT ((WDT_TypeDef *)(WDT_BASE))
#define RTOS_TIMER ((RTMR_TypeDef *)(RTOS_TIMER_BASE))
#define TFDP ((TFDP_TypeDef *)(TFDP_BASE))
#define VBAT_REGS ((VBATREGS_TypeDef *)(VBAT_REGS_BASE))
#define BBLED0 ((BBLED_TypeDef *)(LED0_BASE))
#define BBLED1 ((BBLED_TypeDef *)(LED1_BASE))
#define BBLED2 ((BBLED_TypeDef *)(LED2_BASE))
#define ECS ((ECS_TypeDef *)(ECS_BASE))
#define ECS_REG ((ECS_TypeDef *)(ECS_BASE + 0x20))
/* Chip Bus Segment Devices */
#define PCR ((PCR_TypeDef *)(PCR_BASE))
#define GPIO ((GPIO_TypeDef *)(GPIO_BASE))
#define GPIO_CTRL ((GPIO_CTRL_TypeDef *) (GPIO_BASE))
#define GPIO_PAROUT ((GPIO_PAROUT_TypeDef *)(GPIO_POUT_BASE))
#define GPIO_PARIN ((GPIO_PARIN_TypeDef *)(GPIO_PIN_BASE))
#define GPIO_LOCK ((GPIO_LOCK_Typedef *)(GPIO_LOCK_BASE))
#define GPIO_DRVSTR ((GPIO_DRVSTR_Typedef *)(GPIO_PCTRL2_BASE))
/*@}*/ /* end of group MEC14xx_PeripheralDecl */
/*@}*/ /* end of group MEC14xx_Definitions */
/*
* Convert MEC14xx MIPS M14K virtual address to physical
* Physical address is bits [31:29] = 000b
* [28:0] = virtual [28:0]
*/
#define sys_virt_to_phys(v) ( (uint32_t)(v) & 0x1FFFFFFFul )
/*
* Convert MEC14xx MIPS M14K physical address to virtual.
* Bit-wise OR bits[31:29] of physical with 101b
*/
#define sys_phys_to_virt(p) ( (uint32_t)(p) | 0xA0000000ul )
#ifdef __cplusplus
}
#endif
#endif /* MEC14XX_H */
/** @}
*/

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_bbled.h
*MEC14xx Blinking Breathing LED definitions
*/
/** @defgroup MEC14xx Peripherals LED
*/
#ifndef _MEC14XX_BBLED_H
#define _MEC14XX_BBLED_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define LED_NUM_BLOCKS (3)
#define LED_INSTANCE_OFFSET (0x100UL)
//
// LED Configuration Register
//
#define LED_CFG_CNTL_MASK (0x0003u)
#define LED_CFG_CNTL_LO (0x0000u)
#define LED_CFG_CNTL_BREATH (0x0001u)
#define LED_CFG_CNTL_BLINK (0x0002u)
#define LED_CFG_CNTL_HI (0x0003u)
#define LED_CFG_CLK_SRC_MCLK (0x0002u)
#define LED_CFG_CLK_SRC_32K (0x0000u)
#define LED_CFG_SYNC (0x0008u)
#define LED_CFG_PWM_COUNT_WIDTH_MASK (0x0030u)
#define LED_CFG_COUNT_WIDTH_8 (0x0000u)
#define LED_CFG_COUNT_WIDTH_7 (0x0010u)
#define LED_CFG_COUNT_WIDTH_6 (0x0020u)
#define LED_CFG_EN_UPDATE (0x0040u)
#define LED_CFG_RESET (0x0080u)
#define LED_CFG_WDT_PRELOAD_MASK (0xFF00u)
#define LED_CFG_WDT_PRELOAD_POR (0x1400u)
#define LED_CFG_SYMMETRY_EN (0x10000u)
//
// LED Limit Register
//
#define LED_LIMIT_MIN_BITPOS (0u)
#define LED_LIMIT_MIN_MASK (0xFFu)
#define LED_LIMIT_MAX_BITPOS (8u)
#define LED_LIMIT_MAX_MASK (0xFF00u)
//
// LED Delay Register
//
#define LED_DELAY_LOW_MASK (0x0000FFFu)
#define LED_DELAY_HIGH_MASK (0x0FFF000u)
#define LED_DELAY_HIGH_BITPOS (12u)
//
// LED Step Size Register
//
#define LED_STEP_FIELD_WIDTH (4u)
#define LED_STEP0_MASK (0x0000000Fu)
#define LED_STEP1_MASK (0x000000F0u)
#define LED_STEP2_MASK (0x00000F00u)
#define LED_STEP3_MASK (0x0000F000u)
#define LED_STEP4_MASK (0x000F0000u)
#define LED_STEP5_MASK (0x00F00000u)
#define LED_STEP6_MASK (0x0F000000u)
#define LED_STEP7_MASK (0xF0000000u)
//
// LED Update Register
//
#define LED_UPDATE_FIELD_WIDTH (4u)
#define LED_UPDATE0_MASK (0x0000000Fu)
#define LED_UPDATE1_MASK (0x000000F0u)
#define LED_UPDATE2_MASK (0x00000F00u)
#define LED_UPDATE3_MASK (0x0000F000u)
#define LED_UPDATE4_MASK (0x000F0000u)
#define LED_UPDATE5_MASK (0x00F00000u)
#define LED_UPDATE6_MASK (0x0F000000u)
#define LED_UPDATE7_MASK (0xF0000000u)
#define BLINK_0P5_HZ_DUTY_CYCLE (0x010ul)
#define BLINK_0P5_HZ_PRESCALE (0x0FFul)
#define BLINK_1_HZ_DUTY_CYCLE (0x020ul)
#define BLINK_1_HZ_PRESCALE (0x07Ful)
/*****************************************************************************
* BBLED API
*****************************************************************************/
#define LED0_ID (0x00u)
#define LED1_ID (0x01u)
#define LED2_ID (0x02u)
#define LED_ID_MAX (0x03u)
#define BLINK_0P5_HZ_DUTY_CYCLE (0x010ul)
#define BLINK_0P5_HZ_PRESCALE (0x0FFul)
#define BLINK_1_HZ_DUTY_CYCLE (0x020ul)
#define BLINK_1_HZ_PRESCALE (0x07Ful)
uint8_t led_get_gpio_num(uint8_t led_id);
void led_init(uint8_t led_id);
void led_sleep_en(uint8_t led_id, uint8_t sleep_en);
void led_reset(uint8_t led_id);
void led_mode_blink(uint8_t led_id,
uint8_t duty_cycle,
uint16_t prescale);
void led_out_high(uint8_t led_id);
void led_out_low(uint8_t led_id);
void led_out_toggle(uint8_t led_id);
#ifdef __cplusplus
}
#endif
#endif // #ifndef _MEC14XX_BBLED_H
/* end hw_led.h */
/** @}
*/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_girqm.h
*MEC14xx JTVIC Disaggregation Control Flags
*/
/** @defgroup MEC14xx interrupt
*/
/*
* This file is intended to be included in both C source and assembly language
* files. The assembly language C pre-processor cannot handle complex macros.
* Keep it simple!
*/
/* Include FreeRTOS configuration settings.
* These include porting layer switches affecting interrupt aggregation
* of GIRQ23 & GIRQ24
*/
#include "FreeRTOSConfig.h"
/*
* Set to 0 for Aggregated GIRQ
* Set to 1 for Dis-aggregated(Jump Table) GIRQ
*/
#define GIRQ08_DISAGG (0)
#define GIRQ09_DISAGG (0)
#define GIRQ10_DISAGG (0)
#define GIRQ11_DISAGG (0)
#define GIRQ12_DISAGG (0)
#define GIRQ13_DISAGG (0)
#define GIRQ14_DISAGG (0)
#define GIRQ15_DISAGG (0)
#define GIRQ16_DISAGG (0)
#define GIRQ17_DISAGG (0)
#define GIRQ18_DISAGG (0)
#define GIRQ19_DISAGG (0)
#define GIRQ20_DISAGG (0)
#define GIRQ21_DISAGG (0)
#define GIRQ22_DISAGG (0)
#if configTIMERS_DISAGGREGATED_ISRS == 0
#define GIRQ23_DISAGG (0)
#else
#define GIRQ23_DISAGG (1)
#endif
#if configCPU_DISAGGREGATED_ISRS == 0
#define GIRQ24_DISAGG (0)
#else
#define GIRQ24_DISAGG (1)
#endif
#define GIRQ25_DISAGG (0)
#define GIRQ26_DISAGG (0)
/*
* Aggregated/Dis-aggrated bit-map
*/
#define JTVIC_DISAGR_BITMAP ( ((GIRQ08_DISAGG)<<0) + \
((GIRQ09_DISAGG)<<1) + ((GIRQ10_DISAGG)<<2) + \
((GIRQ11_DISAGG)<<3) + ((GIRQ12_DISAGG)<<4) + \
((GIRQ13_DISAGG)<<5) + ((GIRQ14_DISAGG)<<6) + \
((GIRQ15_DISAGG)<<7) + ((GIRQ16_DISAGG)<<8) + \
((GIRQ17_DISAGG)<<9) + ((GIRQ18_DISAGG)<<10) + \
((GIRQ19_DISAGG)<<11) + ((GIRQ20_DISAGG)<<12) + \
((GIRQ21_DISAGG)<<13) + ((GIRQ22_DISAGG)<<14) + \
((GIRQ23_DISAGG)<<15) + ((GIRQ24_DISAGG)<<16) + \
((GIRQ25_DISAGG)<<17) + ((GIRQ26_DISAGG)<<18) )
#define GIRQ08_NUM_SOURCES (23)
#define GIRQ08_SRC_MASK (0x007FFFFFul)
#define GIRQ09_NUM_SOURCES (31)
#define GIRQ09_SRC_MASK (0x7FFFFFFFul)
#define GIRQ10_NUM_SOURCES (24)
#define GIRQ10_SRC_MASK (0x00FFFFFFul)
#define GIRQ11_NUM_SOURCES (30)
#define GIRQ11_SRC_MASK (0x7FFFFFFEul)
#define GIRQ12_NUM_SOURCES (3)
#define GIRQ12_SRC_MASK (0x00000007ul)
#define GIRQ13_NUM_SOURCES (7)
#define GIRQ13_SRC_MASK (0x0000007Ful)
#define GIRQ14_NUM_SOURCES (6)
#define GIRQ14_SRC_MASK (0x0000003Ful)
#define GIRQ15_NUM_SOURCES (19)
#define GIRQ15_SRC_MASK (0x0007FFFFul)
#define GIRQ16_NUM_SOURCES (10)
#define GIRQ16_SRC_MASK (0x000003FFul)
#define GIRQ17_NUM_SOURCES (11)
#define GIRQ17_SRC_MASK (0x000007FFul)
#define GIRQ18_NUM_SOURCES (1)
#define GIRQ18_SRC_MASK (0x00000001ul)
#define GIRQ19_NUM_SOURCES (9)
#define GIRQ19_SRC_MASK (0x000001FFul)
#define GIRQ20_NUM_SOURCES (6)
#define GIRQ20_SRC_MASK (0x0000003Ful)
#define GIRQ21_NUM_SOURCES (3)
#define GIRQ21_SRC_MASK (0x00000007ul)
#define GIRQ22_NUM_SOURCES (10)
#define GIRQ22_SRC_MASK (0x000003FFul)
#define GIRQ23_NUM_SOURCES (14)
#define GIRQ23_SRC_MASK (0x00003FFFul)
#define GIRQ24_NUM_SOURCES (3)
#define GIRQ24_SRC_MASK (0x00000007ul)
#define GIRQ25_NUM_SOURCES (28)
#define GIRQ25_SRC_MASK (0x0FFFFFFFul)
#define GIRQ26_NUM_SOURCES (12)
#define GIRQ26_SRC_MASK (0x00000FFFul)
/** @}
*/

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_gpio.h
*MEC14xx GPIO definitions
*/
/** @defgroup MEC14xx Peripherals GPIO
*/
#ifndef _MEC14XX_GPIO_H
#define _MEC14XX_GPIO_H
#include <stdint.h>
#include "mec14xx.h"
#ifdef __cplusplus
extern "C" {
#endif
#define NUM_GPIO_PORTS (MEC14xx_NUM_GPIO_BANKS)
#define MAX_NUM_GPIO (NUM_GPIO_PORTS * 32)
#define GPIO_PORT_A_BITMAP (0x7FFFFFFFul) // GPIO_0000 to GPIO_0037
#define GPIO_PORT_B_BITMAP (0x00FFFFFFul) // GPIO_0040 to GPIO_0077
#define GPIO_PORT_C_BITMAP (0x7FFFFFFFul) // GPIO_0100 to GPIO_0137
#define GPIO_PORT_D_BITMAP (0x7FFFFFFFul) // GPIO_0140 to GPIO_0177
#define GPIO_PORT_A_DRVSTR_BITMAP (0x7FFFFFFEul)
#define GPIO_PORT_B_DRVSTR_BITMAP (0x006FFFFFul)
#define GPIO_PORT_C_DRVSTR_BITMAP (0x7FFFFFFFul)
#define GPIO_PORT_D_DRVSTR_BITMAP (0x007FFFFFul)
//
// Control
//
#define GPIO_CTRL_RSVD_MASK (0xFEFEC000UL)
//
#define GPIO_PUD_BITPOS (0)
#define GPIO_PUD_BLEN (2)
#define GPIO_PUD_MASK (0x03UL << (GPIO_PUD_BITPOS))
#define GPIO_PUD_NONE (0x00)
#define GPIO_PUD_PU (0x01)
#define GPIO_PUD_PD (0x02)
#define GPIO_PUD_NONE2 (0x03)
//
#define GPIO_PWRG_BITPOS (2)
#define GPIO_PWRG_BLEN (2)
#define GPIO_PWRG_MASK (0x03UL << (GPIO_PWRG_BITPOS))
#define GPIO_PWRG_V3_S5 (0x00UL << (GPIO_PWRG_BITPOS))
#define GPIO_PWRG_VCC_MAIN (0x01UL << (GPIO_PWRG_BITPOS))
#define GPIO_PWRG_V3_DUAL (0x02UL << (GPIO_PWRG_BITPOS))
#define GPIO_PWRG_UNPWRD (0x03UL << (GPIO_PWRG_BITPOS))
//
#define GPIO_INTDET_BITPOS (4)
#define GPIO_INTDET_BLEN (4)
#define GPIO_INTDET_MASK (0x0FUL << (GPIO_INTDET_BITPOS))
#define GPIO_INTDET_LVL_LOW (0x00UL << (GPIO_INTDET_BITPOS))
#define GPIO_INTDET_LVL_HI (0x01UL << (GPIO_INTDET_BITPOS))
#define GPIO_INTDET_DISABLE (0x04UL << (GPIO_INTDET_BITPOS))
#define GPIO_INTDET_RISE_EDG (0x0DUL << (GPIO_INTDET_BITPOS))
#define GPIO_INTDET_FALL_EDG (0x0EUL << (GPIO_INTDET_BITPOS))
#define GPIO_INTDET_BOTH_EDG (0x0FUL << (GPIO_INTDET_BITPOS))
//
#define GPIO_BUFFTYPE_BITPOS (8)
#define GPIO_BUFFTYPE_BLEN (1)
#define GPIO_BUFFTYPE_PUSHPULL (0x00UL << (GPIO_BUFFTYPE_BITPOS))
#define GPIO_BUFFTYPE_OPENDRAIN (0x01UL << (GPIO_BUFFTYPE_BITPOS))
//
#define GPIO_DIR_BITPOS (9)
#define GPIO_DIR_BLEN (1)
#define GPIO_DIR_MASK (0x01UL << (GPIO_DIR_BITPOS))
#define GPIO_DIR_INPUT (0x00UL << (GPIO_DIR_BITPOS))
#define GPIO_DIR_OUTPUT (0x01UL << (GPIO_DIR_BITPOS))
//
#define GPIO_PARWEN_BITPOS (10)
#define GPIO_PARWEN_BLEN (1)
#define GPIO_PARWEN_DIS (0x00UL << (GPIO_PARWEN_BITPOS))
#define GPIO_PARWEN_EN (0x01UL << (GPIO_PARWEN_BITPOS))
//
#define GPIO_POLARITY_BITPOS (11)
#define GPIO_POLARITY_BLEN (1)
#define GPIO_POLARITY_NON_INV (0x00UL << (GPIO_POLARITY_BITPOS))
#define GPIO_POLARITY_INV (0x01UL << (GPIO_POLARITY_BITPOS))
//
#define GPIO_MUX_BITPOS (12)
#define GPIO_MUX_BLEN (2)
#define GPIO_MUX_MASK (0x0FUL << (GPIO_MUX_BITPOS))
#define GPIO_MUX_GPIO (0x00UL << (GPIO_MUX_BITPOS))
#define GPIO_MUX_FUNC1 (0x01UL << (GPIO_MUX_BITPOS))
#define GPIO_MUX_FUNC2 (0x02UL << (GPIO_MUX_BITPOS))
#define GPIO_MUX_FUNC3 (0x03UL << (GPIO_MUX_BITPOS))
//
#define GPIO_OUTPUT_BITPOS (16)
#define GPIO_OUTPUT_BLEN (1)
#define GPIO_OUTPUT_0 (0x00UL << (GPIO_OUTPUT_BITPOS))
#define GPIO_OUTPUT_1 (0x01UL << (GPIO_OUTPUT_BITPOS))
#define GP_OUTPUT_0 (0x00UL) // Byte or Bit-banding usage
#define GP_OUTPUT_1 (0x01UL)
//
#define GPIO_PADIN_BITPOS (24)
#define GPIO_PADIN_BLEN (1)
#define GPIO_PADIN_LOW (0x00UL << (GPIO_PADIN_BITPOS))
#define GPIO_PADIN_HI (0x01UL << (GPIO_PADIN_BITPOS))
#define GP_PADIN_LO (0x00UL) // Byte or Bit-banding usage
#define GP_PADIN_HI (0x01UL)
#define GPIO_PIN_LOW (0UL)
#define GPIO_PIN_HIGH (1UL)
//
// Drive Strength
// For GPIO pins that implement drive strength each pin
// has a 32-bit register containing bit fields for
// slew rate and buffer current strength
//
#define GPIO_DRV_STR_OFFSET (0x0500ul)
#define GPIO_DRV_SLEW_BITPOS (0ul)
#define GPIO_DRV_SLEW_MASK (1ul << GPIO_DRV_SLEW_BITPOS)
#define GPIO_DRV_SLEW_SLOW (0ul << GPIO_DRV_SLEW_BITPOS)
#define GPIO_DRV_SLEW_FAST (1ul << GPIO_DRV_SLEW_BITPOS)
#define GPIO_DRV_STR_BITPOS (4ul)
#define GPIO_DRV_STR_LEN (2ul)
#define GPIO_DRV_STR_MASK (0x03ul << GPIO_DRV_STR_BITPOS)
#define GPIO_DRV_STR_2MA (0ul << GPIO_DRV_STR_BITPOS)
#define GPIO_DRV_STR_4MA (1ul << GPIO_DRV_STR_BITPOS)
#define GPIO_DRV_STR_8MA (2ul << GPIO_DRV_STR_BITPOS)
#define GPIO_DRV_STR_12MA (3ul << GPIO_DRV_STR_BITPOS)
/*****************************************************************************
* GPIO API
****************************************************************************/
#define GPIO_PORTA (0u)
#define GPIO_PORTB (1u)
#define GPIO_PORTC (2u)
#define GPIO_PORTD (3u)
#define GPIO_PORTE (4u)
#define GPIO_MAX_PORT (5u)
/*
* GPIO Functionality
*/
typedef enum gpio_id_t
{
GPIO_0000_ID, // 00h: Begin Port A
GPIO_0001_ID,
GPIO_0002_ID,
GPIO_0003_ID,
GPIO_0004_ID,
GPIO_0005_ID,
GPIO_0006_ID,
GPIO_0007_ID,
//
GPIO_0010_ID, // 08h
GPIO_0011_ID,
GPIO_0012_ID,
GPIO_0013_ID,
GPIO_0014_ID,
GPIO_0015_ID,
GPIO_0016_ID,
GPIO_0017_ID,
//
GPIO_0020_ID, // 10h
GPIO_0021_ID,
GPIO_0022_ID,
GPIO_0023_ID,
GPIO_0024_ID,
GPIO_0025_ID,
GPIO_0026_ID,
GPIO_0027_ID,
//
GPIO_0030_ID, // 18h
GPIO_0031_ID,
GPIO_0032_ID,
GPIO_0033_ID,
GPIO_0034_ID,
GPIO_0035_ID,
GPIO_0036_ID,
GPIO_0037_ID, // End Port A
//
GPIO_0040_ID, // 20h: Begin Port B
GPIO_0041_ID,
GPIO_0042_ID,
GPIO_0043_ID,
GPIO_0044_ID,
GPIO_0045_ID,
GPIO_0046_ID,
GPIO_0047_ID,
//
GPIO_0050_ID, // 28h
GPIO_0051_ID,
GPIO_0052_ID,
GPIO_0053_ID,
GPIO_0054_ID,
GPIO_0055_ID,
GPIO_0056_ID,
GPIO_0057_ID,
//
GPIO_0060_ID, // 30h
GPIO_0061_ID,
GPIO_0062_ID,
GPIO_0063_ID,
GPIO_0064_ID,
GPIO_0065_ID,
GPIO_0066_ID,
GPIO_0067_ID,
//
GPIO_0070_ID, // 38h
GPIO_0071_ID,
GPIO_0072_ID,
GPIO_0073_ID,
GPIO_0074_ID,
GPIO_0075_ID,
GPIO_0076_ID,
GPIO_0077_ID, // End Port B
//
GPIO_0100_ID, // 40h: Begin Port C
GPIO_0101_ID,
GPIO_0102_ID,
GPIO_0103_ID,
GPIO_0104_ID,
GPIO_0105_ID,
GPIO_0106_ID,
GPIO_0107_ID,
//
GPIO_0110_ID, // 48h
GPIO_0111_ID,
GPIO_0112_ID,
GPIO_0113_ID,
GPIO_0114_ID,
GPIO_0115_ID,
GPIO_0116_ID,
GPIO_0117_ID,
//
GPIO_0120_ID, // 50h
GPIO_0121_ID,
GPIO_0122_ID,
GPIO_0123_ID,
GPIO_0124_ID,
GPIO_0125_ID,
GPIO_0126_ID,
GPIO_0127_ID,
//
GPIO_0130_ID, // 58h
GPIO_0131_ID,
GPIO_0132_ID,
GPIO_0133_ID,
GPIO_0134_ID,
GPIO_0135_ID,
GPIO_0136_ID,
GPIO_0137_ID, // End Port C
//
GPIO_0140_ID, // 60h: Begin Port D
GPIO_0141_ID,
GPIO_0142_ID,
GPIO_0143_ID,
GPIO_0144_ID,
GPIO_0145_ID,
GPIO_0146_ID,
GPIO_0147_ID,
//
GPIO_0150_ID, // 68h
GPIO_0151_ID,
GPIO_0152_ID,
GPIO_0153_ID,
GPIO_0154_ID,
GPIO_0155_ID,
GPIO_0156_ID,
GPIO_0157_ID,
//
GPIO_0160_ID, // 70h
GPIO_0161_ID,
GPIO_0162_ID,
GPIO_0163_ID,
GPIO_0164_ID,
GPIO_0165_ID,
GPIO_0166_ID,
GPIO_0167_ID,
//
MAX_GPIO_ID
} GPIO_ID;
enum gpio_prop_t
{
GPIO_PROP_PU_PD,
GPIO_PROP_PWR_GATE,
GPIO_PROP_INT_DET,
GPIO_PROP_OBUFF_TYPE,
GPIO_PROP_DIR,
GPIO_PROP_ALT_OUT_EN,
GPIO_PROP_POLARITY,
GPIO_PROP_MUX_SEL,
GPIO_PROP_ALL,
GPIO_PROP_MAX
};
enum gpio_pupd_t
{
GPIO_PUPD_NONE,
GPIO_PULLUP_EN,
GPIO_PULLDN_EN,
GPIO_PUPD_NONE2
};
enum gpio_idetect_t
{
GPIO_DET_LEVEL_LOW,
GPIO_DET_LEVEL_HIGH,
GPIO_DET_RSVD2,
GPIO_DET_RSVD3,
GPIO_DET_DISABLE,
GPIO_DET_RSVD5,
GPIO_DET_RSVD6,
GPIO_DET_RSVD7,
GPIO_DET_RSVD8,
GPIO_DET_RSVD9,
GPIO_DET_RSVDA,
GPIO_DET_RSVDB,
GPIO_DET_RSVDC,
GPIO_DET_RISING_EDGE,
GPIO_DET_FALLING_EDGE,
GPIO_DET_BOTH_EDGES
};
enum gpio_buff_type_t
{
GPIO_OUT_BUFF_PUSH_PULL,
GPIO_OUT_BUFF_OPEN_DRAIN
};
enum gpio_dir_t
{
GPIO_DIR_IN,
GPIO_DIR_OUT
};
enum gpio_polarity_t
{
GPIO_NON_INVERT,
GPIO_INVERT
};
enum gpio_mux_t
{
GPIO_FUNC_GPIO,
GPIO_FUNC_1,
GPIO_FUNC_2,
GPIO_FUNC_3
};
// Slew Rate & Drive Strength
enum gpio_slew_rate_t
{
GPIO_SLEW_SLOW,
GPIO_SLEW_FAST
};
enum gpio_drv_str_t
{
GPIO_DRV_2MA = 0,
GPIO_DRV_4MA,
GPIO_DRV_8MA,
GPIO_DRV_12MA
};
uint16_t GPIOGetConfig(enum gpio_id_t gpio_id);
void GPIOSetConfig(enum gpio_id_t gpio_id, uint16_t config);
void GPIOConfigAndOr(enum gpio_id_t gpio_id, uint16_t and_mask, uint16_t or_mask);
uint32_t GPIOGetControl(enum gpio_id_t gpio_id);
void GPIOSetControl(enum gpio_id_t gpio_id, uint32_t ctrl_val);
void GPIOControlAndOr(enum gpio_id_t gpio_id, uint32_t and_mask, uint32_t or_mask);
void GPIOPropertySet ( enum gpio_id_t gpio_id,
enum gpio_prop_t gpio_prop,
uint16_t prop_val
);
uint8_t GPIOGetSlewRate( enum gpio_id_t gpio_id );
void GPIOSetSlewRate ( enum gpio_id_t gpio_id,
enum gpio_slew_rate_t slew_rate );
uint8_t GPIOGetDriveStr ( enum gpio_id_t gpio_id );
void GPIOSetDriveStr ( enum gpio_id_t gpio_id,
enum gpio_drv_str_t drv_str );
uint8_t GPIOGetDriveStrAndSlew ( enum gpio_id_t gpio_id );
void GPIOSetDriveStrAndSlew ( enum gpio_id_t gpio_id,
uint8_t drv_and_slew );
void GPIOSetOutput ( enum gpio_id_t gpio_id,
uint8_t gpio_state
);
void GPIOToggleOutput ( enum gpio_id_t gpio_id );
uint8_t GPIOReadPin( enum gpio_id_t gpio_id );
void GPIOPinLock(enum gpio_id_t gpio_id);
#ifdef __cplusplus
}
#endif
#endif // #ifndef _MEC14XX_GPIO_H
/* end mec14XX_gpio.h */
/** @}
*/

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_jtvic.h
*MEC14xx JTVIC HW defines
*/
/** @defgroup MEC14xx Peripherals JTVIC
*/
#ifndef _MEC14XX_JTVIC_H
#define _MEC14XX_JTVIC_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define JTVIC_PRI1 0
#define JTVIC_PRI3 1
#define JTVIC_PRI5 2
#define JTVIC_PRI7 3
/* Each JTVIC GIRQx has 4 32-bit priority registers where each nibble
* encodes one of four priorities.
* Generate JTVIC GIRQx Priority Register value for field number b with
* priority p
* b is the field [0,7]
* p is the priority 0=IPL1, 1=IPL3, 2=IPL5, 3=IPL7
*/
#define JTVIC_PRI_VAL(b,p) ((uint32_t)((p) & 0x03) << (((b) & 0x07) << 2))
#define JTVIC_GIRQ_NPRI_REGS (4)
typedef struct {
uint32_t isr_addr;
uint32_t pri[JTVIC_GIRQ_NPRI_REGS];
} JTVIC_CFG;
#define JTVIC_FLAG_DISAGR_SPACING_8 (0)
#define JTVIC_FLAG_DISAGR_SPACING_512 (1ul << 0)
#define JTVIC_NO_CLR_SRC (0)
#define JTVIC_CLR_SRC (1)
void jtvic_init(const JTVIC_CFG *ih_table, uint32_t disagg_bitmap, uint32_t cflags);
void jtvic_clr_source(uint8_t girq_num, uint8_t bit_num);
void jtvic_dis_clr_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src);
void jtvic_en_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src);
#ifdef __cplusplus
}
#endif
#endif // #ifndef _MEC14XX_JTVIC_H
/* end mec14XX_jtvic.h */
/** @}
*/

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_pcr.h
*MEC14xx Power Control Reset definitions
*/
/** @defgroup MEC14xx Peripherals PCR
*/
#ifndef _MEC14XX_PCR_H
#define _MEC14XX_PCR_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define PCR_SLEEP_EN (1u)
#define PCR_SLEEP_DIS (0u)
//
// VTR Powered PCR registers
//
//
// Chip Sleep Enable Reg (Offset +00h)
// Chip Clock Required Status Reg (Offset +04h)
//
#define PCR_CHIP_SLP_EN_OFFSET (0ul)
#define PCR_CHIP_SLP_EN_MASK (0x03ul)
#define PCR_CHIP_STAP_BITPOS (0)
#define PCR_CHIP_EFUSE_BITPOS (1)
#define PCR_CHIP_CLK_REQ_OFFSET (0x04ul)
#define PCR_CHIP_CLK_REQ_MASK (0x03ul)
//
#define PCR_CHIP_STAP_SLP_CLK (1ul << (PCR_CHIP_STAP_BITPOS))
#define PCR_CHIP_EFUSE_SLP_CLK (1ul << (PCR_CHIP_EFUSE_BITPOS))
//
#define PCR_CHIP_STAP_NOSLP_CLK (0ul)
#define PCR_CHIP_EFUSE_NOSLP_CLK (0ul)
//
// EC Sleep Enable Reg (Offset +08h)
// EC Clock Required Status Reg (Offset +0Ch)
//
#define PCR_EC_SLP_EN_OFFSET (0x08ul)
#define PCR_EC_SLP_EN_MASK (0xE7F00FF7ul)
#define PCR_EC_CLK_REQ_OFFSET (0x0Cul)
#define PCR_EC_CLK_REQ_MASK (0xE7F00FF7ul)
//
#define PCR_EC_INT_SLP_BITPOS (0)
#define PCR_EC_PECI_SLP_BITPOS (1)
#define PCR_EC_TACH0_SLP_BITPOS (2)
// bit[3] Reserved
#define PCR_EC_PWM0_SLP_BITPOS (4)
#define PCR_EC_PMC_SLP_BITPOS (5)
#define PCR_EC_DMA_SLP_BITPOS (6)
#define PCR_EC_TFDP_SLP_BITPOS (7)
#define PCR_EC_CPU_SLP_BITPOS (8)
#define PCR_EC_WDT_SLP_BITPOS (9)
#define PCR_EC_SMB0_SLP_BITPOS (10)
#define PCR_EC_TACH1_SLP_BITPOS (11)
// bits[19:12] Rerserved
#define PCR_EC_PWM1_SLP_BITPOS (20)
#define PCR_EC_PWM2_SLP_BITPOS (21)
#define PCR_EC_PWM3_SLP_BITPOS (22)
#define PCR_EC_PWM4_SLP_BITPOS (23)
#define PCR_EC_PWM5_SLP_BITPOS (24)
#define PCR_EC_PWM6_SLP_BITPOS (25)
#define PCR_EC_PWM7_SLP_BITPOS (26)
// bits[28:17] Reserved
#define PCR_EC_REG_SLP_BITPOS (29)
#define PCR_EC_TIMER0_SLP_BITPOS (30)
#define PCR_EC_TIMER1_SLP_BITPOS (31)
//
#define PCR_EC_INT_SLP_CLK (1ul << (PCR_EC_INT_SLP_BITPOS))
#define PCR_EC_PECI_SLP_CLK (1ul << (PCR_EC_PECI_SLP_BITPOS))
#define PCR_EC_TACH0_SLP_CLK (1ul << PCR_EC_TACH0_SLP_BITPOS))
// bit[3] Reserved
#define PCR_EC_PWM0_SLP_CLK (1ul << (PCR_EC_PWM0_SLP_BITPOS))
#define PCR_EC_PMC_SLP_CLK (1ul << (PCR_EC_PMC_SLP_BITPOS))
#define PCR_EC_DMA_SLP_CLK (1ul << (PCR_EC_DMA_SLP_BITPOS))
#define PCR_EC_TFDP_SLP_CLK (1ul << (PCR_EC_TFDP_SLP_BITPOS))
#define PCR_EC_CPU_SLP_CLK (1ul << (PCR_EC_CPU_SLP_BITPOS))
#define PCR_EC_WDT_SLP_CLK (1ul << (PCR_EC_WDT_SLP_BITPOS))
#define PCR_EC_SMB0_SLP_CLK (1ul << (PCR_EC_SMB0_SLP_BITPOS))
#define PCR_EC_TACH1_SLP_CLK (1ul << (PCR_EC_TACH1_SLP_BITPOS))
// bits[19:12] Rerserved
#define PCR_EC_PWM1_SLP_CLK (1ul << (PCR_EC_PWM1_SLP_BITPOS))
#define PCR_EC_PWM2_SLP_CLK (1ul << (PCR_EC_PWM2_SLP_BITPOS))
#define PCR_EC_PWM3_SLP_CLK (1ul << (PCR_EC_PWM3_SLP_BITPOS))
#define PCR_EC_PWM4_SLP_CLK (1ul << (PCR_EC_PWM4_SLP_BITPOS))
#define PCR_EC_PWM5_SLP_CLK (1ul << (PCR_EC_PWM5_SLP_BITPOS))
#define PCR_EC_PWM6_SLP_CLK (1ul << (PCR_EC_PWM6_SLP_BITPOS))
#define PCR_EC_PWM7_SLP_CLK (1ul << (PCR_EC_PWM7_SLP_BITPOS))
// bits[28:17] Reserved
#define PCR_EC_REG_SLP_CLK (1ul << (PCR_EC_REG_SLP_BITPOS))
#define PCR_EC_TIMER0_SLP_CLK (1ul << (PCR_EC_TIMER0_SLP_BITPOS))
#define PCR_EC_TIMER1_SLP_CLK (1ul << (PCR_EC_TIMER1_SLP_BITPOS))
//
// Host Sleep Enable Reg (Offset +10h)
// Host Clock Required Status Reg (Offset +14h)
//
#define PCR_HOST_SLP_EN_OFFSET (0x10UL)
#define PCR_HOST_SLP_EN_MASK (0x001BFC0Ful)
#define PCR_HOST_CLK_REQ_OFFSET (0x14UL)
#define PCR_HOST_CLK_REQ_MASK (0x001BFC0Ful)
//
#define PCR_HOST_LPC_SLP_BITPOS (0)
#define PCR_HOST_UART0_SLP_BITPOS (1)
#define PCR_HOST_P80A_SLP_BITPOS (2)
#define PCR_HOST_P80B_SLP_BITPOS (3)
// b[9:4] Reserved
#define PCR_HOST_ACPI_EC2_SLP_BITPOS (10)
#define PCR_HOST_ACPI_EC3_SLP_BITPOS (11)
#define PCR_HOST_GLBL_CFG_SLP_BITPOS (12)
#define PCR_HOST_APCI_EC0_SLP_BITPOS (13)
#define PCR_HOST_APCI_EC1_SLP_BITPOS (14)
#define PCR_HOST_APCI_PM1_SLP_BITPOS (15)
#define PCR_HOST_MIF8042_SLP_BITPOS (16)
#define PCR_HOST_MBOX_SLP_BITPOS (17)
// b[18] Reserved
#define PCR_HOST_ESPI_SLP_BITPOS (19)
#define PCR_HOST_TSCR_SLP_BITPOS (20)
// b[31:12] Reserved
//
#define PCR_HOST_LPC_SLP_CLK (1UL<<(PCR_HOST_LPC_SLP_BITPOS))
#define PCR_HOST_UART0_SLP_CLK (1UL<<(PCR_HOST_UART0_SLP_BITPOS))
#define PCR_HOST_P80A_SLP_CLK (1UL<<(PCR_HOST_P80A_SLP_BITPOS))
#define PCR_HOST_P80B_SLP_CLK (1UL<<(PCR_HOST_P80B_SLP_BITPOS))
#define PCR_HOST_ACPI_EC2_SLP_CLK (1UL<<(PCR_HOST_ACPI_EC2_SLP_BITPOS))
#define PCR_HOST_ACPI_EC3_SLP_CLK (1UL<<(PCR_HOST_ACPI_EC3_SLP_BITPOS))
#define PCR_HOST_GLBL_CFG_SLP_CLK (1UL<<(PCR_HOST_GLBL_CFG_SLP_BITPOS))
#define PCR_HOST_APCI_EC0_SLP_CLK (1UL<<(PCR_HOST_APCI_EC0_SLP_BITPOS))
#define PCR_HOST_APCI_EC1_SLP_CLK (1UL<<(PCR_HOST_APCI_EC1_SLP_BITPOS))
#define PCR_HOST_APCI_PM1_SLP_CLK (1UL<<(PCR_HOST_APCI_PM1_SLP_BITPOS))
#define PCR_HOST_MIF8042_SLP_CLK (1UL<<(PCR_HOST_MIF8042_SLP_BITPOS))
#define PCR_HOST_MBOX_SLP_CLK (1UL<<(PCR_HOST_MBOX_SLP_BITPOS))
#define PCR_HOST_ESPI_SLP_CLK (1UL<<(PCR_HOST_ESPI_SLP_BITPOS))
#define PCR_HOST_TSCR_SLP_CLK (1UL<<(PCR_HOST_TSCR_SLP_BITPOS))
//
#define PCR_HOST_LPC_NOSLP_CLK (0)
#define PCR_HOST_UART0_NOSLP_CLK (0)
#define PCR_HOST_P80A_NOSLP_CLK (0)
#define PCR_HOST_P80B_NOSLP_CLK (0)
#define PCR_HOST_ACPI_EC2_NOSLP_CLK (0)
#define PCR_HOST_ACPI_EC3_NOSLP_CLK (0)
#define PCR_HOST_GLBL_CFG_NOSLP_CLK (0)
#define PCR_HOST_APIC_EC0_NOSLP_CLK (0)
#define PCR_HOST_APIC_EC1_NOSLP_CLK (0)
#define PCR_HOST_APIC_PM1_NOSLP_CLK (0)
#define PCR_HOST_MIF8042_NOSLP_CLK (0)
#define PCR_HOST_MBOX_NOSLP_CLK (0)
#define PCR_HOST_ESPI_NOSLP_CLK (0)
#define PCR_HOST_TSCR_NOSLP_CLK (0)
//
// System Sleep Control Reg (Offset +18h)
//
#define PCR_SYS_SLP_CTRL_OFFSET (0x18ul)
#define PCR_SYS_SLP_CTRL_MASK (0x77ul)
#define PCR_SYS_SLP_ROSC_PD_BITPOS (0u)
#define PCR_SYS_SLP_ROSC_GATE_BITPOS (1u)
#define PCR_SYS_SLP_CORE_VREG_STDBY_BITPOS (2u)
#define PCR_SYS_SLP_ALL_BITPOS (4u)
#define PCR_SYS_SLP_DBG_BITPOS (5u)
#define PCR_SYS_SLP_AUTO_CLR_BITPOS (6u)
#define PCR_SYS_SLP_ROSC_PD (1ul<<(PCR_SYS_SLP_ROSC_PD_BITPOS))
#define PCR_SYS_SLP_ROSC_GATE (1ul<<(PCR_SYS_SLP_ROSC_GATE_BITPOS))
#define PCR_SYS_SLP_CORE_VREG_STDBY (1ul<<(PCR_SYS_SLP_CORE_VREG_STDBY_BITPOS))
#define PCR_SYS_SLP_ALL (1ul<<(PCR_SYS_SLP_ALL_BITPOS))
#define PCR_SYS_SLP_DBG (1ul<<(PCR_SYS_SLP_DBG_BITPOS))
#define PCR_SYS_SLP_AUTO_CLR (1ul<<(PCR_SYS_SLP_AUTO_CLR_BITPOS))
//
// Reserved (Offset +1Ch)
//
//
// Processor Clock Control Reg (Offset +20h)
//
#define PCR_CLK_CTRL_OFFSET (0x20UL)
#define PCR_CLK_CTRL_MASK (0xFFUL)
#define PCR_CLK_CTRL_48M (0x01UL)
#define PCR_CLK_CTRL_24M (0x02UL)
#define PCR_CLK_CTRL_16M (0x03UL)
#define PCR_CLK_CTRL_12M (0x04UL)
#define PCR_CLK_CTRL_9P6M (0x05UL)
#define PCR_CLK_CTRL_8M (0x06UL)
#define PCR_CLK_CTRL_6P9M (0x07UL)
#define PCR_CLK_CTRL_6M (0x08UL)
#define PCR_CLK_CTRL_4M (0x0CUL)
#define PCR_CLK_CTRL_1M (0x30UL)
//
// EC Sleep Enable 2 Reg (Offset +24h)
// EC Clock Required 2 Reg (Offset +28h)
//
#define PCR_SLP_EN2_OFFSET (0x24UL)
#define PCR_SLP_EN2_MASK (0x00FF7E6Eul)
#define PCR_CLK_REQ2_OFFSET (0x28UL)
#define PCR_CLK_REQ2_MASK (0x00FF7E6EUL)
//
#define PCR_EC2_DAC0_SLP_BITPOS (1)
#define PCR_EC2_DAC1_SLP_BITPOS (2)
#define PCR_EC2_ADC_SLP_BITPOS (3)
// bit[4] Reserved
#define PCR_EC2_PS2_0_SLP_BITPOS (5)
#define PCR_EC2_PS2_1_SLP_BITPOS (6)
// bits[8:7] Reserved
#define PCR_EC2_SPI0_SLP_BITPOS (9)
#define PCR_EC2_HIB_SLP_BITPOS (10)
#define PCR_EC2_KEY_SLP_BITPOS (11)
#define PCR_EC2_RTOS_TMR_SLP_BITPOS (12)
#define PCR_EC2_SMB1_SLP_BITPOS (13)
#define PCR_EC2_SMB2_SLP_BITPOS (14)
// bit[15] Reserved
#define PCR_EC2_LED0_SLP_BITPOS (16)
#define PCR_EC2_LED1_SLP_BITPOS (17)
#define PCR_EC2_LED2_SLP_BITPOS (18)
#define PCR_EC2_BCM0_SLP_BITPOS (19)
#define PCR_EC2_BCM1_SLP_BITPOS (20)
#define PCR_EC2_TIMER2_SLP_BITPOS (21)
#define PCR_EC2_TIMER3_SLP_BITPOS (22)
#define PCR_EC2_SUBDEC_SLP_BITPOS (23)
//
#define PCR_EC2_DAC0_SLP_CLK (1ul << (PCR_EC2_DAC0_SLP_BITPOS))
#define PCR_EC2_DAC1_SLP_CLK (1ul << (PCR_EC2_DAC1_SLP_BITPOS))
#define PCR_EC2_ADC_SLP_CLK (1ul << (PCR_EC2_ADC_SLP_BITPOS))
#define PCR_EC2_PS2_0_SLP_CLK (1ul << (PCR_EC2_PS2_0_SLP_BITPOS))
#define PCR_EC2_PS2_1_SLP_CLK (1ul << (PCR_EC2_PS2_1_SLP_BITPOS))
#define PCR_EC2_SPI0_SLP_CLK (1ul << (PCR_EC2_SPI0_SLP_BITPOS))
#define PCR_EC2_HIB_SLP_CLK (1ul << (PCR_EC2_SPI0_SLP_BITPOS))
#define PCR_EC2_KEY_SLP_CLK (1ul << (PCR_EC2_KEY_SLP_BITPOS))
#define PCR_EC2_RTOS_TMR_SLP_CLK (1ul << (PCR_EC2_RTOS_TMR_SLP_BITPOS))
#define PCR_EC2_SMB1_SLP_CLK (1ul << (PCR_EC2_SMB1_SLP_BITPOS))
#define PCR_EC2_SMB2_SLP_CLK (1ul << (PCR_EC2_SMB2_SLP_BITPOS))
#define PCR_EC2_LED0_SLP_CLK (1ul << (PCR_EC2_LED0_SLP_BITPOS))
#define PCR_EC2_LED1_SLP_CLK (1ul << (PCR_EC2_LED1_SLP_BITPOS))
#define PCR_EC2_LED2_SLP_CLK (1ul << (PCR_EC2_LED2_SLP_BITPOS))
#define PCR_EC2_BCM0_SLP_CLK (1ul << (PCR_EC2_BCM0_SLP_BITPOS))
#define PCR_EC2_BCM1_SLP_CLK (1ul << (PCR_EC2_BCM1_SLP_BITPOS))
#define PCR_EC2_TIMER2_SLP_CLK (1ul << (PCR_EC2_TIMER2_SLP_BITPOS))
#define PCR_EC2_TIMER3_SLP_CLK (1ul << (PCR_EC2_TIMER3_SLP_BITPOS))
#define PCR_EC2_SUBDEC_SLP_CLK (1ul << (PCR_EC2_SUBDEC_SLP_BITPOS))
//
#define PCR_EC2_DAC0_NOSLP_CLK (0)
#define PCR_EC2_DAC1_NOSLP_CLK (0)
#define PCR_EC2_ADC_NOSLP_CLK (0)
#define PCR_EC2_PS2_0_NOSLP_CLK (0)
#define PCR_EC2_PS2_1_NOSLP_CLK (0)
#define PCR_EC2_SPI0_NOSLP_CLK (0)
#define PCR_EC2_HIB_NOSLP_CLK (0)
#define PCR_EC2_KEY_NOSLP_CLK (0)
#define PCR_EC2_RTOS_TMR_NOSLP_CLK (0)
#define PCR_EC2_SMB1_NOSLP_CLK (0)
#define PCR_EC2_SMB2_NOSLP_CLK (0)
#define PCR_EC2_LED0_NOSLP_CLK (0)
#define PCR_EC2_LED1_NOSLP_CLK (0)
#define PCR_EC2_LED2_NOSLP_CLK (0)
#define PCR_EC2_BCM0_NOSLP_CLK (0)
#define PCR_EC2_BCM1_NOSLP_CLK (0)
#define PCR_EC2_TIMER2_NOSLP_CLK (0)
#define PCR_EC2_TIMER3_NOSLP_CLK (0)
#define PCR_EC2_SUBDEC_NOSLP_CLK (0)
//
// Slow Clock Control Reg (Offset +2Ch)
//
#define PCR_SLOW_CLK_CTRL_OFFSET (0x2Cul)
#define PCR_SLOW_CLK_CTRL_MASK (0x03FFul)
#define PCR_SLOW_CLK_OFF (0ul)
#define PCR_SLOW_CLK_48M (1ul)
#define PCR_SLOW_CLK_24M (2ul)
#define PCR_SLOW_CLK_16M (3ul)
#define PCR_SLOW_CLK_12M (4ul)
#define PCR_SLOW_CLK_9P6M (5ul)
#define PCR_SLOW_CLK_8M (6ul)
#define PCR_SLOW_CLK_6M (8ul)
#define PCR_SLOW_CLK_4M (12ul)
#define PCR_SLOW_CLK_3M (16ul)
#define PCR_SLOW_CLK_2M (24ul)
#define PCR_SLOW_CLK_1M (48ul)
//
// Oscillator ID Reg (Offset +30h)
//
#define PCR_OSC_ID_OFFSET (0x30ul)
#define PCR_OSC_LOCK (1ul<<8)
//
// Chip Sub-system Power Reset Status (Offset +34h)
//
#define PCR_CHIP_PRS_OFFSET (0x34ul)
#define PCR_CHIP_PRS_MASK (0x0E6Cul)
#define PCR_CHIP_PRS_VCC_PWRGD_RO (1ul << 2)
#define PCR_CHIP_PRS_SIO_RSTN_RO (1ul << 3)
#define PCR_CHIP_PRS_VBAT_RST_RW1C (1ul << 5)
#define PCR_CHIP_PRS_VTR_RST_RW1C (1ul << 6)
#define PCR_CHIP_PRS_VBAT_LOW_RO (1ul << 9)
#define PCR_CHIP_PRS_32K_ACT_RO (1ul << 10)
#define PCR_CHIP_PRS_PCICLK_ACT_RO (1ul << 11)
//
// Chip Reset Enable Reg (Offset +38h)
//
#define PCR_CHIP_RST_EN_OFFSET (0x38ul)
#define PCR_CHIP_RST_EN_STAP (1ul << 0)
#define PCR_CHIP_RST_EN_EFUSE (1ul << 1)
//
// Host Reset Enable Reg (Offset +3Ch)
//
#define PCR_HOST_RST_EN_OFFSET (0x3Cul)
#define PCR_HOST_RST_EN_MASK (0x0001F003ul)
#define PCR_HOST_RST_EN_LPC (1ul << 0)
#define PCR_HOST_RST_EN_UART0 (1ul << 1)
#define PCR_HOST_RST_EN_GLBL_CFG (1ul << 12)
#define PCR_HOST_RST_EN_ACPI_EC0 (1ul << 13)
#define PCR_HOST_RST_EN_ACPI_EC1 (1ul << 14)
#define PCR_HOST_RST_EN_ACPI_PM1 (1ul << 15)
#define PCR_HOST_RST_EN_MIF8042 (1ul << 16)
//
// EC Reset Enable Register (Offset +40h)
//
#define PCR_EC_RST_EN_OFFSET (0x40ul)
#define PCR_EC_RST_EN_MASK (0xE7F00FF7ul)
#define PCR_EC_RST_EN_INT (1ul << 0)
#define PCR_EC_RST_EN_PECI (1ul << 1)
#define PCR_EC_RST_EN_TACH0 (1ul << 2)
// bit[3] Reserved
#define PCR_EC_RST_EN_PWM0 (1ul << 4)
#define PCR_EC_RST_EN_PMC (1ul << 5)
#define PCR_EC_RST_EN_DMA (1ul << 6)
#define PCR_EC_RST_EN_TFDP (1ul << 7)
#define PCR_EC_RST_EN_CPU (1ul << 8)
#define PCR_EC_RST_EN_WDT (1ul << 9)
#define PCR_EC_RST_EN_SMB0 (1ul << 10)
#define PCR_EC_RST_EN_TACH1 (1ul << 11)
// bits[19:12] Reserved
#define PCR_EC_RST_EN_PWM1 (1ul << 20)
#define PCR_EC_RST_EN_PWM2 (1ul << 21)
#define PCR_EC_RST_EN_PWM3 (1ul << 22)
#define PCR_EC_RST_EN_PWM4 (1ul << 23)
#define PCR_EC_RST_EN_PWM5 (1ul << 24)
#define PCR_EC_RST_EN_PWM6 (1ul << 25)
#define PCR_EC_RST_EN_PWM7 (1ul << 26)
// bits[28:27] Reserved
#define PCR_EC_RST_EN_REG (1ul << 29)
#define PCR_EC_RST_EN_TIMER0 (1ul << 30)
#define PCR_EC_RST_EN_TIMER1 (1ul << 31)
//
// EC Reset Enable 2 Register (Offset +44h)
//
#define PCR_EC_RST_EN2_OFFSET (0x44ul)
#define PCR_EC_RST_EN2_MASK (0x007FEE68ul)
#define PCR_EC2_RST_EN_ADC (1ul << 3)
#define PCR_EC2_RST_EN_PS2_0 (1ul << 5)
#define PCR_EC2_RST_EN_PS2_1 (1ul << 6)
#define PCR_EC2_RST_EN_SPI0 (1ul << 9)
#define PCR_EC2_RST_EN_HIB (1ul << 10)
#define PCR_EC2_RST_EN_KEY (1ul << 11)
#define PCR_EC2_RST_EN_SMB1 (1ul << 13)
#define PCR_EC2_RST_EN_SMB2 (1ul << 14)
#define PCR_EC2_RST_EN_SMB3 (1ul << 15)
#define PCR_EC2_RST_EN_LED0 (1ul << 16)
#define PCR_EC2_RST_EN_LED1 (1ul << 17)
#define PCR_EC2_RST_EN_LED2 (1ul << 18)
#define PCR_EC2_RST_EN_BCM0 (1ul << 19)
#define PCR_EC2_RST_EN_BCM1 (1ul << 20)
#define PCR_EC2_RST_EN_TIMER2 (1ul << 21)
#define PCR_EC2_RST_EN_TIMER3 (1ul << 22)
//
// Host Reset
//
// Power Reset Control Reg (Offset +48h)
//
#define PCR_HOST_OFFSET (0x48ul)
#define PCR_HOST_MASK (0x03ul)
#define PCR_HOST_IRESET_OUT_BITPOS (0)
#define PCR_HOST_IRESET_OUT_ASSERT (1ul << (PCR_HOST_IRESET_OUT_BITPOS))
#define PCR_HOST_RESET_SEL_BITPOS (1)
#define PCR_HOST_RESET_SEL_LPC (0ul << (PCR_HOST_RESET_SEL_BITPOS))
#define PCR_HOST_RESET_SEL_ESPI (1ul << (PCR_HOST_RESET_SEL_BITPOS))
//
// ------------------------------------------------------------------
//
//
// VBAT Powered Register Bank
//
#define VBATR_PWR_FAIL_RESET_OFS (0)
#define VBATR_ATE_REG_CTRL_OFS (4)
#define VBATR_CLOCK_ENABLE_OFS (8)
#define VBATR_ATE_TEST_OFS (0x10)
#define VBATR_OSC_32K_TRIM_OFS (0x14)
#define VBATR_VTR_ALT_CTRL_OFS (0x18)
#define VBATR_OSC_TRIM_CTRL_OFS (0x1C)
//
// Power Fail Reset Status Reg
//
#define VBATR_PFR_MASK (0xA1)
#define VBATR_PFR_RESERVED_MASK ~(VBATR_PFR_MASK)
#define VBATR_PFR_DET32K_BITPOS (0)
#define VBATR_PFR_DET32K (1U << (VBATR_PFR_DET32K_BITPOS))
#define VBATR_PFR_WDT_STS_BITPOS (5)
#define VBATR_PFR_WDT_STS (1U << (VBATR_PFR_WDT_STS_BITPOS))
#define VBATR_PFR_VBAT_RST_STS_BITPOS (7)
#define VBATR_PFR_VBAT_RST_STS (1U << (VBATR_PFR_VBAT_RST_STS_BITPOS))
//
// ATE Regulator Control, offset 0x04
//
// Clock Enable Reg, offset 0x08
//
#define PCRVB_CLKEN_XOSEL_BITPOS (0)
#define PCRVB_CLKEN_XOSEL (1U<<0)
#define PCRVB_CLKEN_EN_32K_BITPOS (1)
#define PCRVB_CLKEN_EN_32K (1U<<1)
//
// 32KHz Oscillator Trim, offset 0x14
//
#define PCRVB_OSC_32K_TRIM_MASK (0x1Ful)
#ifdef __cplusplus
}
#endif
#endif // #ifndef _MEC14XX_PCR_H
/* end mec14xx_pcr.h */
/** @}
*/

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/*****************************************************************************
* (c) 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_system.h
*MEC14xx System header
*/
/** @defgroup MEC14xx system
*/
#ifndef __SYSTEM_MEC14xx_H
#define __SYSTEM_MEC14xx_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "appcfg.h"
#include "platform.h"
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit (void);
uint32_t sys_code_sram_base(void);
uint8_t sys_valid_sram_addr(void * const p);
uint8_t sys_valid_sram_range(void * const p, const uint32_t byte_len);
void sys_cpu_en_timer(uint32_t counts, uint8_t ien);
uint32_t cpu_microsecond_interval(uint32_t start_count);
uint32_t cpu_microsecond_count(void);
#define CPU_US_DELTA(x) cpu_microsecond_interval(x)
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_MEC14xx_H */
/** @}
*/

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_tfdp.h
*MEC14xx TRACE FIFO Data Port definitions
*/
/** @defgroup MEC14xx Peripherals TFDP
*/
#ifndef _MEC14XX_TFDP_H
#define _MEC14XX_TFDP_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define TFDP_NUM_INSTANCES (1u)
#define TFDP_FRAME_START (0xFD)
//
// Offset +00h TFDP Data Register: 8-bit R/W
//
#define TFDP_DATA_REG_OFS (0ul)
#define TFDP_DATA_REG_MASK (0xFFul)
//
// Offset +04h TFDP Control Register 8-bit R/W
//
#define TFDP_CTRL_REG_OFS (0x04ul)
#define TFDP_CTRL_REG_MASK (0x7Ful)
//
#define TFDP_CTRL_ENABLE_BITPOS (0u)
#define TFDP_CTRL_EDGE_SEL_BITPOS (1u)
#define TFDP_CTRL_DIVSEL_BITPOS (2ul)
#define TFDP_CTRL_IP_DELAY_BITPOS (4ul)
// Enable/disable
#define TFDP_CTRL_ENABLE (1u << (TFDP_CTRL_ENABLE_BITPOS))
// Select clock edge data on which data is shifted out
#define TFDP_CTRL_RISING_EDGE (0u << (TFDP_CTRL_EDGE_SEL_BITPOS))
#define TFDP_CTRL_FALLING_EDGE (1u << (TFDP_CTRL_EDGE_SEL_BITPOS))
// TFDP Clock divisor
#define TFDP_CTRL_CLK_DIV2 (0u << (TFDP_CTRL_DIVSEL_BITPOS))
#define TFDP_CTRL_CLK_DIV4 (1u << (TFDP_CTRL_DIVSEL_BITPOS))
#define TFDP_CTRL_CLK_DIV8 (2u << (TFDP_CTRL_DIVSEL_BITPOS))
#define TFDP_CTRL_CLK_DIV2_RSVD (3u << (TFDP_CTRL_DIVSEL_BITPOS))
// Number of clocks to delay between each byte
// Note: this will affect time TFDP block holds off CPU on next
// write to TFDP data register.
#define TFDP_CTRL_IP_1CLKS (0u << (TFDP_CTRL_IP_DELAY_BITPOS))
#define TFDP_CTRL_IP_2CLKS (1u << (TFDP_CTRL_IP_DELAY_BITPOS))
#define TFDP_CTRL_IP_3CLKS (2u << (TFDP_CTRL_IP_DELAY_BITPOS))
#define TFDP_CTRL_IP_4CLKS (3u << (TFDP_CTRL_IP_DELAY_BITPOS))
#define TFDP_CTRL_IP_5CLKS (4u << (TFDP_CTRL_IP_DELAY_BITPOS))
#define TFDP_CTRL_IP_6CLKS (5u << (TFDP_CTRL_IP_DELAY_BITPOS))
#define TFDP_CTRL_IP_7CLKS (6u << (TFDP_CTRL_IP_DELAY_BITPOS))
#define TFDP_CTRL_IP_8CLKS (7u << (TFDP_CTRL_IP_DELAY_BITPOS))
#ifdef __cplusplus
}
#endif
#endif // #ifndef _MEC14XX_TFDP_H
/* end mec14xx_tfdp.h */
/** @}
*/

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_timers.h
*MEC14xx Timer definitions
*/
/** @defgroup MEC14xx Peripherals Timers
*/
#ifndef _MEC14XX_TIMERS_H
#define _MEC14XX_TIMERS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* Basic 16-bit Timer
******************************************************************************/
//
// Basic 16-bit timers, Number of Instances
//
#define BTMR_MAX_INSTANCE (4ul)
//
// Offset between instances of the TMR blocks
//
#define BTMR_INSTANCE_BITPOS (5ul)
#define BTMR_INSTANCE_OFFSET (1ul << (BTMR_INSTANCE_BITPOS))
//
// Basic Timer Count Register (Offset +00h), 32-bit, uses b[15:0]
//
#define BTMR_CNT_MASK (0x0000FFFFUL)
//
// Basic Timer Preload Register (Offset +04h), 32-bit, uses b[15:0]
//
#define BTMR_PRELOAD_MASK (0x0000FFFFUL)
//
// Basic Timer Status Register (Offset +08h), 32-bit, uses b[0] (R/W1C)
//
#define BTMR_STATUS_ACTIVE (0x01UL)
//
// Basic Timer Interrupt Enable Register (Offset +0Ch), 32-bit, uses b[0]
//
#define BTMR_INTEN (0x01UL)
#define BTMR_INTDIS (0ul)
//
// Basic Timer Control Register (Offset +10h), 32-bit, uses b[31:0]
//
#define BTMR_CNTL (0x10UL)
//
#define BTMR_CNTL_PRESCALE_MASK (0xFFFF0000UL)
#define BTMR_CNTL_PRESCALE_BITPOS (16U)
#define BTMR_CNTL_PRESCALE_FIELD_WIDTH (16U)
#define BTMR_CNTL_RSVD_MASK (0x0000FF02UL)
#define BTMR_CNTL_HALT (0x80UL)
#define BTMR_CNTL_RELOAD (0x40UL)
#define BTMR_CNTL_START (0x20UL)
#define BTMR_CNTL_SOFT_RESET (0x10UL)
#define BTMR_CNTL_AUTO_RESTART (0x08UL)
#define BTMR_CNTL_COUNT_UP (0x04UL)
#define BTMR_CNTL_ENABLE (0x01UL)
//
#define BTMR_CNTL_HALT_BIT (7U)
#define BTMR_CNTL_RELOAD_BIT (6U)
#define BTMR_CNTL_START_BIT (5U)
#define BTMR_CNTRL_SOFT_RESET_BIT (4U)
#define BTMR_CNTL_AUTO_RESTART_BIT (3U)
#define BTMR_CNTL_COUNT_DIR_BIT (2U)
#define BTMR_CNTL_ENABLE_BIT (0U)
/*******************************************************************************
* RTOS Timer
******************************************************************************/
#define RTMR_MAX_INSTANCE (1)
/* RTOS Timer clock input is 32KHz.
* FW must enable 32KHz clock domain.
* NOTE: AHB register interface uses 48MHz
* clock domain.
*/
#define RTMR_CLOCK_SRC_FREQ_HZ (32768ul)
//
// +00h Count Value, 32-bit Read-Only
// NOTE: Register must be read as 32-bit, there is no
// latch mechanism.
//
#define RTMR_COUNT_RO_OFS (0ul)
//
// +04h Pre-load, 32-bit Read-Write
//
#define RTMR_PRELOAD_OFS (4ul)
//
// +08h Control, 32-bit Read-Write
// Implements bits[4:0]
//
#define RTMR_CONTROL_OFS (8ul)
#define RTMR_CONTROL_MASK (0x1Ful)
#define RTMR_BLOCK_EN_BITPOS (0)
#define RTMR_BLOCK_EN (1ul << (RTMR_BLOCK_EN_BITPOS))
#define RTMR_AUTO_RELOAD_BITPOS (1)
#define RTMR_AUTO_RELOAD_EN (1ul << (RTMR_AUTO_RELOAD_BITPOS))
#define RTMR_START_BITPOS (2)
#define RTMR_START (1ul << (RTMR_START_BITPOS))
#define RTMR_EXT_HW_HALT_EN_BITPOS (3)
#define RTMR_EXT_HW_HALT_EN (1ul << (RTMR_EXT_HW_HALT_EN_BITPOS))
#define RTMR_FW_HALT_BITPOS (4)
#define RTMR_FW_HALT (1ul << (RTMR_FW_HALT_BITPOS))
/*******************************************************************************
* Hibernation Timer
******************************************************************************/
#define HIBTMR_MAX_INSTANCE (1)
/* Hibernation Timer clock input is 32KHz.
* FW must enable 32KHz clock domain.
* NOTE: AHB register interface uses 48MHz
* clock domain.
*/
#define HIBTMR_CLOCK_SRC_FREQ_HZ (32768ul)
//
// +00h Preload, 16-bit Read-Write
//
#define HIBTMR_PRELOAD_OFS (0ul)
/* Write 0 to Preload to disable timer, non-zero loads COUNT
* and starts timer */
#define HIBTMR_PRELOAD_DISABLE (0)
//
// +04h Control, 16-bit Read-Write
// Implements bit[0]
//
#define HIBTMR_CNTRL_OFS (4ul)
#define HIBTMR_CNTRL_RESERVED_MASK (0xFFFEu)
#define HIBTMR_CNTRL_MASK (0x01ul)
#define HIBTMR_CNTRL_FREQ_32KHZ (0)
#define HIBTMR_CNTRL_FREQ_8HZ (1)
//
// +08h Count, 16-bit Read-Only
//
#define HIBTMR_COUNT_RO_OFS (8ul)
/*******************************************************************************
* RTC/Week Timer
******************************************************************************/
#define WKTMR_MAX_INSTANCE (1)
/* Week Timer clock input is 32KHz.
* FW must enable 32KHz clock domain.
* NOTE: AHB register interface uses 48MHz
* clock domain.
*/
#define WKTMR_CLOCK_SRC_FREQ_HZ (32768ul)
//
// +00h Control, 8-bit Read-Write
//
#define WKTMR_CNTRL_OFS (0ul)
#define WKTMR_CNTRL_MASK (0x61u)
#define WKTMR_CNTRL_RESERVED_MASK (~(WKTMR_CNTRL_MASK))
#define WKTMR_CNTRL_EN_BITPOS (0)
#define WKTMR_CNTRL_EN (1ul << (WKTMR_CNTRL_EN_BITPOS))
#define WKTMR_BGPO_BITPOS (5)
#define WKTMR_BGPO_LO (0ul << (WKTMR_BGPO_BITPOS))
#define WKTMR_BGPO_HI (1ul << (WKTMR_BGPO_BITPOS))
#define WKTMR_PWRUP_EVENT_EN_BITPOS (6)
#define WKTMR_PWRUP_EVENT_EN (1ul << (WKTMR_PWRUP_EVENT_EN_BITPOS))
//
// +04h 1-second COUNT, 32-bit Read-Write
// Implements bits[27:0]
//
#define WKTMR_COUNT_1S_OFS (4ul)
#define WKTMR_COUNT_1S_MASK (0x0FFFFFFFul)
//
// +08h COMPARE, 32-bit Read-Write
// Implements bits[27:0]
//
#define WKTMR_COMPARE_OFS (8ul)
#define WKTMR_COUNT_1S_MASK (0x0FFFFFFFul)
//
// +0Ch Clock Divider, 32-bit Read-Only
// Implements b[14:0]
//
#define WKTMR_CLOCK_DIVIDER_RO_OFS (0x0Cul)
#define WKTMR_CLOCK_DIVIDER_RO_MASK (0x7FFFul)
//
// +10h Sub-second Interrupt Events Select, 32-bit Read-Write
// Implements bits[3:0]
//
#define WKTMR_SUBSEC_EVENTS_SEL_OFS (0x10ul)
#define WKTMR_SUBSEC_EVENTS_SEL_MASK (0x0Ful)
#define WKTMR_SUBSEC_EV_DIS (0u)
#define WKTMR_SUBSEC_EV_2HZ (1u)
#define WKTMR_SUBSEC_EV_4HZ (2u)
#define WKTMR_SUBSEC_EV_8HZ (3u)
#define WKTMR_SUBSEC_EV_16HZ (4u)
#define WKTMR_SUBSEC_EV_32HZ (5u)
#define WKTMR_SUBSEC_EV_64HZ (6u)
#define WKTMR_SUBSEC_EV_128HZ (7u)
#define WKTMR_SUBSEC_EV_256HZ (8u)
#define WKTMR_SUBSEC_EV_512HZ (9u)
#define WKTMR_SUBSEC_EV_1024HZ (10u)
#define WKTMR_SUBSEC_EV_2048HZ (11u)
#define WKTMR_SUBSEC_EV_4096HZ (12u)
#define WKTMR_SUBSEC_EV_8192HZ (13u)
#define WKTMR_SUBSEC_EV_16384HZ (14u)
#define WKTMR_SUBSEC_EV_32768HZ (15u)
//
// +14h Sub-Week Control, 32-bit Read-Write
// Implements bits[9:4, 1:0]
// Bits[1:0] = Read-Write-1-Clear
// Bit[4] = Read-Only
// Bits[9:5] = Read-Write
//
#define WKTMR_SUB_CNTRL_OFS (0x14ul)
#define WKTMR_SUB_CNTRL_MASK (0x3F3ul)
#define WKTMR_SUB_CNTRL_RESERVED_MASK (~(WKTMR_SUB_CNTRL_MASK))
#define WKTMR_SC_PWRUP_EV_STS_BITPOS (0)
#define WKTMR_SC_PWRUP_EV_STS (1ul << (WKTMR_SC_PWRUP_EV_STS_BITPOS))
#define WKTMR_WK_PWRUP_EV_STS_BITPOS (1)
#define WKTMR_WK_PWRUP_EV_STS (1ul << (WKTMR_WK_PWRUP_EV_STS_BITPOS))
#define WKTMR_SC_SYSPWR_PRES_STS_BITPOS (4)
#define WKTMR_SC_SYSPWR_PRES_STS (1ul << (WKTMR_SC_SYSPWR_PRES_STS_BITPOS))
#define WKTMR_SC_SYSPWR_PRES_EN_BITPOS (5)
#define WKTMR_SC_SYSPWR_PRES_EN (1ul << (WKTMR_SC_SYSPWR_PRES_EN_BITPOS))
#define WKTMR_SC_AUTO_RELOAD_EN_BITPOS (6)
#define WKTMR_SC_AUTO_RELOAD_EN (1ul << (WKTMR_SC_AUTO_RELOAD_EN_BITPOS))
#define WKTMR_SC_CLKSRC_BITPOS (7)
#define WKTMR_SC_CLKSRC_MASK (0x07ul << (WKTMR_SC_CLKSRC_BITPOS))
//
// +18h Sub-Week Count, 32-bit Read-Write
// Implements bits[24:16, 8:0]
// Bit2[24:16] = Read-Only
// Bits[8:0] = Read-Write
//
#define WKTMR_SUBWK_COUNT_OFS (0x18ul)
#define WKTMR_SUBWK_COUNT_MASK (0x01FF01FFul)
#define WKTMR_SUBWK_COUNT_RESERVED_MASK (~(WKTMR_SUBWK_COUNT_MASK))
#define WKTMR_SUBWK_CNT_LOAD_BITPOS (0)
#define WKTMR_SUBWK_CNT_LOAD_MASK (0x1FFul)
#define WKTMR_SUBWK_CNT_VAL_RO_BITPOS (16)
#define WKTMR_SUBWK_CNT_VAL_RO_MASK (0x01FFul)
/*******************************************************************************
* Basic 16-bit Timer API
******************************************************************************/
//
// Logical Basic Timer ID for API calls
//
#define BTMR0_ID (0x00u)
#define BTMR1_ID (0x01u)
#define BTMR2_ID (0x02u)
#define BTMR3_ID (0x03u)
#define BTMR_ID_MAX (0x04u)
//
// Logical flags for tmr_cntl parameter of TMRInit
// b[31:16] = prescaler
//
#define BTMR_AUTO_RESTART (0x08u)
#define BTMR_ONE_SHOT (0u)
#define BTMR_COUNT_UP (0x04u)
#define BTMR_COUNT_DOWN (0u)
#define BTMR_INT_EN (0x01u)
#define BTMR_NO_INT (0u)
uint32_t btmr_get_hw_addr(uint8_t btmr_id);
void btmr_sleep_en(uint8_t tmr_id, uint8_t sleep_en);
void btmr_reset(uint8_t tmr_id);
void btmr_init(uint8_t tmr_id,
uint16_t tmr_cntl,
uint16_t prescaler,
uint32_t initial_count,
uint32_t preload_count);
void btmr_ien(uint8_t tmr_id, uint8_t ien);
uint8_t btmr_get_clr_ists(uint8_t tmr_id);
void btmr_reload(uint8_t tmr_id);
void btmr_set_count(uint8_t tmr_id, uint32_t count);
uint32_t btmr_count(uint8_t tmr_id);
void btmr_start(uint8_t tmr_id);
void btmr_stop(uint8_t tmr_id);
uint8_t btmr_is_stopped(uint8_t tmr_id);
void btmr_halt(uint8_t tmr_id);
void btmr_uhalt(uint8_t tmr_id);
/*******************************************************************************
* End Basic 16-bit Timer API
******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif // #ifndef _MEC14XX_TIMERS_H
/* end mec14xx_timers.h */
/** @}
*/

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_trace_func.h
*MEC14xx TFDP Peripheral Library API
*/
/** @defgroup MEC14xx Peripherals Trace
*/
#ifndef _MEC14XX_TRACE_FUNC_H
#define _MEC14XX_TRACE_FUNC_H
#include "appcfg.h"
#include "mec14xx.h"
#include "mec14xx_tfdp.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef ENABLE_TFDP_TRACE
#ifdef ENABLE_TRACE_HOST_LINK
#include <stdio.h>
#include <stdlib.h>
#endif
#define TFDP_SLEEP_EN (1u)
#define TFDP_SLEEP_DIS (0u)
#define TFDP_EN (1u)
#define TFDP_DIS (0u)
#define TFDP_CFG_PINS (1u)
#define TFDP_NO_CFG_PINS (0u)
void tfdp_sleep_en(uint8_t sleep_en);
void tfdp_enable(uint8_t en, uint8_t pin_cfg);
void TFDPTrace0( uint16_t nbr, uint8_t b );
void TFDPTrace1( uint16_t nbr, uint8_t b, uint32_t p1 );
void TFDPTrace2( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2 );
void TFDPTrace3( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2, uint32_t p3);
void TFDPTrace4( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4);
void TFDPTrace11( uint16_t nbr, uint8_t b, uint32_t p1);
void TFDPTrace12( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2);
#if defined(ENABLE_TRACE_HOST_LINK)
#define TRACE0(nbr,cat,b,str) printf(str)
#define TRACE1(nbr,cat,b,str,p1) printf(str,p1)
#define TRACE2(nbr,cat,b,str,p1,p2) printf(str,p1,p2)
#define TRACE3(nbr,cat,b,str,p1,p2,p3) printf(str,p1,p2,p3)
#define TRACE4(nbr,cat,b,str,p1,p2,p3,p4) printf(str,p1,p2,p3,p4)
#define TRACE11(nbr,cat,b,str,p1) printf(str,p1)
#define TRACE12(nbr,cat,b,str,p1,p2) printf(str,p1,p2)
#elif defined(TRACE_NO_PREPROC)
/* C pre-processor - don't substitute TRACE macros */
#else // not ENABLE_TRACE_HOST_LINK
#define TRACE0(nbr,cat,b,str) TFDPTrace0(nbr,b)
#define TRACE1(nbr,cat,b,str,p1) TFDPTrace1(nbr,b,p1)
#define TRACE2(nbr,cat,b,str,p1,p2) TFDPTrace2(nbr,b,p1,p2)
#define TRACE3(nbr,cat,b,str,p1,p2,p3) TFDPTrace3(nbr,b,p1,p2,p3)
#define TRACE4(nbr,cat,b,str,p1,p2,p3,p4) TFDPTrace4(nbr,b,p1,p2,p3,p4)
#define TRACE11(nbr,cat,b,str,p1) TFDPTrace11(nbr,b,p1)
#define TRACE12(nbr,cat,b,str,p1,p2) TFDPTrace12(nbr,b,p1,p2)
#endif
#else // #ifdef ENABLE_TFDP_TRACE
#define tfdp_sleep_en(sleep_en)
#define tfdp_enable(en,pin_cfg)
#define TRACE0(nbr,cat,b,str)
#define TRACE1(nbr,cat,b,str,p1)
#define TRACE2(nbr,cat,b,str,p1,p2)
#define TRACE3(nbr,cat,b,str,p1,p2,p3)
#define TRACE4(nbr,cat,b,str,p1,p2,p3,p4)
#define TRACE11(nbr,cat,b,str,p1)
#define TRACE12(nbr,cat,b,str,p1,p2)
#endif // #ifdef ENABLE_TFDP_TRACE
#define trace0(nbr,cat,b,str)
#define trace1(nbr,cat,b,str,p1)
#define trace2(nbr,cat,b,str,p1,p2)
#define trace3(nbr,cat,b,str,p1,p2,p3)
#define trace4(nbr,cat,b,str,p1,p2,p3,p4)
#define trace11(nbr,cat,b,str,p1)
#define trace12(nbr,cat,b,str,p1,p2)
#ifdef __cplusplus
}
#endif
#endif // #ifndef _MEC14XX_TRACE_FUNC_H
/* end mec14xx_trace_func.h */
/** @}
*/

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file mec14xx_trace_inline.h
*MEC14xx Inline TRACE macros
*/
/** @defgroup MEC14xx TRACE
*/
#ifndef _MEC14XX_TRACE_INLINE_H
#define _MEC14XX_TRACE_INLINE_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define INLINE_TRACE_ENABLE
#ifdef INLINE_TRACE_ENABLE
#define TRDA (0xA0008c00ul)
#define TRHDR() *(volatile uint8_t *)(TRDA)=0xFDu
#define TRB0(v) *(volatile uint8_t *)(TRDA)=(uint8_t)v
#define TRB1(v) *(volatile uint8_t *)(TRDA)=(uint8_t)(v>>8)
#define TRB2(v) *(volatile uint8_t *)(TRDA)=(uint8_t)(v>>16)
#define TRB3(v) *(volatile uint8_t *)(TRDA)=(uint8_t)(v>>24)
#define TRACE0(nbr,cat,b,str) TRHDR();TRB0(nbr);TRB1(nbr);
#define TRACE1(nbr,cat,b,str,p1) TRHDR();TRB0(nbr);TRB1(nbr);TRB0(p1);TRB1(p1);
#define TRACE2(nbr,cat,b,str,p1,p2) TRHDR();TRB0(nbr);TRB1(nbr);TRB0(p1);TRB1(p1);TRB0(p2);TRB1(p2);
#define TRACE3(nbr,cat,b,str,p1,p2,p3) TRHDR();TRB0(nbr);TRB1(nbr);TRB0(p1);TRB1(p1);TRB0(p2);TRB1(p2);TRB0(p3);TRB1(p3);
#define TRACE4(nbr,cat,b,str,p1,p2,p3,p4) TRHDR();TRB0(nbr);TRB1(nbr);TRB0(p1);TRB1(p1);TRB0(p2);TRB1(p2);TRB0(p3);TRB1(p3);TRB0(p4);TRB1(p4);
#define TRACE11(nbr,cat,b,str,p1) TRHDR();TRB0(nbr);TRB1(nbr);TRB0(p1);TRB1(p1);TRB2(p1);TRB3(p1);
#define TRACE12(nbr,cat,b,str,p1,p2) TRHDR();TRB0(nbr);TRB1(nbr);TRB0(p1);TRB1(p1);TRB2(p1);TRB3(p1);TRB0(p2);TRB1(p2);TRB2(p2);TRB3(p2);
#else // #ifdef INLINE_TRACE_ENABLE
#define TRACE0(nbr,cat,b,str)
#define TRACE1(nbr,cat,b,str,p1)
#define TRACE2(nbr,cat,b,str,p1,p2)
#define TRACE3(nbr,cat,b,str,p1,p2,p3)
#define TRACE4(nbr,cat,b,str,p1,p2,p3,p4)
#define TRACE11(nbr,cat,b,str,p1)
#define TRACE12(nbr,cat,b,str,p1,p2)
#define trace0(nbr,cat,b,str)
#define trace1(nbr,cat,b,str,p1)
#define trace2(nbr,cat,b,str,p1,p2)
#define trace3(nbr,cat,b,str,p1,p2,p3)
#define trace4(nbr,cat,b,str,p1,p2,p3,p4)
#define trace11(nbr,cat,b,str,p1)
#define trace12(nbr,cat,b,str,p1,p2)
#endif // #ifdef PLIB_TRACE_ENABLE
#define trace0(nbr,cat,b,str)
#define trace1(nbr,cat,b,str,p1)
#define trace2(nbr,cat,b,str,p1,p2)
#define trace3(nbr,cat,b,str,p1,p2,p3)
#define trace4(nbr,cat,b,str,p1,p2,p3,p4)
#define trace11(nbr,cat,b,str,p1)
#define trace12(nbr,cat,b,str,p1,p2)
#ifdef __cplusplus
}
#endif
#endif // #ifndef _MEC14XX_TRACE_INLINE_H
/* end mec14xx_trace_inline.h */
/** @}
*/

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/*****************************************************************************
* Copyright 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file appcfg.h
*MEC14xx build configuration
*/
/** @defgroup common
*/
#ifndef _APPCFG_H
#define _APPCFG_H
#define ADISABLE (0)
#define AENABLE (1)
#define FALSE (0)
#define TRUE (1)
#define OFF (0)
#define ON (1)
/*
* Choose MEC1404 or MEC1418 Device
*/
#define MEC1403_DEVID (0x00011000) /* Code 96KB, 84-pin */
#define MEC1404_DEVID (0x00021000) /* Code 96KB, 128-pin */
#define MEC1405_DEVID (0x00031000) /* Code 128KB 84-pin */
#define MEC1406_DEVID (0x00041000) /* Code 128KB 128-pin */
#define MEC1407_DEVID (0x00051000) /* Code 160KB 84-pin */
#define MEC1408_DEVID (0x00061000) /* Code 160KB 128-pin */
#define MEC1413_DEVID (0x00071000) /* Code 96KB 84-pin */
#define MEC1414_DEVID (0x00081000) /* Code 96KB 128-pin */
#define MEC1415_DEVID (0x00091000) /* Code 128KB 84-pin */
#define MEC1416_DEVID (0x000A1000) /* Code 128KB 128-pin */
#define MEC1417_DEVID (0x000B1000) /* Code 160KB 84-pin */
#define MEC1418_DEVID (0x000C1000) /* Code 160KB 128-pin */
#define MEC14XX_DEVID (MEC1404_DEVID)
/*
* MEC14xx Power-Control-Reset Processor clock divider value
* MIPS M14K Processor clock = Chip_Input_Clock / PCR_PROC_CLK_DIV
* MEC14xx POR PCR Processor Clock divider = 4
*
* Silicon Chip_Input_Clock = 48MHz
*
*/
#define PCR_CLOCK_DIVIDER (1)
// GPIO_0102/KSO9 0102(octal)=0x42.
#define CR_STRAP_GPIO (0x42ul)
#define CR_STRAP_GPIO_BANK (2u)
#define CR_STRAP_BITPOS (2u)
/* GPIO_0123 0:[0,37], 1:[40,77], 2:[100,137], 3:[140,177], 4[200,237] */
#define SPI0_CS0_REG_IDX (0x53u)
#define SPI0_CS0_GPIO_BANK (2ul)
#define SPI0_CS0_BITPOS (19u)
/* GPIO_0015 0:[0,37], 1:[40,77], 2:[100,137], 3:[140,177], 4[200,237] */
#define SPI1_CS0_REG_IDX (0x0Du)
#define SPI1_CS0_GPIO_BANK (0ul)
#define SPI1_CS0_BITPOS (13u)
/*
* ASIC at full speed (48MHz)
* M14K CP0 Counter increments at 1/2 CPU core clock.
*/
#define M14K_TIMER_COMPARE_2SEC (0x00B71B00ul)
#define M14K_TIMER_COMPARE_1SEC (0x005B8D80ul)
#define M14K_TIMER_COMPARE_10MS (0x0000EA60ul)
#define M14K_TIMER_COMPARE (M14K_TIMER_COMPARE_2SEC)
/* 16-bit Timer 0 */
// Prescale value for 10KHz tick rate
#define BASIC_TIMER0_PRESCALE_10KHZ_ASIC (4799ul)
#define BASIC_TIMER0_PRESCALE_1KHZ_ASIC (47999ul)
// Preload/Count value for 1.733 seconds
#define BASIC_TIMER0_PRESCALE (BASIC_TIMER0_PRESCALE_1KHZ_ASIC)
#define BASIC_TIMER0_PRELOAD (2000ul)
/* RTOS Timer (32KHz) */
#define RTOS_TIMER_COUNT_10MS (328ul)
/*
* Enable check of GPIO access in mec14xx_gpio module
*/
#define ENABLE_GPIO_PIN_VALIDATION
/*
* Enable check of Basic Timer ID in API calls
*/
#define MEC14XX_BTIMER_CHECK_ID
/*
* Enable GPIO Pin Debug
*/
//#define DEBUG_GPIO_PIN
/*
* Enable TFDP TRACE
*/
#define ENABLE_TFDP_TRACE
/*
* Use C-library printf for TFDP Trace
*
#define ENABLE_TRACE_HOST_LINK
*/
/*
* Delay between writes to TFDP data register
*/
#define TFDP_DELAY()
#endif // #ifndef _APPCFG_H
/** @}
*/

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/*****************************************************************************
* © 2014 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*****************************************************************************/
/** @file platform.h
*MEC14xx platform/cpu abstractions
*/
/** @defgroup MEC14xx
*/
#ifndef _PLATFORM_H
#define _PLATFORM_H
#if defined(__GNUC__) && defined(__mips__)
#if defined(__XC32__) // Microchip XC32 GCC
/* Pull in MIPS32 specific special instructions instrinsics for
* interrupt control, NOP, Wait-for-Interrupt and accessing
* MSR's.
* Issue: MPLAB-X IDE editor and the CPU macros in xc.h & cp0defs.h.
* The IDE editor will show red ! on every line of code using the above
* macros due to a bug in the IDE's C language preprocessor.
*/
#include <xc.h>
#define CPU_DISABLE_INTERRUPTS() __builtin_disable_interrupts()
#define CPU_GET_DISABLE_INTERRUPTS(x) { x=_CP0_GET_STATUS()&0x1ul; __builtin_disable_interrupts() }
#define CPU_ENABLE_INTERRUPTS() __builtin_enable_interrupts()
#define CPU_RESTORE_INTERRUPTS(x) { if (x) { __builtin_enable_interrupts(); } }
#define Disable_Irq() CPU_DISABLE_INTERRUPTS()
#define Enable_Irq() CPU_ENABLE_INTERRUPTS()
#define __CLZ(x) __builtin_clz(x)
#define __CTZ(x) __builtin_ctz (x)
#define __CLO(x) _clo(x)
#define __INS(tgt,val,pos,sz) _ins(tgt,val,pos,sz)
#define __EXT(x,pos,sz) _ext(x,pos,sz)
#define CPU_NOP() __asm__ __volatile ("%(ssnop%)" : :)
#define CPU_WAIT_FOR_INTR() __asm__ __volatile ("wait")
#define __REV(x) _bswapw(x)
#define __EHB() _ehb()
#else
/* Include MIPS specific inline assembly functions for accessing
* MIPS CP0 registers, NOP, WAIT, ASET, ACLR, byte-reverse, etc.
*/
#include "mipscpu.h"
#define CPU_DISABLE_INTERRUPTS() mips32r2_dis_intr()
#define CPU_GET_DISABLE_INTERRUPTS(x) x=mips32r2_dis_intr()
#define CPU_ENABLE_INTERRUPTS() mips32r2_en_intr()
#define CPU_RESTORE_INTERRUPTS(x) mips32r2_restore_intr(x)
#define Disable_Irq() CPU_DISABLE_INTERRUPTS()
#define Enable_Irq() CPU_ENABLE_INTERRUPTS()
#define __CLZ(x) __builtin_clz(x)
#define __CTZ(x) __builtin_ctz (x)
#define __CLO(x) __extension__({ \
unsigned int __x = (x); \
unsigned int __v; \
__asm__ ("clo %0,%1" : "=d" (__v) : "d" (__x)); \
__v; \
})
/* MIPS32r2 insert bits */
#define __INS(tgt,val,pos,sz) __extension__({ \
unsigned int __t = (tgt), __v = (val); \
__asm__ ("ins %0,%z1,%2,%3" \
: "+d" (__t) \
: "dJ" (__v), "I" (pos), "I" (sz)); \
__t; \
})
/* MIPS32r2 extract bits */
#define __EXT(x,pos,sz) __extension__({ \
unsigned int __x = (x), __v; \
__asm__ ("ext %0,%z1,%2,%3" \
: "=d" (__v) \
: "dJ" (__x), "I" (pos), "I" (sz)); \
__v; \
})
#define CPU_NOP() __asm__ __volatile ("%(ssnop%)" : :)
#define CPU_WAIT_FOR_INTR() __asm__ __volatile ("wait")
#define __REV(x) mips32r2_rev_word(x)
#define __EHB() __asm__ __volatile__ ("%(ehb%)" : :)
#define _CP0_GET_BADVADDR() mips32r2_cp0_badvaddr_get()
#define _CP0_GET_COUNT() mips32r2_cp0_count_get()
#define _CP0_SET_COUNT(val) mips32r2_cp0_count_set((unsigned long)val)
#define _CP0_GET_COMPARE() mips32r2_cp0_compare_get()
#define _CP0_SET_COMPARE(val) mips32r2_cp0_compare_set((unsigned long)val)
#define _CP0_GET_STATUS() mips32r2_cp0_status_get()
#define _CP0_SET_STATUS(val) mips32r2_cp0_status_set((unsigned long)val)
#define _CP0_BIC_STATUS(val) mips32r2_cp0_status_bic(val)
#define _CP0_BIS_STATUS(val) mips32r2_cp0_status_bis(val)
#define _CP0_GET_INTCTL() mips32r2_cp0_intctl_get()
#define _CP0_SET_INTCTL(val) mips32r2_cp0_intctl_set((unsigned long)val)
#define _CP0_GET_VIEW_IPL() mips32r2_cp0_view_ipl_get()
#define _CP0_SET_VIEW_IPL(val) mips32r2_cp0_view_ipl_set((unsigned long)val)
#define _CP0_GET_CAUSE() mips32r2_cp0_cause_get()
#define _CP0_SET_CAUSE(val) mips32r2_cp0_cause_set((unsigned long)val)
#define _CP0_BIC_CAUSE(val) mips32r2_cp0_cause_bic((unsigned long)val)
#define _CP0_BIS_CAUSE(val) mips32r2_cp0_cause_bis((unsigned long)val)
#define _CP0_GET_VIEW_RIPL() mips32r2_cp0_view_ripl_get()
#define _CP0_SET_VIEW_RIPL(val) mips32r2_cp0_view_ripl_set((unsigned long)val)
#define _CP0_GET_EPC() mips32r2_cp0_epc_get()
#define _CP0_SET_EPC(val) mips32r2_cp0_epc_set((unsigned long)val)
#define _CP0_GET_EBASE() mips32r2_cp0_ebase_get()
#define _CP0_SET_EBASE(val) mips32r2_cp0_ebase_set((unsigned long)val)
#define _CP0_GET_CONFIG() mips32r2_cp0_config_get()
#define _CP0_GET_CONFIG3() mips32r2_cp0_config3_get()
#define _CP0_GET_DEPC() mips32r2_cp0_depc_get()
#endif
#else // Any other compiler
#error "FORCED BUILD ERROR: Unknown compiler"
#endif
/*
Need to define NULL
*/
#ifndef NULL
#ifdef __CPLUSPLUS__
#define NULL 0
#else
#define NULL ((void *)0)
#endif
#endif
#endif // #ifndef _PLATFORM_H
/** @}
*/

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/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* This project provides two demo applications. A simple blinky style project,
* and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
* select between the two. The simply blinky demo is implemented and described
* in main_blinky.c. The more comprehensive test and demo application is
* implemented and described in main_full.c.
*
* This file implements the code that is not demo specific, including the
* hardware setup and FreeRTOS hook functions.
*****************************************************************************/
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "timers.h"
/* Target includes. */
#include "appcfg.h"
#include "MEC14xx/mec14xx.h"
#include "MEC14xx/mec14xx_jtvic.h"
#include "MEC14xx/mec14xx_bbled.h"
#include "MEC14xx/mec14xx_girqs.h"
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
or 0 to run the more comprehensive test and demo application. */
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
/*-----------------------------------------------------------*/
/*
* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
* main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
*/
extern void main_blinky( void );
extern void main_full( void );
/*
* Performs any hardware setup necessary.
*/
static void __attribute__((nomips16)) prvSetupHardware( void );
/*
* Add some thread safety to the LED toggle function.
*/
void vToggleLED( uint8_t ucLED );
/*-----------------------------------------------------------*/
int main( void )
{
/* Perform any hardware initialisation necessary. */
prvSetupHardware();
/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
of this file. */
#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
{
main_blinky();
}
#else
{
main_full();
}
#endif
/* Should never be reached. */
return 0;
}
/*-----------------------------------------------------------*/
void vToggleLED( uint8_t ucLED )
{
taskENTER_CRITICAL();
{
led_out_toggle( ucLED );
}
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
static void __attribute__((nomips16)) prvSetupHardware( void )
{
volatile uint32_t ulTemp;
/* Interrupts are automatically re-enabled when the scheduler is started. */
__asm volatile( "di" );
/* Enable M14K Vector Pre-fetch: CP0.IntCtl b[22]=1
IRET (interrupt chaining): b[21]=1
Enable Auto-Prolog: b[14]=1 */
ulTemp = _CP0_GET_INTCTL();
ulTemp |= ( 1ul << 22 ) + ( 1ul << 21 ) + ( 1ul << 14 );
_CP0_SET_INTCTL( ulTemp );
/* Configure 32KHz for Switched Clock Source always ON
b[ 0 ] = XOSEL = 1
b[ 1 ] = EXT_32K_OSC_EN = 1
b[ 2 ] = INT_32K_OSC_EN = 1
b[ 3 ] = INT_32K_VTR_PWR_WELL_EMUL = 0
b[ 4 ] = 32K_SWITCHER_CTRL = 0 */
VBAT_REGS->CLOCK_ENABLE = 0x07;
ulTemp = 256;
while (ulTemp--)
{
__asm volatile( "NOP" );
__asm volatile( "NOP" );
__asm volatile( "NOP" );
__asm volatile( "NOP" );
}
/* Disaggregate GIRQ23 & GIRQ24 for FreeRTOS. Second parameter is a bit-map
for each GIRQ where
0 = Aggregated, 1 = Dis-aggregate
Bit position = GIRQ_Number - 8
Example: GIRQ23 ( 23 - 8 ) = 15
Dis-aggregate GIRQ23 & GIRQ24
The symbols JTVIC_DISAGR_BITMAP is generated in header file mec14xx_girqm.h
Each disaggregated interrupt handler is spaced 8-bytes apart starting at
base address for that GIRQ. */
jtvic_init( dflt_ih_table, ( JTVIC_DISAGR_BITMAP ), ( JTVIC_FLAG_DISAGR_SPACING_8 ) );
/* Initialise the LEDs. */
for( ulTemp = 0; ulTemp < LED_ID_MAX; ulTemp++ )
{
led_sleep_en( ulTemp, ADISABLE );
led_init( ulTemp );
led_out_high( ulTemp );
}
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* vApplicationMallocFailedHook() will only be called if
configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
function that will get called if a call to pvPortMalloc() fails.
pvPortMalloc() is called internally by the kernel whenever a task, queue,
timer or semaphore is created. It is also called by various parts of the
demo application. If heap_1.c or heap_2.c are used, then the size of the
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
to query the size of free heap space that remains (although it does not
provide information on how the remaining heap might be fragmented). */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
task. It is essential that code added to this hook function never attempts
to block in any way (for example, call xQueueReceive() with a block time
specified, or call vTaskDelay()). If the application makes use of the
vTaskDelete() API function (as this demo application does) then it is also
important that vApplicationIdleHook() is permitted to return to its calling
function, because it is the responsibility of the idle task to clean up
memory allocated by the kernel to any task that has since been deleted. */
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time task stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
called if a task stack overflow is detected. Note the system/interrupt
stack is not checked. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationTickHook( void )
{
/* This function will be called by each tick interrupt if
configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
added here, but the tick hook is called from an interrupt context, so
code must not attempt to block, and only the interrupt safe FreeRTOS API
functions can be used (those that end in FromISR()). */
}
/*-----------------------------------------------------------*/
void vAssertCalled( const char * pcFile, unsigned long ulLine )
{
volatile char *pcFileName;
volatile unsigned long ulLineNumber;
/* Prevent things that are useful to view in the debugger from being
optimised away. */
pcFileName = ( char * ) pcFile;
( void ) pcFileName;
ulLineNumber = ulLine;
/* Set ulLineNumber to 0 in the debugger to break out of this loop and
return to the line that triggered the assert. */
while( ulLineNumber != 0 )
{
__asm volatile( "NOP" );
__asm volatile( "NOP" );
__asm volatile( "NOP" );
__asm volatile( "NOP" );
__asm volatile( "NOP" );
}
}

256
FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/ISR_Support.h Normal file
View File

@ -0,0 +1,256 @@
/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#include "FreeRTOSConfig.h"
#define portCONTEXT_SIZE 132
#define portEPC_STACK_LOCATION 124
#define portSTATUS_STACK_LOCATION 128
#ifdef __LANGUAGE_ASSEMBLY__
/******************************************************************/
.macro portSAVE_CONTEXT
/* Make room for the context. First save the current status so it can be
manipulated, and the cause and EPC registers so their original values are
captured. */
mfc0 k0, _CP0_CAUSE
addiu sp, sp, -portCONTEXT_SIZE
mfc0 k1, _CP0_STATUS
/* Also save s6 and s5 so they can be used. Any nesting interrupts should
maintain the values of these registers across the ISR. */
sw s6, 44(sp)
sw s5, 40(sp)
sw k1, portSTATUS_STACK_LOCATION(sp)
/* Prepare to enable interrupts above the current priority.
k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
srl k0, k0, 0xa
/* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
ins k1, k0, 10, 7
/* Sets CP0.Status.IPL = CP0.Cause.RIPL
Copy the MSB of the IPL, but it would be an error if it was set anyway. */
srl k0, k0, 0x7
/* MSB of IPL is bit[18] of CP0.Status */
ins k1, k0, 18, 1
/* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
b[3]=Rsvd, b[2]=ERL, b[1]=EXL
Setting EXL=0 allows higher priority interrupts
to preempt this handler */
ins k1, zero, 1, 4
/* s5 is used as the frame pointer. */
add s5, zero, sp
/* Check the nesting count value. */
la k0, uxInterruptNesting
lw s6, (k0)
/* If the nesting count is 0 then swap to the the system stack, otherwise
the system stack is already being used. */
bne s6, zero, 1f
nop
/* Swap to the system stack. */
la sp, xISRStackTop
lw sp, (sp)
/* Increment and save the nesting count. */
1: addiu s6, s6, 1
sw s6, 0(k0)
/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
mfc0 s6, _CP0_EPC
/* Re-enable interrupts. */
mtc0 k1, _CP0_STATUS
/* Save the context into the space just created. s6 is saved again
here as it now contains the EPC value. No other s registers need be
saved. */
sw ra, 120(s5) /* Return address (RA=R31) */
sw s8, 116(s5) /* Frame Pointer (FP=R30) */
sw t9, 112(s5)
sw t8, 108(s5)
sw t7, 104(s5)
sw t6, 100(s5)
sw t5, 96(s5)
sw t4, 92(s5)
sw t3, 88(s5)
sw t2, 84(s5)
sw t1, 80(s5)
sw t0, 76(s5)
sw a3, 72(s5)
sw a2, 68(s5)
sw a1, 64(s5)
sw a0, 60(s5)
sw v1, 56(s5)
sw v0, 52(s5)
sw s6, portEPC_STACK_LOCATION(s5)
sw $1, 16(s5)
/* MEC14xx does not have DSP, removed 7 words */
mfhi s6
sw s6, 12(s5)
mflo s6
sw s6, 8(s5)
/* Update the task stack pointer value if nesting is zero. */
la s6, uxInterruptNesting
lw s6, (s6)
addiu s6, s6, -1
bne s6, zero, 1f
nop
/* Save the stack pointer. */
la s6, uxSavedTaskStackPointer
sw s5, (s6)
1:
.endm
/******************************************************************/
.macro portRESTORE_CONTEXT
/* Restore the stack pointer from the TCB. This is only done if the
nesting count is 1. */
la s6, uxInterruptNesting
lw s6, (s6)
addiu s6, s6, -1
bne s6, zero, 1f
nop
la s6, uxSavedTaskStackPointer
lw s5, (s6)
/* Restore the context.
MCHP MEC14xx does not include DSP */
1:
lw s6, 8(s5)
mtlo s6
lw s6, 12(s5)
mthi s6
lw $1, 16(s5)
/* s6 is loaded as it was used as a scratch register and therefore saved
as part of the interrupt context. */
lw s6, 44(s5)
lw v0, 52(s5)
lw v1, 56(s5)
lw a0, 60(s5)
lw a1, 64(s5)
lw a2, 68(s5)
lw a3, 72(s5)
lw t0, 76(s5)
lw t1, 80(s5)
lw t2, 84(s5)
lw t3, 88(s5)
lw t4, 92(s5)
lw t5, 96(s5)
lw t6, 100(s5)
lw t7, 104(s5)
lw t8, 108(s5)
lw t9, 112(s5)
lw s8, 116(s5)
lw ra, 120(s5)
/* Protect access to the k registers, and others. */
di
ehb
/* Decrement the nesting count. */
la k0, uxInterruptNesting
lw k1, (k0)
addiu k1, k1, -1
sw k1, 0(k0)
lw k0, portSTATUS_STACK_LOCATION(s5)
lw k1, portEPC_STACK_LOCATION(s5)
/* Leave the stack in its original state. First load sp from s5, then
restore s5 from the stack. */
add sp, zero, s5
lw s5, 40(sp)
addiu sp, sp, portCONTEXT_SIZE
mtc0 k0, _CP0_STATUS
mtc0 k1, _CP0_EPC
ehb
eret
nop
.endm
#endif /* #ifdef __LANGUAGE_ASSEMBLY__ */

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