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Remove demo that used the now defunct Keil compiler.

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This commit is contained in:
Richard Barry 2008-10-23 11:23:13 +00:00
parent c59af80374
commit 8347299546
11 changed files with 0 additions and 1703 deletions
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97
Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h
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/*
FreeRTOS.org V5.0.4 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
* SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
* and even write all or part of your application on your behalf. *
* See http://www.OpenRTOS.com for details of the services we provide to *
* expedite your project. *
* *
***************************************************************************
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <lpc21xx.h>
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* =12.0MHz xtal multiplied by 5 using the PLL. */
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) 14250 )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

114
Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c
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@ -1,114 +0,0 @@
/*
FreeRTOS.org V5.0.4 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
* SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
* and even write all or part of your application on your behalf. *
* See http://www.OpenRTOS.com for details of the services we provide to *
* expedite your project. *
* *
***************************************************************************
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#include "FreeRTOS.h"
#include "portable.h"
#include "partest.h"
#define partstFIRST_IO ( ( unsigned portLONG ) 0x10000 )
#define partstNUM_LEDS ( 8 )
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
/* This is performed from main() as the io bits are shared with other setup
functions. */
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned portLONG ulLED = partstFIRST_IO;
if( uxLED < partstNUM_LEDS )
{
/* Rotate to the wanted bit of port 0. Only P16 to P23 have an LED
attached. */
ulLED <<= ( unsigned portLONG ) uxLED;
/* Set or clear the output. */
if( xValue )
{
IOSET1 = ulLED;
}
else
{
IOCLR1 = ulLED;
}
}
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState;
if( uxLED < partstNUM_LEDS )
{
/* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED
attached. */
ulLED <<= ( unsigned portLONG ) uxLED;
/* If this bit is already set, clear it, and visa versa. */
ulCurrentState = IOPIN1;
if( ulCurrentState & ulLED )
{
IOCLR1 = ulLED;
}
else
{
IOSET1 = ulLED;
}
}
}

40
Demo/ARM7_LPC2129_Keil/RTOSDemoSignal.UVL
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@ -1,40 +0,0 @@
[Signal 1]
DispName=Port1
PlotType=1
Color=16711935
MinDec=0
MinVal=0.
MaxDec=0
MaxVal=-1.
Mask=65536
Offset=16
[Signal 2]
DispName=Port1
PlotType=1
Color=255
MinDec=0
MinVal=0.
MaxDec=0
MaxVal=-1.
Mask=131072
Offset=17
[Signal 3]
DispName=Port1
PlotType=1
Color=32768
MinDec=0
MinVal=0.
MaxDec=0
MaxVal=-1.
Mask=262144
Offset=18
[Signal 4]
DispName=Port1
PlotType=1
Color=16711680
MinDec=0
MinVal=0.
MaxDec=0
MaxVal=-1.
Mask=524288
Offset=19

379
Demo/ARM7_LPC2129_Keil/Startup.s
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@ -1,379 +0,0 @@
/***********************************************************************/
/* This file is part of the uVision/ARM development tools */
/* Copyright KEIL ELEKTRONIK GmbH 2002-2004 */
/***********************************************************************/
/* */
/* STARTUP.S: Startup file for Philips LPC2000 device series */
/* */
/***********************************************************************/
/*
//*** <<< Use Configuration Wizard in Context Menu >>> ***
*/
// *** Startup Code (executed after Reset) ***
// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 /* when I bit is set, IRQ is disabled */
F_Bit EQU 0x40 /* when F bit is set, FIQ is disabled */
/*
// <h> Stack Configuration (Stack Sizes in Bytes)
// <o0> Undefined Mode <0x0-0xFFFFFFFF>
// <o1> Supervisor Mode <0x0-0xFFFFFFFF>
// <o2> Abort Mode <0x0-0xFFFFFFFF>
// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF>
// <o4> Interrupt Mode <0x0-0xFFFFFFFF>
// <o5> User/System Mode <0x0-0xFFFFFFFF>
// </h>
*/
UND_Stack_Size EQU 0x00000004
SVC_Stack_Size EQU 0x00000100
ABT_Stack_Size EQU 0x00000004
FIQ_Stack_Size EQU 0x00000004
IRQ_Stack_Size EQU 0x00000300
USR_Stack_Size EQU 0x00000200
AREA STACK, DATA, READWRITE, ALIGN=2
DS (USR_Stack_Size+3)&~3 ; Stack for User/System Mode
DS (IRQ_Stack_Size+3)&~3 ; Stack for Interrupt Mode
DS (FIQ_Stack_Size+3)&~3 ; Stack for Fast Interrupt Mode
DS (ABT_Stack_Size+3)&~3 ; Stack for Abort Mode
DS (SVC_Stack_Size+3)&~3 ; Stack for Supervisor Mode
DS (UND_Stack_Size+3)&~3 ; Stack for Undefined Mode
Top_Stack:
// Phase Locked Loop (PLL) definitions
PLL_BASE EQU 0xE01FC080 /* PLL Base Address */
PLLCON_OFS EQU 0x00 /* PLL Control Offset*/
PLLCFG_OFS EQU 0x04 /* PLL Configuration Offset */
PLLSTAT_OFS EQU 0x08 /* PLL Status Offset */
PLLFEED_OFS EQU 0x0C /* PLL Feed Offset */
PLLCON_PLLE EQU (1<<0) /* PLL Enable */
PLLCON_PLLC EQU (1<<1) /* PLL Connect */
PLLCFG_MSEL EQU (0x1F<<0) /* PLL Multiplier */
PLLCFG_PSEL EQU (0x03<<5) /* PLL Divider */
PLLSTAT_PLOCK EQU (1<<10) /* PLL Lock Status */
/*
// <e> PLL Setup
// <i> Phase Locked Loop
// <o1.0..4> MSEL: PLL Multiplier Selection
// <1-32><#-1>
// <i> M Value
// <o1.5..6> PSEL: PLL Divider Selection
// <0=> 1 <1=> 2 <2=> 4 <3=> 8
// <i> P Value
// </e>
*/
PLL_SETUP EQU 1
PLLCFG_Val EQU 0x00000024
// Memory Accelerator Module (MAM) definitions
MAM_BASE EQU 0xE01FC000 /* MAM Base Address */
MAMCR_OFS EQU 0x00 /* MAM Control Offset*/
MAMTIM_OFS EQU 0x04 /* MAM Timing Offset */
/*
// <e> MAM Setup
// <i> Memory Accelerator Module
// <o1.0..1> MAM Control
// <0=> Disabled
// <1=> Partially Enabled
// <2=> Fully Enabled
// <i> Mode
// <o2.0..2> MAM Timing
// <0=> Reserved <1=> 1 <2=> 2 <3=> 3
// <4=> 4 <5=> 5 <6=> 6 <7=> 7
// <i> Fetch Cycles
// </e>
*/
MAM_SETUP EQU 1
MAMCR_Val EQU 0x00000002
MAMTIM_Val EQU 0x00000003
// External Memory Controller (EMC) definitions
EMC_BASE EQU 0xFFE00000 /* EMC Base Address */
BCFG0_OFS EQU 0x00 /* BCFG0 Offset */
BCFG1_OFS EQU 0x04 /* BCFG1 Offset */
BCFG2_OFS EQU 0x08 /* BCFG2 Offset */
BCFG3_OFS EQU 0x0C /* BCFG3 Offset */
/*
// <e> External Memory Controller (EMC)
*/
EMC_SETUP EQU 0
/*
// <e> Bank Configuration 0 (BCFG0)
// <o1.0..3> IDCY: Idle Cycles <0-15>
// <o1.5..9> WST1: Wait States 1 <0-31>
// <o1.11..15> WST2: Wait States 2 <0-31>
// <o1.10> RBLE: Read Byte Lane Enable
// <o1.26> WP: Write Protect
// <o1.27> BM: Burst ROM
// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
// <2=> 32-bit <3=> Reserved
// </e>
*/
BCFG0_SETUP EQU 0
BCFG0_Val EQU 0x0000FBEF
/*
// <e> Bank Configuration 1 (BCFG1)
// <o1.0..3> IDCY: Idle Cycles <0-15>
// <o1.5..9> WST1: Wait States 1 <0-31>
// <o1.11..15> WST2: Wait States 2 <0-31>
// <o1.10> RBLE: Read Byte Lane Enable
// <o1.26> WP: Write Protect
// <o1.27> BM: Burst ROM
// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
// <2=> 32-bit <3=> Reserved
// </e>
*/
BCFG1_SETUP EQU 0
BCFG1_Val EQU 0x0000FBEF
/*
// <e> Bank Configuration 0 (BCFG2)
// <o1.0..3> IDCY: Idle Cycles <0-15>
// <o1.5..9> WST1: Wait States 1 <0-31>
// <o1.11..15> WST2: Wait States 2 <0-31>
// <o1.10> RBLE: Read Byte Lane Enable
// <o1.26> WP: Write Protect
// <o1.27> BM: Burst ROM
// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
// <2=> 32-bit <3=> Reserved
// </e>
*/
BCFG2_SETUP EQU 0
BCFG2_Val EQU 0x0000FBEF
/*
// <e> Bank Configuration 3 (BCFG3)
// <o1.0..3> IDCY: Idle Cycles <0-15>
// <o1.5..9> WST1: Wait States 1 <0-31>
// <o1.11..15> WST2: Wait States 2 <0-31>
// <o1.10> RBLE: Read Byte Lane Enable
// <o1.26> WP: Write Protect
// <o1.27> BM: Burst ROM
// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
// <2=> 32-bit <3=> Reserved
// </e>
*/
BCFG3_SETUP EQU 0
BCFG3_Val EQU 0x0000FBEF
/*
// </e> End of EMC
*/
// External Memory Pins definitions
PINSEL2 EQU 0xE002C014 /* PINSEL2 Address */
PINSEL2_Val EQU 0x0E6149E4 /* CS0..3, OE, WE, BLS0..3,
D0..31, A2..23, JTAG Pins */
// Starupt Code must be linked first at Address at which it expects to run.
$IF (EXTERNAL_MODE)
CODE_BASE EQU 0x80000000
$ELSE
CODE_BASE EQU 0x00000000
$ENDIF
AREA STARTUPCODE, CODE, AT CODE_BASE // READONLY, ALIGN=4
PUBLIC __startup
EXTERN CODE32 (?C?INIT)
__startup PROC CODE32
// Pre-defined interrupt handlers that may be directly
// overwritten by C interrupt functions
EXTERN CODE32 (Undef_Handler?A)
EXTERN CODE32 (vPortYieldProcessor?A)
EXTERN CODE32 (PAbt_Handler?A)
EXTERN CODE32 (DAbt_Handler?A)
EXTERN CODE32 (IRQ_Handler?A)
EXTERN CODE32 (FIQ_Handler?A)
// Exception Vectors
// Mapped to Address 0.
// Absolute addressing mode must be used.
Vectors: LDR PC,Reset_Addr
LDR PC,Undef_Addr
LDR PC,SWI_Addr
LDR PC,PAbt_Addr
LDR PC,DAbt_Addr
NOP /* Reserved Vector */
; LDR PC,IRQ_Addr
LDR PC,[PC, #-0x0FF0] /* Vector from VicVectAddr */
LDR PC,FIQ_Addr
Reset_Addr: DD Reset_Handler
Undef_Addr: DD Undef_Handler?A
SWI_Addr: DD vPortYieldProcessor?A
PAbt_Addr: DD PAbt_Handler?A
DAbt_Addr: DD DAbt_Handler?A
DD 0 /* Reserved Address */
IRQ_Addr: DD IRQ_Handler?A
FIQ_Addr: DD FIQ_Handler?A
// Reset Handler
Reset_Handler:
$IF (EXTERNAL_MODE)
LDR R0, =PINSEL2
LDR R1, =PINSEL2_Val
STR R1, [R0]
$ENDIF
IF (EMC_SETUP != 0)
LDR R0, =EMC_BASE
IF (BCFG0_SETUP != 0)
LDR R1, =BCFG0_Val
STR R1, [R0, #BCFG0_OFS]
ENDIF
IF (BCFG1_SETUP != 0)
LDR R1, =BCFG1_Val
STR R1, [R0, #BCFG1_OFS]
ENDIF
IF (BCFG2_SETUP != 0)
LDR R1, =BCFG2_Val
STR R1, [R0, #BCFG2_OFS]
ENDIF
IF (BCFG3_SETUP != 0)
LDR R1, =BCFG3_Val
STR R1, [R0, #BCFG3_OFS]
ENDIF
ENDIF
IF (PLL_SETUP != 0)
LDR R0, =PLL_BASE
MOV R1, #0xAA
MOV R2, #0x55
// Configure and Enable PLL
MOV R3, #PLLCFG_Val
STR R3, [R0, #PLLCFG_OFS]
MOV R3, #PLLCON_PLLE
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
// Wait until PLL Locked
PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS]
ANDS R3, R3, #PLLSTAT_PLOCK
BEQ PLL_Loop
// Switch to PLL Clock
MOV R3, #(PLLCON_PLLE | PLLCON_PLLC)
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
ENDIF
IF (MAM_SETUP != 0)
LDR R0, =MAM_BASE
MOV R1, #MAMTIM_Val
STR R1, [R0, #MAMTIM_OFS]
MOV R1, #MAMCR_Val
STR R1, [R0, #MAMCR_OFS]
ENDIF
// Memory Mapping (when Interrupt Vectors are in RAM)
MEMMAP EQU 0xE01FC040 /* Memory Mapping Control */
$IF (RAM_INTVEC)
LDR R0, =MEMMAP
MOV R1, #2
STR R1, [R0]
$ENDIF
// Setup Stack for each mode
LDR R0, =Top_Stack
// Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
// Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
// Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
// Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
// Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
// Enter S Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SYS
MOV SP, R0
// Start in supervisor mode
MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
// Enter the C code
LDR R0,=?C?INIT
TST R0,#1 ; Bit-0 set: INIT is Thumb
LDREQ LR,=exit?A ; ARM Mode
LDRNE LR,=exit?T ; Thumb Mode
BX R0
ENDP
PUBLIC exit?A
exit?A PROC CODE32
B exit?A
ENDP
PUBLIC exit?T
exit?T PROC CODE16
exit: B exit?T
ENDP
END

299
Demo/ARM7_LPC2129_Keil/main.c
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@ -1,299 +0,0 @@
/*
FreeRTOS.org V5.0.4 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
* SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
* and even write all or part of your application on your behalf. *
* See http://www.OpenRTOS.com for details of the services we provide to *
* expedite your project. *
* *
***************************************************************************
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks.
*
* Main.c also creates a task called "Check". This only executes every three
* seconds but has the highest priority so is guaranteed to get processor time.
* Its main function is to check that all the other tasks are still operational.
* Each task (other than the "flash" tasks) maintains a unique count that is
* incremented each time the task successfully completes its function. Should
* any error occur within such a task the count is permanently halted. The
* check task inspects the count of each task to ensure it has changed since
* the last time the check task executed. If all the count variables have
* changed all the tasks are still executing error free, and the check task
* toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo application includes. */
#include "partest.h"
#include "flash.h"
#include "integer.h"
#include "comtest2.h"
#include "serial.h"
#ifdef KEIL_THUMB_INTERWORK
/*
THUMB mode allows more tasks to be created without the executable
binary exceeding the limits allowed by the evaluation version of
uVision3.
*/
#include "PollQ.h"
#include "BlockQ.h"
#include "semtest.h"
#include "dynamic.h"
#endif
/*-----------------------------------------------------------*/
/* Constants to setup I/O and processor. */
#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 )
#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 )
#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 )
#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 )
/* Constants for the ComTest demo application tasks. */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )
#define mainCOM_TEST_LED ( 3 )
/* Priorities for the demo application tasks. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
/* Constants used by the "check" task. As described at the head of this file
the check task toggles an LED. The rate at which the LED flashes is used to
indicate whether an error has been detected or not. If the LED toggles every
3 seconds then no errors have been detected. If the rate increases to 500ms
then an error has been detected in at least one of the demo application tasks. */
#define mainCHECK_LED ( 7 )
#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )
#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )
/*-----------------------------------------------------------*/
/*
* Checks that all the demo application tasks are still executing without error
* - as described at the top of the file.
*/
static portLONG prvCheckOtherTasksAreStillRunning( void );
/*
* The task that executes at the highest priority and calls
* prvCheckOtherTasksAreStillRunning(). See the description at the top
* of the file.
*/
static void vErrorChecks( void *pvParameters );
/*
* Configure the processor for use with the Keil demo board. This is very
* minimal as most of the setup is managed by the settings in the project
* file.
*/
static void prvSetupHardware( void );
/*-----------------------------------------------------------*/
/*
* Application entry point:
* Starts all the other tasks, then starts the scheduler.
*/
int main( void )
{
/* Setup the hardware for use with the Keil demo board. */
prvSetupHardware();
/* Start the demo/test application tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
#ifdef KEIL_THUMB_INTERWORK
/* When using THUMB mode we can start more tasks without the executable
exceeding the size limit imposed by the evaluation version of uVision3. */
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartDynamicPriorityTasks();
#endif
/* Start the check task - which is defined in this file. This is the task
that periodically checks to see that all the other tasks are executing
without error. */
xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Now all the tasks have been started - start the scheduler.
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used here. */
vTaskStartScheduler();
/* Should never reach here! */
return 0;
}
/*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters )
{
portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
/* Parameters are not used. */
( void ) pvParameters;
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. If an error is detected then the delay period
is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
the on board LED flash rate will increase.
This task runs at the highest priority. */
for( ;; )
{
/* The period of the delay depends on whether an error has been
detected or not. If an error has been detected then the period
is reduced to increase the LED flash rate. */
vTaskDelay( xDelayPeriod );
if( prvCheckOtherTasksAreStillRunning() != pdPASS )
{
/* An error has been detected in one of the tasks - flash faster. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
/* Toggle the LED before going back to wait for the next cycle. */
vParTestToggleLED( mainCHECK_LED );
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Perform the hardware setup required. This is minimal as most of the
setup is managed by the settings in the project file. */
/* Configure the RS2332 pins. All other pins remain at their default of 0. */
PINSEL0 |= mainTX_ENABLE;
PINSEL0 |= mainRX_ENABLE;
/* LED pins need to be output. */
IODIR1 = mainLED_TO_OUTPUT;
/* Setup the peripheral bus to be the same as the PLL output. */
VPBDIV = mainBUS_CLK_FULL;
}
/*-----------------------------------------------------------*/
static portLONG prvCheckOtherTasksAreStillRunning( void )
{
portLONG lReturn = pdPASS;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none of them have detected
an error. */
if( xAreIntegerMathsTaskStillRunning() != pdPASS )
{
lReturn = pdFAIL;
}
if( xAreComTestTasksStillRunning() != pdPASS )
{
lReturn = pdFAIL;
}
#ifdef KEIL_THUMB_INTERWORK
/* When using THUMB mode we can start more tasks without the executable
exceeding the size limit imposed by the evaluation version of uVision3. */
if( xArePollingQueuesStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
#endif
return lReturn;
}
/*-----------------------------------------------------------*/

58
Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Opt
View File

@ -1,58 +0,0 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
cExt (*.c)
aExt (*.s*; *.src; *.a*)
oExt (*.obj)
lExt (*.lib)
tExt (*.txt; *.h; *.inc)
pExt (*.plm)
CppX (*.cpp)
DaveTm { 0,0,0,0,0,0,0,0 }
Target (FreeRTOS), 0x0005 // Tools: ''
GRPOPT 1,(ARM_DEMO),1,0,0
OPTFFF 1,1,1,2,0,127,137,0,<.\main.c><main.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,27,0,0,0,27,0,0,0,41,4,0,0,102,2,0,0 }
OPTFFF 1,2,2,0,0,0,0,0,<.\Startup.s><Startup.s>
OPTFFF 1,3,1,0,0,0,0,0,<.\ParTest\ParTest.c><ParTest.c>
OPTFFF 1,4,1,0,0,0,0,0,<.\serial\serial.c><serial.c>
OPTFFF 1,5,1,0,0,0,0,0,<.\serial\serialISR.c><serialISR.c>
OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\tasks.c><tasks.c>
OPTFFF 1,7,1,0,0,0,0,0,<..\..\Source\queue.c><queue.c>
OPTFFF 1,8,1,0,0,0,0,0,<..\..\Source\list.c><list.c>
OPTFFF 1,9,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\port.c><port.c>
OPTFFF 1,10,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\portISR.c><portISR.c>
OPTFFF 1,11,1,0,0,0,0,0,<..\Common\Minimal\flash.c><flash.c>
OPTFFF 1,12,1,16777216,0,0,0,0,<..\Common\Minimal\comtest.c><comtest.c>
OPTFFF 1,13,1,0,0,0,0,0,<..\Common\Minimal\integer.c><integer.c>
OPTFFF 1,14,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c>
TARGOPT 1, (FreeRTOS)
KACLK=12000000
OPTTT 1,1,1,0
OPTHX 0,65535,0,0,0
OPTLX 120,65,8,<.\>
OPTOX 16
OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
OPTXL 1,1,1,1,1,1,1,0,0
OPTFL 1,0,1
OPTBL 0,(Data Sheet)<DATASHTS\PHILIPS\LPC2119_2129.PDF>
OPTBL 1,(User Manual)<DATASHTS\PHILIPS\UM_LPC21XX_LPC22XX.PDF>
OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)
OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
OPTKEY 0,(DLGTARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
OPTKEY 0,(UL2ARM)(-U174073036 -O7 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)
OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
OPTKEY 0,(ARMDBGFLAGS)(-T5F)
OPTMM 1,0,(0x40001800)
OPTDF 0x1000080
OPTLE <>
OPTLC <>
OPTLA 0,((Port1 & 0x10000) >> 16)(FF00FF000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000)
OPTLA 1,((Port1 & 0x20000) >> 17)(FF0000000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000)
OPTLA 2,((Port1 & 0x40000) >> 18)(008000000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000)
OPTLA 3,((Port1 & 0x80000) >> 19)(0000FF000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000)
EndOpt

106
Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Uv2
View File

@ -1,106 +0,0 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (FreeRTOS), 0x0005 // Tools: ''
Group (ARM_DEMO)
File 1,1,<.\main.c><main.c> 0x4162D96A
File 1,2,<.\Startup.s><Startup.s> 0x415AF382
File 1,1,<.\ParTest\ParTest.c><ParTest.c> 0x415AF50E
File 1,1,<.\serial\serial.c><serial.c> 0x4162D488
File 1,1,<.\serial\serialISR.c><serialISR.c> 0x4162D404
File 1,1,<..\..\Source\tasks.c><tasks.c> 0x4162D9E6
File 1,1,<..\..\Source\queue.c><queue.c> 0x411B5F14
File 1,1,<..\..\Source\list.c><list.c> 0x411B5F24
File 1,1,<..\..\Source\portable\Keil\ARM7\port.c><port.c> 0x4162D434
File 1,1,<..\..\Source\portable\Keil\ARM7\portISR.c><portISR.c> 0x415A85E0
File 1,1,<..\Common\Minimal\flash.c><flash.c> 0x411B5F8E
File 1,1,<..\Common\Minimal\comtest.c><comtest.c> 0x413335E6
File 1,1,<..\Common\Minimal\integer.c><integer.c> 0x415FB7EE
File 1,1,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> 0x0
Options 1,0,0 // Target 'FreeRTOS'
Device (LPC2129)
Vendor (Philips)
Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI))
FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1))
StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code"))
FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000))
Rgf (LPC21xx.H)
Mem ()
C ()
A ()
RL ()
OH ()
DBC_IFX ()
DBC_CMS ()
DBC_AMS ()
DBC_LMS ()
UseEnv=0
EnvBin (D:\DevTools\Keil\arm\ARM\BIN\)
EnvInc ()
EnvLib ()
EnvReg (ÿPhilips\)
OrgReg (ÿPhilips\)
TgStat=16
OutDir (.\)
OutName (rtosdemo_ARM)
GenApp=1
GenLib=0
GenHex=0
Debug=1
Browse=0
LstDir (.\)
HexSel=0
MG32K=0
TGMORE=0
RunUsr 0 0 <>
RunUsr 1 0 <>
BrunUsr 0 0 <>
BrunUsr 1 0 <>
SVCSID <>
KACPU (ARM7TDMI)
TKAFL { 0,27,183,0,0,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KIROM { 1,0,0,0,0,0,0,4,0 }
KIRAM { 0,0,0,0,64,0,64,0,0 }
KXRAM { 0,0,0,0,0,0,0,0,0 }
KAOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KCAFLG { 197,132,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KCAMSC (INTERWORK)
KCADEF (KEIL_ARM7)
KCAUDF ()
KCAINC (..\Common\include\;..\..\Source\include\;..\..\Source\portable\Keil\ARM7\)
KAAFLG { 20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KAAMSC ()
KAASET ()
KAARST ()
KAAINC ()
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IncBld=1
AlwaysBuild=0
GenAsm=0
AsmAsm=0
PublicsOnly=0
StopCode=3
CustArgs ()
LibMods ()
KLAFLG { 44,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KLAMSC ()
KLADWN (25)
KLACFI ()
KLAASN ()
KLARES ()
KLACCL ()
KLAUCL ()
KLACSC ()
KLAUCS ()
OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)
OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
FLASH1 { 1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
FLASH2 (BIN\UL2ARM.DLL)
FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1))
FLASH4 ()
EndOpt

63
Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Opt
View File

@ -1,63 +0,0 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
cExt (*.c)
aExt (*.s*; *.src; *.a*)
oExt (*.obj)
lExt (*.lib)
tExt (*.txt; *.h; *.inc)
pExt (*.plm)
CppX (*.cpp)
DaveTm { 0,0,0,0,0,0,0,0 }
Target (FreeRTOS), 0x0005 // Tools: ''
GRPOPT 1,(THUMB_DEMO),1,0,0
OPTFFF 1,1,1,1,0,121,137,0,<.\main.c><main.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,0,0,0,0,0,0,0,0,14,4,0,0,75,2,0,0 }
OPTFFF 1,2,2,0,0,0,0,0,<.\Startup.s><Startup.s>
OPTFFF 1,3,1,1040187392,0,0,0,0,<.\ParTest\ParTest.c><ParTest.c>
OPTFFF 1,4,1,0,0,0,0,0,<.\serial\serial.c><serial.c>
OPTFFF 1,5,1,0,0,0,0,0,<.\serial\serialISR.c><serialISR.c>
OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\tasks.c><tasks.c>
OPTFFF 1,7,1,0,0,0,0,0,<..\..\Source\queue.c><queue.c>
OPTFFF 1,8,1,0,0,0,0,0,<..\..\Source\list.c><list.c>
OPTFFF 1,9,1,553648128,0,0,0,0,<..\..\Source\portable\Keil\ARM7\port.c><port.c>
OPTFFF 1,10,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\portISR.c><portISR.c>
OPTFFF 1,11,1,0,0,0,0,0,<..\Common\Minimal\BlockQ.c><BlockQ.c>
OPTFFF 1,12,1,402653184,0,0,0,0,<..\Common\Minimal\semtest.c><semtest.c>
OPTFFF 1,13,1,0,0,0,0,0,<..\Common\Minimal\PollQ.c><PollQ.c>
OPTFFF 1,14,1,0,0,0,0,0,<..\Common\Minimal\flash.c><flash.c>
OPTFFF 1,15,1,0,0,0,0,0,<..\Common\Minimal\comtest.c><comtest.c>
OPTFFF 1,16,1,0,0,0,0,0,<..\Common\Minimal\integer.c><integer.c>
OPTFFF 1,17,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c>
OPTFFF 1,18,1,0,0,0,0,0,<..\Common\Minimal\dynamic.c><dynamic.c>
ExtF <..\..\SOURCE\PORTABLE\KEIL\ARM7\PORTMACRO.H> 127,127,0,{ 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,27,0,0,0,27,0,0,0,72,4,0,0,33,2,0,0 }
TARGOPT 1, (FreeRTOS)
KACLK=12000000
OPTTT 1,1,1,0
OPTHX 0,65535,0,0,0
OPTLX 120,65,8,<.\>
OPTOX 16
OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
OPTXL 1,1,1,1,1,1,1,0,0
OPTFL 1,0,1
OPTBL 0,(Data Sheet)<DATASHTS\PHILIPS\LPC2119_2129.PDF>
OPTBL 1,(User Manual)<DATASHTS\PHILIPS\UM_LPC21XX_LPC22XX.PDF>
OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)
OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
OPTKEY 0,(DLGTARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
OPTKEY 0,(UL2ARM)(-U170927308 -O7 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)
OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
OPTKEY 0,(ARMDBGFLAGS)(-T5F)
OPTMM 1,0,(0x40000840)
OPTDF 0x1000086
OPTLE <>
OPTLC <>
OPTLA 0,((Port1 & 0x10000) >> 16)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000)
OPTLA 1,((Port1 & 0x20000) >> 17)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000)
OPTLA 2,((Port1 & 0x40000) >> 18)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000)
OPTLA 3,((Port1 & 0x80000) >> 19)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000)
EndOpt

110
Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Uv2
View File

@ -1,110 +0,0 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (FreeRTOS), 0x0005 // Tools: ''
Group (THUMB_DEMO)
File 1,1,<.\main.c><main.c> 0x4162D96A
File 1,2,<.\Startup.s><Startup.s> 0x415AF382
File 1,1,<.\ParTest\ParTest.c><ParTest.c> 0x415AF50E
File 1,1,<.\serial\serial.c><serial.c> 0x4162D488
File 1,1,<.\serial\serialISR.c><serialISR.c> 0x4162D404
File 1,1,<..\..\Source\tasks.c><tasks.c> 0x4162D9E6
File 1,1,<..\..\Source\queue.c><queue.c> 0x411B5F14
File 1,1,<..\..\Source\list.c><list.c> 0x411B5F24
File 1,1,<..\..\Source\portable\Keil\ARM7\port.c><port.c> 0x4162D434
File 1,1,<..\..\Source\portable\Keil\ARM7\portISR.c><portISR.c> 0x415A85E0
File 1,1,<..\Common\Minimal\BlockQ.c><BlockQ.c> 0x411B5F8C
File 1,1,<..\Common\Minimal\semtest.c><semtest.c> 0x411B5F8C
File 1,1,<..\Common\Minimal\PollQ.c><PollQ.c> 0x411B5F8E
File 1,1,<..\Common\Minimal\flash.c><flash.c> 0x411B5F8E
File 1,1,<..\Common\Minimal\comtest.c><comtest.c> 0x413335E6
File 1,1,<..\Common\Minimal\integer.c><integer.c> 0x415FB7EE
File 1,1,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> 0x0
File 1,1,<..\Common\Minimal\dynamic.c><dynamic.c> 0x0
Options 1,0,0 // Target 'FreeRTOS'
Device (LPC2129)
Vendor (Philips)
Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI))
FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1))
StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code"))
FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000))
Rgf (LPC21xx.H)
Mem ()
C ()
A ()
RL ()
OH ()
DBC_IFX ()
DBC_CMS ()
DBC_AMS ()
DBC_LMS ()
UseEnv=0
EnvBin (D:\DevTools\Keil\arm\ARM\BIN\)
EnvInc ()
EnvLib ()
EnvReg (ÿPhilips\)
OrgReg (ÿPhilips\)
TgStat=16
OutDir (.\)
OutName (rtosdemo_THUMB)
GenApp=1
GenLib=0
GenHex=0
Debug=1
Browse=0
LstDir (.\)
HexSel=0
MG32K=0
TGMORE=0
RunUsr 0 0 <>
RunUsr 1 0 <>
BrunUsr 0 0 <>
BrunUsr 1 0 <>
SVCSID <>
KACPU (ARM7TDMI)
TKAFL { 0,27,183,0,0,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KIROM { 1,0,0,0,0,0,0,4,0 }
KIRAM { 0,0,0,0,64,0,64,0,0 }
KXRAM { 0,0,0,0,0,0,0,0,0 }
KAOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KCAFLG { 197,156,20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KCAMSC (INTERWORK)
KCADEF (KEIL_ARM7 KEIL_THUMB_INTERWORK)
KCAUDF ()
KCAINC (..\Common\include\;..\..\Source\include\;..\..\Source\portable\Keil\ARM7\)
KAAFLG { 20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KAAMSC ()
KAASET ()
KAARST ()
KAAINC ()
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IncBld=1
AlwaysBuild=0
GenAsm=0
AsmAsm=0
PublicsOnly=0
StopCode=3
CustArgs ()
LibMods ()
KLAFLG { 44,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KLAMSC ()
KLADWN (25)
KLACFI ()
KLAASN ()
KLARES ()
KLACCL ()
KLAUCL ()
KLACSC ()
KLAUCS ()
OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)
OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
FLASH1 { 1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
FLASH2 (BIN\UL2ARM.DLL)
FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1))
FLASH4 ()
EndOpt

264
Demo/ARM7_LPC2129_Keil/serial/serial.c
View File

@ -1,264 +0,0 @@
/*
FreeRTOS.org V5.0.4 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
* SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
* and even write all or part of your application on your behalf. *
* See http://www.OpenRTOS.com for details of the services we provide to *
* expedite your project. *
* *
***************************************************************************
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
This file contains all the serial port components that can be compiled to
either ARM or THUMB mode. Components that must be compiled to ARM mode are
contained in serialISR.c.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Constants to setup and access the UART. */
#define serDLAB ( ( unsigned portCHAR ) 0x80 )
#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 )
#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 )
#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 )
#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 )
#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 )
#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 )
#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 )
/* Constants to setup and access the VIC. */
#define serU0VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 )
#define serU0VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 )
#define serU0VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )
/* Misc. */
#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
#define serHANDLE ( ( xComPortHandle ) 1 )
#define serNO_BLOCK ( ( portTickType ) 0 )
/*-----------------------------------------------------------*/
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
/*-----------------------------------------------------------*/
/* Communication flag between the interrupt service routine and serial API. */
static volatile portLONG *plTHREEmpty;
/*
* The queues are created in serialISR.c as they are used from the ISR.
* Obtain references to the queues and THRE Empty flag.
*/
extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag );
/*-----------------------------------------------------------*/
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
unsigned portLONG ulDivisor, ulWantedClock;
xComPortHandle xReturn = serHANDLE;
/* The queues are used in the serial ISR routine, so are created from
serialISR.c (which is always compiled to ARM mode). */
vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx, &plTHREEmpty );
if(
( xRxedChars != serINVALID_QUEUE ) &&
( xCharsForTx != serINVALID_QUEUE ) &&
( ulWantedBaud != ( unsigned portLONG ) 0 )
)
{
portENTER_CRITICAL();
{
/* The reference to the ISR function is required to load into the
interrupt controller. The prototype is slightly different
depending on whether in ARM or THUMB mode. */
#ifdef KEIL_THUMB_INTERWORK
extern void ( vUART_ISR )( void ) __arm __task;
#else
extern void ( vUART_ISR )( void ) __task;
#endif
/* Setup the baud rate: Calculate the divisor value. */
ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;
ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;
/* Set the DLAB bit so we can access the divisor. */
U0LCR |= serDLAB;
/* Setup the divisor. */
U0DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
ulDivisor >>= 8;
U0DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
/* Turn on the FIFO's and clear the buffers. */
U0FCR = ( serFIFO_ON | serCLEAR_FIFO );
/* Setup transmission format. */
U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;
/* Setup the VIC for the UART. */
VICIntSelect &= ~( serU0VIC_CHANNEL_BIT );
VICIntEnable |= serU0VIC_CHANNEL_BIT;
VICVectAddr1 = ( unsigned portLONG ) vUART_ISR;
VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE;
/* Enable UART0 interrupts. */
U0IER |= serENABLE_INTERRUPTS;
}
portEXIT_CRITICAL();
}
else
{
xReturn = ( xComPortHandle ) 0;
}
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
{
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
{
signed portCHAR *pxNext;
/* NOTE: This implementation does not handle the queue being full as no
block time is used! */
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
( void ) usStringLength;
/* Send each character in the string, one at a time. */
pxNext = ( signed portCHAR * ) pcString;
while( *pxNext )
{
xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
pxNext++;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
{
signed portBASE_TYPE xReturn;
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
portENTER_CRITICAL();
{
/* Is there space to write directly to the UART? */
if( *plTHREEmpty == ( portLONG ) pdTRUE )
{
/* We wrote the character directly to the UART, so was
successful. */
*plTHREEmpty = pdFALSE;
U0THR = cOutChar;
xReturn = pdPASS;
}
else
{
/* We cannot write directly to the UART, so queue the character.
Block for a maximum of xBlockTime if there is no space in the
queue. It is ok to block within a critical section as each
task has it's own critical section management. */
xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
/* Depending on queue sizing and task prioritisation: While we
were blocked waiting to post interrupts were not disabled. It is
possible that the serial ISR has emptied the Tx queue, in which
case we need to start the Tx off again. */
if( *plTHREEmpty == ( portLONG ) pdTRUE )
{
xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
*plTHREEmpty = pdFALSE;
U0THR = cOutChar;
}
}
}
portEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/

173
Demo/ARM7_LPC2129_Keil/serial/serialISR.c
View File

@ -1,173 +0,0 @@
/*
FreeRTOS.org V5.0.4 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
* SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
* and even write all or part of your application on your behalf. *
* See http://www.OpenRTOS.com for details of the services we provide to *
* expedite your project. *
* *
***************************************************************************
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
This file contains all the serial port components that must be compiled
to ARM mode. The components that can be compiled to either ARM or THUMB
mode are contained in serial.c.
*/
/* This file must always be compiled to ARM mode as it contains ISR
definitions. */
#pragma ARM
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Constant to access the VIC. */
#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
/* Constants to determine the ISR source. */
#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 )
#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c )
#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 )
#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 )
#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f )
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
static volatile portLONG lTHREEmpty;
/*-----------------------------------------------------------*/
/* UART0 interrupt service routine. This can cause a context switch so MUST
be declared "naked". */
void vUART_ISR( void );
/*-----------------------------------------------------------*/
void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars,
xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag )
{
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
/* Pass back a reference to the queues so the serial API file can
post/receive characters. */
*pxRxedChars = xRxedChars;
*pxCharsForTx = xCharsForTx;
/* Initialise the THRE empty flag - and pass back a reference. */
lTHREEmpty = pdTRUE;
*pplTHREEmptyFlag = &lTHREEmpty;
}
/*-----------------------------------------------------------*/
void vUART_ISR( void ) __task
{
portENTER_SWITCHING_ISR()
/* Now we can declare the local variables. */
static signed portCHAR cChar;
static portBASE_TYPE xHigherPriorityTaskWoken;
xHigherPriorityTaskWoken = pdFALSE;
/* What caused the interrupt? */
switch( U0IIR & serINTERRUPT_SOURCE_MASK )
{
case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */
cChar = U0LSR;
break;
case serSOURCE_THRE : /* The THRE is empty. If there is another
character in the Tx queue, send it now. */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
{
U0THR = cChar;
}
else
{
/* There are no further characters
queued to send so we can indicate
that the THRE is available. */
lTHREEmpty = pdTRUE;
}
break;
case serSOURCE_RX_TIMEOUT :
case serSOURCE_RX : /* A character was received. Place it in
the queue of received characters. */
cChar = U0RBR;
xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
break;
default : /* There is nothing to do, leave the ISR. */
break;
}
/* Clear the ISR in the VIC. */
VICVectAddr = serCLEAR_VIC_INTERRUPT;
/* Exit the ISR. If a task was woken by either a character being received
or transmitted then a context switch will occur. */
portEXIT_SWITCHING_ISR( xHigherPriorityTaskWoken );
}
/*-----------------------------------------------------------*/