Revert critical section handling back to the original method.

This commit is contained in:
Richard Barry 2008-02-15 13:33:44 +00:00
parent 991624461f
commit 61efe2504c
3 changed files with 20 additions and 65 deletions

View File

@ -78,6 +78,12 @@
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Critical section management. */ /* Critical section management. */
#if configKERNEL_INTERRUPT_PRIORITY != 30
#error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - 30 (1Eh) being the default.
#endif
#define portDISABLE_INTERRUPTS() __asm(" STILM #1Eh ")
#define portENABLE_INTERRUPTS() __asm(" MOVL ILM, #1Fh ")
#define portENTER_CRITICAL() \ #define portENTER_CRITICAL() \
__asm(" ST PS,@-R15 "); \ __asm(" ST PS,@-R15 "); \
__asm(" ANDCCR #0xef "); \ __asm(" ANDCCR #0xef "); \
@ -86,9 +92,6 @@
#define portEXIT_CRITICAL() \ #define portEXIT_CRITICAL() \
__asm(" LD @R15+,PS "); \ __asm(" LD @R15+,PS "); \
#define portDISABLE_INTERRUPTS() __DI();
#define portENABLE_INTERRUPTS() __EI();
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Architecture specifics. */ /* Architecture specifics. */

View File

@ -73,10 +73,6 @@ static void prvSetupRLT0Interrupt( void );
typedef void tskTCB; typedef void tskTCB;
extern volatile tskTCB * volatile pxCurrentTCB; extern volatile tskTCB * volatile pxCurrentTCB;
/* Constants required to handle critical sections. */
#define portNO_CRITICAL_NESTING ( ( unsigned portBASE_TYPE ) 0 )
volatile unsigned portBASE_TYPE uxCriticalNesting = 9999UL;
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* /*
@ -116,11 +112,6 @@ volatile unsigned portBASE_TYPE uxCriticalNesting = 9999UL;
__asm(" AND CCR,#H'DF "); \ __asm(" AND CCR,#H'DF "); \
__asm(" PUSHW A "); \ __asm(" PUSHW A "); \
__asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ __asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \
\
/* Save the critical nesting count to the stack. */ \
__asm(" MOVW RW0, _uxCriticalNesting "); \
__asm(" PUSHW (RW0) "); \
\
__asm(" MOVW A, _pxCurrentTCB "); \ __asm(" MOVW A, _pxCurrentTCB "); \
__asm(" MOVW A, SP "); \ __asm(" MOVW A, SP "); \
__asm(" SWAPW "); \ __asm(" SWAPW "); \
@ -143,13 +134,6 @@ volatile unsigned portBASE_TYPE uxCriticalNesting = 9999UL;
__asm(" MOVW A, @A "); \ __asm(" MOVW A, @A "); \
__asm(" AND CCR,#H'DF "); \ __asm(" AND CCR,#H'DF "); \
__asm(" MOVW SP, A "); \ __asm(" MOVW SP, A "); \
\
/* Load the saved uxCriticalNesting value into RW0. */ \
__asm(" POPW (RW0) "); \
\
/* Save the loaded value into the uxCriticalNesting variable. */ \
__asm(" MOVW _uxCriticalNesting, RW0 "); \
\
__asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ __asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \
__asm(" POPW A "); \ __asm(" POPW A "); \
__asm(" OR CCR,#H'20 "); \ __asm(" OR CCR,#H'20 "); \
@ -203,11 +187,6 @@ volatile unsigned portBASE_TYPE uxCriticalNesting = 9999UL;
__asm(" AND CCR,#H'DF "); \ __asm(" AND CCR,#H'DF "); \
__asm(" PUSHW A "); \ __asm(" PUSHW A "); \
__asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ __asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \
\
/* Save the critical nesting count to the stack. */ \
__asm(" MOVW RW0, _uxCriticalNesting "); \
__asm(" PUSHW (RW0) "); \
\
__asm(" MOVL A, _pxCurrentTCB "); \ __asm(" MOVL A, _pxCurrentTCB "); \
__asm(" MOVL RL2, A "); \ __asm(" MOVL RL2, A "); \
__asm(" MOVW A, SP "); \ __asm(" MOVW A, SP "); \
@ -224,13 +203,6 @@ volatile unsigned portBASE_TYPE uxCriticalNesting = 9999UL;
__asm(" MOVW SP, A "); \ __asm(" MOVW SP, A "); \
__asm(" MOV A, @RL2+2 "); \ __asm(" MOV A, @RL2+2 "); \
__asm(" MOV USB, A "); \ __asm(" MOV USB, A "); \
\
/* Load the saved uxCriticalNesting value into RW0. */ \
__asm(" POPW (RW0) "); \
\
/* Save the loaded value into the uxCriticalNesting variable. */ \
__asm(" MOVW _uxCriticalNesting, RW0 "); \
\
__asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ __asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \
__asm(" POPW A "); \ __asm(" POPW A "); \
__asm(" OR CCR,#H'20 "); \ __asm(" OR CCR,#H'20 "); \
@ -398,11 +370,6 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE
*pxTopOfStack = ( portSTACK_TYPE ) 0x1111; /* RW1 */ *pxTopOfStack = ( portSTACK_TYPE ) 0x1111; /* RW1 */
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x8888; /* RW0 */ *pxTopOfStack = ( portSTACK_TYPE ) 0x8888; /* RW0 */
pxTopOfStack--;
/* The task starts with its uxCriticalNesting variable set to 0, interrupts
being enabled. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
return pxTopOfStack; return pxTopOfStack;
} }
@ -554,28 +521,3 @@ __nosavereg __interrupt void vPortYieldDelayed( void )
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
/* Disable interrupts */
portDISABLE_INTERRUPTS();
/* Now interrupts are disabled uxCriticalNesting can be accessed
directly. Increment uxCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
uxCriticalNesting++;
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
if( uxCriticalNesting > portNO_CRITICAL_NESTING )
{
uxCriticalNesting--;
if( uxCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Enable all interrupt/exception. */
portENABLE_INTERRUPTS();
}
}
}
/*-----------------------------------------------------------*/

View File

@ -87,10 +87,20 @@ FreeRTOSConfig.h to set the configMEMMODEL value. */
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Critical section handling. */ /* Critical section handling. */
#define portDISABLE_INTERRUPTS() __DI(); #if configKERNEL_INTERRUPT_PRIORITY != 6
#define portENABLE_INTERRUPTS() __EI(); #error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - #06H being the default.
#define portENTER_CRITICAL() vPortEnterCritical() #endif
#define portEXIT_CRITICAL() vPortExitCritical() #define portENABLE_INTERRUPTS() __asm(" MOV ILM, #06h ")
#define portDISABLE_INTERRUPTS() __asm(" MOV ILM, #07h ")
#define portENTER_CRITICAL() \
{ __asm(" PUSHW PS "); \
portDISABLE_INTERRUPTS(); \
}
#define portEXIT_CRITICAL() \
{ __asm(" POPW PS "); \
}
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/