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Added PPC440 demo that does not use any floating point hardware.

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This commit is contained in:
Richard Barry 2009-06-30 19:42:21 +00:00
parent b49cf69600
commit 3634ebb497
113 changed files with 26580 additions and 0 deletions
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115
Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h Normal file
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/*
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License (version 2) as published
by the Free Software Foundation and modified by the FreeRTOS exception.
**NOTE** The exception to the GPL is included to allow you to distribute a
combined work that includes FreeRTOS.org without being obliged to provide
the source code for any proprietary components. Alternative commercial
license and support terms are also available upon request. See the
licensing section of http://www.FreeRTOS.org for full details.
FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along
with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
Temple Place, Suite 330, Boston, MA 02111-1307 USA.
***************************************************************************
* *
* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
* *
* This is a concise, step by step, 'hands on' guide that describes both *
* general multitasking concepts and FreeRTOS specifics. It presents and *
* explains numerous examples that are written using the FreeRTOS API. *
* Full source code for all the examples is provided in an accompanying *
* .zip file. *
* *
***************************************************************************
1 tab == 4 spaces!
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 250 )
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 200000000 ) /* Clock setup from start.asm in the demo application. */
#define configTICK_RATE_HZ ( (portTickType) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 )
#define configTOTAL_HEAP_SIZE ( (size_t) (80 * 1024) )
#define configMAX_TASK_NAME_LEN ( 20 )
#define configUSE_16_BIT_TICKS 1
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configUSE_TRACE_FACILITY 0
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_APPLICATION_TASK_TAG 1
#define configUSE_FPU 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 4 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vResumeFromISR 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_uxTaskGetStackHighWaterMark 1
#define configUSE_RECURSIVE_MUTEXES 1
#if configUSE_FPU == 1
/* Include the header that define the traceTASK_SWITCHED_IN() and
traceTASK_SWITCHED_OUT() macros to save and restore the floating
point registers for tasks that have requested this behaviour. */
#include "FPU_Macros.h"
#endif
#endif /* FREERTOS_CONFIG_H */

226
Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld Normal file
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/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: Xilinx EDK 11.1 EDK_L.29.1 */
/* */
/* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */
/* */
/* Description : PowerPC440 Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;
/* Define Memories in the system */
MEMORY
{
DDR2_SDRAM_C_MEM_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x10000000
SRAM_C_MEM0_BASEADDR : ORIGIN = 0xF8000000, LENGTH = 0x00100000
xps_bram_if_cntlr_1 : ORIGIN = 0xFFFFE000, LENGTH = 0x00001F00
}
/* Specify the default entry point to the program */
ENTRY(_boot)
STARTUP(boot.o)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.vectors : {
__vectors_start = .;
*(.vectors)
__vectors_end = .;
} > SRAM_C_MEM0_BASEADDR
.text : {
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
} > SRAM_C_MEM0_BASEADDR
.init : {
KEEP (*(.init))
} > SRAM_C_MEM0_BASEADDR
.fini : {
KEEP (*(.fini))
} > SRAM_C_MEM0_BASEADDR
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > SRAM_C_MEM0_BASEADDR
.rodata1 : {
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > SRAM_C_MEM0_BASEADDR
.sdata2 : {
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > SRAM_C_MEM0_BASEADDR
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > SRAM_C_MEM0_BASEADDR
.data : {
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
__data_end = .;
} > SRAM_C_MEM0_BASEADDR
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > SRAM_C_MEM0_BASEADDR
.got : {
*(.got)
} > SRAM_C_MEM0_BASEADDR
.got1 : {
*(.got1)
} > SRAM_C_MEM0_BASEADDR
.got2 : {
*(.got2)
} > SRAM_C_MEM0_BASEADDR
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > SRAM_C_MEM0_BASEADDR
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > SRAM_C_MEM0_BASEADDR
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > SRAM_C_MEM0_BASEADDR
.eh_frame : {
*(.eh_frame)
} > SRAM_C_MEM0_BASEADDR
.jcr : {
*(.jcr)
} > SRAM_C_MEM0_BASEADDR
.gcc_except_table : {
*(.gcc_except_table)
} > SRAM_C_MEM0_BASEADDR
.sdata : {
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > SRAM_C_MEM0_BASEADDR
.sbss : {
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
__sbss_end = .;
} > SRAM_C_MEM0_BASEADDR
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > SRAM_C_MEM0_BASEADDR
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > SRAM_C_MEM0_BASEADDR
.bss : {
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
__bss_end = .;
} > SRAM_C_MEM0_BASEADDR
.boot0 0xFFFFFF00 : {
__boot0_start = .;
*(.boot0)
__boot0_end = .;
}
.boot 0xFFFFFFFC : {
__boot_start = .;
*(.boot)
__boot_end = .;
}
/* Generate Stack and Heap Sections */
.stack : {
_stack_end = .;
. += _STACK_SIZE;
. = ALIGN(16);
__stack = .;
} > SRAM_C_MEM0_BASEADDR
.heap : {
. = ALIGN(16);
_heap_start = .;
. += _HEAP_SIZE;
. = ALIGN(16);
_heap_end = .;
_end = .;
} > SRAM_C_MEM0_BASEADDR
}

246
Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c Normal file
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/*
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License (version 2) as published
by the Free Software Foundation and modified by the FreeRTOS exception.
**NOTE** The exception to the GPL is included to allow you to distribute a
combined work that includes FreeRTOS.org without being obliged to provide
the source code for any proprietary components. Alternative commercial
license and support terms are also available upon request. See the
licensing section of http://www.FreeRTOS.org for full details.
FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along
with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
Temple Place, Suite 330, Boston, MA 02111-1307 USA.
***************************************************************************
* *
* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
* *
* This is a concise, step by step, 'hands on' guide that describes both *
* general multitasking concepts and FreeRTOS specifics. It presents and *
* explains numerous examples that are written using the FreeRTOS API. *
* Full source code for all the examples is provided in an accompanying *
* .zip file. *
* *
***************************************************************************
1 tab == 4 spaces!
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
* Tests the floating point context save and restore mechanism.
*
* Two tasks are created - each of which is allocated a buffer of
* portNO_FLOP_REGISTERS_TO_SAVE 32bit variables into which the flop context
* of the task is saved when the task is switched out, and from which the
* flop context of the task is restored when the task is switch in. Prior to
* the tasks being created each position in the two buffers is filled with a
* unique value - this way the flop context of each task is different.
*
* The two test tasks never block so are always in either the Running or
* Ready state. They execute at the lowest priority so will get pre-empted
* regularly, although the yield frequently so will not get much execution
* time. The lack of execution time is not a problem as its only the
* switching in and out that is being tested.
*
* Whenever a task is moved from the Ready to the Running state its flop
* context will be loaded from the buffer, but while the task is in the
* Running state the buffer is not used and can contain any value - in this
* case and for test purposes the task itself clears the buffer to zero.
* The next time the task is moved out of the Running state into the
* Ready state the flop context will once more get saved to the buffer -
* overwriting the zeros.
*
* Therefore whenever the task is not in the Running state its buffer contains
* the most recent values of its floating point registers - the zeroing out
* of the buffer while the task was executing being used to ensure the values
* the buffer contains are not stale.
*
* When neither test task is in the Running state the buffers should contain
* the unique values allocated before the tasks were created. If so then
* the floating point context has been maintained. This check is performed
* by the 'check' task (defined in main.c) by calling
* xAreFlopRegisterTestsStillRunning().
*
* The test tasks also increment a value each time they execute.
* xAreFlopRegisterTestsStillRunning() also checks that this value has changed
* since it last ran to ensure the test tasks are still getting processing time.
*/
/* Standard includes files. */
#include <string.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/*-----------------------------------------------------------*/
#define flopNUMBER_OF_TASKS 2
#define flopSTART_VALUE ( 0x1 )
/*-----------------------------------------------------------*/
/* The two test tasks as described at the top of this file. */
static void vFlopTest1( void *pvParameters );
static void vFlopTest2( void *pvParameters );
/*-----------------------------------------------------------*/
/* Buffers into which the flop registers will be saved. There is a buffer for
both tasks. */
static volatile unsigned portLONG ulFlopRegisters[ flopNUMBER_OF_TASKS ][ portNO_FLOP_REGISTERS_TO_SAVE ];
/* Variables that are incremented by the tasks to indicate that they are still
running. */
static volatile unsigned portLONG ulFlop1CycleCount = 0, ulFlop2CycleCount = 0;
/*-----------------------------------------------------------*/
void vStartFlopRegTests( void )
{
xTaskHandle xTaskJustCreated;
unsigned portBASE_TYPE x, y, z = flopSTART_VALUE;
/* Fill the arrays into which the flop registers are to be saved with
known values. These are the values that will be written to the flop
registers when the tasks start, and as the tasks do not perform any
flop operations the values should never change. Each position in the
buffer contains a different value so the flop context of each task
will be different. */
for( x = 0; x < flopNUMBER_OF_TASKS; x++ )
{
for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1); y++ )
{
ulFlopRegisters[ x ][ y ] = z;
z++;
}
}
/* Create the first task. */
xTaskCreate( vFlopTest1, ( signed portCHAR * ) "flop1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTaskJustCreated );
/* The task tag value is a value that can be associated with a task, but
is not used by the scheduler itself. Its use is down to the application so
it makes a convenient place in this case to store the pointer to the buffer
into which the flop context of the task will be stored. The first created
task uses ulFlopRegisters[ 0 ], the second ulFlopRegisters[ 1 ]. */
vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 0 ][ 0 ] ) );
/* Do the same for the second task. */
xTaskCreate( vFlopTest2, ( signed portCHAR * ) "flop2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTaskJustCreated );
vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 1 ][ 0 ] ) );
}
/*-----------------------------------------------------------*/
static void vFlopTest1( void *pvParameters )
{
/* Just to remove compiler warning. */
( void ) pvParameters;
for( ;; )
{
/* The values from the buffer should have now been written to the flop
registers. Clear the buffer to ensure the same values then get written
back the next time the task runs. Being preempted during this memset
could cause the test to fail, hence the critical section. */
portENTER_CRITICAL();
memset( ( void * ) ulFlopRegisters[ 0 ], 0x00, ( portNO_FLOP_REGISTERS_TO_SAVE * sizeof( unsigned portBASE_TYPE ) ) );
portEXIT_CRITICAL();
/* We don't have to do anything other than indicate that we are
still running. */
ulFlop1CycleCount++;
taskYIELD();
}
}
/*-----------------------------------------------------------*/
static void vFlopTest2( void *pvParameters )
{
/* Just to remove compiler warning. */
( void ) pvParameters;
for( ;; )
{
/* The values from the buffer should have now been written to the flop
registers. Clear the buffer to ensure the same values then get written
back the next time the task runs. */
portENTER_CRITICAL();
memset( ( void * ) ulFlopRegisters[ 1 ], 0x00, ( portNO_FLOP_REGISTERS_TO_SAVE * sizeof( unsigned portBASE_TYPE ) ) );
portEXIT_CRITICAL();
/* We don't have to do anything other than indicate that we are
still running. */
ulFlop2CycleCount++;
taskYIELD();
}
}
/*-----------------------------------------------------------*/
portBASE_TYPE xAreFlopRegisterTestsStillRunning( void )
{
portBASE_TYPE xReturn = pdPASS;
unsigned portBASE_TYPE x, y, z = flopSTART_VALUE;
static unsigned portLONG ulLastFlop1CycleCount = 0, ulLastFlop2CycleCount = 0;
/* Called from the 'check' task.
The flop tasks cannot be currently running, check their saved registers
are as expected. The tests tasks do not perform any flop operations so
their registers should be as per their initial setting. */
for( x = 0; x < flopNUMBER_OF_TASKS; x++ )
{
for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1 ); y++ )
{
if( ulFlopRegisters[ x ][ y ] != z )
{
xReturn = pdFAIL;
break;
}
z++;
}
}
/* Check both tasks have actually been swapped in and out since this function
last executed. */
if( ulFlop1CycleCount == ulLastFlop1CycleCount )
{
xReturn = pdFAIL;
}
if( ulFlop2CycleCount == ulLastFlop2CycleCount )
{
xReturn = pdFAIL;
}
ulLastFlop1CycleCount = ulFlop1CycleCount;
ulLastFlop2CycleCount = ulFlop2CycleCount;
return xReturn;
}

58
Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h Normal file
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/*
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License (version 2) as published
by the Free Software Foundation and modified by the FreeRTOS exception.
**NOTE** The exception to the GPL is included to allow you to distribute a
combined work that includes FreeRTOS.org without being obliged to provide
the source code for any proprietary components. Alternative commercial
license and support terms are also available upon request. See the
licensing section of http://www.FreeRTOS.org for full details.
FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along
with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
Temple Place, Suite 330, Boston, MA 02111-1307 USA.
***************************************************************************
* *
* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
* *
* This is a concise, step by step, 'hands on' guide that describes both *
* general multitasking concepts and FreeRTOS specifics. It presents and *
* explains numerous examples that are written using the FreeRTOS API. *
* Full source code for all the examples is provided in an accompanying *
* .zip file. *
* *
***************************************************************************
1 tab == 4 spaces!
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef FLOP_REG_TEST_H
#define FLOP_REG_TEST_H
void vStartFlopRegTests( void );
portBASE_TYPE xAreFlopRegisterTestsStillRunning( void );
#endif

402
Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c Normal file
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/*
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License (version 2) as published
by the Free Software Foundation and modified by the FreeRTOS exception.
**NOTE** The exception to the GPL is included to allow you to distribute a
combined work that includes FreeRTOS.org without being obliged to provide
the source code for any proprietary components. Alternative commercial
license and support terms are also available upon request. See the
licensing section of http://www.FreeRTOS.org for full details.
FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along
with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
Temple Place, Suite 330, Boston, MA 02111-1307 USA.
***************************************************************************
* *
* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
* *
* This is a concise, step by step, 'hands on' guide that describes both *
* general multitasking concepts and FreeRTOS specifics. It presents and *
* explains numerous examples that are written using the FreeRTOS API. *
* Full source code for all the examples is provided in an accompanying *
* .zip file. *
* *
***************************************************************************
1 tab == 4 spaces!
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
* Creates eight tasks, each of which loops continuously performing a
* floating point calculation.
*
* All the tasks run at the idle priority and never block or yield. This causes
* all eight tasks to time slice with the idle task. Running at the idle priority
* means that these tasks will get pre-empted any time another task is ready to run
* or a time slice occurs. More often than not the pre-emption will occur mid
* calculation, creating a good test of the schedulers context switch mechanism - a
* calculation producing an unexpected result could be a symptom of a corruption in
* the context of a task.
*
* This file demonstrates the use of the task tag and traceTASK_SWITCHED_IN and
* traceTASK_SWITCHED_OUT macros to save and restore the floating point context.
*/
#include <stdlib.h>
#include <math.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo program include files. */
#include "flop.h"
/* Misc. definitions. */
#define mathSTACK_SIZE configMINIMAL_STACK_SIZE
#define mathNUMBER_OF_TASKS ( 8 )
/* Four tasks, each of which performs a different floating point calculation.
Each of the four is created twice. */
static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters );
static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters );
static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters );
static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters );
/* These variables are used to check that all the tasks are still running. If a
task gets a calculation wrong it will stop incrementing its check variable. */
static volatile unsigned portSHORT usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 };
/* Buffers into which the flop registers will be saved. There is a buffer for
each task created within this file. Zeroing out this array is the normal and
safe option as this will cause the task to start with all zeros in its flop
context. */
static unsigned portLONG ulFlopRegisters[ mathNUMBER_OF_TASKS ][ portNO_FLOP_REGISTERS_TO_SAVE ];
/*-----------------------------------------------------------*/
void vStartMathTasks( unsigned portBASE_TYPE uxPriority )
{
xTaskHandle xTaskJustCreated;
portBASE_TYPE x, y;
/* Place known values into the buffers into which the flop registers are
to be saved. This is for debug purposes only, it is not normally
required. The last position in each array is left at zero as the status
register will be loaded from there.
It is intended that these values can be viewed being loaded into the
flop registers when a task is started - however the Insight debugger
does not seem to want to show the flop register values. */
for( x = 0; x < mathNUMBER_OF_TASKS; x++ )
{
for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1 ); y++ )
{
ulFlopRegisters[ x ][ y ] = ( x + 1 );
}
}
/* Create the first task - passing it the address of the check variable
that it is going to increment. This check variable is used as an
indication that the task is still running. */
xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, &xTaskJustCreated );
/* The task tag value is a value that can be associated with a task, but
is not used by the scheduler itself. Its use is down to the application so
it makes a convenient place in this case to store the pointer to the buffer
into which the flop context of the task will be stored. The first created
task uses ulFlopRegisters[ 0 ], the second ulFlopRegisters[ 1 ], etc. */
vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 0 ][ 0 ] ) );
/* Create another 7 tasks, allocating a buffer for each. */
xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, &xTaskJustCreated );
vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 1 ][ 0 ] ) );
xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, &xTaskJustCreated );
vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 2 ][ 0 ] ) );
xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, &xTaskJustCreated );
vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 3 ][ 0 ] ) );
xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, &xTaskJustCreated );
vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 4 ][ 0 ] ) );
xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, &xTaskJustCreated );
vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 5 ][ 0 ] ) );
xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, &xTaskJustCreated );
vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 6 ][ 0 ] ) );
xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, &xTaskJustCreated );
vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 7 ][ 0 ] ) );
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask1, pvParameters )
{
volatile portFLOAT ff1, ff2, ff3, ff4;
volatile unsigned portSHORT *pusTaskCheckVariable;
volatile portFLOAT fAnswer;
portSHORT sError = pdFALSE;
ff1 = 123.4567F;
ff2 = 2345.6789F;
ff3 = -918.222F;
fAnswer = ( ff1 + ff2 ) * ff3;
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
/* Keep performing a calculation and checking the result against a constant. */
for(;;)
{
ff1 = 123.4567F;
ff2 = 2345.6789F;
ff3 = -918.222F;
ff4 = ( ff1 + ff2 ) * ff3;
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* If the calculation does not match the expected constant, stop the
increment of the check variable. */
if( fabs( ff4 - fAnswer ) > 0.001F )
{
sError = pdTRUE;
}
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know this task is still running okay. */
( *pusTaskCheckVariable )++;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
}
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask2, pvParameters )
{
volatile portFLOAT ff1, ff2, ff3, ff4;
volatile unsigned portSHORT *pusTaskCheckVariable;
volatile portFLOAT fAnswer;
portSHORT sError = pdFALSE;
ff1 = -389.38F;
ff2 = 32498.2F;
ff3 = -2.0001F;
fAnswer = ( ff1 / ff2 ) * ff3;
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
/* Keep performing a calculation and checking the result against a constant. */
for( ;; )
{
ff1 = -389.38F;
ff2 = 32498.2F;
ff3 = -2.0001F;
ff4 = ( ff1 / ff2 ) * ff3;
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
/* If the calculation does not match the expected constant, stop the
increment of the check variable. */
if( fabs( ff4 - fAnswer ) > 0.001F )
{
sError = pdTRUE;
}
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know
this task is still running okay. */
( *pusTaskCheckVariable )++;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
}
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask3, pvParameters )
{
volatile portFLOAT *pfArray, fTotal1, fTotal2, fDifference;
volatile unsigned portSHORT *pusTaskCheckVariable;
const size_t xArraySize = 10;
size_t xPosition;
portSHORT sError = pdFALSE;
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
pfArray = ( portFLOAT * ) pvPortMalloc( xArraySize * sizeof( portFLOAT ) );
/* Keep filling an array, keeping a running total of the values placed in the
array. Then run through the array adding up all the values. If the two totals
do not match, stop the check variable from incrementing. */
for( ;; )
{
fTotal1 = 0.0F;
fTotal2 = 0.0F;
for( xPosition = 0; xPosition < xArraySize; xPosition++ )
{
pfArray[ xPosition ] = ( portFLOAT ) xPosition + 5.5F;
fTotal1 += ( portFLOAT ) xPosition + 5.5F;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
for( xPosition = 0; xPosition < xArraySize; xPosition++ )
{
fTotal2 += pfArray[ xPosition ];
}
fDifference = fTotal1 - fTotal2;
if( fabs( fDifference ) > 0.001F )
{
sError = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know this task is still running okay. */
( *pusTaskCheckVariable )++;
}
}
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask4, pvParameters )
{
volatile portFLOAT *pfArray, fTotal1, fTotal2, fDifference;
volatile unsigned portSHORT *pusTaskCheckVariable;
const size_t xArraySize = 10;
size_t xPosition;
portSHORT sError = pdFALSE;
/* The variable this task increments to show it is still running is passed in
as the parameter. */
pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters;
pfArray = ( portFLOAT * ) pvPortMalloc( xArraySize * sizeof( portFLOAT ) );
/* Keep filling an array, keeping a running total of the values placed in the
array. Then run through the array adding up all the values. If the two totals
do not match, stop the check variable from incrementing. */
for( ;; )
{
fTotal1 = 0.0F;
fTotal2 = 0.0F;
for( xPosition = 0; xPosition < xArraySize; xPosition++ )
{
pfArray[ xPosition ] = ( portFLOAT ) xPosition * 12.123F;
fTotal1 += ( portFLOAT ) xPosition * 12.123F;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
for( xPosition = 0; xPosition < xArraySize; xPosition++ )
{
fTotal2 += pfArray[ xPosition ];
}
fDifference = fTotal1 - fTotal2;
if( fabs( fDifference ) > 0.001F )
{
sError = pdTRUE;
}
#if configUSE_PREEMPTION == 0
taskYIELD();
#endif
if( sError == pdFALSE )
{
/* If the calculation has always been correct, increment the check
variable so we know this task is still running okay. */
( *pusTaskCheckVariable )++;
}
}
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreMathsTaskStillRunning( void )
{
/* Keep a history of the check variables so we know if they have been incremented
since the last call. */
static unsigned portSHORT usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 };
portBASE_TYPE xReturn = pdTRUE, xTask;
/* Check the maths tasks are still running by ensuring their check variables
are still incrementing. */
for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )
{
if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )
{
/* The check has not incremented so an error exists. */
xReturn = pdFALSE;
}
usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];
}
return xReturn;
}

707
Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c Normal file
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@ -0,0 +1,707 @@
/*
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License (version 2) as published
by the Free Software Foundation and modified by the FreeRTOS exception.
**NOTE** The exception to the GPL is included to allow you to distribute a
combined work that includes FreeRTOS.org without being obliged to provide
the source code for any proprietary components. Alternative commercial
license and support terms are also available upon request. See the
licensing section of http://www.FreeRTOS.org for full details.
FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along
with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
Temple Place, Suite 330, Boston, MA 02111-1307 USA.
***************************************************************************
* *
* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
* *
* This is a concise, step by step, 'hands on' guide that describes both *
* general multitasking concepts and FreeRTOS specifics. It presents and *
* explains numerous examples that are written using the FreeRTOS API. *
* Full source code for all the examples is provided in an accompanying *
* .zip file. *
* *
***************************************************************************
1 tab == 4 spaces!
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks.
*
* In addition to the standard demo tasks, the follow demo specific tasks are
* create:
*
* The "Check" task. This only executes every three seconds but has the highest
* priority so is guaranteed to get processor time. Its main function is to
* check that all the other tasks are still operational. Most tasks maintain
* a unique count that is incremented each time the task successfully completes
* its function. Should any error occur within such a task the count is
* permanently halted. The check task inspects the count of each task to ensure
* it has changed since the last time the check task executed. If all the count
* variables have changed all the tasks are still executing error free, and the
* check task toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
* The "Register Check" tasks. These tasks fill the CPU registers with known
* values, then check that each register still contains the expected value, the
* discovery of an unexpected value being indicative of an error in the RTOS
* context switch mechanism. The register check tasks operate at low priority
* so are switched in and out frequently.
*
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Xilinx library includes. */
#include "xcache_l.h"
#include "xintc.h"
/* Demo application includes. */
#include "flash.h"
#include "integer.h"
#include "comtest2.h"
#include "semtest.h"
#include "BlockQ.h"
#include "dynamic.h"
#include "GenQTest.h"
#include "QPeek.h"
#include "blocktim.h"
#include "death.h"
#include "partest.h"
#include "countsem.h"
#include "recmutex.h"
#include "flop.h"
#include "flop-reg-test.h"
/* Priorities assigned to the demo tasks. */
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainFLOP_PRIORITY ( tskIDLE_PRIORITY )
/* The first LED used by the COM test and check tasks respectively. */
#define mainCOM_TEST_LED ( 4 )
#define mainCHECK_TEST_LED ( 3 )
/* The baud rate used by the comtest tasks is set by the hardware, so the
baud rate parameters passed into the comtest initialisation has no effect. */
#define mainBAUD_SET_IN_HARDWARE ( 0 )
/* Delay periods used by the check task. If no errors have been found then
the check LED will toggle every mainNO_ERROR_CHECK_DELAY milliseconds. If an
error has been found at any time then the toggle rate will increase to
mainERROR_CHECK_DELAY milliseconds. */
#define mainNO_ERROR_CHECK_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS )
#define mainERROR_CHECK_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
/*
* The tasks defined within this file - described within the comments at the
* head of this page.
*/
static void prvRegTestTask1( void *pvParameters );
static void prvRegTestTask2( void *pvParameters );
static void prvErrorChecks( void *pvParameters );
/*
* Called by the 'check' task to inspect all the standard demo tasks within
* the system, as described within the comments at the head of this page.
*/
static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void );
/*
* Perform any hardware initialisation required by the demo application.
*/
static void prvSetupHardware( void );
/*-----------------------------------------------------------*/
/* xRegTestStatus will get set to pdFAIL by the regtest tasks if they
discover an unexpected value. */
static volatile unsigned portBASE_TYPE xRegTestStatus = pdPASS;
/* Counters used to ensure the regtest tasks are still running. */
static volatile unsigned portLONG ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL;
/*-----------------------------------------------------------*/
int main( void )
{
/* Must be called prior to installing any interrupt handlers! */
vPortSetupInterruptController();
/* In this case prvSetupHardware() just enables the caches and and
configures the IO ports for the LED outputs. */
prvSetupHardware();
/* Start the standard demo application tasks. Note that the baud rate used
by the comtest tasks is set by the hardware, so the baud rate parameter
passed has no effect. */
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_SET_IN_HARDWARE, mainCOM_TEST_LED );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartBlockingQueueTasks ( mainQUEUE_BLOCK_PRIORITY );
vStartDynamicPriorityTasks();
vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY );
vStartQueuePeekTasks();
vCreateBlockTimeTasks();
vStartCountingSemaphoreTasks();
vStartRecursiveMutexTasks();
#if ( configUSE_FPU == 1 )
{
/* A different project is provided that has configUSE_FPU set to 1
in order to demonstrate all the settings required to use the floating
point unit. If you wish to use the floating point unit do not start
with this project. */
vStartMathTasks( mainFLOP_PRIORITY );
vStartFlopRegTests();
}
#endif
/* Create the tasks defined within this file. */
xTaskCreate( prvRegTestTask1, ( signed portCHAR * ) "Regtest1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
xTaskCreate( prvRegTestTask2, ( signed portCHAR * ) "Regtest2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
xTaskCreate( prvErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* The suicide tasks must be started last as they record the number of other
tasks that exist within the system. The value is then used to ensure at run
time the number of tasks that exists is within expected bounds. */
vCreateSuicidalTasks( mainDEATH_PRIORITY );
/* Now start the scheduler. Following this call the created tasks should
be executing. */
vTaskStartScheduler();
/* vTaskStartScheduler() will only return if an error occurs while the
idle task is being created. */
for( ;; );
return 0;
}
/*-----------------------------------------------------------*/
static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void )
{
portBASE_TYPE lReturn = pdPASS;
static unsigned portLONG ulLastRegTest1Counter= 0UL, ulLastRegTest2Counter = 0UL;
/* The demo tasks maintain a count that increments every cycle of the task
provided that the task has never encountered an error. This function
checks the counts maintained by the tasks to ensure they are still being
incremented. A count remaining at the same value between calls therefore
indicates that an error has been detected. */
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreComTestTasksStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xIsCreateTaskStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreGenericQueueTasksStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreQueuePeekTasksStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
#if ( configUSE_FPU == 1 )
if( xAreMathsTaskStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreFlopRegisterTestsStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
#endif
/* Have the register test tasks found any errors? */
if( xRegTestStatus != pdPASS )
{
lReturn = pdFAIL;
}
/* Are the register test tasks still looping? */
if( ulLastRegTest1Counter == ulRegTest1Counter )
{
lReturn = pdFAIL;
}
else
{
ulLastRegTest1Counter = ulRegTest1Counter;
}
if( ulLastRegTest2Counter == ulRegTest2Counter )
{
lReturn = pdFAIL;
}
else
{
ulLastRegTest2Counter = ulRegTest2Counter;
}
return lReturn;
}
/*-----------------------------------------------------------*/
static void prvErrorChecks( void *pvParameters )
{
portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY, xLastExecutionTime;
volatile unsigned portBASE_TYPE uxFreeStack;
/* Just to remove compiler warning. */
( void ) pvParameters;
/* This call is just to demonstrate the use of the function - nothing is
done with the value. You would expect the stack high water mark to be
lower (the function to return a larger value) here at function entry than
later following calls to other functions. */
uxFreeStack = uxTaskGetStackHighWaterMark( NULL );
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
works correctly. */
xLastExecutionTime = xTaskGetTickCount();
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. */
for( ;; )
{
/* Again just for demo purposes - uxFreeStack should have a lower value
here than following the call to uxTaskGetStackHighWaterMark() on the
task entry. */
uxFreeStack = uxTaskGetStackHighWaterMark( NULL );
/* Wait until it is time to check again. The time we wait here depends
on whether an error has been detected or not. When an error is
detected the time is shortened resulting in a faster LED flash rate. */
vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
/* See if the other tasks are all ok. */
if( prvCheckOtherTasksAreStillRunning() != pdPASS )
{
/* An error occurred in one of the tasks so shorten the delay
period - which has the effect of increasing the frequency of the
LED toggle. */
xDelayPeriod = mainERROR_CHECK_DELAY;
}
/* Flash! */
vParTestToggleLED( mainCHECK_TEST_LED );
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
XCache_EnableICache( 0x80000000 );
XCache_EnableDCache( 0x80000000 );
/* Setup the IO port for use with the LED outputs. */
vParTestInitialise();
}
/*-----------------------------------------------------------*/
void prvRegTest1Pass( void )
{
/* Called from the inline assembler - this cannot be static
otherwise it can get optimised away. */
ulRegTest1Counter++;
}
/*-----------------------------------------------------------*/
void prvRegTest2Pass( void )
{
/* Called from the inline assembler - this cannot be static
otherwise it can get optimised away. */
ulRegTest2Counter++;
}
/*-----------------------------------------------------------*/
void prvRegTestFail( void )
{
/* Called from the inline assembler - this cannot be static
otherwise it can get optimised away. */
xRegTestStatus = pdFAIL;
}
/*-----------------------------------------------------------*/
static void prvRegTestTask1( void *pvParameters )
{
/* Just to remove compiler warning. */
( void ) pvParameters;
/* The first register test task as described at the top of this file. The
values used in the registers are different to those use in the second
register test task. Also, unlike the second register test task, this task
yields between setting the register values and subsequently checking the
register values. */
asm volatile
(
"RegTest1Start: \n\t" \
" \n\t" \
" li 0, 301 \n\t" \
" mtspr 256, 0 #USPRG0 \n\t" \
" li 0, 501 \n\t" \
" mtspr 8, 0 #LR \n\t" \
" li 0, 4 \n\t" \
" mtspr 1, 0 #XER \n\t" \
" \n\t" \
" li 0, 1 \n\t" \
" li 2, 2 \n\t" \
" li 3, 3 \n\t" \
" li 4, 4 \n\t" \
" li 5, 5 \n\t" \
" li 6, 6 \n\t" \
" li 7, 7 \n\t" \
" li 8, 8 \n\t" \
" li 9, 9 \n\t" \
" li 10, 10 \n\t" \
" li 11, 11 \n\t" \
" li 12, 12 \n\t" \
" li 13, 13 \n\t" \
" li 14, 14 \n\t" \
" li 15, 15 \n\t" \
" li 16, 16 \n\t" \
" li 17, 17 \n\t" \
" li 18, 18 \n\t" \
" li 19, 19 \n\t" \
" li 20, 20 \n\t" \
" li 21, 21 \n\t" \
" li 22, 22 \n\t" \
" li 23, 23 \n\t" \
" li 24, 24 \n\t" \
" li 25, 25 \n\t" \
" li 26, 26 \n\t" \
" li 27, 27 \n\t" \
" li 28, 28 \n\t" \
" li 29, 29 \n\t" \
" li 30, 30 \n\t" \
" li 31, 31 \n\t" \
" \n\t" \
" sc \n\t" \
" nop \n\t" \
" \n\t" \
" cmpwi 0, 1 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 2, 2 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 3, 3 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 4, 4 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 5, 5 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 6, 6 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 7, 7 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 8, 8 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 9, 9 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 10, 10 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 11, 11 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 12, 12 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 13, 13 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 14, 14 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 15, 15 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 16, 16 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 17, 17 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 18, 18 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 19, 19 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 20, 20 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 21, 21 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 22, 22 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 23, 23 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 24, 24 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 25, 25 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 26, 26 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 27, 27 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 28, 28 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 29, 29 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 30, 30 \n\t" \
" bne RegTest1Fail \n\t" \
" cmpwi 31, 31 \n\t" \
" bne RegTest1Fail \n\t" \
" \n\t" \
" mfspr 0, 256 #USPRG0 \n\t" \
" cmpwi 0, 301 \n\t" \
" bne RegTest1Fail \n\t" \
" mfspr 0, 8 #LR \n\t" \
" cmpwi 0, 501 \n\t" \
" bne RegTest1Fail \n\t" \
" mfspr 0, 1 #XER \n\t" \
" cmpwi 0, 4 \n\t" \
" bne RegTest1Fail \n\t" \
" \n\t" \
" bl prvRegTest1Pass \n\t" \
" b RegTest1Start \n\t" \
" \n\t" \
"RegTest1Fail: \n\t" \
" \n\t" \
" \n\t" \
" bl prvRegTestFail \n\t" \
" b RegTest1Start \n\t" \
);
}
/*-----------------------------------------------------------*/
static void prvRegTestTask2( void *pvParameters )
{
/* Just to remove compiler warning. */
( void ) pvParameters;
/* The second register test task as described at the top of this file.
Note that this task fills the registers with different values to the
first register test task. */
asm volatile
(
"RegTest2Start: \n\t" \
" \n\t" \
" li 0, 300 \n\t" \
" mtspr 256, 0 #USPRG0 \n\t" \
" li 0, 500 \n\t" \
" mtspr 8, 0 #LR \n\t" \
" li 0, 4 \n\t" \
" mtspr 1, 0 #XER \n\t" \
" \n\t" \
" li 0, 11 \n\t" \
" li 2, 12 \n\t" \
" li 3, 13 \n\t" \
" li 4, 14 \n\t" \
" li 5, 15 \n\t" \
" li 6, 16 \n\t" \
" li 7, 17 \n\t" \
" li 8, 18 \n\t" \
" li 9, 19 \n\t" \
" li 10, 110 \n\t" \
" li 11, 111 \n\t" \
" li 12, 112 \n\t" \
" li 13, 113 \n\t" \
" li 14, 114 \n\t" \
" li 15, 115 \n\t" \
" li 16, 116 \n\t" \
" li 17, 117 \n\t" \
" li 18, 118 \n\t" \
" li 19, 119 \n\t" \
" li 20, 120 \n\t" \
" li 21, 121 \n\t" \
" li 22, 122 \n\t" \
" li 23, 123 \n\t" \
" li 24, 124 \n\t" \
" li 25, 125 \n\t" \
" li 26, 126 \n\t" \
" li 27, 127 \n\t" \
" li 28, 128 \n\t" \
" li 29, 129 \n\t" \
" li 30, 130 \n\t" \
" li 31, 131 \n\t" \
" \n\t" \
" cmpwi 0, 11 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 2, 12 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 3, 13 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 4, 14 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 5, 15 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 6, 16 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 7, 17 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 8, 18 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 9, 19 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 10, 110 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 11, 111 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 12, 112 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 13, 113 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 14, 114 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 15, 115 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 16, 116 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 17, 117 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 18, 118 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 19, 119 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 20, 120 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 21, 121 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 22, 122 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 23, 123 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 24, 124 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 25, 125 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 26, 126 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 27, 127 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 28, 128 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 29, 129 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 30, 130 \n\t" \
" bne RegTest2Fail \n\t" \
" cmpwi 31, 131 \n\t" \
" bne RegTest2Fail \n\t" \
" \n\t" \
" mfspr 0, 256 #USPRG0 \n\t" \
" cmpwi 0, 300 \n\t" \
" bne RegTest2Fail \n\t" \
" mfspr 0, 8 #LR \n\t" \
" cmpwi 0, 500 \n\t" \
" bne RegTest2Fail \n\t" \
" mfspr 0, 1 #XER \n\t" \
" cmpwi 0, 4 \n\t" \
" bne RegTest2Fail \n\t" \
" \n\t" \
" bl prvRegTest2Pass \n\t" \
" b RegTest2Start \n\t" \
" \n\t" \
"RegTest2Fail: \n\t" \
" \n\t" \
" \n\t" \
" bl prvRegTestFail \n\t" \
" b RegTest2Start \n\t" \
);
}
/*-----------------------------------------------------------*/
/* This hook function will get called if there is a suspected stack overflow.
An overflow can cause the task name to be corrupted, in which case the task
handle needs to be used to determine the offending task. */
void vApplicationStackOverflowHook( xTaskHandle xTask, signed portCHAR *pcTaskName );
void vApplicationStackOverflowHook( xTaskHandle xTask, signed portCHAR *pcTaskName )
{
/* To prevent the optimiser removing the variables. */
volatile xTaskHandle xTaskIn = xTask;
volatile signed portCHAR *pcTaskNameIn = pcTaskName;
/* Remove compiler warnings. */
( void ) xTaskIn;
( void ) pcTaskNameIn;
/* The following three calls are simply to stop compiler warnings about the
functions not being used - they are called from the inline assembly. */
prvRegTest1Pass();
prvRegTest2Pass();
prvRegTestFail();
for( ;; );
}

170
Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c Normal file
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@ -0,0 +1,170 @@
/*
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License (version 2) as published
by the Free Software Foundation and modified by the FreeRTOS exception.
**NOTE** The exception to the GPL is included to allow you to distribute a
combined work that includes FreeRTOS.org without being obliged to provide
the source code for any proprietary components. Alternative commercial
license and support terms are also available upon request. See the
licensing section of http://www.FreeRTOS.org for full details.
FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along
with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
Temple Place, Suite 330, Boston, MA 02111-1307 USA.
***************************************************************************
* *
* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
* *
* This is a concise, step by step, 'hands on' guide that describes both *
* general multitasking concepts and FreeRTOS specifics. It presents and *
* explains numerous examples that are written using the FreeRTOS API. *
* Full source code for all the examples is provided in an accompanying *
* .zip file. *
* *
***************************************************************************
1 tab == 4 spaces!
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
/* Demo application includes. */
#include "partest.h"
/* Library includes. */
#include "xparameters.h"
#include "xgpio_l.h"
/* Misc hardware specific definitions. */
#define partstALL_AS_OUTPUT 0x00
#define partstCHANNEL_1 0x01
#define partstMAX_8BIT_LED 0x07
/* The outputs are split into two IO sections, these variables maintain the
current value of either section. */
static unsigned portBASE_TYPE uxCurrentOutput8Bit, uxCurrentOutput5Bit;
/*-----------------------------------------------------------*/
/*
* Setup the IO for the LED outputs.
*/
void vParTestInitialise( void )
{
/* Set both sets of LED's on the demo board to outputs. */
XGpio_mSetDataDirection( XPAR_LEDS_8BIT_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT );
XGpio_mSetDataDirection( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT );
/* Start with all outputs off. */
uxCurrentOutput8Bit = 0;
XGpio_mSetDataReg( XPAR_LEDS_8BIT_BASEADDR, partstCHANNEL_1, 0x00 );
uxCurrentOutput5Bit = 0;
XGpio_mSetDataReg( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, 0x00 );
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;
portENTER_CRITICAL();
{
/* Which IO section does the LED being set/cleared belong to? The
8 bit or 5 bit outputs? */
if( uxLED <= partstMAX_8BIT_LED )
{
uxBaseAddress = XPAR_LEDS_8BIT_BASEADDR;
puxCurrentValue = &uxCurrentOutput5Bit;
}
else
{
uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;
puxCurrentValue = &uxCurrentOutput8Bit;
uxLED -= partstMAX_8BIT_LED;
}
/* Setup the bit mask accordingly. */
uxLED = 0x01 << uxLED;
/* Maintain the current output value. */
if( xValue )
{
*puxCurrentValue |= uxLED;
}
else
{
*puxCurrentValue &= ~uxLED;
}
/* Write the value to the port. */
XGpio_mSetDataReg( uxBaseAddress, partstCHANNEL_1, *puxCurrentValue );
}
portEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;
portENTER_CRITICAL();
{
/* Which IO section does the LED being toggled belong to? The
8 bit or 5 bit outputs? */
if( uxLED <= partstMAX_8BIT_LED )
{
uxBaseAddress = XPAR_LEDS_8BIT_BASEADDR;
puxCurrentValue = &uxCurrentOutput5Bit;
}
else
{
uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;
puxCurrentValue = &uxCurrentOutput8Bit;
uxLED -= partstMAX_8BIT_LED;
}
/* Setup the bit mask accordingly. */
uxLED = 0x01 << uxLED;
/* Maintain the current output value. */
if( *puxCurrentValue & uxLED )
{
*puxCurrentValue &= ~uxLED;
}
else
{
*puxCurrentValue |= uxLED;
}
/* Write the value to the port. */
XGpio_mSetDataReg(uxBaseAddress, partstCHANNEL_1, *puxCurrentValue );
}
portEXIT_CRITICAL();
}

235
Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c Normal file
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@ -0,0 +1,235 @@
/*
FreeRTOS.org V5.3.1 - Copyright (C) 2003-2009 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License (version 2) as published
by the Free Software Foundation and modified by the FreeRTOS exception.
**NOTE** The exception to the GPL is included to allow you to distribute a
combined work that includes FreeRTOS.org without being obliged to provide
the source code for any proprietary components. Alternative commercial
license and support terms are also available upon request. See the
licensing section of http://www.FreeRTOS.org for full details.
FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along
with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
Temple Place, Suite 330, Boston, MA 02111-1307 USA.
***************************************************************************
* *
* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
* *
* This is a concise, step by step, 'hands on' guide that describes both *
* general multitasking concepts and FreeRTOS specifics. It presents and *
* explains numerous examples that are written using the FreeRTOS API. *
* Full source code for all the examples is provided in an accompanying *
* .zip file. *
* *
***************************************************************************
1 tab == 4 spaces!
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
/* Library includes. */
#include "xparameters.h"
#include "xuartlite.h"
#include "xuartlite_l.h"
/*-----------------------------------------------------------*/
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
/* Structure that maintains information on the UART being used. */
static XUartLite xUART;
/*
* Sample UART interrupt handler. Note this is used to demonstrate the kernel
* features and test the port - it is not intended to represent an efficient
* implementation.
*/
static void vSerialISR( XUartLite *pxUART );
/*-----------------------------------------------------------*/
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
/* NOTE: The baud rate used by this driver is determined by the hardware
parameterization of the UART Lite peripheral, and the baud value passed to
this function has no effect. */
( void ) ulWantedBaud;
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
/* Only initialise the UART if the queues were created correctly. */
if( ( xRxedChars != NULL ) && ( xCharsForTx != NULL ) )
{
XUartLite_Initialize( &xUART, XPAR_RS232_UART_1_DEVICE_ID );
XUartLite_ResetFifos( &xUART );
XUartLite_DisableInterrupt( &xUART );
if( xPortInstallInterruptHandler( XPAR_XPS_INTC_0_RS232_UART_1_INTERRUPT_INTR, ( XInterruptHandler )vSerialISR, (void *)&xUART ) == pdPASS )
{
/* xPortInstallInterruptHandler() could fail if
vPortSetupInterruptController() has not been called prior to this
function. */
XUartLite_EnableInterrupt( &xUART );
}
}
/* There is only one port so the handle is not used. */
return ( xComPortHandle ) 0;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
{
/* The port handle is not required as this driver only supports one UART. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
{
portBASE_TYPE xReturn = pdTRUE;
/* Just to remove compiler warning. */
( void ) pxPort;
portENTER_CRITICAL();
{
/* If the UART FIFO is full we can block posting the new data on the
Tx queue. */
if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_1_BASEADDR ) )
{
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
{
xReturn = pdFAIL;
}
}
/* Otherwise, if there is data already in the queue we should add the
new data to the back of the queue to ensure the sequencing is
maintained. */
else if( uxQueueMessagesWaiting( xCharsForTx ) )
{
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
{
xReturn = pdFAIL;
}
}
/* If the UART FIFO is not full and there is no data already in the
queue we can write directly to the FIFO without disrupting the
sequence. */
else
{
XIo_Out32( XPAR_RS232_UART_1_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar );
}
}
portEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not supported as not required by the demo application. */
( void ) xPort;
}
/*-----------------------------------------------------------*/
static void vSerialISR( XUartLite *pxUART )
{
unsigned portLONG ulISRStatus;
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE, lDidSomething;
portCHAR cChar;
/* Just to remove compiler warning. */
( void ) pxUART;
do
{
lDidSomething = pdFALSE;
ulISRStatus = XIo_In32( XPAR_RS232_UART_1_BASEADDR + XUL_STATUS_REG_OFFSET );
if( ( ulISRStatus & XUL_SR_RX_FIFO_VALID_DATA ) != 0 )
{
/* A character is available - place it in the queue of received
characters. This might wake a task that was blocked waiting for
data. */
cChar = ( portCHAR ) XIo_In32( XPAR_RS232_UART_1_BASEADDR + XUL_RX_FIFO_OFFSET );
xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
lDidSomething = pdTRUE;
}
if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 )
{
/* There is space in the FIFO - if there are any characters queue for
transmission they can be sent to the UART now. This might unblock a
task that was waiting for space to become available on the Tx queue. */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
{
XIo_Out32( XPAR_RS232_UART_1_BASEADDR + XUL_TX_FIFO_OFFSET, cChar );
lDidSomething = pdTRUE;
}
}
} while( lDidSomething == pdTRUE );
/* If we woke any tasks we may require a context switch. */
if( xHigherPriorityTaskWoken )
{
portYIELD_FROM_ISR();
}
}

15
Demo/PPC440_Xilinx_Virtex5_GCC/Version_Changes.log Normal file
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The following files will be modified:
system.mhs
system.mss
--------------------------------------
The following changes will be made:
Core ppc440mc_ddr2 2.00.a will be replaced by 2.00.b
Core clock_generator 3.00.a will be replaced by 3.01.a
Driver cpu_ppc440 1.00.b will be replaced by 1.01.a
Driver iic 1.14.a will be replaced by 1.15.a
--------------------------------------
The following changes need to be made manually by the user:
Core plbv46_pcie 3.00.b needs to be replaced by 4.01.a
Core xps_ethernetlite 2.01.a needs to be replaced by 3.00.a

173
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtSvgBLKD_Dimensions.xsl Normal file
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<?xml version="1.0" standalone="no"?>
<xsl:stylesheet version="1.0"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
xmlns:exsl="http://exslt.org/common"
xmlns:xlink="http://www.w3.org/1999/xlink">
<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"
doctype-public="-//W3C//DTD SVG 1.0//EN"
doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/>
<!--
======================================================
BUS INTERFACE DIMENSIONS
======================================================
-->
<xsl:variable name="BLKD_BIF_H" select="16"/>
<xsl:variable name="BLKD_BIF_W" select="32"/>
<xsl:variable name="BLKD_BIFC_H" select="24"/>
<xsl:variable name="BLKD_BIFC_W" select="24"/>
<xsl:variable name="BLKD_BIFC_dx" select="ceiling($BLKD_BIFC_W div 5)"/>
<xsl:variable name="BLKD_BIFC_dy" select="ceiling($BLKD_BIFC_H div 5)"/>
<xsl:variable name="BLKD_BIFC_Hi" select="($BLKD_BIFC_H - ($BLKD_BIFC_dy * 2))"/>
<xsl:variable name="BLKD_BIFC_Wi" select="($BLKD_BIFC_W - ($BLKD_BIFC_dx * 2))"/>
<xsl:variable name="BLKD_BIF_TYPE_ONEWAY" select="'OneWay'"/>
<!--
======================================================
GLOLBAL BUS INTERFACE DIMENSIONS
(Define for global MdtSVG_BifShapes.xsl which is used across all
diagrams to define the shapes of bifs the same across all diagrams)
======================================================
-->
<xsl:variable name="BIF_H" select="$BLKD_BIF_H"/>
<xsl:variable name="BIF_W" select="$BLKD_BIF_W"/>
<xsl:variable name="BIFC_H" select="$BLKD_BIFC_H"/>
<xsl:variable name="BIFC_W" select="$BLKD_BIFC_W"/>
<xsl:variable name="BIFC_dx" select="$BLKD_BIFC_dx"/>
<xsl:variable name="BIFC_dy" select="$BLKD_BIFC_dy"/>
<xsl:variable name="BIFC_Hi" select="$BLKD_BIFC_Hi"/>
<xsl:variable name="BIFC_Wi" select="$BLKD_BIFC_Wi"/>
<!--
======================================================
BUS DIMENSIONS
======================================================
-->
<xsl:variable name="BLKD_P2P_BUS_W" select="($BLKD_BUS_ARROW_H - ($BLKD_BUS_ARROW_G * 2))"/>
<xsl:variable name="BLKD_SBS_LANE_H" select="($BLKD_MOD_H + ($BLKD_BIF_H * 2))"/>
<xsl:variable name="BLKD_BUS_LANE_W" select="($BLKD_BIF_W + ($BLKD_MOD_BIF_GAP_H * 2))"/>
<xsl:variable name="BLKD_BUS_ARROW_W" select="ceiling($BLKD_BIFC_W div 3)"/>
<xsl:variable name="BLKD_BUS_ARROW_H" select="ceiling($BLKD_BIFC_H div 2)"/>
<xsl:variable name="BLKD_BUS_ARROW_G" select="ceiling($BLKD_BIFC_W div 12)"/>
<!--
======================================================
IO PORT DIMENSIONS
======================================================
-->
<xsl:variable name="BLKD_IOP_H" select="16"/>
<xsl:variable name="BLKD_IOP_W" select="16"/>
<xsl:variable name="BLKD_IOP_SPC" select="12"/>
<!--
======================================================
INTERRUPT NOTATION DIMENSIONS
======================================================
-->
<xsl:variable name="BLKD_INTR_W" select="18"/>
<xsl:variable name="BLKD_INTR_H" select="18"/>
<!--
======================================================
MODULE DIMENSIONS
======================================================
-->
<xsl:variable name="BLKD_MOD_IO_GAP" select="8"/>
<xsl:variable name="BLKD_MOD_W" select="( ($BLKD_BIF_W * 2) + ($BLKD_MOD_BIF_GAP_H * 1) + ($BLKD_MOD_LANE_W * 2))"/>
<xsl:variable name="BLKD_MOD_H" select="($BLKD_MOD_LABEL_H + ($BLKD_BIF_H * 1) + ($BLKD_MOD_BIF_GAP_V * 1) + ($BLKD_MOD_LANE_H * 2))"/>
<xsl:variable name="BLKD_MOD_BIF_GAP_H" select="ceiling($BLKD_BIF_H div 4)"/>
<xsl:variable name="BLKD_MOD_BIF_GAP_V" select="ceiling($BLKD_BIFC_H div 2)"/>
<xsl:variable name="BLKD_MOD_LABEL_W" select="(($BLKD_BIF_W * 2) + $BLKD_MOD_BIF_GAP_H)"/>
<xsl:variable name="BLKD_MOD_LABEL_H" select="(($BLKD_BIF_H * 2) + ceiling($BLKD_BIF_H div 3))"/>
<xsl:variable name="BLKD_MOD_LANE_W" select="ceiling($BLKD_BIF_W div 3)"/>
<xsl:variable name="BLKD_MOD_LANE_H" select="ceiling($BLKD_BIF_H div 4)"/>
<xsl:variable name="BLKD_MOD_EDGE_W" select="ceiling($BLKD_MOD_LANE_W div 2)"/>
<xsl:variable name="BLKD_MOD_SHAPES_G" select="($BLKD_BIF_W + $BLKD_BIF_W)"/>
<xsl:variable name="BLKD_MOD_BKTLANE_H" select="$BLKD_BIF_H"/>
<xsl:variable name="BLKD_MOD_BKTLANE_W" select="$BLKD_BIF_H"/>
<xsl:variable name="BLKD_MOD_BUCKET_G" select="ceiling($BLKD_BIF_W div 2)"/>
<xsl:variable name="BLKD_MPMC_MOD_H" select="(($BLKD_BIF_H * 1) + ($BLKD_MOD_BIF_GAP_V * 2) + ($BLKD_MOD_LANE_H * 2))"/>
<!--
======================================================
GLOBAL DIAGRAM DIMENSIONS
======================================================
-->
<xsl:variable name="BLKD_IORCHAN_H" select="$BLKD_BIF_H"/>
<xsl:variable name="BLKD_IORCHAN_W" select="$BLKD_BIF_H"/>
<xsl:variable name="BLKD_PRTCHAN_H" select="($BLKD_BIF_H * 2) + ceiling($BLKD_BIF_H div 2)"/>
<xsl:variable name="BLKD_PRTCHAN_W" select="($BLKD_BIF_H * 2) + ceiling($BLKD_BIF_H div 2) + 8"/>
<xsl:variable name="BLKD_DRAWAREA_MIN_W" select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * 3) + ($BLKD_MOD_BUCKET_G * 2)))"/>
<xsl:variable name="BLKD_INNER_X" select="($BLKD_PRTCHAN_W + $BLKD_IORCHAN_W + $BLKD_INNER_GAP)"/>
<xsl:variable name="BLKD_INNER_Y" select="($BLKD_PRTCHAN_H + $BLKD_IORCHAN_H + $BLKD_INNER_GAP)"/>
<xsl:variable name="BLKD_INNER_GAP" select="ceiling($BLKD_MOD_W div 2)"/>
<xsl:variable name="BLKD_SBS2IP_GAP" select="$BLKD_MOD_H"/>
<xsl:variable name="BLKD_BRIDGE_GAP" select="($BLKD_BUS_LANE_W * 4)"/>
<xsl:variable name="BLKD_IP2UNK_GAP" select="$BLKD_MOD_H"/>
<xsl:variable name="BLKD_PROC2SBS_GAP" select="($BLKD_BIF_H * 2)"/>
<xsl:variable name="BLKD_IOR2PROC_GAP" select="$BLKD_BIF_W"/>
<xsl:variable name="BLKD_MPMC2PROC_GAP" select="($BLKD_BIF_H * 2)"/>
<xsl:variable name="BLKD_SPECS2KEY_GAP" select="$BLKD_BIF_W"/>
<xsl:variable name="BLKD_DRAWAREA2KEY_GAP" select="ceiling($BLKD_BIF_W div 3)"/>
<xsl:variable name="BLKD_KEY_H" select="250"/>
<xsl:variable name="BLKD_KEY_W" select="($BLKD_DRAWAREA_MIN_W + ceiling($BLKD_DRAWAREA_MIN_W div 2.5))"/>
<xsl:variable name="BLKD_SPECS_H" select="100"/>
<xsl:variable name="BLKD_SPECS_W" select="300"/>
<xsl:variable name="BLKD_BKT_MODS_PER_ROW" select="3"/>
<!--
<xsl:template name="Print_Dimensions">
<xsl:message>MOD_LABEL_W : <xsl:value-of select="$MOD_LABEL_W"/></xsl:message>
<xsl:message>MOD_LABEL_H : <xsl:value-of select="$MOD_LABEL_H"/></xsl:message>
<xsl:message>MOD_LANE_W : <xsl:value-of select="$MOD_LANE_W"/></xsl:message>
<xsl:message>MOD_LANE_H : <xsl:value-of select="$MOD_LANE_H"/></xsl:message>
<xsl:message>MOD_EDGE_W : <xsl:value-of select="$MOD_EDGE_W"/></xsl:message>
<xsl:message>MOD_SHAPES_G : <xsl:value-of select="$MOD_SHAPES_G"/></xsl:message>
<xsl:message>MOD_BKTLANE_W : <xsl:value-of select="$MOD_BKTLANE_W"/></xsl:message>
<xsl:message>MOD_BKTLANE_H : <xsl:value-of select="$MOD_BKTLANE_H"/></xsl:message>
<xsl:message>MOD_BUCKET_G : <xsl:value-of select="$MOD_BUCKET_G"/></xsl:message>
</xsl:template>
-->
</xsl:stylesheet>

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<?xml version="1.0" standalone="no"?>
<xsl:stylesheet version="1.0"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
xmlns:exsl="http://exslt.org/common"
xmlns:xlink="http://www.w3.org/1999/xlink">
<xsl:variable name="COL_RED" select="'#AA0000'"/>
<xsl:variable name="COL_GRAY" select="'#E1E1E1'"/>
<xsl:variable name="COL_XLNX" select="'#AA0017'"/>
<xsl:variable name="COL_BLACK" select="'#000000'"/>
<xsl:variable name="COL_WHITE" select="'#FFFFFF'"/>
<xsl:variable name="COL_YELLOW" select="'#FFFFDD'"/>
<xsl:variable name="COL_YELLOW_LT" select="'#FFFFEE'"/>
<xsl:variable name="COL_BG" select="'#CCCCCC'"/>
<xsl:variable name="COL_BG_LT" select="'#EEEEEE'"/>
<xsl:variable name="COL_BG_UNK" select="'#DDDDDD'"/>
<xsl:variable name="COL_PROC_BG" select="'#FFCCCC'"/>
<xsl:variable name="COL_PROC_BG_MB" select="'#222222'"/>
<xsl:variable name="COL_PROC_BG_PP" select="'#90001C'"/>
<xsl:variable name="COL_PROC_BG_USR" select="'#666699'"/>
<xsl:variable name="COL_MPMC_BG" select="'#8B0800'"/>
<xsl:variable name="COL_MOD_BG" select="'#F0F0F0'"/>
<xsl:variable name="COL_MOD_SPRT" select="'#888888'"/>
<xsl:variable name="COL_MOD_MPRT" select="'#888888'"/>
<xsl:variable name="COL_IORING" select="'#000088'"/>
<xsl:variable name="COL_IORING_LT" select="'#CCCCFF'"/>
<xsl:variable name="COL_SYSPRT" select="'#0000BB'"/>
<!--
<xsl:variable name="COL_INTR_0" select="'#FF9900'"/>
<xsl:variable name="COL_INTR_1" select="'#00CCCC'"/>
<xsl:variable name="COL_INTR_2" select="'#33FF33'"/>
<xsl:variable name="COL_INTR_3" select="'#FF00CC'"/>
<xsl:variable name="COL_INTR_4" select="'#99FF33'"/>
<xsl:variable name="COL_INTR_5" select="'#0066CC'"/>
<xsl:variable name="COL_INTR_6" select="'#9933FF'"/>
<xsl:variable name="COL_INTR_7" select="'#3300FF'"/>
<xsl:variable name="COL_INTR_8" select="'#00FF33'"/>
<xsl:variable name="COL_INTR_9" select="'#FF3333'"/>
-->
<xsl:variable name="COL_INTCS">
<INTCCOLOR INDEX="0" RGB="#FF9900"/>
<INTCCOLOR INDEX="1" RGB="#00CCCC"/>
<INTCCOLOR INDEX="2" RGB="#33FF33"/>
<INTCCOLOR INDEX="3" RGB="#FF00CC"/>
<INTCCOLOR INDEX="4" RGB="#99FF33"/>
<INTCCOLOR INDEX="5" RGB="#0066CC"/>
<INTCCOLOR INDEX="6" RGB="#9933FF"/>
<INTCCOLOR INDEX="7" RGB="#3300FF"/>
<INTCCOLOR INDEX="8" RGB="#00FF33"/>
<INTCCOLOR INDEX="9" RGB="#FF3333"/>
</xsl:variable>
<xsl:variable name="COL_BUSSTDS">
<BUSCOLOR BUSSTD="XIL" RGB="#990066" RGB_LT="#CC3399"/>
<BUSCOLOR BUSSTD="OCM" RGB="#0000DD" RGB_LT="#9999DD"/>
<BUSCOLOR BUSSTD="OPB" RGB="#339900" RGB_LT="#CCDDCC"/>
<BUSCOLOR BUSSTD="LMB" RGB="#7777FF" RGB_LT="#DDDDFF"/>
<BUSCOLOR BUSSTD="FSL" RGB="#CC00CC" RGB_LT="#FFBBFF"/>
<BUSCOLOR BUSSTD="DCR" RGB="#6699FF" RGB_LT="#BBDDFF"/>
<BUSCOLOR BUSSTD="FCB" RGB="#8C00FF" RGB_LT="#CCCCFF"/>
<BUSCOLOR BUSSTD="PLB" RGB="#FF5500" RGB_LT="#FFBB00"/>
<BUSCOLOR BUSSTD="PLBV34" RGB="#FF5500" RGB_LT="#FFBB00"/>
<BUSCOLOR BUSSTD="PLBV34_P2P" RGB="#FF5500" RGB_LT="#FFBB00"/>
<BUSCOLOR BUSSTD="PLBV46" RGB="#BB9955" RGB_LT="#FFFFDD"/>
<BUSCOLOR BUSSTD="PLBV46_P2P" RGB="#BB9955" RGB_LT="#FFFFDD"/>
<!--
<BUSCOLOR BUSSTD="PLBV46" RGB="#9966FF" RGB_LT="#CCCCFF"/>
<BUSCOLOR BUSSTD="PLBV46_P2P" RGB="#9966FF" RGB_LT="#CCCCFF"/>
<BUSCOLOR BUSSTD="PLB" RGB="#FFAA33" RGB_LT="#FFEE33"/>
<BUSCOLOR BUSSTD="PLBV46" RGB="#FF5500" RGB_LT="#FFBB00"/>
<BUSCOLOR BUSSTD="PLBV46_P2P" RGB="#FF5500" RGB_LT="#FFBB00"/>
-->
<BUSCOLOR BUSSTD="TARGET" RGB="#009999" RGB_LT="#00CCCC"/>
<BUSCOLOR BUSSTD="INITIATOR" RGB="#009999" RGB_LT="#00CCCC"/>
<BUSCOLOR BUSSTD="USER" RGB="#009999" RGB_LT="#00CCCC"/>
<BUSCOLOR BUSSTD="KEY" RGB="#444444" RGB_LT="#888888"/>
</xsl:variable>
<xsl:template name="F_BusStd2RGB">
<xsl:param name="iBusStd" select="'USER'"/>
<xsl:choose>
<xsl:when test="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB">
<xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB"/>
</xsl:when>
<xsl:otherwise>
<xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = 'USER')]/@RGB"/>
</xsl:otherwise>
</xsl:choose>
</xsl:template>
<xsl:template name="F_BusStd2RGB_LT">
<xsl:param name="iBusStd" select="'USER'"/>
<xsl:choose>
<xsl:when test="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB_LT">
<xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = $iBusStd)]/@RGB_LT"/>
</xsl:when>
<xsl:otherwise>
<xsl:value-of select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR[(@BUSSTD = 'USER')]/@RGB_LT"/>
</xsl:otherwise>
</xsl:choose>
</xsl:template>
<xsl:template name="F_IntcIdx2RGB">
<xsl:param name="iIntcIdx" select="'0'"/>
<xsl:variable name="index_" select="$iIntcIdx mod 9"/>
<xsl:choose>
<xsl:when test="exsl:node-set($COL_INTCS)/INTCCOLOR[(@INDEX = $index_)]/@RGB">
<xsl:value-of select="exsl:node-set($COL_INTCS)/INTCCOLOR[(@INDEX = $index_)]/@RGB"/>
</xsl:when>
<xsl:otherwise>
<xsl:value-of select="exsl:node-set($COL_INTCS)/INTCCOLOR[(@INDEX = '0')]/@RGB"/>
</xsl:otherwise>
</xsl:choose>
</xsl:template>
</xsl:stylesheet>

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<?xml version="1.0" standalone="no"?>
<xsl:stylesheet version="1.0"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
xmlns:exsl="http://exslt.org/common"
xmlns:xlink="http://www.w3.org/1999/xlink">
<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"
doctype-public="-//W3C//DTD SVG 1.0//EN"
doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/>
<xsl:variable name="G_ROOT" select="/"/>
<xsl:variable name="G_BIFTYPES">
<BIFTYPE TYPE="SLAVE"/>
<BIFTYPE TYPE="MASTER"/>
<BIFTYPE TYPE="MASTER_SLAVE"/>
<BIFTYPE TYPE="TARGET"/>
<BIFTYPE TYPE="INITIATOR"/>
<BIFTYPE TYPE="MONITOR"/>
<BIFTYPE TYPE="USER"/>
</xsl:variable>
<xsl:variable name="G_BUSSTDS">
<BUSSTD NAME="XIL"/>
<BUSSTD NAME="OCM"/>
<BUSSTD NAME="OPB"/>
<BUSSTD NAME="LMB"/>
<BUSSTD NAME="FSL"/>
<BUSSTD NAME="DCR"/>
<BUSSTD NAME="FCB"/>
<BUSSTD NAME="PLB"/>
<BUSSTD NAME="PLBV46"/>
<BUSSTD NAME="PLBV46_P2P"/>
<BUSSTD NAME="USER"/>
</xsl:variable>
</xsl:stylesheet>

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<?xml version="1.0" standalone="no"?>
<xsl:stylesheet version="1.0"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
xmlns:exsl="http://exslt.org/common"
xmlns:xlink="http://www.w3.org/1999/xlink">
<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"
doctype-public="-//W3C//DTD SVG 1.0//EN"
doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/>
<!--
======================================================
Function to put TEXT CSS and other Internal
Styling properties directly into the output
svg. The Qt 4.3 Renderer
cannot handle separate CSS StyleSheets
======================================================
-->
<xsl:template name="F_WriteText">
<xsl:param name="iClass" select="'_UNKNOWN_'"/>
<xsl:param name="iText" select="' '"/>
<xsl:param name="iX" select="'0'"/>
<xsl:param name="iY" select="'0'"/>
<!--
<xsl:message>TEXT <xsl:value-of select="$iText"/></xsl:message>
<xsl:message>CLASS <xsl:value-of select="$iClass"/></xsl:message>
-->
<xsl:element name="text">
<xsl:attribute name="x"><xsl:value-of select="$iX"/></xsl:attribute>
<xsl:attribute name="y"><xsl:value-of select="$iY"/></xsl:attribute>
<xsl:choose>
<xsl:when test="$iClass = 'sharedbus_label'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'12pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Verdana Courier Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'p2pbus_label'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Verdana Courier Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'p2pbus_label_horiz'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'12pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
<xsl:attribute name="writing-mode"><xsl:value-of select="'tb'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Verdana Courier Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'bif_label'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Verdana Courier Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'bc_ipinst'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Courier Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'bc_iptype'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_XLNX"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'iogrp_label'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_IORING"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'mpmc_title'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_WHITE"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'16pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'oblique'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'mpmc_biflabel'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_WHITE"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'intr_symbol'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'bkt_label'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'9pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'ipclass_label'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'9pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'key_header'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'key_title'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_XLNX"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'14pt'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'key_label'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'key_label_small'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'900'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'key_label_ul'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
<xsl:attribute name="text-decoration"><xsl:value-of select="'underline'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'ipd_portlabel'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'ipd_biflabel'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'normal'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'ipd_iptype'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_XLNX"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Verdana Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'ipd_ipname'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'8pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Courier Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'blkd_spec_name'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'start'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:when test="$iClass = 'blkd_spec_value_mid'">
<xsl:attribute name="fill"><xsl:value-of select="$COL_BLACK"/></xsl:attribute>
<xsl:attribute name="stroke"><xsl:value-of select="'none'"/></xsl:attribute>
<xsl:attribute name="font-size"><xsl:value-of select="'10pt'"/></xsl:attribute>
<xsl:attribute name="font-style"><xsl:value-of select="'italic'"/></xsl:attribute>
<xsl:attribute name="font-weight"><xsl:value-of select="'bold'"/></xsl:attribute>
<xsl:attribute name="text-anchor"><xsl:value-of select="'middle'"/></xsl:attribute>
<xsl:attribute name="font-family"><xsl:value-of select="'Courier Arial Helvetica san-serif'"/></xsl:attribute>
</xsl:when>
<xsl:otherwise><xsl:message>UNKNOWN Text style class <xsl:value-of select="$iClass"/></xsl:message></xsl:otherwise>
</xsl:choose>
<xsl:value-of select="$iText"/>
</xsl:element>
</xsl:template>
</xsl:stylesheet>
<!--
text.ioplblgrp {
fill: #000088;
stroke: none;
font-size: 10pt;
font-style: normal;
font-weight: 900;
text-anchor: middle;
font-family: Verdana Arial Helvetica sans-serif;
}
text.iplabel {
fill: #000000;
stroke: none;
font-size: 8pt;
font-style: italic;
font-weight: 800;
text-anchor: middle;
font-family: Courier Arial Helvetica sans-serif;
}
text.iptype {
fill: #AA0017;
stroke: none;
font-size: 8pt;
font-style: italic;
font-weight: bold;
text-anchor: middle;
font-family: Verdana Arial Helvetica sans-serif;
}
text.busintlabel {
fill: #810017;
stroke: none;
font-size: 7pt;
font-style: italic;
font-weight: 900;
text-anchor: middle;
font-family: Verdana Arial Helvetica sans-serif;
}
text.mpmcbiflabel {
fill: #FFFFFF;
stroke: none;
font-size: 6pt;
font-style: normal;
font-weight: 900;
text-anchor: middle;
font-family: Verdana Arial Helvetica sans-serif;
}
text.buslabel {
fill: #CC3333;
stroke: none;
font-size: 8pt;
font-style: italic;
font-weight: bold;
text-anchor: middle;
font-family: Verdana Arial Helvetica sans-serif;
}
text.ipclass {
fill: #000000;
stroke: none;
font-size: 7pt;
font-style: normal;
font-weight: bold;
text-anchor: start;
font-family: Times Arial Helvetica sans-serif;
}
text.procclass {
fill: #000000;
stroke: none;
font-size: 7pt;
font-style: normal;
font-weight: bold;
text-anchor: middle;
font-family: Times Arial Helvetica sans-serif;
}
text.portlabel {
fill: #000000;
stroke: none;
font-size: 8pt;
font-style: normal;
font-weight: bold;
text-anchor: middle;
font-family: Verdana Arial Helvetica sans-serif;
}
text.ipdbiflbl {
fill: #000000;
stroke: none;
font-size: 8pt;
font-style: normal;
font-weight: bold;
font-family: Verdana Arial Helvetica sans-serif;
}
text.mmMHeader {
fill: #FFFFFF;
stroke: none;
font-size: 10pt;
font-style: normal;
font-weight: bold;
text-anchor: middle;
font-family: Verdana Arial Helvetica sans-serif;
}
text.mmSHeader {
fill: #810017;
stroke: none;
font-size: 10pt;
font-style: normal;
font-weight: bold;
text-anchor: middle;
font-family: Verdana Arial Helvetica sans-serif;
}
text.dbglabel {
fill: #555555;
stroke: none;
font-size: 8pt;
font-style: normal;
font-weight: 900;
text-anchor: middle;
font-family: Times Arial Helvetica sans-serif;
}
text.iopnumb {
fill: #555555;
stroke: none;
font-size: 10pt;
font-style: normal;
font-weight: 900;
text-anchor: middle;
font-family: Verdana Arial Helvetica sans-serif;
}
tspan.iopgrp {
fill: #000000;
stroke: none;
font-size: 8pt;
font-style: normal;
font-weight: 900;
text-anchor: middle;
baseline-shift:super;
font-family: Arial Courier san-serif;
}
text.biflabel {
fill: #000000;
stroke: none;
font-size: 6pt;
font-style: normal;
font-weight: 900;
text-anchor: middle;
font-family: Verdana Arial Helvetica sans-serif;
}
text.p2pbuslabel {
fill: #000000;
stroke: none;
font-size: 10pt;
font-style: italic;
font-weight: bold;
text-anchor: start;
writing-mode: tb;
font-family: Verdana Arial Helvetica sans-serif;
}
text.mpbuslabel {
fill: #000000;
stroke: none;
font-size: 6pt;
font-style: italic;
font-weight: bold;
text-anchor: start;
writing-mode: tb;
font-family: Verdana Arial Helvetica sans-serif;
}
text.sharedbuslabel {
fill: #000000;
stroke: none;
font-size: 10pt;
font-style: italic;
font-weight: bold;
text-anchor: start;
font-family: Verdana Arial Helvetica sans-serif;
}
text.splitbustxt {
fill: #000000;
stroke: none;
font-size: 6pt;
font-style: normal;
font-weight: bold;
text-anchor: middle;
font-family: sans-serif;
}
text.horizp2pbuslabel {
fill: #000000;
stroke: none;
font-size: 6pt;
font-style: italic;
font-weight: bold;
text-anchor: start;
font-family: Verdana Arial Helvetica sans-serif;
}
text.keytitle {
fill: #AA0017;
stroke: none;
font-size: 12pt;
font-weight: bold;
text-anchor: middle;
font-family: Arial Helvetica sans-serif;
}
text.keyheader {
fill: #000000;
stroke: none;
font-size: 10pt;
font-weight: bold;
text-anchor: middle;
font-family: Arial Helvetica sans-serif;
}
text.keylabel {
fill: #000000;
stroke: none;
font-size: 8pt;
font-style: italic;
font-weight: bold;
text-anchor: start;
font-family: Verdana Arial Helvetica sans-serif;
}
text.keylblul {
fill: #000000;
stroke: none;
font-size: 8pt;
font-style: italic;
font-weight: bold;
text-anchor: start;
text-decoration: underline;
font-family: Verdana Arial Helvetica sans-serif;
}
text.specsheader {
fill: #000000;
stroke: none;
font-size: 10pt;
font-weight: bold;
text-anchor: start;
font-family: Arial Helvetica sans-serif;
}
text.specsvalue {
fill: #000000;
stroke: none;
font-size: 8pt;
font-style: italic;
font-weight: bold;
text-anchor: start;
font-family: Verdana Arial Helvetica sans-serif;
}
text.specsvaluemid {
fill: #000000;
stroke: none;
font-size: 8pt;
font-style: italic;
font-weight: bold;
text-anchor: middle;
font-family: Verdana Arial Helvetica sans-serif;
}
text.intrsymbol {
fill: #000000;
stroke: none;
font-size: 8pt;
font-weight: bold;
text-anchor: start;
font-family: Arial Helvetica sans-serif;
}
-->

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<?xml version="1.0" standalone="no"?>
<xsl:stylesheet version="1.0"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
xmlns:exsl="http://exslt.org/common"
xmlns:xlink="http://www.w3.org/1999/xlink">
<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"
doctype-public="-//W3C//DTD SVG 1.0//EN"
doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/>
<xsl:template name="Define_Busses">
<!--
<xsl:param name="drawarea_w" select="500"/>
<xsl:param name="drawarea_h" select="500"/>
-->
<xsl:for-each select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR">
<xsl:call-template name="Define_BusArrowsEastWest">
<xsl:with-param name="iBusStd" select="@BUSSTD"/>
</xsl:call-template>
<xsl:call-template name="Define_BusArrowsNorthSouth">
<xsl:with-param name="iBusStd" select="@BUSSTD"/>
</xsl:call-template>
<xsl:call-template name="Define_SplitBusses">
<xsl:with-param name="iBusStd" select="@BUSSTD"/>
</xsl:call-template>
</xsl:for-each>
<xsl:call-template name="Define_SharedBus">
<xsl:with-param name="iBusStd" select="'PLB'"/>
</xsl:call-template>
<xsl:call-template name="Define_SharedBus">
<xsl:with-param name="iBusStd" select="'PLBV46'"/>
</xsl:call-template>
<xsl:call-template name="Define_SharedBus">
<xsl:with-param name="iBusStd" select="'OPB'"/>
</xsl:call-template>
<xsl:call-template name="Define_SharedBus_Group"/>
</xsl:template>
<xsl:template name="Define_BusArrowsEastWest">
<xsl:param name="iBusStd" select="'PLB'"/>
<xsl:variable name="busStdColor_">
<xsl:call-template name="F_BusStd2RGB">
<xsl:with-param name="iBusStd" select="$iBusStd"/>
</xsl:call-template>
</xsl:variable>
<xsl:variable name="busStdColor_lt_">
<xsl:call-template name="F_BusStd2RGB_LT">
<xsl:with-param name="iBusStd" select="$iBusStd"/>
</xsl:call-template>
</xsl:variable>
<g id="{$iBusStd}_BusArrowEast">
<path class="bus"
d="M 0,0
L {$BLKD_BUS_ARROW_W}, {ceiling($BLKD_BUS_ARROW_H div 2)}
L 0,{$BLKD_BUS_ARROW_H},
Z" style="stroke:none; fill:{$busStdColor_}"/>
</g>
<g id="{$iBusStd}_BusArrowWest">
<use x="0" y="0" xlink:href="#{$iBusStd}_BusArrowEast" transform="scale(-1,1) translate({$BLKD_BUS_ARROW_W * -1},0)"/>
</g>
<g id="{$iBusStd}_BusArrowHInitiator">
<rect x="0"
y="{$BLKD_BUS_ARROW_G}"
width= "{$BLKD_BUS_ARROW_W}"
height="{$BLKD_P2P_BUS_W}"
style="stroke:none; fill:{$busStdColor_}"/>
</g>
</xsl:template>
<!--
<xsl:param name="bus_col" select="'OPB'"/>
-->
<xsl:template name="Define_BusArrowsNorthSouth">
<xsl:param name="iBusStd" select="'PLB'"/>
<xsl:variable name="busStdColor_">
<xsl:call-template name="F_BusStd2RGB">
<xsl:with-param name="iBusStd" select="$iBusStd"/>
</xsl:call-template>
</xsl:variable>
<xsl:variable name="busStdColor_lt_">
<xsl:call-template name="F_BusStd2RGB_LT">
<xsl:with-param name="iBusStd" select="$iBusStd"/>
</xsl:call-template>
</xsl:variable>
<g id="{$iBusStd}_BusArrowSouth">
<path class="bus"
d="M 0,0
L {$BLKD_BUS_ARROW_H},0
L {ceiling($BLKD_BUS_ARROW_H div 2)}, {$BLKD_BUS_ARROW_W}
Z" style="stroke:none; fill:{$busStdColor_}"/>
</g>
<g id="{$iBusStd}_BusArrowNorth">
<use x="0" y="0" xlink:href="#{$iBusStd}_BusArrowSouth" transform="scale(1,-1) translate(0,{$BLKD_BUS_ARROW_H * -1})"/>
</g>
<g id="{$iBusStd}_BusArrowInitiator">
<rect x="{$BLKD_BUS_ARROW_G}"
y="0"
width= "{$BLKD_BUS_ARROW_W - ($BLKD_BUS_ARROW_G * 2)}"
height="{$BLKD_BUS_ARROW_H}"
style="stroke:none; fill:{$busStdColor_}"/>
</g>
</xsl:template>
<xsl:template name="Draw_P2PBus">
<xsl:param name="iBusX" select="0"/>
<xsl:param name="iBusTop" select="0"/>
<xsl:param name="iBusBot" select="0"/>
<xsl:param name="iBusStd" select="'_bstd_'"/>
<xsl:param name="iBusName" select="'_p2pbus_'"/>
<xsl:param name="iBotBifType" select="'_unk_'"/>
<xsl:param name="iTopBifType" select="'_unk_'"/>
<xsl:variable name="busStdColor_">
<xsl:choose>
<xsl:when test="@BUSSTD">
<xsl:call-template name="F_BusStd2RGB">
<xsl:with-param name="iBusStd" select="@BUSSTD"/>
</xsl:call-template>
</xsl:when>
<xsl:when test="not($iBusStd = '_bstd_')">
<xsl:call-template name="F_BusStd2RGB">
<xsl:with-param name="iBusStd" select="$iBusStd"/>
</xsl:call-template>
</xsl:when>
<xsl:otherwise>
<xsl:call-template name="F_BusStd2RGB">
<xsl:with-param name="iBusStd" select="'TRS'"/>
</xsl:call-template>
</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="p2pH_" select="($iBusBot - $iBusTop) - ($BLKD_BUS_ARROW_H * 2)"/>
<xsl:variable name="botArrow_">
<xsl:choose>
<xsl:when test="((($iBotBifType = 'INITIATOR') or ($iBotBifType = 'MASTER')) and ($iBusStd = 'FSL'))">BusArrowInitiator</xsl:when>
<xsl:otherwise>BusArrowSouth</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="topArrow_">
<xsl:choose>
<xsl:when test="((($iTopBifType = 'INITIATOR') or ($iTopBifType = 'MASTER')) and ($iBusStd = 'FSL'))">BusArrowInitiator</xsl:when>
<xsl:otherwise>BusArrowNorth</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:if test="@BUSSTD">
<use x="{($iBusX + ceiling($BLKD_BIFC_W div 2)) - ceiling($BLKD_BUS_ARROW_W div 2)}"
y="{$iBusTop + ($BLKD_BIFC_H - $BLKD_BUS_ARROW_H) + $BLKD_BUS_ARROW_H}"
xlink:href="#{@BUSSTD}_{$topArrow_}"/>
<use x="{($iBusX + ceiling($BLKD_BIFC_W div 2)) - ceiling($BLKD_BUS_ARROW_W div 2)}"
y="{$iBusBot - $BLKD_BUS_ARROW_H}"
xlink:href="#{@BUSSTD}_{$botArrow_}"/>
</xsl:if>
<xsl:if test="(not(@BUSSTD) and not($iBusStd = '_bstd_'))">
<use x="{($iBusX + ceiling($BLKD_BIFC_W div 2)) - ceiling($BLKD_BUS_ARROW_W div 2)}"
y="{$iBusTop + ($BLKD_BIFC_H - $BLKD_BUS_ARROW_H) + $BLKD_BUS_ARROW_H}"
xlink:href="#{$iBusStd}_{$topArrow_}"/>
<use x="{($iBusX + ceiling($BLKD_BIFC_W div 2)) - ceiling($BLKD_BUS_ARROW_W div 2)}"
y="{$iBusBot - $BLKD_BUS_ARROW_H}"
xlink:href="#{$iBusStd}_{$botArrow_}"/>
</xsl:if>
<rect x="{($iBusX + ceiling($BLKD_BIFC_W div 2)) - ceiling($BLKD_BUS_ARROW_W div 2) + $BLKD_BUS_ARROW_G}"
y="{$iBusTop + $BLKD_BIFC_H + $BLKD_BUS_ARROW_H}"
height= "{$p2pH_ - ($BLKD_BUS_ARROW_H * 2)}"
width="{$BLKD_BUS_ARROW_W - ($BLKD_BUS_ARROW_G * 2)}"
style="stroke:none; fill:{$busStdColor_}"/>
<!--
<text class="p2pbuslabel"
x="{$iBusX + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 4}"
y="{$iBusTop + ($BLKD_BUS_ARROW_H * 3)}">
<xsl:value-of select="$iBusName"/>
</text>
-->
<xsl:call-template name="F_WriteText">
<xsl:with-param name="iX" select="($iBusX + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 4)"/>
<xsl:with-param name="iY" select="($iBusTop + ($BLKD_BUS_ARROW_H * 3))"/>
<xsl:with-param name="iText" select="$iBusName"/>
<xsl:with-param name="iClass" select="'p2pbus_label'"/>
</xsl:call-template>
<xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iBusName)]/@GROUP">
<!--
<text class="ioplblgrp"
x="{$iBusX + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6}"
y="{$iBusTop + ($BLKD_BUS_ARROW_H * 10)}">
<xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iBusName)]/@GROUP"/>
</text>
-->
<xsl:call-template name="F_WriteText">
<xsl:with-param name="iX" select="(iBusX + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 6)"/>
<xsl:with-param name="iY" select="($iBusTop + ($BLKD_BUS_ARROW_H * 10))"/>
<xsl:with-param name="iText" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iBusName)]/@GROUP"/>
<xsl:with-param name="iClass" select="'iogrp_label'"/>
</xsl:call-template>
</xsl:if>
</xsl:template>
<xsl:template name="Draw_Proc2ProcBus">
<xsl:param name="iBc_Y" select="0"/>
<xsl:param name="iBusStd" select="'_bstd_'"/>
<xsl:param name="iBusName" select="'_p2pbus_'"/>
<xsl:param name="iBcLeft_X" select="0"/>
<xsl:param name="iBcRght_X" select="0"/>
<xsl:param name="iLeftBifType" select="'_unk_'"/>
<xsl:param name="iRghtBifType" select="'_unk_'"/>
<xsl:variable name="busStdColor_">
<xsl:call-template name="F_BusStd2RGB">
<xsl:with-param name="iBusStd" select="$iBusStd"/>
</xsl:call-template>
</xsl:variable>
<xsl:variable name="pr2pr_W_" select="($iBcRght_X - $iBcLeft_X)"/>
<xsl:variable name="leftArrow_">
<xsl:choose>
<xsl:when test="((($iLeftBifType = 'INITIATOR') or ($iLeftBifType = 'MASTER')) and ($iBusStd = 'FSL'))">BusArrowHInitiator</xsl:when>
<xsl:otherwise>BusArrowWest</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="rghtArrow_">
<xsl:choose>
<xsl:when test="((($iRghtBifType = 'INITIATOR') or ($iRghtBifType = 'MASTER')) and ($iBusStd = 'FSL'))">BusArrowHInitiator</xsl:when>
<xsl:otherwise>BusArrowEast</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="bus_Y_" select="($iBc_Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2))"/>
<use x="{$iBcLeft_X}" y="{$bus_Y_}" xlink:href="#{$iBusStd}_{$leftArrow_}"/>
<use x="{$iBcRght_X - $BLKD_BUS_ARROW_W}" y="{$bus_Y_}" xlink:href="#{$iBusStd}_{$rghtArrow_}"/>
<rect x="{$iBcLeft_X + $BLKD_BUS_ARROW_W}"
y="{$bus_Y_ + $BLKD_BUS_ARROW_G}"
width= "{$pr2pr_W_ - (2 * $BLKD_BUS_ARROW_W)}"
height="{$BLKD_BUS_ARROW_H - (2 * $BLKD_BUS_ARROW_G)}" style="stroke:none; fill:{$busStdColor_}"/>
<!--
<text class="horizp2pbuslabel"
x="{$iBcLeft_X + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 4}"
y="{($bus_Y_)}"><xsl:value-of select="$iBusName"/></text>
<text class="horizp2pbuslabel"
x="{$iBcRght_X - (string-length($iBusName) * 8)}"
y="{($bus_Y_)}"><xsl:value-of select="$iBusName"/></text>
-->
<xsl:call-template name="F_WriteText">
<xsl:with-param name="iX" select="($iBcLeft_X + $BLKD_BUS_ARROW_W + ceiling($BLKD_BUS_ARROW_W div 2) + ceiling($BLKD_BUS_ARROW_W div 4) + 4)"/>
<xsl:with-param name="iY" select="$bus_Y_"/>
<xsl:with-param name="iText" select="$iBusName"/>
<xsl:with-param name="iClass" select="'p2pbus_label'"/>
</xsl:call-template>
<xsl:call-template name="F_WriteText">
<xsl:with-param name="iX" select="(iBcRght_X - (string-length($iBusName) * 8))"/>
<xsl:with-param name="iY" select="$bus_Y_"/>
<xsl:with-param name="iText" select="$iBusName"/>
<xsl:with-param name="iClass" select="'p2pbus_label'"/>
</xsl:call-template>
</xsl:template>
<xsl:template name="Draw_SplitConnBus">
<xsl:param name="iBc_X" select="0"/>
<xsl:param name="iBc_Y" select="0"/>
<xsl:param name="iBc_Type" select="'_unk_'"/>
<xsl:param name="iBc_Side" select="'_unk_'"/>
<xsl:param name="iBusStd" select="'_bstd_'"/>
<xsl:param name="iBusName" select="'_p2pbus_'"/>
<xsl:variable name="busStdColor_">
<xsl:call-template name="F_BusStd2RGB">
<xsl:with-param name="iBusStd" select="$iBusStd"/>
</xsl:call-template>
</xsl:variable>
<xsl:variable name="connArrow_">
<xsl:choose>
<xsl:when test="((($iBc_Type = 'INITIATOR') or ($iBc_Type = 'MASTER')) and ($iBusStd = 'FSL'))">BusArrowHInitiator</xsl:when>
<xsl:otherwise>BusArrowEast</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="arrow_Y_" select="($iBc_Y + ceiling($BLKD_BIFC_H div 2) - ceiling($BLKD_BUS_ARROW_H div 2))"/>
<xsl:variable name="bus_X_">
<xsl:choose>
<xsl:when test="$iBc_Side = '0'"><xsl:value-of select="($iBc_X - ($BLKD_BUS_ARROW_W * 2))"/></xsl:when>
<xsl:when test="$iBc_Side = '1'"><xsl:value-of select="($iBc_X + $BLKD_BIFC_W + $BLKD_BUS_ARROW_W)"/></xsl:when>
</xsl:choose>
</xsl:variable>
<!--
<use x="{$bus_X_}" y="{$arrow_Y_}" xlink:href="#{$busStd}_BusArrowHInitiator"/>
-->
<xsl:variable name="arrow_X_">
<xsl:choose>
<xsl:when test="$iBc_Side = '0'"><xsl:value-of select="($iBc_X - $BLKD_BUS_ARROW_W)"/></xsl:when>
<xsl:when test="$iBc_Side = '1'"><xsl:value-of select="($iBc_X + $BLKD_BIFC_W)"/></xsl:when>
</xsl:choose>
</xsl:variable>
<xsl:choose>
<xsl:when test="(($iBusStd = 'FSL') and (($iBc_Type = 'MASTER') or ($iBc_Type = 'INITIATOR')))">
<use x="{$arrow_X_}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_{$connArrow_}"/>
<use x="{$bus_X_}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_BusArrowHInitiator"/>
</xsl:when>
<xsl:when test="(($iBc_Side = '1') and not($iBusStd = 'FSL') and (($iBc_Type = 'MASTER') or ($iBc_Type = 'INITIATOR')))">
<use x="{$arrow_X_ - $BLKD_BIFC_W}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_SplitBus_WEST"/>
</xsl:when>
<xsl:when test="(($iBc_Side = '1') and (($iBc_Type = 'SLAVE') or ($iBc_Type = 'TARGET') or ($iBc_Type = 'USER')))">
<use x="{$arrow_X_}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_SplitBus_EAST"/>
</xsl:when>
<xsl:otherwise>
<use x="{$arrow_X_}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_{$connArrow_}"/>
<use x="{$bus_X_}" y="{$arrow_Y_}" xlink:href="#{$iBusStd}_BusArrowHInitiator"/>
</xsl:otherwise>
</xsl:choose>
<xsl:variable name="text_X_">
<xsl:choose>
<xsl:when test="$iBc_Side = '0'"><xsl:value-of select="($bus_X_ - $BLKD_BUS_ARROW_W - (string-length($iBusName) * 5))"/></xsl:when>
<xsl:when test="$iBc_Side = '1'"><xsl:value-of select="($bus_X_ + $BLKD_BUS_ARROW_W)"/></xsl:when>
</xsl:choose>
</xsl:variable>
<!--
<text class="horizp2pbuslabel"
x="{$text_X_}"
y="{($arrow_Y_)}">
<xsl:value-of select="$iBusName"/>
</text>
-->
<xsl:call-template name="F_WriteText">
<xsl:with-param name="iX" select="$text_X_"/>
<xsl:with-param name="iY" select="$arrow_Y_"/>
<xsl:with-param name="iText" select="$iBusName"/>
<xsl:with-param name="iClass" select="'p2pbus_label'"/>
</xsl:call-template>
</xsl:template>
<xsl:template name="Define_SharedBus">
<xsl:param name="iBusStd" select="'PLB46'"/>
<xsl:variable name="sharedbus_w_" select="($G_Total_DrawArea_W - ($BLKD_INNER_GAP * 2))"/>
<xsl:variable name="busStdColor_">
<xsl:call-template name="F_BusStd2RGB">
<xsl:with-param name="iBusStd" select="$iBusStd"/>
</xsl:call-template>
</xsl:variable>
<xsl:variable name="busStdColor_lt_">
<xsl:call-template name="F_BusStd2RGB_LT">
<xsl:with-param name="iBusStd" select="$iBusStd"/>
</xsl:call-template>
</xsl:variable>
<g id="{$iBusStd}_SharedBus">
<use x="0" y="0" xlink:href="#{$iBusStd}_BusArrowWest"/>
<use x="{$sharedbus_w_ - $BLKD_BUS_ARROW_W}" y="0" xlink:href="#{$iBusStd}_BusArrowEast"/>
<rect x="{$BLKD_BUS_ARROW_W}"
y="{$BLKD_BUS_ARROW_G}"
width= "{$sharedbus_w_ - ($BLKD_BUS_ARROW_W * 2)}"
height="{$BLKD_BUS_ARROW_H - (2 * $BLKD_BUS_ARROW_G)}" style="stroke:none; fill:{$busStdColor_}"/>
</g>
</xsl:template>
<xsl:template name="Define_SplitBusses">
<xsl:param name="iBusStd" select="'FSL'"/>
<xsl:variable name="busStdColor_">
<xsl:call-template name="F_BusStd2RGB">
<xsl:with-param name="iBusStd" select="$iBusStd"/>
</xsl:call-template>
</xsl:variable>
<xsl:variable name="bifc_r_" select="ceiling($BLKD_BIFC_W div 3)"/>
<g id="{$iBusStd}_SplitBus_EAST">
<use x="0" y="0" xlink:href="#{$iBusStd}_BusArrowWest"/>
<rect x="{$BLKD_BUS_ARROW_W}"
y="{$BLKD_BUS_ARROW_G}"
width= "{$BLKD_BIFC_W}"
height="{$BLKD_BUS_ARROW_H - (2 * $BLKD_BUS_ARROW_G)}" style="stroke:none; fill:{$busStdColor_}"/>
</g>
<xsl:variable name="splbus_w_" select="($BLKD_BUS_ARROW_W + $BLKD_BIFC_W + $BLKD_BIFC_Wi)"/>
<g id="{$iBusStd}_SplitBus_WEST">
<use x="0" y="0" xlink:href="#{$iBusStd}_SplitBus_EAST" transform="scale(-1,1) translate({$splbus_w_ * -1},0)"/>
</g>
<g id="{$iBusStd}_SplitBus_OneWay">
<rect x="0"
y="{$BLKD_BUS_ARROW_G}"
width= "{($BLKD_BUS_ARROW_W * 2)}"
height="{$BLKD_BUS_ARROW_H - (2 * $BLKD_BUS_ARROW_G)}" style="stroke:none; fill:{$busStdColor_}"/>
<rect x="{($BLKD_BUS_ARROW_W * 2)}"
y="0"
width= "{$BLKD_BUS_ARROW_H}"
height="{$BLKD_BUS_ARROW_H}" style="stroke:none; fill:{$busStdColor_}"/>
</g>
</xsl:template>
<xsl:template name="Define_SharedBus_Group">
<!-- The Bridges go into the shared bus shape -->
<xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE">
<xsl:variable name="modInst_" select="@INSTANCE"/>
<xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInst_)]/@MODTYPE"/>
<xsl:call-template name="Define_Peripheral">
<xsl:with-param name="iModVori" select="'normal'"/>
<xsl:with-param name="iModInst" select="$modInst_"/>
<xsl:with-param name="iModType" select="$modType_"/>
</xsl:call-template>
</xsl:for-each>
<g id="group_sharedBusses">
<!-- Draw the shared bus shapes first -->
<xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSSHAPES/MODULE">
<xsl:variable name="instance_" select="@INSTANCE"/>
<xsl:variable name="busStd_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $instance_)]/@BUSSTD"/>
<xsl:variable name="busIndex_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $instance_)]/@BUS_INDEX"/>
<xsl:variable name="busY_" select="($busIndex_ * $BLKD_SBS_LANE_H)"/>
<use x="0" y="{$busY_}" xlink:href="#{$busStd_}_SharedBus"/>
<!--
<text class="sharedbuslabel"
x="8"
y="{$busY_ + $BLKD_BUS_ARROW_H + 10}">
<xsl:value-of select="$instance_"/>
</text>
-->
<xsl:call-template name="F_WriteText">
<xsl:with-param name="iX" select="'8'"/>
<xsl:with-param name="iY" select="($busY_ + $BLKD_BUS_ARROW_H + 10)"/>
<xsl:with-param name="iText" select="$instance_"/>
<xsl:with-param name="iClass" select="'sharedbus_label'"/>
</xsl:call-template>
</xsl:for-each>
</g>
<g id="KEY_SharedBus">
<use x="0" y="0" xlink:href="#KEY_BusArrowWest"/>
<use x="30" y="0" xlink:href="#KEY_BusArrowEast"/>
<xsl:variable name="key_col_">
<xsl:call-template name="F_BusStd2RGB">
<xsl:with-param name="iBusStd" select="'KEY'"/>
</xsl:call-template>
</xsl:variable>
<rect x="{$BLKD_BUS_ARROW_W}"
y="{$BLKD_BUS_ARROW_G}"
width= "{30 - $BLKD_BUS_ARROW_W}"
height="{$BLKD_BUS_ARROW_H - (2 * $BLKD_BUS_ARROW_G)}" style="stroke:none; fill:{$key_col_}"/>
</g>
</xsl:template>
</xsl:stylesheet>

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<?xml version="1.0" standalone="no"?>
<xsl:stylesheet version="1.0"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
xmlns:exsl="http://exslt.org/common"
xmlns:xlink="http://www.w3.org/1999/xlink">
<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"
doctype-public="-//W3C//DTD SVG 1.0//EN"
doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/>
<!--
===========================================================================
CALCULATE GLOBAL VARIABLES BASED ON BLKDIAGRAM DEF IN INPUT XML
===========================================================================
-->
<xsl:variable name="G_Total_StandAloneMpmc_H">
<xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE">
<xsl:value-of select="($BLKD_MPMC_MOD_H + $BLKD_MPMC2PROC_GAP)"/>
</xsl:if>
<xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/MPMCSHAPE)">0</xsl:if>
</xsl:variable>
<xsl:variable name="G_Max_Stack_BlwSbs_H">
<xsl:call-template name="F_Calc_Max_Stack_BlwSbs_Height"/>
</xsl:variable>
<xsl:variable name="G_Max_Stack_AbvSbs_H">
<xsl:call-template name="F_Calc_Max_Stack_AbvSbs_Height"/>
</xsl:variable>
<xsl:variable name="G_Total_Stacks_W">
<xsl:call-template name="F_Calc_Stack_X">
<xsl:with-param name="iStackIdx" select="($G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH)"/>
</xsl:call-template>
</xsl:variable>
<xsl:variable name="G_NumOfSharedBusses" select="count($G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSSHAPES/MODULE)"/>
<xsl:variable name="G_Total_SharedBus_H" select="($G_NumOfSharedBusses * $BLKD_SBS_LANE_H)"/>
<xsl:variable name="G_NumOfBridges" select="count($G_ROOT/EDKSYSTEM/BLKDIAGRAM/BRIDGESHAPES/MODULE)"/>
<xsl:variable name="G_Total_Bridges_W" select="(($G_NumOfBridges * ($BLKD_MOD_W + ($BLKD_BUS_LANE_W * 2))) + $BLKD_BRIDGE_GAP)"/>
<xsl:variable name="G_Total_DrawArea_CLC" select="($G_Total_Stacks_W + $G_Total_Bridges_W + ($BLKD_INNER_GAP * 2))"/>
<xsl:variable name="G_Total_DrawArea_W">
<xsl:if test="$G_Total_DrawArea_CLC &gt; ($BLKD_KEY_W + $BLKD_SPECS_W + $BLKD_SPECS2KEY_GAP)">
<xsl:value-of select="$G_Total_DrawArea_CLC"/>
</xsl:if>
<xsl:if test="not($G_Total_DrawArea_CLC &gt; ($BLKD_KEY_W + $BLKD_SPECS2KEY_GAP + $BLKD_SPECS_W))">
<xsl:value-of select="($BLKD_KEY_W + $BLKD_SPECS_W + $BLKD_SPECS2KEY_GAP)"/>
</xsl:if>
</xsl:variable>
<xsl:variable name="G_IpBucketMods_H">
<xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/IPBUCKET/@MODS_H"><xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/IPBUCKET/@MODS_H"/></xsl:if>
<xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/IPBUCKET/@MODS_H)">0</xsl:if>
</xsl:variable>
<xsl:variable name="G_Total_IpBucket_H" select="($G_IpBucketMods_H * ($BLKD_MOD_H + $BLKD_BIF_H))"/>
<xsl:variable name="G_Total_UnkBucket_H">
<xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET">
<xsl:variable name="unkBucketMods_H_">
<xsl:if test="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@MODS_H"><xsl:value-of select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@MODS_H"/></xsl:if>
<xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@MODS_H)">0</xsl:if>
</xsl:variable>
<xsl:variable name="total_UnkMod_H_" select="($unkBucketMods_H_ * ($BLKD_MOD_H + $BLKD_BIF_H))"/>
<xsl:variable name="unkBucketBifs_H_">
<xsl:if test="/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@BIFS_H"><xsl:value-of select="/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@BIFS_H"/></xsl:if>
<xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET/@BIFS_H)">0</xsl:if>
</xsl:variable>
<xsl:variable name="total_UnkBif_H_" select="($unkBucketBifs_H_ * ($BLKD_MOD_H + $BLKD_BIF_H))"/>
<xsl:value-of select="($total_UnkBif_H_ + $total_UnkMod_H_)"/>
</xsl:if>
<xsl:if test="not($G_ROOT/EDKSYSTEM/BLKDIAGRAM/UNKBUCKET)">0</xsl:if>
</xsl:variable>
<xsl:variable name="G_SharedBus_Y" select="($BLKD_INNER_Y + $G_Total_StandAloneMpmc_H + $G_Max_Stack_AbvSbs_H + $BLKD_PROC2SBS_GAP)"/>
<!-- ===========================================================================
Calculate the width of the Block Diagram based on the total number of
buslanes and modules in the design. If there are no buslanes or modules,
a default width, just wide enough to display the KEY and SPECS is used
=========================================================================== -->
<xsl:variable name="G_Total_Blkd_W" select="($G_Total_DrawArea_W + (($BLKD_PRTCHAN_W + $BLKD_IORCHAN_W)* 2))"/>
<xsl:variable name="G_Total_Diag_W" select="$G_Total_Blkd_W"/>
<!-- =========================================================================== -->
<!-- Calculate the height of the Block Diagram based on the total number of -->
<!-- buslanes and modules in the design. Take into account special shapes such -->
<!-- as MultiProc shapes. -->
<!-- =========================================================================== -->
<xsl:variable name="G_Total_DrawArea_H" select="($G_Total_StandAloneMpmc_H + $G_Max_Stack_AbvSbs_H + $BLKD_PROC2SBS_GAP + $G_Total_SharedBus_H + $G_Max_Stack_BlwSbs_H + $BLKD_SBS2IP_GAP + $G_Total_IpBucket_H + $BLKD_IP2UNK_GAP + $G_Total_UnkBucket_H + ($BLKD_INNER_GAP * 2))"/>
<xsl:variable name="G_Total_Blkd_H" select="($G_Total_DrawArea_H + (($BLKD_PRTCHAN_H + $BLKD_IORCHAN_H)* 2))"/>
<xsl:variable name="G_Total_Diag_H">
<xsl:if test="($IN_TESTMODE = 'TRUE')">
<xsl:message>Generating Blkdiagram in TestMode </xsl:message>
<xsl:value-of select="$G_Total_Blkd_H"/>
</xsl:if>
<xsl:if test="(not($IN_TESTMODE) or ($IN_TESTMODE = 'FALSE'))">
<xsl:value-of select="($G_Total_Blkd_H + $BLKD_DRAWAREA2KEY_GAP + $BLKD_KEY_H)"/>
</xsl:if>
</xsl:variable>
</xsl:stylesheet>

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<?xml version="1.0" standalone="no"?>
<xsl:stylesheet version="1.0"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
xmlns:math="http://exslt.org/math"
xmlns:exsl="http://exslt.org/common"
xmlns:xlink="http://www.w3.org/1999/xlink"
extension-element-prefixes="math">
<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"
doctype-public="-//W3C//DTD SVG 1.0//EN"
doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/>
<!-- ======================= DEF BLOCK =============================== -->
<xsl:template name="Define_IOPorts">
<xsl:variable name="key_col_">
<xsl:call-template name="F_BusStd2RGB">
<xsl:with-param name="iBusStd" select="'KEY'"/>
</xsl:call-template>
</xsl:variable>
<xsl:variable name="key_lt_col_">
<xsl:call-template name="F_BusStd2RGB_LT">
<xsl:with-param name="iBusStd" select="'KEY'"/>
</xsl:call-template>
</xsl:variable>
<g id="G_IOPort">
<rect
x="0"
y="0"
width= "{$BLKD_IOP_W}"
height="{$BLKD_IOP_H}" style="fill:{$COL_IORING_LT}; stroke:{$COL_IORING}; stroke-width:1"/>
<path class="ioport"
d="M 0,0
L {$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)}
L 0,{$BLKD_IOP_H}
Z" style="stroke:none; fill:{$COL_SYSPRT}"/>
</g>
<g id="G_BIPort">
<rect
x="0"
y="0"
width= "{$BLKD_IOP_W}"
height="{$BLKD_IOP_H}" style="fill:{$COL_IORING_LT}; stroke:{$COL_IORING}; stroke-width:1"/>
<path class="btop"
d="M 0,{ceiling($BLKD_IOP_H div 2)}
{ceiling($BLKD_IOP_W div 2)},0
{$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)}
Z" style="stroke:none; fill:{$COL_SYSPRT}"/>
<path class="bbot"
d="M 0,{ceiling($BLKD_IOP_H div 2)}
{ceiling($BLKD_IOP_W div 2)},{$BLKD_IOP_H}
{$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)}
Z" style="stroke:none; fill:{$COL_SYSPRT}"/>
</g>
<g id="KEY_IOPort">
<rect
x="0"
y="0"
width= "{$BLKD_IOP_W}"
height="{$BLKD_IOP_H}" style="fill:{$key_lt_col_}; stroke:none;"/>
<path class="ioport"
d="M 0,0
L {$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)}
L 0,{$BLKD_IOP_H}
Z" style="stroke:none; fill:{$key_col_}"/>
</g>
<g id="KEY_BIPort">
<rect
x="0"
y="0"
width= "{$BLKD_IOP_W}"
height="{$BLKD_IOP_H}" style="fill:{$key_lt_col_}; stroke:none;"/>
<path class="btop"
d="M 0,{ceiling($BLKD_IOP_H div 2)}
{ceiling($BLKD_IOP_W div 2)},0
{$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)}
Z" style="stroke:none; fill:{$key_col_}"/>
<path class="bbot"
d="M 0,{ceiling($BLKD_IOP_H div 2)}
{ceiling($BLKD_IOP_W div 2)},{$BLKD_IOP_H}
{$BLKD_IOP_W},{ceiling($BLKD_IOP_H div 2)}
Z" style="stroke:none; fill:{$key_col_}"/>
</g>
<g id="KEY_INPort">
<use x="0" y="0" xlink:href="#KEY_IOPort"/>
<rect
x="{$BLKD_IOP_W}"
y="0"
width= "{ceiling($BLKD_IOP_W div 2)}"
height="{$BLKD_IOP_H}" style="fill:{$COL_SYSPRT}; stroke:none;"/>
</g>
<g id="KEY_OUTPort">
<use x="0" y="0" xlink:href="#KEY_IOPort" transform="scale(-1,1) translate({$BLKD_IOP_W * -1},0)"/>
<rect
x="{$BLKD_IOP_W}"
y="0"
width= "{ceiling($BLKD_IOP_W div 2)}"
height="{$BLKD_IOP_H}" style="fill:{$COL_SYSPRT}; stroke:none;"/>
</g>
<g id="KEY_INOUTPort">
<use x="0" y="0" xlink:href="#KEY_BIPort"/>
<rect
x="{$BLKD_IOP_W}"
y="0"
width= "{ceiling($BLKD_IOP_W div 2)}"
height="{$BLKD_IOP_H}" style="fill:{$COL_SYSPRT}; stroke:none;"/>
</g>
</xsl:template>
<!-- ======================= DRAW BLOCK =============================== -->
<xsl:template name="Draw_IOPorts">
<xsl:variable name="ports_count_" select="count($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT)"/>
<xsl:if test="($ports_count_ &gt; 30)">
<xsl:call-template name="Draw_IOPorts_4Sides"/>
</xsl:if>
<xsl:if test="($ports_count_ &lt;= 30)">
<xsl:call-template name="Draw_IOPorts_2Sides"/>
</xsl:if>
</xsl:template>
<xsl:template name="Draw_IOPorts_2Sides">
<xsl:variable name="ports_count_" select="count($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT)"/>
<xsl:variable name="ports_per_side_" select="ceiling($ports_count_ div 2)"/>
<xsl:variable name="h_ofs_">
<xsl:value-of select="$BLKD_PRTCHAN_W + ceiling(($G_Total_DrawArea_W - (($ports_per_side_ * $BLKD_IOP_W) + (($ports_per_side_ - 1) * $BLKD_IOP_SPC))) div 2)"/>
</xsl:variable>
<xsl:variable name="v_ofs_">
<xsl:value-of select="$BLKD_PRTCHAN_H + ceiling(($G_Total_DrawArea_H - (($ports_per_side_ * $BLKD_IOP_H) + (($ports_per_side_ - 1) * $BLKD_IOP_SPC))) div 2)"/>
</xsl:variable>
<xsl:for-each select="EXTERNALPORTS/PORT">
<xsl:sort data-type="number" select="@INDEX" order="ascending"/>
<xsl:variable name="poffset_" select="0"/>
<xsl:variable name="pcount_" select="$poffset_ + (position() -1)"/>
<xsl:variable name="pdir_">
<xsl:choose>
<xsl:when test="(@DIR='I' or @DIR='IN' or @DIR='INPUT')">I</xsl:when>
<xsl:when test="(@DIR='O' or @DIR='OUT' or @DIR='OUTPUT')">O</xsl:when>
<xsl:when test="(@DIR='IO' or @DIR='INOUT')">B</xsl:when>
<xsl:otherwise>I</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="pside_">
<xsl:choose>
<xsl:when test="($pcount_ &gt;= ($ports_per_side_ * 0) and ($pcount_ &lt; ($ports_per_side_ * 1)))">W</xsl:when>
<xsl:when test="($pcount_ &gt;= ($ports_per_side_ * 1) and ($pcount_ &lt; ($ports_per_side_ * 2)))">E</xsl:when>
<xsl:otherwise>D</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="pdec_">
<xsl:choose>
<xsl:when test="($pside_ = 'W')"><xsl:value-of select="($ports_per_side_ * 0)"/></xsl:when>
<xsl:when test="($pside_ = 'E')"><xsl:value-of select="($ports_per_side_ * 1)"/></xsl:when>
<xsl:otherwise>0</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="px_">
<xsl:choose>
<xsl:when test="($pside_ = 'W')"><xsl:value-of select="($BLKD_PRTCHAN_W - $BLKD_IOP_W)"/></xsl:when>
<xsl:when test="($pside_ = 'S')"><xsl:value-of select="($h_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_W)) - 2)"/></xsl:when>
<xsl:when test="($pside_ = 'E')"><xsl:value-of select="($BLKD_PRTCHAN_W + ($BLKD_IORCHAN_W * 2) + $G_Total_DrawArea_W)"/></xsl:when>
<xsl:when test="($pside_ = 'N')"><xsl:value-of select="($h_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_W)))"/></xsl:when>
<xsl:otherwise>0</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="py_">
<xsl:choose>
<xsl:when test="($pside_ = 'W')"><xsl:value-of select="($v_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_H)))"/></xsl:when>
<xsl:when test="($pside_ = 'S')"><xsl:value-of select="($BLKD_PRTCHAN_H + ($BLKD_IORCHAN_H * 2) + $G_Total_DrawArea_H)"/></xsl:when>
<xsl:when test="($pside_ = 'E')"><xsl:value-of select="($v_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_H)))"/></xsl:when>
<xsl:when test="($pside_ = 'N')"><xsl:value-of select="($BLKD_PRTCHAN_H - $BLKD_IOP_H)"/></xsl:when>
<xsl:otherwise>0</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="prot_">
<xsl:choose>
<xsl:when test="(($pside_ = 'W') and ($pdir_ = 'I'))">0</xsl:when>
<xsl:when test="(($pside_ = 'S') and ($pdir_ = 'I'))">-90</xsl:when>
<xsl:when test="(($pside_ = 'E') and ($pdir_ = 'I'))">180</xsl:when>
<xsl:when test="(($pside_ = 'N') and ($pdir_ = 'I'))">90</xsl:when>
<xsl:when test="(($pside_ = 'W') and ($pdir_ = 'O'))">180</xsl:when>
<xsl:when test="(($pside_ = 'S') and ($pdir_ = 'O'))">90</xsl:when>
<xsl:when test="(($pside_ = 'E') and ($pdir_ = 'O'))">0</xsl:when>
<xsl:when test="(($pside_ = 'N') and ($pdir_ = 'O'))">-90</xsl:when>
<xsl:when test="(($pside_ = 'W') and ($pdir_ = 'B'))">0</xsl:when>
<xsl:when test="(($pside_ = 'S') and ($pdir_ = 'B'))">0</xsl:when>
<xsl:when test="(($pside_ = 'E') and ($pdir_ = 'B'))">0</xsl:when>
<xsl:when test="(($pside_ = 'N') and ($pdir_ = 'B'))">0</xsl:when>
<xsl:otherwise>0</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="txo_">
<xsl:choose>
<xsl:when test="($pside_ = 'W')">-10</xsl:when>
<xsl:when test="($pside_ = 'S')">6</xsl:when>
<xsl:when test="($pside_ = 'E')"><xsl:value-of select="(($BLKD_IOP_W * 2) - 4)"/></xsl:when>
<xsl:when test="($pside_ = 'N')">6</xsl:when>
<xsl:otherwise>0</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="tyo_">
<xsl:choose>
<xsl:when test="($pside_ = 'W')"><xsl:value-of select="ceiling($BLKD_IOP_H div 2) + 6"/></xsl:when>
<xsl:when test="($pside_ = 'S')"><xsl:value-of select="($BLKD_IOP_H * 2) + 4"/></xsl:when>
<xsl:when test="($pside_ = 'E')"><xsl:value-of select="ceiling($BLKD_IOP_H div 2) + 6"/></xsl:when>
<xsl:when test="($pside_ = 'N')">-2</xsl:when>
<xsl:otherwise>0</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:if test="$pdir_ = 'B'">
<use x="{$px_}"
y="{$py_}"
id="{@NAME}"
xlink:href="#G_BIPort"
transform="rotate({$prot_},{$px_ + ceiling($BLKD_IOP_W div 2)},{$py_ + ceiling($BLKD_IOP_H div 2)})"/>
</xsl:if>
<xsl:if test="(($pside_ = 'S') and not($pdir_ = 'B'))">
<rect
x="{$px_}"
y="{$py_}"
width= "{$BLKD_IOP_W}"
height="{$BLKD_IOP_H}" style="stroke:{$COL_IORING}; stroke-width:1"/>
</xsl:if>
<xsl:if test="not($pdir_ = 'B')">
<use x="{$px_}"
y="{$py_}"
id="{@NAME}"
xlink:href="#G_IOPort"
transform="rotate({$prot_},{$px_ + ceiling($BLKD_IOP_W div 2)},{$py_ + ceiling($BLKD_IOP_H div 2)})"/>
</xsl:if>
<text class="iopnumb"
x="{$px_ + $txo_}"
y="{$py_ + $tyo_}">
<xsl:value-of select="@INDEX"/><tspan class="iopgrp"><xsl:value-of select="@GROUP"/></tspan>
</text>
</xsl:for-each>
</xsl:template>
<xsl:template name="Draw_IOPorts_4Sides">
<xsl:variable name="ports_count_" select="count($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT)"/>
<xsl:variable name="ports_per_side_" select="ceiling($ports_count_ div 4)"/>
<xsl:variable name="h_ofs_">
<xsl:value-of select="$BLKD_PRTCHAN_W + ceiling(($G_Total_DrawArea_W - (($ports_per_side_ * $BLKD_IOP_W) + (($ports_per_side_ - 1) * $BLKD_IOP_SPC))) div 2)"/>
</xsl:variable>
<xsl:variable name="v_ofs_">
<xsl:value-of select="$BLKD_PRTCHAN_H + ceiling(($G_Total_DrawArea_H - (($ports_per_side_ * $BLKD_IOP_H) + (($ports_per_side_ - 1) * $BLKD_IOP_SPC))) div 2)"/>
</xsl:variable>
<xsl:for-each select="$G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT">
<xsl:sort data-type="number" select="@INDEX" order="ascending"/>
<xsl:variable name="poffset_" select="0"/>
<xsl:variable name="pcount_" select="$poffset_ + (position() -1)"/>
<xsl:variable name="pdir_">
<xsl:choose>
<xsl:when test="(@DIR='I' or @DIR='IN' or @DIR='INPUT')">I</xsl:when>
<xsl:when test="(@DIR='O' or @DIR='OUT' or @DIR='OUTPUT')">O</xsl:when>
<xsl:when test="(@DIR='IO' or @DIR='INOUT')">B</xsl:when>
<xsl:otherwise>I</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="pside_">
<xsl:choose>
<xsl:when test="($pcount_ &gt;= ($ports_per_side_ * 0) and ($pcount_ &lt; ($ports_per_side_ * 1)))">W</xsl:when>
<xsl:when test="($pcount_ &gt;= ($ports_per_side_ * 1) and ($pcount_ &lt; ($ports_per_side_ * 2)))">S</xsl:when>
<xsl:when test="($pcount_ &gt;= ($ports_per_side_ * 2) and ($pcount_ &lt; ($ports_per_side_ * 3)))">E</xsl:when>
<xsl:when test="($pcount_ &gt;= ($ports_per_side_ * 3) and ($pcount_ &lt; ($ports_per_side_ * 4)))">N</xsl:when>
<xsl:otherwise>D</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="pdec_">
<xsl:choose>
<xsl:when test="($pside_ = 'W')"><xsl:value-of select="($ports_per_side_ * 0)"/></xsl:when>
<xsl:when test="($pside_ = 'S')"><xsl:value-of select="($ports_per_side_ * 1)"/></xsl:when>
<xsl:when test="($pside_ = 'E')"><xsl:value-of select="($ports_per_side_ * 2)"/></xsl:when>
<xsl:when test="($pside_ = 'N')"><xsl:value-of select="($ports_per_side_ * 3)"/></xsl:when>
<xsl:otherwise>0</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="px_">
<xsl:choose>
<xsl:when test="($pside_ = 'W')"><xsl:value-of select="($BLKD_PRTCHAN_W - $BLKD_IOP_W)"/></xsl:when>
<xsl:when test="($pside_ = 'S')"><xsl:value-of select="($h_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_W)) - 2)"/></xsl:when>
<xsl:when test="($pside_ = 'E')"><xsl:value-of select="($BLKD_PRTCHAN_W + ($BLKD_IORCHAN_W * 2) + $G_Total_DrawArea_W)"/></xsl:when>
<xsl:when test="($pside_ = 'N')"><xsl:value-of select="($h_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_W)))"/></xsl:when>
<xsl:otherwise>0</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="py_">
<xsl:choose>
<xsl:when test="($pside_ = 'W')"><xsl:value-of select="($v_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_H)))"/></xsl:when>
<xsl:when test="($pside_ = 'S')"><xsl:value-of select="($BLKD_PRTCHAN_H + ($BLKD_IORCHAN_H * 2) + $G_Total_DrawArea_H)"/></xsl:when>
<xsl:when test="($pside_ = 'E')"><xsl:value-of select="($v_ofs_ + (((position() - 1) - $pdec_) * ($BLKD_IOP_SPC + $BLKD_IOP_H)))"/></xsl:when>
<xsl:when test="($pside_ = 'N')"><xsl:value-of select="($BLKD_PRTCHAN_H - $BLKD_IOP_H)"/></xsl:when>
<xsl:otherwise>0</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="prot_">
<xsl:choose>
<xsl:when test="(($pside_ = 'W') and ($pdir_ = 'I'))">0</xsl:when>
<xsl:when test="(($pside_ = 'S') and ($pdir_ = 'I'))">-90</xsl:when>
<xsl:when test="(($pside_ = 'E') and ($pdir_ = 'I'))">180</xsl:when>
<xsl:when test="(($pside_ = 'N') and ($pdir_ = 'I'))">90</xsl:when>
<xsl:when test="(($pside_ = 'W') and ($pdir_ = 'O'))">180</xsl:when>
<xsl:when test="(($pside_ = 'S') and ($pdir_ = 'O'))">90</xsl:when>
<xsl:when test="(($pside_ = 'E') and ($pdir_ = 'O'))">0</xsl:when>
<xsl:when test="(($pside_ = 'N') and ($pdir_ = 'O'))">-90</xsl:when>
<xsl:when test="(($pside_ = 'W') and ($pdir_ = 'B'))">0</xsl:when>
<xsl:when test="(($pside_ = 'S') and ($pdir_ = 'B'))">0</xsl:when>
<xsl:when test="(($pside_ = 'E') and ($pdir_ = 'B'))">0</xsl:when>
<xsl:when test="(($pside_ = 'N') and ($pdir_ = 'B'))">0</xsl:when>
<xsl:otherwise>0</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="txo_">
<xsl:choose>
<xsl:when test="($pside_ = 'W')">-14</xsl:when>
<xsl:when test="($pside_ = 'S')">8</xsl:when>
<xsl:when test="($pside_ = 'E')"><xsl:value-of select="(($BLKD_IOP_W * 2) - 4)"/></xsl:when>
<xsl:when test="($pside_ = 'N')">8</xsl:when>
<xsl:otherwise>0</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="tyo_">
<xsl:choose>
<xsl:when test="($pside_ = 'W')"><xsl:value-of select="ceiling($BLKD_IOP_H div 2) + 6"/></xsl:when>
<xsl:when test="($pside_ = 'S')"><xsl:value-of select="($BLKD_IOP_H * 2) + 4"/></xsl:when>
<xsl:when test="($pside_ = 'E')"><xsl:value-of select="ceiling($BLKD_IOP_H div 2) + 6"/></xsl:when>
<xsl:when test="($pside_ = 'N')">-2</xsl:when>
<xsl:otherwise>0</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:if test="$pdir_ = 'B'">
<use x="{$px_}"
y="{$py_}"
id="{@NAME}"
xlink:href="#G_BIPort"
transform="rotate({$prot_},{$px_ + ceiling($BLKD_IOP_W div 2)},{$py_ + ceiling($BLKD_IOP_H div 2)})"/>
</xsl:if>
<xsl:if test="(($pside_ = 'S') and not($pdir_ = 'B'))">
<rect
x="{$px_}"
y="{$py_}"
width= "{$BLKD_IOP_W}"
height="{$BLKD_IOP_H}" style="stroke:{$COL_IORING}; stroke-width:1"/>
</xsl:if>
<xsl:if test="not($pdir_ = 'B')">
<use x="{$px_}"
y="{$py_}"
id="{@NAME}"
xlink:href="#G_IOPort"
transform="rotate({$prot_},{$px_ + ceiling($BLKD_IOP_W div 2)},{$py_ + ceiling($BLKD_IOP_H div 2)})"/>
</xsl:if>
<text class="iopnumb"
x="{$px_ + $txo_}"
y="{$py_ + $tyo_}"><xsl:value-of select="@INDEX"/><tspan class="iopgrp"><xsl:value-of select="@GROUP"/></tspan>
</text>
</xsl:for-each>
</xsl:template>
<xsl:template name="Define_ExtPortsTable">
<!--
<xsl:if test="$oriented_= 'WEST'"><xsl:value-of select="$proc2procX_ - (string-length(@BUSNAME) * 6)"/></xsl:if>
<xsl:variable name="max_name_" select="math:max(string-length($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT/@NAME))"/>
<xsl:variable name="max_sgnm_" select="math:max(string-length($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT/@SIGNAME))"/>
<xsl:message>MAX NAME <xsl:value-of select="$max_name_"/></xsl:message>
<xsl:message>MAX SIG <xsl:value-of select="$max_sgnm_"/></xsl:message>
-->
<xsl:variable name="ext_ports_">
<xsl:if test="not($G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT)">
<EXTPORT NAME="__none__" SIGNAME="__none_" NAMELEN="0" SIGLEN="0"/>
</xsl:if>
<xsl:if test="$G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT">
<xsl:for-each select="$G_ROOT/EDKSYSTEM/EXTERNALPORTS/PORT">
<EXTPORT NAME="{@NAME}" SIGNAME="{@SIGNAME}" NAMELEN="{string-length(@NAME)}" SIGLEN="{string-length(@SIGNAME)}"/>
</xsl:for-each>
</xsl:if>
</xsl:variable>
<xsl:variable name="max_name_" select="math:max(exsl:node-set($ext_ports_)/EXTPORT/@NAMELEN)"/>
<xsl:variable name="max_sign_" select="math:max(exsl:node-set($ext_ports_)/EXTPORT/@SIGLEN)"/>
<xsl:variable name="h_font_" select="12"/>
<xsl:variable name="w_font_" select="12"/>
<xsl:variable name="w_num_" select="($w_font_ * 5)"/>
<xsl:variable name="w_dir_" select="($w_font_ * 3)"/>
<xsl:variable name="w_lsbmsb_" select="($w_font_ * 9)"/>
<xsl:variable name="w_attr_" select="($w_font_ * 4)"/>
<xsl:variable name="w_name_" select="($w_font_ * $max_name_)"/>
<xsl:variable name="w_sign_" select="($w_font_ * $max_sign_)"/>
<xsl:variable name="w_table_" select="($w_num_ + $w_name_ + $w_dir_ + $w_sign_ + $w_attr_)"/>
<!--
<xsl:message>MAX NAME <xsl:value-of select="$max_name_"/></xsl:message>
<xsl:message>MAX SIG <xsl:value-of select="$max_sign_"/></xsl:message>
<xsl:message>W NUM <xsl:value-of select="$w_num_"/></xsl:message>
<xsl:message>W DIR <xsl:value-of select="$w_dir_"/></xsl:message>
<xsl:message>W NAM <xsl:value-of select="$w_name_"/></xsl:message>
<xsl:message>W SIG <xsl:value-of select="$w_sign_"/></xsl:message>
<xsl:message>W ATT <xsl:value-of select="$w_attr_"/></xsl:message>
<xsl:message>W TABLE <xsl:value-of select="$w_table_"/></xsl:message>
-->
<g id="BlkDiagram_ExtPortsTable">
<rect
x="0"
y="0"
width= "{$w_table_}"
height="{$h_font_}" style="fill:{$COL_RED}; stroke:none; stroke-width:1"/>
</g>
</xsl:template>
<!-- ======================= END MAIN BLOCK =========================== -->
</xsl:stylesheet>

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<?xml version="1.0" standalone="no"?>
<xsl:stylesheet version="1.0"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
xmlns:math="http://exslt.org/math"
xmlns:exsl="http://exslt.org/common"
xmlns:xlink="http://www.w3.org/1999/xlink"
extension-element-prefixes="math">
<xsl:output method="xml"
version="1.0"
encoding="UTF-8"
indent="yes"
doctype-public="-//W3C//DTD SVG 1.0//EN"
doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/>
<!-- ======================= DEF BLOCK =================================== -->
<xsl:template name="Define_AllStacks">
<xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/BCLANESPACES/BCLANESPACE[(@EAST &lt; $G_ROOT/EDKSYSTEM/BLKDIAGRAM/@STACK_HORIZ_WIDTH)]">
<xsl:call-template name="Define_Stack">
<xsl:with-param name="iStackIdx" select="@EAST"/>
</xsl:call-template>
</xsl:for-each>
</xsl:template>
<xsl:template name="Define_Stack">
<xsl:param name="iStackIdx" select="100"/>
<!-- Define the stack's peripheral shapes-->
<xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and not(@MODCLASS = 'MEMORY_UNIT'))]">
<xsl:for-each select="MODULE">
<xsl:variable name="modInst_" select="@INSTANCE"/>
<xsl:variable name="modType_" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $modInst_)]/@MODTYPE"/>
<xsl:call-template name="Define_Peripheral">
<xsl:with-param name="iModInst" select="$modInst_"/>
<xsl:with-param name="iModType" select="$modType_"/>
<xsl:with-param name="iShapeId" select="../@SHAPE_ID"/>
<xsl:with-param name="iHorizIdx" select="../@STACK_HORIZ_INDEX"/>
<xsl:with-param name="iVertiIdx" select="../@SHAPE_VERTI_INDEX"/>
</xsl:call-template>
</xsl:for-each>
</xsl:for-each>
<!-- Define the stack's memory shapes-->
<xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[((@STACK_HORIZ_INDEX = $iStackIdx) and (@MODCLASS='MEMORY_UNIT'))]">
<xsl:call-template name="Define_MemoryUnit">
<xsl:with-param name="iShapeId" select="@SHAPE_ID"/>
</xsl:call-template>
</xsl:for-each>
<!-- Define the stack's processors-->
<xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[@INSTANCE and @BIFS_W and @BIFS_H and (@STACK_HORIZ_INDEX = $iStackIdx)]">
<xsl:call-template name="Define_Processor"/>
</xsl:for-each>
<!-- Make an inventory of all the things in this processor's stack -->
<xsl:variable name="pstackW_">
<xsl:call-template name="F_Calc_Stack_Width">
<xsl:with-param name="iStackIdx" select="$iStackIdx"/>
</xsl:call-template>
</xsl:variable>
<xsl:variable name="pstackH_">
<xsl:call-template name="F_Calc_Stack_Height">
<xsl:with-param name="iStackIdx" select="$iStackIdx"/>
</xsl:call-template>
</xsl:variable>
<!--
<xsl:message>Proc Stack Height <xsl:value-of select="$pstackH_"/></xsl:message>
<xsl:message>Proc Stack Height <xsl:value-of select="$pstackH_"/></xsl:message>
-->
<xsl:variable name="procW_" select="$BLKD_MOD_W"/>
<xsl:variable name="procX_" select="(ceiling($pstackW_ div 2) - ceiling($procW_ div 2))"/>
<xsl:variable name="sbsGap_" select="($BLKD_PROC2SBS_GAP + $G_Total_SharedBus_H)"/>
<xsl:variable name="stack_name_">
<xsl:call-template name="F_generate_Stack_Name">
<xsl:with-param name="iHorizIdx" select="$iStackIdx"/>
</xsl:call-template>
</xsl:variable>
<!--
<xsl:message>Horiz index<xsl:value-of select="$stackIdx"/></xsl:message>
<xsl:message>Drawing stack <xsl:value-of select="$stack_name_"/></xsl:message>
-->
<!-- Now use all this stuff to draw the stack-->
<g id="{$stack_name_}">
<rect x="0"
y="0"
rx="6"
ry="6"
width = "{$pstackW_}"
height= "{$pstackH_}"
style="fill:{$COL_BG}; stroke:none;"/>
<!-- First draw the the processor's peripherals-->
<xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/CMPLXSHAPES/CMPLXSHAPE[(@STACK_HORIZ_INDEX = $iStackIdx)]">
<xsl:sort select="@STACK_VERTI_INDEX" data-type="number"/>
<xsl:variable name="shapeW_" select="(@MODS_W * $BLKD_MOD_W)"/>
<xsl:variable name="shapeX_" select="(ceiling($pstackW_ div 2) - ceiling($shapeW_ div 2))"/>
<xsl:variable name="stack_SymName_">
<xsl:call-template name="F_generate_Stack_SymbolName">
<xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/>
<xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/>
</xsl:call-template>
</xsl:variable>
<!--
<xsl:message>Drawing stack peripheral <xsl:value-of select="$stack_SymName_"/></xsl:message>
-->
<xsl:variable name="shapeY_">
<xsl:call-template name="F_Calc_Stack_Shape_Y">
<xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/>
<xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/>
</xsl:call-template>
</xsl:variable>
<use x="{$shapeX_}" y="{$shapeY_}" xlink:href="#{$stack_SymName_}"/>
</xsl:for-each>
<!-- Then draw the slave buckets for the shared busses that this processor is master to -->
<xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/SBSBUCKETS/SBSBUCKET[(@STACK_HORIZ_INDEX = $iStackIdx)]">
<xsl:sort select="@SHAPE_VERTI_INDEX" data-type="number"/>
<xsl:variable name="bucketW_" select="(($BLKD_MOD_BKTLANE_W * 2) + (($BLKD_MOD_W * @MODS_W) + ($BLKD_MOD_BUCKET_G * (@MODS_W - 1))))"/>
<xsl:variable name="bucketX_" select="(ceiling($pstackW_ div 2) - ceiling($bucketW_ div 2))"/>
<xsl:variable name="bucketY_">
<xsl:call-template name="F_Calc_Stack_Shape_Y">
<xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/>
<xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/>
</xsl:call-template>
</xsl:variable>
<!--
<xsl:message>SBS Bucket Y <xsl:value-of select="$bucketY_"/></xsl:message>
-->
<use x="{$bucketX_}" y="{$bucketY_}" xlink:href="#sbsbucket_{@BUSNAME}"/>
<xsl:variable name="slavesOfTxt_">SLAVES OF <xsl:value-of select="@BUSNAME"/></xsl:variable>
<!--
<text class="bkt_label"
x="{$bucketX_}"
y="{$bucketY_ - 4}"><xsl:value-of select="$slavesOfTxt_"/></text>
-->
<xsl:call-template name="F_WriteText">
<xsl:with-param name="iX" select="$bucketX_"/>
<xsl:with-param name="iY" select="($bucketY_ - 4)"/>
<xsl:with-param name="iText" select="$slavesOfTxt_"/>
<xsl:with-param name="iClass" select="'bkt_label'"/>
</xsl:call-template>
</xsl:for-each>
<!-- Then draw the the processor itself -->
<xsl:for-each select="$G_ROOT/EDKSYSTEM/BLKDIAGRAM/PROCSHAPES/MODULE[(@STACK_HORIZ_INDEX = $iStackIdx)]">
<xsl:sort select="@SHAPE_VERTI_INDEX" data-type="number"/>
<xsl:variable name="procY_">
<xsl:call-template name="F_Calc_Stack_Shape_Y">
<xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/>
<xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/>
</xsl:call-template>
</xsl:variable>
<xsl:variable name="stack_SymName_">
<xsl:call-template name="F_generate_Stack_SymbolName">
<xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/>
<xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/>
</xsl:call-template>
</xsl:variable>
<use x="{$procX_}" y="{$procY_}" xlink:href="#{$stack_SymName_}"/>
<!--
<xsl:if test = "not(@IS_LIKEPROC)">
<text class="ipclass_label"
x="{$procX_}"
y="{$procY_ - 4}">PROCESSOR</text>
</xsl:if>
<xsl:if test = "@IS_LIKEPROC = 'TRUE'">
<text class="ipclass_label"
x="{$procX_}"
y="{$procY_ - 4}">USER MODULE</text>
</xsl:if>
-->
<xsl:if test = "not(@IS_LIKEPROC)">
<xsl:call-template name="F_WriteText">
<xsl:with-param name="iX" select="$procX_"/>
<xsl:with-param name="iY" select="($procY_ - 4)"/>
<xsl:with-param name="iText" select="'PROCESSOR'"/>
<xsl:with-param name="iClass" select="'ipclass_label'"/>
</xsl:call-template>
</xsl:if>
<xsl:if test = "@IS_LIKEPROC = 'TRUE'">
<xsl:call-template name="F_WriteText">
<xsl:with-param name="iX" select="$procX_"/>
<xsl:with-param name="iY" select="($procY_ - 4)"/>
<xsl:with-param name="iText" select="'USER MODULE'"/>
<xsl:with-param name="iClass" select="'ipclass_label'"/>
</xsl:call-template>
</xsl:if>
</xsl:for-each>
</g>
</xsl:template>
<xsl:template name="Define_Processor">
<xsl:param name="iProcInst" select="@INSTANCE"/>
<xsl:param name="iModType" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/@MODTYPE"/>
<xsl:variable name="label_y_">
<xsl:value-of select="$BLKD_MOD_LANE_H"/>
</xsl:variable>
<!--
<xsl:message>The proctype is <xsl:value-of select="$procType"/></xsl:message>
-->
<xsl:variable name="procH_" select="(($BLKD_MOD_LANE_H * 2) + (($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIFS_H) + ($BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
<xsl:variable name="procW_" select="(($BLKD_MOD_LANE_W * 2) + (($BLKD_BIF_W * @BIFS_W) + $BLKD_MOD_BIF_GAP_H))"/>
<xsl:variable name="procColor_">
<xsl:choose>
<xsl:when test="contains($iModType,'microblaze')"><xsl:value-of select="$COL_PROC_BG_MB"/></xsl:when>
<xsl:when test="contains($iModType,'ppc')"><xsl:value-of select="$COL_PROC_BG_PP"/></xsl:when>
<xsl:otherwise>
<xsl:value-of select="$COL_PROC_BG_USR"/>
</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<!--
<xsl:message>The proc color is <xsl:value-of select="$procColor"/></xsl:message>
-->
<xsl:variable name="procName_">
<xsl:call-template name="F_generate_Stack_SymbolName">
<xsl:with-param name="iHorizIdx" select="@STACK_HORIZ_INDEX"/>
<xsl:with-param name="iVertiIdx" select="@SHAPE_VERTI_INDEX"/>
</xsl:call-template>
</xsl:variable>
<!--
<xsl:message>The proc name is <xsl:value-of select="$procName_"/></xsl:message>
-->
<g id="{$procName_}">
<rect x="0"
y="0"
rx="6"
ry="6"
width = "{$procW_}"
height= "{$procH_}"
style="fill:{$procColor_}; stroke:{$COL_WHITE}; stroke-width:2"/>
<rect x="{ceiling($procW_ div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}"
y="{$BLKD_MOD_LANE_H}"
rx="3"
ry="3"
width= "{$BLKD_MOD_LABEL_W}"
height="{$BLKD_MOD_LABEL_H}"
style="fill:{$COL_WHITE}; stroke:none;"/>
<!--
<text class="bciptype"
x="{ceiling($procW_ div 2)}"
y="{$BLKD_MOD_LANE_H + 8}">
<xsl:value-of select="$iModType"/>
</text>
<text class="bciplabel"
x="{ceiling($procW_ div 2)}"
y="{$BLKD_MOD_LANE_H + 16}">
<xsl:value-of select="$iProcInst"/>
</text>
-->
<xsl:call-template name="F_WriteText">
<xsl:with-param name="iX" select="ceiling($procW_ div 2)"/>
<xsl:with-param name="iY" select="($BLKD_MOD_LANE_H + 8)"/>
<xsl:with-param name="iText" select="$iModType"/>
<xsl:with-param name="iClass" select="'bc_iptype'"/>
</xsl:call-template>
<xsl:call-template name="F_WriteText">
<xsl:with-param name="iX" select="ceiling($procW_ div 2)"/>
<xsl:with-param name="iY" select="($BLKD_MOD_LANE_H + 16)"/>
<xsl:with-param name="iText" select="$iProcInst"/>
<xsl:with-param name="iClass" select="'bc_ipinst'"/>
</xsl:call-template>
<xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/@GROUP">
<rect x="{ceiling($BLKD_MOD_W div 2) - ceiling($BLKD_MOD_LABEL_W div 2)}"
y="{$BLKD_MOD_LANE_H + $BIF_H + ceiling($BLKD_BIF_H div 3) - 2}"
rx="3"
ry="3"
width= "{$BLKD_MOD_LABEL_W}"
height="{$BLKD_BIF_H}"
style="fill:{$COL_IORING_LT}; stroke:none;"/>
<!--
<text class="ioplblgrp"
x="{ceiling($BLKD_MOD_W div 2)}"
y="{$BLKD_MOD_LANE_H + $BIF_H + ceiling($BIF_H div 3) + 12}">
<xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/@GROUP"/>
</text>
-->
<xsl:call-template name="F_WriteText">
<xsl:with-param name="iX" select="ceiling($BLKD_MOD_W div 2)"/>
<xsl:with-param name="iY" select="($BLKD_MOD_LANE_H + $BIF_H + ceiling($BIF_H div 3) + 12)"/>
<xsl:with-param name="iText" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/@GROUP"/>
<xsl:with-param name="iClass" select="'iogrp_label'"/>
</xsl:call-template>
</xsl:if>
<xsl:for-each select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/BUSINTERFACE[(@BIF_X and @BIF_Y)]">
<xsl:variable name="bifBusStd_">
<xsl:choose>
<xsl:when test="@BUSSTD">
<xsl:value-of select="@BUSSTD"/>
</xsl:when>
<xsl:otherwise>
<xsl:value-of select="'TRS'"/>
</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="bifBusColor_">
<xsl:call-template name="F_BusStd2RGB">
<xsl:with-param name="iBusStd" select="$bifBusStd_"/>
</xsl:call-template>
</xsl:variable>
<xsl:variable name="bifName_">
<xsl:choose>
<xsl:when test="string-length(@NAME) &lt;= 5">
<xsl:value-of select="@NAME"/>
</xsl:when>
<xsl:otherwise>
<xsl:value-of select="substring(@NAME,0,5)"/>
</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="bif_x_" select="(( $BLKD_BIF_W * @BIF_X) + ($BLKD_MOD_BIF_GAP_H * @BIF_X) + ($BLKD_MOD_LANE_W * 1))"/>
<xsl:variable name="bif_y_" select="((($BLKD_BIF_H + $BLKD_MOD_BIF_GAP_V) * @BIF_Y) + ($BLKD_MOD_LANE_H + $BLKD_MOD_LABEL_H + $BLKD_MOD_BIF_GAP_V))"/>
<xsl:variable name="horz_line_y_" select="($bif_y_ + ceiling($BLKD_BIFC_H div 2))"/>
<xsl:variable name="horz_line_x1_">
<xsl:choose>
<xsl:when test="@BIF_X = '0'">0</xsl:when>
<xsl:otherwise><xsl:value-of select="($BLKD_MOD_W - $BLKD_MOD_LANE_W)"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="horz_line_x2_">
<xsl:choose>
<xsl:when test="@BIF_X = '0'"><xsl:value-of select="$BLKD_MOD_LANE_W"/></xsl:when>
<xsl:otherwise><xsl:value-of select="$BLKD_MOD_W + 1"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<line x1="{$horz_line_x1_}"
y1="{$horz_line_y_ - 2}"
x2="{$horz_line_x2_}"
y2="{$horz_line_y_ - 2}"
style="stroke:{$bifBusColor_};stroke-width:1"/>
<use x="{$bif_x_}" y="{$bif_y_}" xlink:href="#{$bifBusStd_}_BifLabel"/>
<!--
<text class="bif_label"
x="{$bif_x_ + ceiling($BIF_W div 2)}"
y="{$bif_y_ + ceiling($BIF_H div 2) + 3}">
<xsl:value-of select="$bifName_"/>
</text>
-->
<xsl:call-template name="F_WriteText">
<xsl:with-param name="iX" select="($bif_x_ + ceiling($BIF_W div 2))"/>
<xsl:with-param name="iY" select="($bif_y_ + ceiling($BIF_H div 2) + 3)"/>
<xsl:with-param name="iText" select="$bifName_"/>
<xsl:with-param name="iClass" select="'bif_label'"/>
</xsl:call-template>
</xsl:for-each>
<xsl:variable name="intcIdx_">
<xsl:choose>
<xsl:when test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/INTERRUPTINFO/@INTC_INDEX">
<xsl:value-of select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $iProcInst)]/INTERRUPTINFO/@INTC_INDEX"/>
</xsl:when>
<xsl:otherwise>"_no_interrupt_cntlr_"</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<!--
<xsl:message> The intc index should <xsl:value-of select="$interrupt_cntlr_"/></xsl:message>
<xsl:message> The intc index is <xsl:value-of select="/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $interrupt_cntlr_)]/@INTC_INDEX"/></xsl:message>
-->
<xsl:if test="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(INTERRUPTINFO[(@INTC_INDEX = $intcIdx_)])]">
<xsl:variable name="intrColor_">
<xsl:call-template name="F_IntcIdx2RGB">
<xsl:with-param name="iIntcIdx" select="$intcIdx_"/>
<!--
<xsl:with-param name="iIntcIdx" select="$G_ROOT/EDKSYSTEM/MODULES/MODULE[(@INSTANCE = $interrupt_cntlr_)]/INTERRUPTINFO/@INTC_INDEX"/>
-->
</xsl:call-template>
</xsl:variable>
<xsl:call-template name="F_draw_InterruptedProc">
<xsl:with-param name="iIntr_X" select="($BLKD_MOD_W - ceiling($BLKD_INTR_W div 2))"/>
<xsl:with-param name="iIntr_Y" select="3"/>
<xsl:with-param name="iIntr_COL" select="$intrColor_"/>
<xsl:with-param name="iIntr_IDX" select="$intcIdx_"/>
</xsl:call-template>
</xsl:if>
</g>
</xsl:template>
</xsl:stylesheet>

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Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/MdtTinySvgDiag_BifShapes.xsl Normal file
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<?xml version="1.0" standalone="no"?>
<xsl:stylesheet version="1.0"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
xmlns:exsl="http://exslt.org/common"
xmlns:xlink="http://www.w3.org/1999/xlink">
<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"
doctype-public="-//W3C//DTD SVG 1.0//EN"
doctype-system="http://www.w3.org/TR/SVG/DTD/svg10.dtd"/>
<!-- ======================= DEF BLOCK =================================== -->
<xsl:template name="Define_ConnectedBifTypes">
<xsl:for-each select="exsl:node-set($COL_BUSSTDS)/BUSCOLOR">
<xsl:variable name="busStd_" select="@BUSSTD"/>
<xsl:for-each select="exsl:node-set($G_BIFTYPES)/BIFTYPE">
<xsl:variable name="bifType_" select="@TYPE"/>
<xsl:variable name="connectedBifs_cnt_" select="count($G_ROOT/EDKSYSTEM/MODULES/MODULE/BUSINTERFACE[((@IS_INMHS = 'TRUE') and (@TYPE = $bifType_) and (@BUSSTD = $busStd_))])"/>
<xsl:if test="($connectedBifs_cnt_ &gt; 0)">
<!--
<xsl:message>DEBUG : Connected BifType : <xsl:value-of select="$busStd_"/> : <xsl:value-of select="@TYPE"/> : <xsl:value-of select="$connectedBifs_cnt_"/> </xsl:message>
-->
<xsl:call-template name="Define_BifTypeConnector">
<xsl:with-param name="iBusStd" select="$busStd_"/>
<xsl:with-param name="iBifType" select="$bifType_"/>
</xsl:call-template>
<xsl:call-template name="Define_BifLabel">
<xsl:with-param name="iBusStd" select="$busStd_"/>
</xsl:call-template>
</xsl:if>
</xsl:for-each>
</xsl:for-each>
<xsl:for-each select="exsl:node-set($G_BIFTYPES)/BIFTYPE">
<xsl:variable name="bifType_" select="@TYPE"/>
<xsl:call-template name="Define_BifTypeConnector">
<xsl:with-param name="iBusStd" select="'KEY'"/>
<xsl:with-param name="iBifType" select="$bifType_"/>
</xsl:call-template>
<xsl:call-template name="Define_BifLabel">
<xsl:with-param name="iBusStd" select="'KEY'"/>
</xsl:call-template>
</xsl:for-each>
</xsl:template>
<xsl:template name="Define_BifLabel">
<xsl:param name="iBusStd" select="'OPB'"/>
<xsl:variable name="busStdColor_">
<xsl:call-template name="F_BusStd2RGB">
<xsl:with-param name="iBusStd" select="$iBusStd"/>
</xsl:call-template>
</xsl:variable>
<g id="{$iBusStd}_BifLabel">
<rect x="0"
y="0"
rx="3"
ry="3"
width= "{$BIF_W}"
height="{$BIF_H}"
style="fill:{$busStdColor_}; stroke:black; stroke-width:1"/>
</g>
</xsl:template>
<xsl:template name="Define_BifTypeConnector">
<xsl:param name="iBusStd" select="'OPB'"/>
<xsl:param name="iBifType" select="'USER'"/>
<xsl:variable name="busStdColor_">
<xsl:call-template name="F_BusStd2RGB">
<xsl:with-param name="iBusStd" select="$iBusStd"/>
</xsl:call-template>
</xsl:variable>
<xsl:variable name="busStdColor_lt_">
<xsl:call-template name="F_BusStd2RGB_LT">
<xsl:with-param name="iBusStd" select="$iBusStd"/>
</xsl:call-template>
</xsl:variable>
<xsl:variable name="bifc_wi_" select="ceiling($BIFC_W div 3)"/>
<xsl:variable name="bifc_hi_" select="ceiling($BIFC_H div 3)"/>
<xsl:choose>
<xsl:when test="$iBifType = 'SLAVE'">
<g id="{$iBusStd}_busconn_{$iBifType}">
<circle
cx="{ceiling($BIFC_W div 2)}"
cy="{ceiling($BIFC_H div 2)}"
r="{ceiling($BIFC_W div 2)}"
style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/>
<circle
cx="{ceiling($BIFC_W div 2) + 0.5}"
cy="{ceiling($BIFC_H div 2)}"
r="{ceiling($BIFC_Wi div 2)}"
style="fill:{$busStdColor_}; stroke:none;"/>
</g>
</xsl:when>
<xsl:when test="$iBifType = 'MASTER'">
<g id="{$iBusStd}_busconn_{$iBifType}">
<rect x="0"
y="0"
width= "{$BIFC_W}"
height="{$BIFC_H}"
style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/>
<rect x="{$BIFC_dx + 0.5}"
y="{$BIFC_dy}"
width= "{$BIFC_Wi}"
height="{$BIFC_Hi}"
style="fill:{$busStdColor_}; stroke:none;"/>
</g>
</xsl:when>
<xsl:when test="$iBifType = 'INITIATOR'">
<g id="{$iBusStd}_busconn_{$iBifType}">
<rect x="0"
y="0"
width= "{$BIFC_W}"
height="{$BIFC_H}"
style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/>
<rect x="{$BIFC_dx + 0.5}"
y="{$BIFC_dy}"
width= "{$BIFC_Wi}"
height="{$BIFC_Hi}"
style="fill:{$busStdColor_}; stroke:none;"/>
</g>
</xsl:when>
<xsl:when test="$iBifType = 'TARGET'">
<g id="{$iBusStd}_busconn_{$iBifType}">
<circle
cx="{ceiling($BIFC_W div 2)}"
cy="{ceiling($BIFC_H div 2)}"
r="{ceiling($BIFC_W div 2)}"
style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/>
<circle
cx="{ceiling($BIFC_W div 2) + 0.5}"
cy="{ceiling($BIFC_H div 2)}"
r="{ceiling($BIFC_Wi div 2)}"
style="fill:{$busStdColor_}; stroke:none;"/>
</g>
</xsl:when>
<xsl:when test="$iBifType = 'MASTER_SLAVE'">
<g id="{$iBusStd}_busconn_{$iBifType}">
<circle
cx="{ceiling($BIFC_W div 2)}"
cy="{ceiling($BIFC_H div 2)}"
r="{ceiling($BIFC_W div 2)}"
style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/>
<circle
cx="{ceiling($BIFC_W div 2) + 0.5}"
cy="{ceiling($BIFC_H div 2)}"
r="{ceiling($BIFC_Wi div 2)}"
style="fill:{$busStdColor_}; stroke:none;"/>
<rect
x="0"
y="{ceiling($BIFC_H div 2)}"
width= "{$BIFC_W}"
height="{ceiling($BIFC_H div 2)}"
style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/>
<rect
x="{$BIFC_dx + 0.5}"
y="{ceiling($BIFC_H div 2)}"
width= "{$BIFC_Wi}"
height="{ceiling($BIFC_Hi div 2)}"
style="fill:{$busStdColor_}; stroke:none;"/>
</g>
</xsl:when>
<xsl:when test="$iBifType = 'MONITOR'">
<g id="{$iBusStd}_busconn_{$iBifType}">
<rect
x="0"
y="0.5"
width= "{$BIFC_W}"
height="{ceiling($BIFC_Hi div 2)}"
style="fill:{$busStdColor_}; stroke:none;"/>
<rect
x="0"
y="{ceiling($BIFC_H div 2) + 4}"
width= "{$BIFC_W}"
height="{ceiling($BIFC_Hi div 2)}"
style="fill:{$busStdColor_}; stroke:none;"/>
</g>
</xsl:when>
<xsl:when test="$iBifType = 'USER'">
<g id="{$iBusStd}_busconn_USER">
<circle
cx="{ceiling($BIFC_W div 2)}"
cy="{ceiling($BIFC_H div 2)}"
r="{ceiling($BIFC_W div 2)}"
style="fill:{$busStdColor_lt_}; stroke:{$busStdColor_}; stroke-width:1"/>
<circle
cx="{ceiling($BIFC_W div 2) + 0.5}"
cy="{ceiling($BIFC_H div 2)}"
r="{ceiling($BIFC_Wi div 2)}"
style="fill:{$busStdColor_}; stroke:none;"/>
</g>
</xsl:when>
<xsl:otherwise>
<g id="{$iBusStd}_busconn_{$iBifType}">
<circle
cx="{ceiling($BIFC_W div 2)}"
cy="{ceiling($BIFC_H div 2)}"
r="{ceiling($BIFC_W div 2)}"
style="fill:{$COL_WHITE}; stroke:{$busStdColor_}; stroke-width:1"/>
<circle
cx="{ceiling($BIFC_W div 2) + 0.5}"
cy="{ceiling($BIFC_H div 2)}"
r="{ceiling($BIFC_Wi div 2)}"
style="fill:{$COL_WHITE}; stroke:none;"/>
</g>
</xsl:otherwise>
</xsl:choose>
</xsl:template>
</xsl:stylesheet>

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Demo/PPC440_Xilinx_Virtex5_GCC/__xps/.dswkshop/svg10.dtd Normal file
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1
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/bitinit.opt Normal file
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$(PPC440_0_BOOTLOOP)

236
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/map.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Map" num="220" delta="new" >The command line option -timing is automatically supported for this architecture. Therefore, it is not necessary to specify this option.
</msg>
<msg type="warning" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">N194</arg> has no load.
</msg>
<msg type="warning" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">1200</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="4">N195,
N196,
N197,
N198,
N199</arg>
To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.
</msg>
<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.
</msg>
<msg type="info" file="MapLib" num="159" delta="new" >Net Timing constraints on signal <arg fmt="%s" index="1">fpga_0_SysACE_CompactFlash_SysACE_CLK_pin</arg> are pushed forward through input buffer.
</msg>
<msg type="info" file="MapLib" num="856" delta="new" >PLL_ADV <arg fmt="%s" index="1">clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst</arg> CLKIN2 pin was disconnected because a constant 1 is driving the CLKINSEL pin.
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin</arg> connected to top level port <arg fmt="%s" index="2">fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">fpga_0_Ethernet_MAC_PHY_col_pin</arg> connected to top level port <arg fmt="%s" index="2">fpga_0_Ethernet_MAC_PHY_col_pin</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="41" delta="new" >All members of TNM group &quot;<arg fmt="%s" index="1">ppc440_0_PPCS0PLBMBUSY</arg>&quot; have been optimized out of the design.
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0</arg> of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0</arg> of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1</arg> of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1</arg> of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst</arg> of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst</arg> of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst</arg> of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst</arg> of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank</arg> of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank</arg> of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
</msg>
<msg type="info" file="Pack" num="1716" delta="new" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg>
<msg type="info" file="Pack" num="1720" delta="new" >Initializing voltage to <arg fmt="%0.3f" index="1">0.950</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">0.950</arg> to <arg fmt="%0.3f" index="3">1.050</arg> Volts)
</msg>
<msg type="warning" file="Timing" num="3223" delta="new" >Timing constraint <arg fmt="%s" index="1">TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP &quot;TNM_RDEN_SEL_MUX&quot; TO TIMEGRP &quot;TNM_CLK0&quot; TS_MC_CLK * 4</arg> ignored during timing analysis.</msg>
<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Map" num="215" delta="new" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
<msg type="warning" file="Place" num="838" delta="new" >An IO Bus with more than one IO standard is found.
<arg fmt="%s" index="1">Components associated with this bus are as follows:
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin&lt;7&gt; IOSTANDARD = LVCMOS25
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin&lt;6&gt; IOSTANDARD = LVCMOS25
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin&lt;5&gt; IOSTANDARD = LVCMOS25
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin&lt;4&gt; IOSTANDARD = LVCMOS18
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin&lt;3&gt; IOSTANDARD = LVCMOS25
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin&lt;2&gt; IOSTANDARD = LVCMOS18
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin&lt;1&gt; IOSTANDARD = LVCMOS18
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin&lt;0&gt; IOSTANDARD = LVCMOS18
</arg>
</msg>
<msg type="warning" file="Place" num="838" delta="new" >An IO Bus with more than one IO standard is found.
<arg fmt="%s" index="1">Components associated with this bus are as follows:
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;31&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;30&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;29&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;28&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;27&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;26&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;25&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;24&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;23&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;22&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;21&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;20&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;19&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;18&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;17&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;16&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;15&gt; IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;14&gt; IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;13&gt; IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;12&gt; IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;11&gt; IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;10&gt; IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;9&gt; IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;8&gt; IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;7&gt; IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;6&gt; IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;5&gt; IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;4&gt; IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;3&gt; IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;2&gt; IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;1&gt; IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;0&gt; IOSTANDARD = LVCMOS33
</arg>
</msg>
<msg type="info" file="Pack" num="1650" delta="new" >Map created a placed design.
</msg>
<msg type="warning" file="PhysDesignRules" num="0">One or more GTXs are being used in this design. Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX Transceiver User Guide to ensure that the design SelectIO usage meets the guidelines to minimize the impact on GTX performance.
</msg>
<msg type="warning" file="PhysDesignRules" num="372" delta="new" >Gated clock. Clock net <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset&lt;0&gt;</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
<msg type="warning" file="PhysDesignRules" num="372" delta="new" >Gated clock. Clock net <arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n&lt;0&gt;</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn&lt;0&gt;</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr&lt;31&gt;</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr&lt;30&gt;</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
</messages>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="ConstraintSystem" num="65" delta="new" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;PCIe_Bridge/Bridge_Clk&quot; PERIOD = 8 ns HIGH 50%;&gt; [system.pcf(66101)]</arg> overrides constraint <arg fmt="%s" index="2">&lt;NET &quot;PCIe_Bridge/Bridge_Clk&quot; PERIOD = 8 ns HIGH 50%;&gt; [system.pcf(66100)]</arg>.
</msg>
<msg type="warning" file="Timing" num="3223" delta="new" >Timing constraint <arg fmt="%s" index="1">TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP &quot;TNM_RDEN_SEL_MUX&quot; TO TIMEGRP &quot;TNM_CLK0&quot; TS_MC_CLK * 4;</arg> ignored during timing analysis.</msg>
<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n&lt;0&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn&lt;0&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr&lt;31&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr&lt;30&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="info" file="Route" num="501" delta="new" >One or more directed routing (DIRT) constraints generated for a specific device have been found. Note that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail, verify that the same connectivity is available in the target device for this implementation.
</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg>
<msg type="warning" file="ParHelpers" num="361" delta="new" >There are <arg fmt="%d" index="1">5</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
<msg type="warning" file="Par" num="283" delta="new" >There are <arg fmt="%d" index="1">5</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
<msg type="info" file="ParHelpers" num="197" delta="new" >Number of &quot;Exact&quot; mode Directed Routing Constraints: <arg fmt="%d" index="1">128</arg>
</msg>
<msg type="info" file="ParHelpers" num="199" delta="new" >All &quot;EXACT&quot; mode Directed Routing constrained nets successfully routed. The number of constraints found: <arg fmt="%d" index="1">128</arg>, number successful: <arg fmt="%d" index="2">128</arg>
</msg>
</messages>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="ConstraintSystem" num="65" delta="new" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;PCIe_Bridge/Bridge_Clk&quot; PERIOD = 8 ns HIGH 50%;&gt; [system.pcf(66101)]</arg> overrides constraint <arg fmt="%s" index="2">&lt;NET &quot;PCIe_Bridge/Bridge_Clk&quot; PERIOD = 8 ns HIGH 50%;&gt; [system.pcf(66100)]</arg>.
</msg>
<msg type="warning" file="Timing" num="3223" delta="new" >Timing constraint <arg fmt="%s" index="1">TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP &quot;TNM_RDEN_SEL_MUX&quot; TO TIMEGRP &quot;TNM_CLK0&quot; TS_MC_CLK * 4;</arg> ignored during timing analysis.</msg>
<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
</messages>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>

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--------------------
Xst NTRC: "/" : OUT_OF_DATE
--------------------
Map NTRC: "/" : OUT_OF_DATE

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
<files/>
<properties>
<property xil_pn:name="Device" xil_pn:value="xa2c*"/>
<property xil_pn:name="Device Family" xil_pn:value="Automotive CoolRunner2"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="system"/>
<property xil_pn:name="PROP_Enable_Incremental_Messaging" xil_pn:value="true"/>
<property xil_pn:name="PROP_Enable_Message_Filtering" xil_pn:value="true"/>
<property xil_pn:name="Package" xil_pn:value="*"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-*"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
<property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
</properties>
<bindings/>
<libraries/>
<partitions>
<partition xil_pn:name="/"/>
</partitions>
</project>

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0
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CommandLine-Map
s
CommandLine-Ngdbuild
ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm system.bmm E:/my_projects/Wittenstein/release/svn/main/FreeRTOS/Demo/PCC440_Xilinx_Virtex5_GCC/implementation/system.ngc -uc system.ucf system.ngd
s
CommandLine-Par
s
CommandLine-Xst
s
Previous-NGD
s
Previous-NGM
s
Previous-Packed-NCD
s
Previous-Routed-NCD
s

0
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ISE_VERSION_LAST_SAVED_WITH
11.1
s

6
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ISE_VERSION_LAST_SAVED_WITH
11.1
s
XISE_FILE
system.xise
s

3
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ClientMessageOutputFile
_xmsgs/XSLTProcess.xmsgs
s

21
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ISE_VERSION_CREATED_WITH
11.1
s
ISE_VERSION_LAST_SAVED_WITH
11.1
s
LastRepoDir
E:\my_projects\Wittenstein\release\svn\main\FreeRTOS\Demo\PCC440_Xilinx_Virtex5_GCC\__xps\ise\
s
OBJSTORE_VERSION
1.3
s
PROJECT_CREATION_TIMESTAMP
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s
REGISTRY_VERSION
1.1
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REPOSITORY_VERSION
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s

3
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ClientMessageOutputFile
_xmsgs/bitgen.xmsgs
s

3
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ClientMessageOutputFile
_xmsgs/bitinit.xmsgs
s

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IncrementalMessagingEnabled
true
s
MessageCaptureEnabled
true
s
MessageFilterFile
filter.filter
s
MessageFilteringEnabled
true
s

3
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ClientMessageOutputFile
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s

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ClientMessageOutputFile
_xmsgs/dumpngdio.xmsgs
s

3
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ClientMessageOutputFile
_xmsgs/fuse.xmsgs
s

3
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ClientMessageOutputFile
_xmsgs/hprep6.xmsgs
s

3
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ClientMessageOutputFile
_xmsgs/idem.xmsgs
s

3
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ClientMessageOutputFile
_xmsgs/libgen.xmsgs
s

3
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ClientMessageOutputFile
_xmsgs/map.xmsgs
s

3
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ClientMessageOutputFile
_xmsgs/netgen.xmsgs
s

3
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys Normal file
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ClientMessageOutputFile
_xmsgs/ngc2edif.xmsgs
s

3
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys Normal file
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@ -0,0 +1,3 @@
ClientMessageOutputFile
_xmsgs/ngcbuild.xmsgs
s

3
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys Normal file
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@ -0,0 +1,3 @@
ClientMessageOutputFile
_xmsgs/ngdbuild.xmsgs
s

3
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/par/regkeys Normal file
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@ -0,0 +1,3 @@
ClientMessageOutputFile
_xmsgs/par.xmsgs
s

3
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/platgen/regkeys Normal file
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@ -0,0 +1,3 @@
ClientMessageOutputFile
_xmsgs/platgen.xmsgs
s

3
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/runner/regkeys Normal file
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@ -0,0 +1,3 @@
ClientMessageOutputFile
_xmsgs/runner.xmsgs
s

3
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/simgen/regkeys Normal file
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@ -0,0 +1,3 @@
ClientMessageOutputFile
_xmsgs/simgen.xmsgs
s

3
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/taengine/regkeys Normal file
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ClientMessageOutputFile
_xmsgs/taengine.xmsgs
s

3
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/trce/regkeys Normal file
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@ -0,0 +1,3 @@
ClientMessageOutputFile
_xmsgs/trce.xmsgs
s

3
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/tsim/regkeys Normal file
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@ -0,0 +1,3 @@
ClientMessageOutputFile
_xmsgs/tsim.xmsgs
s

3
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys Normal file
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@ -0,0 +1,3 @@
ClientMessageOutputFile
_xmsgs/vhpcomp.xmsgs
s

3
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys Normal file
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@ -0,0 +1,3 @@
ClientMessageOutputFile
_xmsgs/vlogcomp.xmsgs
s

3
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys Normal file
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@ -0,0 +1,3 @@
ClientMessageOutputFile
_xmsgs/xpwr.xmsgs
s

0
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xreport/regkeys Normal file
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3
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/xst/regkeys Normal file
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@ -0,0 +1,3 @@
ClientMessageOutputFile
_xmsgs/xst.xmsgs
s

10
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/version Normal file
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REPOSITORY_VERSION
1.1
REGISTRY_VERSION
1.1
OBJSTORE_VERSION
1.3
ISE_VERSION_CREATED_WITH
11.1
ISE_VERSION_LAST_SAVED_WITH
11.1

0
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/xmsgprops.lst Normal file
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1
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/libgen.opt Normal file
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-p virtex5 -msg __xps/ise/xmsgprops.lst

2
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/platgen.opt Normal file
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-p xc5vfx70tff1136-1 -lang vhdl -msg __xps/ise/xmsgprops.lst

20
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/rtosdemo_compiler.opt Normal file
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ppc440_0
RTOSDEMO_SOURCES = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c
RTOSDEMO_HEADERS =
RTOSDEMO_CC = powerpc-eabi-gcc
RTOSDEMO_CC_SIZE = powerpc-eabi-size
RTOSDEMO_CC_OPT = -O0
RTOSDEMO_CFLAGS = -D GCC_PPC440 -mregnames
RTOSDEMO_CC_SEARCH = # -B
RTOSDEMO_LIBPATH = -L./ppc440_0/lib/ # -L
RTOSDEMO_INCLUDES = -I./ppc440_0/include/ -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop
RTOSDEMO_LFLAGS = # -l
RTOSDEMO_LINKER_SCRIPT = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld
RTOSDEMO_CC_DEBUG_FLAG = -g
RTOSDEMO_CC_PROFILE_FLAG = # -pg
RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi
RTOSDEMO_CC_INFERRED_FLAGS= -mcpu=440
RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR=
RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE=
RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE=
$(RTOSDEMO_CC_INFERRED_FLAGS) \

1
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/simgen.opt Normal file
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-p virtex5 -lang vhdl $(PPC440_0_BOOTLOOP) -msg __xps/ise/xmsgprops.lst -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/

121
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/system.filters Normal file
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<FILTERS>
<SET CLASS="PROJECT" VIEW_ID="BUSINTERFACE">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="217" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="HEADER"/>
</HEADERS>
<SET CLASS="FILTER_GROUP" ID="By Connection" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Connection" VALUE="By Connection" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="Connected" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="Connected" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Unconnected" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="Unconnected" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
<SET CLASS="FILTER_GROUP" ID="By Bus Standard" IS_EXPANDED="TRUE">
<VARIABLE COLINDEX="0" NAME="By Bus Standard" VALUE="By Bus Standard" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="OPB" IS_VISIBLE="FALSE" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="OPB" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="LMB" IS_VISIBLE="FALSE" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="LMB" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="PLBV34" IS_VISIBLE="FALSE" ROW_INDEX="2">
<VARIABLE IS_LABELED="TRUE" NAME="PLBV34" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="PLBV46" ROW_INDEX="3">
<VARIABLE IS_LABELED="TRUE" NAME="PLBV46" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="OCM" IS_VISIBLE="FALSE" ROW_INDEX="4">
<VARIABLE IS_LABELED="TRUE" NAME="OCM" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="FSL" IS_VISIBLE="FALSE" ROW_INDEX="5">
<VARIABLE IS_LABELED="TRUE" NAME="FSL" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="DCR" ROW_INDEX="6">
<VARIABLE IS_LABELED="TRUE" NAME="DCR" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="FCB" ROW_INDEX="7">
<VARIABLE IS_LABELED="TRUE" NAME="FCB" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="XIL" ROW_INDEX="8">
<VARIABLE IS_LABELED="TRUE" NAME="Xilinx Point To Point" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="USER" IS_VISIBLE="FALSE" ROW_INDEX="9">
<VARIABLE IS_LABELED="TRUE" NAME="User Defined" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="XCL" IS_VISIBLE="FALSE" ROW_INDEX="10">
<VARIABLE IS_LABELED="TRUE" NAME="XCL" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
<SET CLASS="FILTER_GROUP" ID="By Interface Type" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Interface Type" VALUE="By Interface Type" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="Slaves" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="Slaves" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Masters" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="Masters" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Master Slaves" ROW_INDEX="2">
<VARIABLE IS_LABELED="TRUE" NAME="Master Slaves" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Monitors" ROW_INDEX="3">
<VARIABLE IS_LABELED="TRUE" NAME="Monitors" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Targets" ROW_INDEX="4">
<VARIABLE IS_LABELED="TRUE" NAME="Targets" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Initiators" ROW_INDEX="5">
<VARIABLE IS_LABELED="TRUE" NAME="Initiators" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
</SET>
<SET CLASS="PROJECT" VIEW_ID="PORT">
<HEADERS>
<VARIABLE COL_WIDTH="50" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
</HEADERS>
<SET CLASS="FILTER_GROUP" ID="By Connection" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Connection" VALUE="By Connection" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="Defaults" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="Defaults" VALUE="FALSE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Connected" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="Connected" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Unconnected" ROW_INDEX="2">
<VARIABLE IS_LABELED="TRUE" NAME="Unconnected" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
<SET CLASS="FILTER_GROUP" ID="By Class" IS_EXPANDED="TRUE">
<VARIABLE COL_INDEX="0" NAME="By Class" VALUE="By Class" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="Clocks" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="Clocks" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Resets" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="Resets" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Interrupts" ROW_INDEX="2">
<VARIABLE IS_LABELED="TRUE" NAME="Interrupts" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Others" ROW_INDEX="3">
<VARIABLE IS_LABELED="TRUE" NAME="Others" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
<SET CLASS="FILTER_GROUP" ID="By Direction" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Direction" VALUE="By Direction" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="Inputs" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="Inputs" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Outputs" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="Outputs" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="InOuts" ROW_INDEX="2">
<VARIABLE IS_LABELED="TRUE" NAME="InOuts" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
</SET>
</FILTERS>

101
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/system.gui Normal file
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<SETTINGS>
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="BUSINTERFACE">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="189" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" COL_WIDTH="227" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="127,724,323" VERSION="0"/>
<STATUS>
<SELECTIONS/>
</STATUS>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="BUSINTERFACE">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="PORT">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="231" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Frequency" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" COL_WIDTH="25" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,586,143" VERSION="0"/>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="PORT">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Port Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Frequency" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="11" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="ADDRESS">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Base Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Base Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="High Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Size" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface(s)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="ICache" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="DCache" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
</HEADERS>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="ADDRESS">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Base Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Base Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="High Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Size" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface(s)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="ICache" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="DCache" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
</HEADERS>
</SET>
</SETTINGS>

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-device xc5vfx70tff1136-1 data/system.ucf 0

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Net fpga_0_RS232_Uart_1_RX_pin LOC = AG15 | IOSTANDARD=LVCMOS33;
Net fpga_0_RS232_Uart_1_TX_pin LOC = AG20 | IOSTANDARD=LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> LOC = AE24 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> LOC = AD24 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> LOC = AD25 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> LOC = G16 | IOSTANDARD=LVCMOS25 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> LOC = AD26 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> LOC = G15 | IOSTANDARD=LVCMOS25 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> LOC = L18 | IOSTANDARD=LVCMOS25 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> LOC = H18 | IOSTANDARD=LVCMOS25 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=E8 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=AF23 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=AG12 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=AG23 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=AF13 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<0> LOC = AJ6 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<1> LOC = AJ7 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<2> LOC = V8 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<3> LOC = AK7 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<4> LOC = U8 | IOSTANDARD=LVCMOS33 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<0> LOC=U25 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<1> LOC=AG27 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<2> LOC=AF25 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<3> LOC=AF26 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<4> LOC=AE27 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<5> LOC=AE26 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<6> LOC=AC25 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<7> LOC=AC24 | IOSTANDARD=LVCMOS18 | PULLDOWN | SLEW=SLOW | DRIVE=2;
Net fpga_0_IIC_EEPROM_Sda_pin LOC=F8 | SLEW = SLOW | DRIVE = 6 | IOSTANDARD=LVCMOS33;
Net fpga_0_IIC_EEPROM_Scl_pin LOC=F9 | SLEW = SLOW | DRIVE = 6 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<30> LOC=K12 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<29> LOC=K13 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<28> LOC=H23 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<27> LOC=G23 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<26> LOC=H12 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<25> LOC=J12 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<24> LOC=K22 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<23> LOC=K23 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<22> LOC=K14 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<21> LOC=L14 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<20> LOC=H22 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<19> LOC=G22 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<18> LOC=J15 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<17> LOC=K16 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<16> LOC=K21 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<15> LOC=J22 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<14> LOC=L16 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<13> LOC=L15 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<12> LOC=L20 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<11> LOC=L21 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<10> LOC=AE23 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<9> LOC=AE22 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<8> LOC=AE12 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<7> LOC=AE13 | SLEW = FAST | DRIVE = 8 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_CEN_pin LOC=J10 | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_OEN_pin LOC=B12 | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_WEN_pin LOC=AF20 | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=J11 | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=K11 | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=D10 | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=D11 | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=H8 | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=AG22 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=AH22 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=AH12 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=AG13 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=AH20 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=AH19 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=AH14 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=AH13 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=AF15 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=AE16 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=AE21 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=AD20 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=AF16 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=AE17 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=AE19 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=AD19 | PULLDOWN | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=J9 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=K8 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=K9 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=B13 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=C13 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=G11 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=G12 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=M8 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=L8 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=F11 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=E11 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=M10 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=L9 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=E12 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=E13 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=N10 | PULLDOWN | IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_ZBT_CLK_OUT_pin LOC=G8 | SLEW = FAST | DRIVE = 12 | IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_ZBT_CLK_FB_pin LOC=AG21 | IOSTANDARD=LVCMOS33;
Net fpga_0_PCIe_Bridge_RXN_pin LOC=AF1 | IOSTANDARD = LVDS_25;
Net fpga_0_PCIe_Bridge_RXP_pin LOC=AE1 | IOSTANDARD = LVDS_25;
Net fpga_0_PCIe_Bridge_TXN_pin LOC=AE2 | IOSTANDARD = LVDS_25;
Net fpga_0_PCIe_Bridge_TXP_pin LOC=AD2 | IOSTANDARD = LVDS_25;
Net "pcie_bridge/*SPLB_Clk" TNM_NET = "SPLB_Clk";
Net "pcie_bridge/*Bridge_Clk" TNM_NET = "Bridge_Clk";
## Timing constraints between clock-domain boundaries
#
TIMESPEC "TS_PLB_PCIe" = FROM "SPLB_Clk" TO "Bridge_Clk" 8 ns datapathonly;
TIMESPEC "TS_PCIe_PLB" = FROM "Bridge_Clk" TO "SPLB_Clk" 8 ns datapathonly;
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=K17 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=H17 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=E34 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=E32 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=A33 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=B33 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=C33 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=C32 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=B32 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=E33 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC=J14 | IOSTANDARD = LVCMOS25 | TIG;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=AJ10 | IOSTANDARD = LVDCI_33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=AH10 | IOSTANDARD = LVDCI_33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=AH9 | IOSTANDARD = LVDCI_33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=AE11 | IOSTANDARD = LVDCI_33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=AF11 | IOSTANDARD = LVDCI_33;
Net fpga_0_Ethernet_MAC_MDINT_pin LOC=H20 | IOSTANDARD = LVCMOS25 | TIG;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<0> LOC=AF30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<1> LOC=AK31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<2> LOC=AF31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<3> LOC=AD30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<4> LOC=AJ30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<5> LOC=AF29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<6> LOC=AD29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<7> LOC=AE29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<8> LOC=AH27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<9> LOC=AF28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<10> LOC=AH28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<11> LOC=AA28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<12> LOC=AG25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<13> LOC=AJ26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<14> LOC=AG28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<15> LOC=AB28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<16> LOC=AC28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<17> LOC=AB25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<18> LOC=AC27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<19> LOC=AA26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<20> LOC=AB26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<21> LOC=AA24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<22> LOC=AB27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<23> LOC=AA25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<24> LOC=AC29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<25> LOC=AB30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<26> LOC=W31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<27> LOC=V30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<28> LOC=AC30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<29> LOC=W29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<30> LOC=V27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<31> LOC=W27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<32> LOC=V29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<33> LOC=Y27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<34> LOC=Y26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<35> LOC=W24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<36> LOC=V28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<37> LOC=W25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<38> LOC=W26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<39> LOC=V24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<40> LOC=R24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<41> LOC=P25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<42> LOC=N24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<43> LOC=P26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<44> LOC=T24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<45> LOC=N25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<46> LOC=P27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<47> LOC=N28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<48> LOC=M28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<49> LOC=L28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<50> LOC=F25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<51> LOC=H25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<52> LOC=K27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<53> LOC=K28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<54> LOC=H24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<55> LOC=G26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<56> LOC=G25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<57> LOC=M26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<58> LOC=J24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<59> LOC=L26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<60> LOC=J27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<61> LOC=M25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<62> LOC=L25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<63> LOC=L24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<0> LOC=AA29 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<1> LOC=AK28 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<2> LOC=AK26 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<3> LOC=AB31 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<4> LOC=Y28 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<5> LOC=E26 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<6> LOC=H28 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<7> LOC=G27 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<0> LOC=AA30 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<1> LOC=AK27 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<2> LOC=AJ27 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<3> LOC=AA31 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<4> LOC=Y29 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<5> LOC=E27 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<6> LOC=G28 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<7> LOC=H27 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<0> LOC=L30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<1> LOC=M30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<2> LOC=N29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<3> LOC=P29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<4> LOC=K31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<5> LOC=L31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<6> LOC=P31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<7> LOC=P30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<8> LOC=M31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<9> LOC=R28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<10> LOC=J31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<11> LOC=R29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<12> LOC=T31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_BA_pin<0> LOC=G31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_BA_pin<1> LOC=J30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin LOC=H30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin LOC=E31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_WE_N_pin LOC=K29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CS_N_pin LOC=L29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin<0> LOC=F31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin<1> LOC=F30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CKE_pin LOC=T28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<0> LOC=AJ31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<1> LOC=AE28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<2> LOC=Y24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<3> LOC=Y31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<4> LOC=V25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<5> LOC=P24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<6> LOC=F26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<7> LOC=J25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CK_pin<0> LOC=AK29 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CK_pin<1> LOC=E28 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CK_N_pin<0> LOC=AJ29 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CK_N_pin<1> LOC=F28 | IOSTANDARD = DIFF_SSTL18_II;
############################################################################
#
# PPC440MC_DDR2 BRAM Location Constraints
#
############################################################################
##------------------------------------------------------------------------------
## MIG 2.0 Constraints
##------------------------------------------------------------------------------
###########################################################################
## Define multicycle paths - these paths may take longer because additional
## time allowed for logic to settle in calibration/initialization FSM
###########################################################################
NET "DDR2_SDRAM*/mc_mibclk" TNM = FFS "TNM_CLK0";
NET "DDR2_SDRAM*/mi_mcclk90" TNM = FFS "TNM_CLK90";
NET "DDR2_SDRAM*/mc_mibclk" TNM_NET = "mc_clk";
TIMESPEC "TS_MC_CLK" = PERIOD "mc_clk" 5.000 ns;
## MUX Select for either rising/falling CLK0 for 2nd stage read capture
INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO "TNM_CLK0"
"TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i" * 4;
## Calibration/Initialization complete status flag (for PHY logic only)
INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO
"TNM_CLK0"
"TS_MC_CLK" * 4;
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO
"TNM_CLK90" "TS_MC_CLK" * 4;
## Select (address) bits for SRL32 shift registers used in stage3/stage4
## calibration
INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO "TNM_CLK0"
"TS_MC_CLK" * 4;
INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO "TNM_CLK0"
"TS_MC_CLK" * 4;
INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly"
TNM = "TNM_CAL_RDEN_DLY";
TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO "TNM_CLK0"
"TS_MC_CLK" * 4;
## MUX select for read data - optional delay on data to account for byte skews
INST "*/usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO "TNM_CLK0"
"TS_MC_CLK" * 4;
###########################################################################
## LOC placment of DQS-squelch related IDDR and IDELAY elements
## Each circuit can be located at any of the following locations:
## 1. Ununsed "N"-side of DQS diff pair I/O
## 2. DM data mask (output only, input side is free for use)
## 3. Any output-only site
###########################################################################
INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y96";
INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y96";
INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y58";
INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y58";
INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y62";
INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y62";
INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y100";
INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y100";
INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y102";
INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y102";
INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y256";
INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y256";
INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y260";
INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y260";
INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y262";
INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y262";
###########################################################################
## DQS Squelch-related timing constraints
###########################################################################
###########################################################################
## Half-cycle path constraint from IDDR to CE pin for all DQ IDDRs
## for DQS Read Postamble Glitch Squelch circuit
###########################################################################
## Max delay from output of IDDR to CE input of DQ IDDRs = tRPST + some slack
## where slack account for rise-time of DQS on board. For now assume slack =
## 0.400ns (based on initial SPICE simulations, assumes use of ODT), so
## time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz
INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 1.9 ns;
###########################################################################
## LOC and timing constraints for flop driving DQS CE enable signal
## from fabric logic. Even though the absolute delay on this path is
## calibrated out (when synchronizing this output to DQS), the delay
## should still be kept as low as possible to reduce post-calibration
## voltage/temp variations - these are roughly proportional to the
## absolute delay of the path
###########################################################################
INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff" LOC = SLICE_X0Y48;
INST "*/u_phy_calib/gen_gate[1].u_en_dqs_ff" LOC = SLICE_X0Y29;
INST "*/u_phy_calib/gen_gate[2].u_en_dqs_ff" LOC = SLICE_X0Y31;
INST "*/u_phy_calib/gen_gate[3].u_en_dqs_ff" LOC = SLICE_X0Y50;
INST "*/u_phy_calib/gen_gate[4].u_en_dqs_ff" LOC = SLICE_X0Y51;
INST "*/u_phy_calib/gen_gate[5].u_en_dqs_ff" LOC = SLICE_X0Y128;
INST "*/u_phy_calib/gen_gate[6].u_en_dqs_ff" LOC = SLICE_X0Y130;
INST "*/u_phy_calib/gen_gate[7].u_en_dqs_ff" LOC = SLICE_X0Y131;
###########################################################################
## Control for DQS gate - from fabric flop. Prevent runaway delay -
## two parts to this path: (1) from fabric flop to IDELAY, (2) from
## IDELAY to asynchronous reset of IDDR that drives the DQ CEs
## A single number is used for all speed grades - value based on 333MHz.
## This can be relaxed for lower frequencies.
###########################################################################
NET "*/u_phy_io/en_dqs*" MAXDELAY = 600 ps;
NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps;
###########################################################################
INST "*/gen_dq[0].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42;
INST "*/gen_dq[1].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y43;
INST "*/gen_dq[2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y45;
INST "*/gen_dq[3].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46;
INST "*/gen_dq[4].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y41;
INST "*/gen_dq[5].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42;
INST "*/gen_dq[6].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44;
INST "*/gen_dq[7].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44;
INST "*/gen_dq[8].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28;
INST "*/gen_dq[9].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y32;
INST "*/gen_dq[10].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33;
INST "*/gen_dq[11].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34;
INST "*/gen_dq[12].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y26;
INST "*/gen_dq[13].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28;
INST "*/gen_dq[14].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33;
INST "*/gen_dq[15].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34;
INST "*/gen_dq[16].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y35;
INST "*/gen_dq[17].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36;
INST "*/gen_dq[18].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38;
INST "*/gen_dq[19].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39;
INST "*/gen_dq[20].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36;
INST "*/gen_dq[21].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y37;
INST "*/gen_dq[22].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38;
INST "*/gen_dq[23].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39;
INST "*/gen_dq[24].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46;
INST "*/gen_dq[25].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49;
INST "*/gen_dq[26].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y53;
INST "*/gen_dq[27].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y55;
INST "*/gen_dq[28].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49;
INST "*/gen_dq[29].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52;
INST "*/gen_dq[30].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54;
INST "*/gen_dq[31].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56;
INST "*/gen_dq[32].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52;
INST "*/gen_dq[33].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56;
INST "*/gen_dq[34].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58;
INST "*/gen_dq[35].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59;
INST "*/gen_dq[36].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54;
INST "*/gen_dq[37].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y57;
INST "*/gen_dq[38].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58;
INST "*/gen_dq[39].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59;
INST "*/gen_dq[40].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120;
INST "*/gen_dq[41].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121;
INST "*/gen_dq[42].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y122;
INST "*/gen_dq[43].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123;
INST "*/gen_dq[44].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120;
INST "*/gen_dq[45].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121;
INST "*/gen_dq[46].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123;
INST "*/gen_dq[47].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124;
INST "*/gen_dq[48].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124;
INST "*/gen_dq[49].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126;
INST "*/gen_dq[50].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y132;
INST "*/gen_dq[51].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133;
INST "*/gen_dq[52].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y125;
INST "*/gen_dq[53].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126;
INST "*/gen_dq[54].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133;
INST "*/gen_dq[55].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134;
INST "*/gen_dq[56].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134;
INST "*/gen_dq[57].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136;
INST "*/gen_dq[58].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y137;
INST "*/gen_dq[59].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138;
INST "*/gen_dq[60].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y135;
INST "*/gen_dq[61].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136;
INST "*/gen_dq[62].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138;
INST "*/gen_dq[63].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y139;
INST "DDR2_SDRAM/*/*u_rdf" LOC = RAMB36_X0Y19;
INST "DDR2_SDRAM/*/*u_rdf1" LOC = RAMB36_X0Y18;
INST "DDR2_SDRAM/*/*gen_wdf[0]*u_wdf" LOC = RAMB36_X0Y17;
INST "DDR2_SDRAM/*/*gen_wdf[1]*u_wdf" LOC = RAMB36_X0Y16;
###############################################################################
# Prevent unrelated logic from being packed into any slices used
# by read data capture RPM's - if unrelated logic gets packed into
# these slices, it could cause the DIRT strings that define the
# IDDR -> fabric flop routing to become unroutable during PAR stage
# (unrelated logic may require routing resources required by the
# DIRT strings - MAP does not currently take into account DIRT
# strings when placing logic
###############################################################################
AREA_GROUP "DDR_CAPTURE_FFS" GROUP = CLOSED;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=G5 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=N7 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=N5 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=P5 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=R6 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=M6 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=L6 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AH17 | IOSTANDARD = LVCMOS33 | PERIOD = 30000 ps;
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=M7 | IOSTANDARD = LVCMOS33 | TIG;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=M5 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=N8 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=R9 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=P9 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=T8 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=J7 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=H7 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=R7 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=U7 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=P7 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=P6 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=R8 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=L5 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=L4 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=K6 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=J5 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=T6 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=K7 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=J6 | IOSTANDARD = LVCMOS33;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
Net fpga_0_clk_1_sys_clk_pin LOC = AH15 | IOSTANDARD=LVCMOS33;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC = E9 | IOSTANDARD=LVCMOS33 | PULLUP;
Net fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin LOC=AF4 | IOSTANDARD = LVDS_25;
Net fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin LOC=AF3 | IOSTANDARD = LVDS_25;

14
Demo/PPC440_Xilinx_Virtex5_GCC/etc/bitgen.ut Normal file
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@ -0,0 +1,14 @@
-g TdoPin:PULLNONE
-g DriveDone:No
-g StartUpClk:JTAGCLK
-g DONE_cycle:4
-g GTS_cycle:5
-g TckPin:PULLUP
-g TdiPin:PULLUP
-g TmsPin:PULLUP
-g DonePipe:No
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:NONE
-g Persist:No

6
Demo/PPC440_Xilinx_Virtex5_GCC/etc/download.cmd Normal file
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@ -0,0 +1,6 @@
setMode -bscan
setCable -p auto
identify
assignfile -p 5 -file implementation/download.bit
program -p 5
quit

83
Demo/PPC440_Xilinx_Virtex5_GCC/etc/fast_runtime.opt Normal file
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@ -0,0 +1,83 @@
FLOWTYPE = FPGA;
###############################################################
## Filename: fast_runtime.opt
##
## Option File For Xilinx FPGA Implementation Flow for Fast
## Runtime.
##
## Version: 4.1.1
###############################################################
#
# Options for Translator
#
# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
#
Program ngdbuild
-p <partname>; # Partname to use - picked from xflow commandline
-nt timestamp; # NGO File generation. Regenerate only when
# source netlist is newer than existing
# NGO file (default)
-bm <design>.bmm # Block RAM memory map file
<userdesign>; # User design - pick from xflow command line
-uc <design>.ucf; # ucf constraints
<design>.ngd; # Name of NGD file. Filebase same as design filebase
End Program ngdbuild
#
# Options for Mapper
#
# Type "map -h <arch>" for a detailed list of map command line options
#
Program map
-o <design>_map.ncd; # Output Mapped ncd file
-w; # Overwrite output files.
-pr b; # Pack internal FF/latches into IOBs
#-fp <design>.mfp; # Floorplan file
-ol high;
-timing;
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
#
# Options for Post Map Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_map_trce
-e 3; # Produce error report limited to 3 items per constraint
#-o <design>_map.twr; # Output trace report file
-xml <design>_map.twx; # Output XML version of the timing report
#-tsi <design>_map.tsi; # Produce Timing Specification Interaction report
<inputdir><design>_map.ncd; # Input mapped ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_map_trce
#
# Options for Place and Route
#
# Type "par -h" for a detailed list of par command line options
#
Program par
-w; # Overwrite existing placed and routed ncd
-ol high; # Overall effort level
<inputdir><design>_map.ncd; # Input mapped NCD file
<design>.ncd; # Output placed and routed NCD
<inputdir><design>.pcf; # Input physical constraints file
END Program par
#
# Options for Post Par Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_par_trce
-e 3; # Produce error report limited to 3 items per constraint
#-o <design>.twr; # Output trace report file
-xml <design>.twx; # Output XML version of the timing report
#-tsi <design>.tsi; # Produce Timing Specification Interaction report
<inputdir><design>.ncd; # Input placed and routed ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_par_trce

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