Initial RZ/T port and demo - work in progress, currently only the tick interrupt can be installed.
This commit is contained in:
Richard Barry
parent
717654471e
commit
28d8a27f8f
146
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.HardwareDebuglinker
Normal file
146
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.HardwareDebuglinker
Normal file
@ -0,0 +1,146 @@
|
||||
<?xml version="1.0" encoding="ASCII"?>
|
||||
<com.renesas.linkersection.model:SectionContainer xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:com.renesas.linkersection.model="http:///LinkerSection.ecore">
|
||||
<sections name=".flash_contents" isKeep="true">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="805306444"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_mloader_text"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs=". = . + (_loader_text_end - _loader_text_start)"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_mtext"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs=". = . + (_text_end - _text_start)"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_mdata"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs=". = . + (_data_end - _data_start)"/>
|
||||
</sections>
|
||||
<sections name=".fvectors" isKeep="true">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_text_start"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".fvectors"/>
|
||||
<reservedMemAddress xsi:type="com.renesas.linkersection.model:ReferencedLabelAddress" label="//@sections.0/@contents.2"/>
|
||||
</sections>
|
||||
<sections name=".text">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.1"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".text"/>
|
||||
</sections>
|
||||
<sections name=".rvectors" isKeep="true">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.2"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_rvectors_start"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".rvectors"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_rvectors_end"/>
|
||||
</sections>
|
||||
<sections name=".init">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.3"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".init"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Keyword" text="PROVIDE_HIDDEN (__exidx_start = .)"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Keyword" text="PROVIDE_HIDDEN (__exidx_end = .)"/>
|
||||
</sections>
|
||||
<sections name=".fini">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.4"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".fini"/>
|
||||
</sections>
|
||||
<sections name=".got">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.5"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".got"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".got.plt"/>
|
||||
</sections>
|
||||
<sections name=".rodata">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.6"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".rodata"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".rodata.*"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_erodata"/>
|
||||
</sections>
|
||||
<sections name=".eh_frame_hdr">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.7"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".eh_frame_hdr"/>
|
||||
</sections>
|
||||
<sections name=".eh_frame">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.8"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".eh_frame"/>
|
||||
</sections>
|
||||
<sections name=".jcr">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.9"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".jcr"/>
|
||||
</sections>
|
||||
<sections name=".tors">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.10"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__CTOR_LIST__"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Keyword" text=". = ALIGN(2)"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__ctors"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".ctors"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__ctors_end"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__CTOR_END__"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__DTOR_LIST__"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="___dtors"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".dtors"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="___dtors_end"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__DTOR_END__"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Keyword" text=". = ALIGN(2)"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_text_end"/>
|
||||
</sections>
|
||||
<sections name=".loader_param" isKeep="true">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="8388608"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".loader_param"/>
|
||||
<reservedMemAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="805306368"/>
|
||||
</sections>
|
||||
<sections name=".loader_text">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="8396800"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_loader_text_start"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".loader_text"/>
|
||||
<reservedMemAddress xsi:type="com.renesas.linkersection.model:ReferencedLabelAddress" label="//@sections.0/@contents.0"/>
|
||||
</sections>
|
||||
<sections name=".loader_text2">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.13"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".loader_text2"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs=". = . + (512 - ((. - _loader_text_start) % 512))"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_loader_text_end"/>
|
||||
</sections>
|
||||
<sections name=".data">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="520192"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_data_start"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".data"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_data_end"/>
|
||||
<reservedMemAddress xsi:type="com.renesas.linkersection.model:ReferencedLabelAddress" label="//@sections.0/@contents.4"/>
|
||||
</sections>
|
||||
<sections name=".bss">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.15"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Keyword" text="PROVIDE(__bss_start__ = .)"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_bss"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".bss"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".bss.**"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name="COMMON"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Keyword" text="PROVIDE(__bss_end__ = .)"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_ebss"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_end"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Keyword" text="PROVIDE(end = .)"/>
|
||||
</sections>
|
||||
<sections name=".heap" isNoLoad="true">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="8417280"/>
|
||||
</sections>
|
||||
<sections name=".sys_stack" isNoLoad="true">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="8419840"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".sys_stack"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_sys_stack"/>
|
||||
</sections>
|
||||
<sections name=".svc_stack" isNoLoad="true">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="8420352"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".svc_stack"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_svc_stack"/>
|
||||
</sections>
|
||||
<sections name=".irq_stack" isNoLoad="true">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="8420608"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".irq_stack"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_irq_stack"/>
|
||||
</sections>
|
||||
<sections name=".fiq_stack" isNoLoad="true">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="8420864"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".fiq_stack"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_fiq_stack"/>
|
||||
</sections>
|
||||
<sections name=".und_stack" isNoLoad="true">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="8421120"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".und_stack"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_und_stack"/>
|
||||
</sections>
|
||||
<sections name=".abt_stack" isNoLoad="true">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="8421376"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".und_stack"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_abt_stack"/>
|
||||
</sections>
|
||||
</com.renesas.linkersection.model:SectionContainer>
|
||||
89
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.Releaselinker
Normal file
89
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.Releaselinker
Normal file
@ -0,0 +1,89 @@
|
||||
<?xml version="1.0" encoding="ASCII"?>
|
||||
<com.renesas.linkersection.model:SectionContainer xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:com.renesas.linkersection.model="http:///LinkerSection.ecore">
|
||||
<sections name=".fvectors" isKeep="true">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="537001984"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".fvectors"/>
|
||||
</sections>
|
||||
<sections name=".text">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="537002240"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".text"/>
|
||||
</sections>
|
||||
<sections name=".rvectors">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.1"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_rvectors_start"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".rvectors"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_rvectors_end"/>
|
||||
</sections>
|
||||
<sections name=".init">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.2"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".init"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Keyword" text="PROVIDE_HIDDEN (__exidx_start = .)"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Keyword" text="PROVIDE_HIDDEN (__exidx_end = .)"/>
|
||||
</sections>
|
||||
<sections name=".fini">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.3"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".fini"/>
|
||||
</sections>
|
||||
<sections name=".got">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.4"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".got"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".got.plt"/>
|
||||
</sections>
|
||||
<sections name=".rodata">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.5"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".rodata"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".rodata.*"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_erodata"/>
|
||||
</sections>
|
||||
<sections name=".eh_frame_hdr">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.6"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".eh_frame_hdr"/>
|
||||
</sections>
|
||||
<sections name=".eh_frame">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.7"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".eh_frame"/>
|
||||
</sections>
|
||||
<sections name=".jcr">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.8"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".jcr"/>
|
||||
</sections>
|
||||
<sections name=".tors">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.9"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__CTOR_LIST__"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Keyword" text=". = ALIGN(2)"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__ctors"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".ctors"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__ctors_end"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__CTOR_END__"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__DTOR_LIST__"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="___dtors"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".dtors"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="___dtors_end"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="__DTOR_END__"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Keyword" text=". = ALIGN(2)"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_mdata"/>
|
||||
</sections>
|
||||
<sections name=".data">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="537264384"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_data"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".data"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_edata"/>
|
||||
<reservedMemAddress xsi:type="com.renesas.linkersection.model:ReferencedLabelAddress" label="//@sections.10/@contents.12"/>
|
||||
</sections>
|
||||
<sections name=".bss">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:ReferencedSectionAddress" referencedSection="//@sections.11"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Keyword" text="PROVIDE(__bss_start__ = .)"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_bss"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".bss"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name=".bss.**"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:WildCardExpression" specificSection="true" name="COMMON"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Keyword" text="PROVIDE(__bss_end__ = .)"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_ebss"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_end"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Keyword" text="PROVIDE(end = .)"/>
|
||||
</sections>
|
||||
<sections name=".stack" isNoLoad="true">
|
||||
<sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="537268480"/>
|
||||
<contents xsi:type="com.renesas.linkersection.model:Label" rhs="= .;" lhs="_stack"/>
|
||||
</sections>
|
||||
</com.renesas.linkersection.model:SectionContainer>
|
||||
166
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.cproject
Normal file
166
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.cproject
Normal file
@ -0,0 +1,166 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
<cconfiguration id="com.renesas.cdt.rz.hardwaredebug.win32.configuration.Id.137003302">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.renesas.cdt.rz.hardwaredebug.win32.configuration.Id.137003302" moduleId="org.eclipse.cdt.core.settings" name="HardwareDebug">
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="org.eclipse.cdt.core.PE" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactName="RTOSDemo" buildArtefactType="com.renesas.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.renesas.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf *.lst *.lis *.lpp *.map" description="" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser" id="com.renesas.cdt.rz.hardwaredebug.win32.configuration.Id.137003302" name="HardwareDebug" parent="com.renesas.cdt.rz.hardwaredebug.win32.configuration.Id" postbuildStep="arm-none-eabi-objcopy -O binary ${ProjName}.x ${ProjName}.bin&">
|
||||
<folderInfo id="com.renesas.cdt.rz.hardwaredebug.win32.configuration.Id.137003302." name="/" resourcePath="">
|
||||
<toolChain id="com.renesas.cdt.rz.hardwaredebug.win32.toolchain.Id.1095218391" name="KPIT GNUARM-NONE-EABI Toolchain" superClass="com.renesas.cdt.rz.hardwaredebug.win32.toolchain.Id">
|
||||
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.PE" id="com.renesas.cdt.rz.hardwaredebug.win32.targetplatform.Id.1812905899" name="Target Platform" osList="all" superClass="com.renesas.cdt.rz.hardwaredebug.win32.targetplatform.Id"/>
|
||||
<builder buildPath="${workspace_loc:/Tutorial}/HardwareDebug" id="com.renesas.cdt.rz.hardwaredebug.win32.builder.Id.325418915" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Builder" superClass="com.renesas.cdt.rz.hardwaredebug.win32.builder.Id"/>
|
||||
<tool command="" id="com.renesas.cdt.rz.hardwaredebug.win32.tool.libgen.Id.1484301438" name="Library Generator" superClass="com.renesas.cdt.rz.hardwaredebug.win32.tool.libgen.Id">
|
||||
<option id="com.renesas.cdt.core.LibraryGenerator.option.stdio.521338791" name="stdio.h : Performs input/output handling" superClass="com.renesas.cdt.core.LibraryGenerator.option.stdio" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.LibraryGenerator.option.stdlib.1342580965" name="stdlib.h : Performs C program standard processing such as storage area management" superClass="com.renesas.cdt.core.LibraryGenerator.option.stdlib" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.LibraryGenerator.option.string.124919993" name="string.h : Performs string comparison, copying " superClass="com.renesas.cdt.core.LibraryGenerator.option.string" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.LibraryGenerator.option.selectLibrary.605211704" name="Select library" superClass="com.renesas.cdt.core.LibraryGenerator.option.selectLibrary" value="com.renesas.core.LibraryGenerator.option.selectLibrary.newLib" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.core.LibraryGenerator.option.libraryType.1944449788" name="Library type" superClass="com.renesas.cdt.core.LibraryGenerator.option.libraryType" value="com.renesas.cdt.core.LibraryGenerator.option.libraryType.preBuilt" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.core.LibraryGenerator.option.misc9.647629590" name="Place each function into its own section in the output file(-ffunction-sections)" superClass="com.renesas.cdt.core.LibraryGenerator.option.misc9" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.LibraryGenerator.option.misc14.1902249451" name="Do not put function addresses in registers(-fno-function-cse)" superClass="com.renesas.cdt.core.LibraryGenerator.option.misc14" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.LibraryGenerator.option.misc36.1398214108" name="Parse the whole compilation unit before starting to produce code ( -funit-at-a-time)" superClass="com.renesas.cdt.core.LibraryGenerator.option.misc36" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.LibraryGenerator.option.misc10.983076495" name="Place each data into its own section in the output file(-fdata-sections)" superClass="com.renesas.cdt.core.LibraryGenerator.option.misc10" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.LibraryGenerator.option.misc37.271380479" name="Align branch targets to a power-of-two boundary (-falign-jumps)" superClass="com.renesas.cdt.core.LibraryGenerator.option.misc37" value="true" valueType="boolean"/>
|
||||
</tool>
|
||||
<tool id="com.renesas.cdt.rz.hardwaredebug.win32.tool.compiler.Id.542544613" name="Compiler" superClass="com.renesas.cdt.rz.hardwaredebug.win32.tool.compiler.Id">
|
||||
<option defaultValue="true" id="com.renesas.cdt.core.Compiler.option.misc2.721392830" name="Don't search standard system directories for header files(-nostdinc)" superClass="com.renesas.cdt.core.Compiler.option.misc2" value="false" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Compiler.option.architecture.638675850" name="Architecture" superClass="com.renesas.cdt.rz.HardwareDebug.Compiler.option.architecture" value="com.renesas.cdt.rz.HardwareDebug.Compiler.option.architecture.armv7r" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Compiler.option.cpuType.585789719" name="CPU type" superClass="com.renesas.cdt.rz.HardwareDebug.Compiler.option.cpuType" value="com.renesas.cdt.rz.HardwareDebug.Compiler.option.cpuType.cortexr4f" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Compiler.option.dataEndian.972047238" name="Endian" superClass="com.renesas.cdt.rz.HardwareDebug.Compiler.option.dataEndian" value="com.renesas.cdt.rz.HardwareDebug.Compiler.option.dataEndian.little" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Compiler.option.instructionset.1821119680" name="Instruction Set" superClass="com.renesas.cdt.rz.HardwareDebug.Compiler.option.instructionset" value="com.renesas.cdt.rz.HardwareDebug.Compiler.option.instructionset.arm" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Compiler.option.interworking.1256187562" name="Interworking (-mthumb-interwork)" superClass="com.renesas.cdt.rz.HardwareDebug.Compiler.option.interworking" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Compiler.option.targetfpu.789930608" name="Target FPU (-mfpu)" superClass="com.renesas.cdt.rz.HardwareDebug.Compiler.option.targetfpu" value="com.renesas.cdt.rz.HardwareDebug.Compiler.option.targetfpu.vfp" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Compiler.option.floatingpointabi.81534707" name="Floating-point ABI (-mfloat-abi=name)" superClass="com.renesas.cdt.rz.HardwareDebug.Compiler.option.floatingpointabi" value="com.renesas.cdt.rz.HardwareDebug.Compiler.option.floatingpointabi.hard" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.device.615172162" name="Device" superClass="com.renesas.cdt.core.Compiler.option.device" value="R7S910018" valueType="string"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.deviceShortName.897790463" name="DeviceShortName" superClass="com.renesas.cdt.core.Compiler.option.deviceShortName" value="R7S910018" valueType="string"/>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.renesas.cdt.core.Compiler.option.includeFileDir.1914876765" name="Include file directories" superClass="com.renesas.cdt.core.Compiler.option.includeFileDir" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""${TCINSTALL}/bin/newlib/libc/sys/arm""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/Full_Demo}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/Full_Demo/Standard_Demo_Tasks/include}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/FreeRTOS_Source/include}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/FreeRTOS_Source/portable/GCC/ARM_CRx_No_GIC}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/cg_src}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/System/GCC/inc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src}""/>
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.renesas.cdt.rz.HardwareDebug.Compiler.option.userDefinedOptions.1781067444" name="User defined options" superClass="com.renesas.cdt.rz.HardwareDebug.Compiler.option.userDefinedOptions" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value=""/>
|
||||
<listOptionValue builtIn="false" value=""/>
|
||||
<listOptionValue builtIn="false" value=""/>
|
||||
</option>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.stdWarnings.1242616069" name="Standard Warnings" superClass="com.renesas.cdt.core.Compiler.option.stdWarnings" value="com.renesas.cdt.core.Compiler.option.stdWarnings.enableAll" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning1.1895271986" name="Issue Warning if an array subscript has type char(-Wchar-subscripts)" superClass="com.renesas.cdt.core.Compiler.option.warning1" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning2.794198457" name="Issue Warning if comment appears within comment(-Wcomment)" superClass="com.renesas.cdt.core.Compiler.option.warning2" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning3.1744608424" name="Issue Warning if string functions format is incorrect(-Wformat)" superClass="com.renesas.cdt.core.Compiler.option.warning3" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning4.1770361117" name="Issue Warning if a function or parameter is implicitly declared(-Wimplicit)" superClass="com.renesas.cdt.core.Compiler.option.warning4" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning5.848851103" name="Disable Warning about the use of #import(-Wno-import)" superClass="com.renesas.cdt.core.Compiler.option.warning5" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning6.950494022" name="Issue Warning if parentheses are omitted in certain contexts(-Wparentheses)" superClass="com.renesas.cdt.core.Compiler.option.warning6" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning7.426570819" name="Issue Warning of possible return type problems(-Wreturn-type)" superClass="com.renesas.cdt.core.Compiler.option.warning7" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning8.1352482889" name="Issue Warning of possible switch statement problems(-Wswitch)" superClass="com.renesas.cdt.core.Compiler.option.warning8" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning9.2116526382" name="Issue Warning if any trigraphs are encountered(-Wtrigraphs)" superClass="com.renesas.cdt.core.Compiler.option.warning9" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning10.1479535529" name="Issue Warning if a variable is unused aside from its declaration(-Wunused)" superClass="com.renesas.cdt.core.Compiler.option.warning10" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning11.1008512093" name="Issue Warning if an uninitialised automatic variable is used(-Wuninitialized)" superClass="com.renesas.cdt.core.Compiler.option.warning11" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning12.1590968671" name="Issue Warning of member initialisation mismatch(-Wreorder)" superClass="com.renesas.cdt.core.Compiler.option.warning12" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning13.1182362547" name="Issue Warning of bad sign comparisions(-Wsign-compare)" superClass="com.renesas.cdt.core.Compiler.option.warning13" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.advWarnings.1053226328" name="Advanced Warnings" superClass="com.renesas.cdt.core.Compiler.option.advWarnings" value="com.renesas.cdt.core.Compiler.option.advWarnings.selectOptions" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning14.2137532876" name="Print extra warning messages(-Wextra)" superClass="com.renesas.cdt.core.Compiler.option.warning14" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning15.28783595" name="Issue Warning if function returns structure or unions(-Waggregate-return)" superClass="com.renesas.cdt.core.Compiler.option.warning15" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning16.781374568" name="Issue Warning if a function call is cast to a nonmatching type(-Wbad-function-cast)" superClass="com.renesas.cdt.core.Compiler.option.warning16" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning17.1726527237" name="Issue Warning of bad alignment pointer casting(-Wcast-align)" superClass="com.renesas.cdt.core.Compiler.option.warning17" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning18.169372107" name="Issue Warning of bad type qualifier pointer casting(-Wcast-qual)" superClass="com.renesas.cdt.core.Compiler.option.warning18" value="false" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning19.2110378361" name="Issue Warning for certain prototype conversions(-Wconversion)" superClass="com.renesas.cdt.core.Compiler.option.warning19" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning20.1001242190" name="Convert all warnings to errors (-Werror) " superClass="com.renesas.cdt.core.Compiler.option.warning20" value="false" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning21.355535354" name="Issue Warning if a function cannot be inline(-Winline)" superClass="com.renesas.cdt.core.Compiler.option.warning21" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning22.927679492" name="Issue Warning if a global function is defined not declared(-Wmissing-declarations)" superClass="com.renesas.cdt.core.Compiler.option.warning22" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning23.226850487" name="Issue Warning if a global function has no prototype declaration(-Wmissing-prototypes)" superClass="com.renesas.cdt.core.Compiler.option.warning23" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning24.1346714519" name="Issue Warning if an extern function is inside a function(-Wnested-externs)" superClass="com.renesas.cdt.core.Compiler.option.warning24" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning25.191482997" name="Issue Warning if dependency on the size of function or void(-Wpointer-arith)" superClass="com.renesas.cdt.core.Compiler.option.warning25" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning26.911763280" name="Issue Warning of multiple declarations(-Wredundant-decls)" superClass="com.renesas.cdt.core.Compiler.option.warning26" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning27.1705887099" name="Issue Warning if a local var shadows another var(-Wshadow)" superClass="com.renesas.cdt.core.Compiler.option.warning27" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning28.1045672769" name="Issue Warning if a function has no argument types(-Wstrict-prototypes)" superClass="com.renesas.cdt.core.Compiler.option.warning28" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning29.1388878801" name="Issue Warning if a bad g++ synthesiser(-Wsynth)" superClass="com.renesas.cdt.core.Compiler.option.warning29" value="false" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning30.1994659686" name="Issue Warning about c and ansi c construct incompatibility(-Wtraditional)" superClass="com.renesas.cdt.core.Compiler.option.warning30" value="false" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.warning31.531473224" name="Give string constants the type 'const char[length]'(-Wwrite-strings)" superClass="com.renesas.cdt.core.Compiler.option.warning31" value="true" valueType="boolean"/>
|
||||
<option id="com.renesas.cdt.core.Compiler.option.CPUSeries.114360178" name="Cpu Series" superClass="com.renesas.cdt.core.Compiler.option.CPUSeries"/>
|
||||
<inputType id="%Base.Compiler.C.InputType.Id.321945067" name="C Input" superClass="%Base.Compiler.C.InputType.Id"/>
|
||||
<inputType id="Base.Compiler.CPP.InputType.Id.678276075" name="C++ Input" superClass="Base.Compiler.CPP.InputType.Id"/>
|
||||
</tool>
|
||||
<tool id="com.renesas.cdt.rz.hardwaredebug.win32.tool.assembler.Id.1682023133" name="Assembler" superClass="com.renesas.cdt.rz.hardwaredebug.win32.tool.assembler.Id">
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Assembler.option.architecture.1247399321" name="Architecture" superClass="com.renesas.cdt.rz.HardwareDebug.Assembler.option.architecture" value="com.renesas.cdt.rz.HardwareDebug.Assembler.option.architecture.armv7r" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Assembler.option.cpuType.924935876" name="CPU type" superClass="com.renesas.cdt.rz.HardwareDebug.Assembler.option.cpuType" value="com.renesas.cdt.rz.HardwareDebug.Assembler.option.cpuType.cortexr4f" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Assembler.option.dataEndian.2127826551" name="Endian" superClass="com.renesas.cdt.rz.HardwareDebug.Assembler.option.dataEndian" value="com.renesas.cdt.rz.HardwareDebug.Assembler.option.dataEndian.little" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Assembler.option.instructionset.500088440" name="Instruction Set" superClass="com.renesas.cdt.rz.HardwareDebug.Assembler.option.instructionset" value="com.renesas.cdt.rz.HardwareDebug.Assembler.option.instructionset.arm" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Assembler.option.targetfpu.590502840" name="Target FPU (-mfpu)" superClass="com.renesas.cdt.rz.HardwareDebug.Assembler.option.targetfpu" value="com.renesas.cdt.rz.HardwareDebug.Assembler.option.targetfpu.vfp" valueType="enumerated"/>
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Assembler.option.floatingpointabi.1360575803" name="Floating-point ABI (-mfloat-abi=name)" superClass="com.renesas.cdt.rz.HardwareDebug.Assembler.option.floatingpointabi" value="Hard" valueType="enumerated"/>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.renesas.cdt.core.Assembler.option.includeFileDirectories.1525014372" name="Include file directories" superClass="com.renesas.cdt.core.Assembler.option.includeFileDirectories" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/System/GCC/asm}""/>
|
||||
</option>
|
||||
<inputType id="%Base.Assembler.inputType.Id.174869644" name="Assembler InputType" superClass="%Base.Assembler.inputType.Id"/>
|
||||
</tool>
|
||||
<tool id="com.renesas.cdt.rz.hardwaredebug.win32.tool.linker.Id.1114307562" name="Linker" superClass="com.renesas.cdt.rz.hardwaredebug.win32.tool.linker.Id">
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.renesas.cdt.rz.HardwareDebug.Linker.option.archiveSearchDirectories.1574512948" name="Archive search directories" superClass="com.renesas.cdt.rz.HardwareDebug.Linker.option.archiveSearchDirectories" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value=""${TCINSTALL}/lib/gcc/arm-none-eabi/${GCC_VERSION}/fpu/interwork""/>
|
||||
<listOptionValue builtIn="false" value=""${TCINSTALL}/arm-none-eabi/lib/fpu/interwork""/>
|
||||
</option>
|
||||
<option id="com.renesas.cdt.rz.HardwareDebug.Linker.option.dataEndian.388928982" name="Endian" superClass="com.renesas.cdt.rz.HardwareDebug.Linker.option.dataEndian" value="com.renesas.cdt.rz.HardwareDebug.Linker.option.dataEndian.little" valueType="enumerated"/>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.renesas.cdt.rz.HardwareDebug.Linker.option.archiveLibraryFiles.1856032828" name="Archive (library) files" superClass="com.renesas.cdt.rz.HardwareDebug.Linker.option.archiveLibraryFiles" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value="m"/>
|
||||
<listOptionValue builtIn="false" value="c"/>
|
||||
<listOptionValue builtIn="false" value="gcc"/>
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.renesas.cdt.core.Linker.option.userDefinedOptions.2087395271" name="User defined options" superClass="com.renesas.cdt.core.Linker.option.userDefinedOptions" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value="-estart"/>
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.renesas.cdt.core.Linker.option.linkOrderList.1339558820" name="" superClass="com.renesas.cdt.core.Linker.option.linkOrderList" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value="".\src\exit.o""/>
|
||||
<listOptionValue builtIn="false" value="".\src\init_main.o""/>
|
||||
<listOptionValue builtIn="false" value="".\src\loader_init.o""/>
|
||||
<listOptionValue builtIn="false" value="".\src\loader_init2.o""/>
|
||||
<listOptionValue builtIn="false" value="".\src\loader_param.o""/>
|
||||
<listOptionValue builtIn="false" value="".\src\r_atcm_init.o""/>
|
||||
<listOptionValue builtIn="false" value="".\src\r_cpg.o""/>
|
||||
<listOptionValue builtIn="false" value="".\src\r_ecm.o""/>
|
||||
<listOptionValue builtIn="false" value="".\src\r_icu_init.o""/>
|
||||
<listOptionValue builtIn="false" value="".\src\r_mpc.o""/>
|
||||
<listOptionValue builtIn="false" value="".\src\r_ram_init.o""/>
|
||||
<listOptionValue builtIn="false" value="".\src\r_reset.o""/>
|
||||
<listOptionValue builtIn="false" value="".\src\vector.o""/>
|
||||
<listOptionValue builtIn="false" value="".\libTutorial.a""/>
|
||||
</option>
|
||||
<option id="com.renesas.cdt.core.Linker.option.commandFileOverride.622113609" name="Command file overide" superClass="com.renesas.cdt.core.Linker.option.commandFileOverride" value="com.renesas.cdt.core.Linker.option.commandFileOverride.externalLinkerScript" valueType="enumerated"/>
|
||||
<option command=" -T"C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM\HardwareDebug\LinkerSubCommand.tmp" -T" id="com.renesas.cdt.core.Linker.option.file.464254322" name="File" superClass="com.renesas.cdt.core.Linker.option.file" value=""${workspace_loc:/${ProjName}/System/GCC/GNU_LINKER_ATCM.ld}"" valueType="string"/>
|
||||
</tool>
|
||||
<tool id="com.renesas.cdt.rz.hardwaredebug.win32.tool.objcopy.Id.1674695683" name="Objcopy" superClass="com.renesas.cdt.rz.hardwaredebug.win32.tool.objcopy.Id"/>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<fileInfo id="com.renesas.cdt.rz.hardwaredebug.win32.configuration.Id.137003302.1852356998" name="IntQueue.c" rcbsApplicability="disable" resourcePath="src/Full_Demo/Standard_Demo_Tasks/IntQueue.c" toolsToInvoke="com.renesas.cdt.rz.hardwaredebug.win32.tool.compiler.Id.542544613.1778364722">
|
||||
<tool id="com.renesas.cdt.rz.hardwaredebug.win32.tool.compiler.Id.542544613.1778364722" name="Compiler" superClass="com.renesas.cdt.rz.hardwaredebug.win32.tool.compiler.Id.542544613"/>
|
||||
</fileInfo>
|
||||
<sourceEntries>
|
||||
<entry excluding="System/GCC/src/gnu_io.c|System/GCC/src/syscalls.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="Tutorial.com.renesas.cdt.rz.projectType.win32.Id.1958300405" name="Executable (Renesas)" projectType="com.renesas.cdt.rz.projectType.win32.Id"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="refreshScope"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
</cproject>
|
||||
7
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.info
Normal file
7
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.info
Normal file
@ -0,0 +1,7 @@
|
||||
TOOL_CHAIN=KPIT GNUARM-NONE-EABI Toolchain
|
||||
VERSION=v14.02
|
||||
TC_INSTALL=C:\Program Files (x86)\KPIT\GNUARM-NONEv14.02-EABI\arm-none-eabi\arm-none-eabi\
|
||||
GCC_STRING=4.9-GNUARM-NONE_v14.02
|
||||
VERSION_IDE=
|
||||
E2STUDIO_VERSION=4.0.2.008
|
||||
ACTIVE_CONFIGURATION=HardwareDebug
|
||||
223
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.project
Normal file
223
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.project
Normal file
@ -0,0 +1,223 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>RTOSDemo</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>com.renesas.cdt.core.genmakebuilder</name>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>com.renesas.cdt.core.kpitcnature</nature>
|
||||
<nature>com.renesas.cdt.core.kpitccnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>src/FreeRTOS_Source</name>
|
||||
<type>2</type>
|
||||
<locationURI>FREERTOS_ROOT/FreeRTOS/Source</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>2</type>
|
||||
<locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks/include</name>
|
||||
<type>2</type>
|
||||
<locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/include</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
<filteredResources>
|
||||
<filter>
|
||||
<id>1440591358527</id>
|
||||
<name>src/FreeRTOS_Source/portable</name>
|
||||
<type>9</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-MemMang</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1440591358537</id>
|
||||
<name>src/FreeRTOS_Source/portable</name>
|
||||
<type>9</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-GCC</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1441019347018</id>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-IntQueue.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1441019347028</id>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-dynamic.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1441019347038</id>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-BlockQ.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1441019347048</id>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-blocktim.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1441019347058</id>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-countsem.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1441019347058</id>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-GenQTest.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1441019347068</id>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-recmutex.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1441019347078</id>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-semtest.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1441019347078</id>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-flop.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1441019347088</id>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-TimerDemo.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1441019347098</id>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-QueueOverwrite.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1441019347098</id>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-EventGroupsDemo.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1441019347108</id>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-TaskNotify.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1441019347108</id>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-IntSemTest.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1441019347118</id>
|
||||
<name>src/Full_Demo/Standard_Demo_Tasks</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-death.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1440591394340</id>
|
||||
<name>src/FreeRTOS_Source/portable/GCC</name>
|
||||
<type>9</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-ARM_CRx_No_GIC</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
<filter>
|
||||
<id>1440591376868</id>
|
||||
<name>src/FreeRTOS_Source/portable/MemMang</name>
|
||||
<type>5</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-heap_4.c</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
</filteredResources>
|
||||
<variableList>
|
||||
<variable>
|
||||
<name>FREERTOS_ROOT</name>
|
||||
<value>$%7BPARENT-3-PROJECT_LOC%7D</value>
|
||||
</variable>
|
||||
</variableList>
|
||||
</projectDescription>
|
||||
@ -0,0 +1,4 @@
|
||||
Build\ project\ excluding\ the\ dependencies=false
|
||||
Re-generate\ and\ use\ dependencies\ during\ project\ build=true
|
||||
Use\ existing\ dependencies\ during\ project\ build=false
|
||||
eclipse.preferences.version=1
|
||||
@ -0,0 +1,36 @@
|
||||
com.renesas.cdt.core.Assembler.option.includeFileDirectories="${workspace_loc\:/${ProjName}}/src";
|
||||
com.renesas.cdt.core.LibraryGenerator.option.ctype=false
|
||||
com.renesas.cdt.core.LibraryGenerator.option.libraryType=Project-Built
|
||||
com.renesas.cdt.core.LibraryGenerator.option.math=false
|
||||
com.renesas.cdt.core.LibraryGenerator.option.selectLibrary=Optimized
|
||||
com.renesas.cdt.core.LibraryGenerator.option.stdio=true
|
||||
com.renesas.cdt.core.LibraryGenerator.option.stdlib=true
|
||||
com.renesas.cdt.core.LibraryGenerator.option.string=true
|
||||
com.renesas.cdt.core.Linker.option.userDefinedOptions=;
|
||||
com.renesas.cdt.rz.HardwareDebug.Assembler.option.architecture=armv7-r
|
||||
com.renesas.cdt.rz.HardwareDebug.Assembler.option.cpuType=cortex-r4f
|
||||
com.renesas.cdt.rz.HardwareDebug.Compiler.option.architecture=armv7-r
|
||||
com.renesas.cdt.rz.HardwareDebug.Compiler.option.cpuType=cortex-r4f
|
||||
com.renesas.cdt.rz.HardwareDebug.Compiler.option.cpuType.585789719=cortex-r4f
|
||||
com.renesas.cdt.rz.HardwareDebug.Compiler.option.dataEndian=Little-endian
|
||||
com.renesas.cdt.rz.HardwareDebug.Compiler.option.floatingpointabi=Soft
|
||||
com.renesas.cdt.rz.HardwareDebug.Compiler.option.instructionset=ARM
|
||||
com.renesas.cdt.rz.HardwareDebug.Compiler.option.interworking=true
|
||||
com.renesas.cdt.rz.HardwareDebug.Compiler.option.macroDefines=
|
||||
com.renesas.cdt.rz.HardwareDebug.Compiler.option.targetfpu=vfp
|
||||
com.renesas.cdt.rz.HardwareDebug.Linker.option.archiveLibraryFiles=${BuildArtifactFileBaseName};gcc;
|
||||
com.renesas.cdt.rz.HardwareDebug.Linker.option.archiveSearchDirectories.1574512948="${TCINSTALL}/lib/gcc/arm-none-eabi/${GCC_VERSION}/fpu/interwork";"${TCINSTALL}/arm-none-eabi/lib/fpu/interwork";
|
||||
com.renesas.cdt.rz.Release.Assembler.option.architecture=armv7-r
|
||||
com.renesas.cdt.rz.Release.Assembler.option.cpuType=cortex-r4f
|
||||
com.renesas.cdt.rz.Release.Compiler.option.architecture=armv7-r
|
||||
com.renesas.cdt.rz.Release.Compiler.option.cpuType=cortex-r4f
|
||||
com.renesas.cdt.rz.Release.Compiler.option.cpuType.963183599=cortex-r4f
|
||||
com.renesas.cdt.rz.Release.Compiler.option.dataEndian=Little-endian
|
||||
com.renesas.cdt.rz.Release.Compiler.option.floatingpointabi=Soft
|
||||
com.renesas.cdt.rz.Release.Compiler.option.instructionset=ARM
|
||||
com.renesas.cdt.rz.Release.Compiler.option.interworking=true
|
||||
com.renesas.cdt.rz.Release.Compiler.option.macroDefines=
|
||||
com.renesas.cdt.rz.Release.Compiler.option.targetfpu=vfp
|
||||
com.renesas.cdt.rz.Release.Linker.option.archiveLibraryFiles=${BuildArtifactFileBaseName};gcc;
|
||||
com.renesas.cdt.rz.Release.Linker.option.archiveSearchDirectories.966751407="${TCINSTALL}/lib/gcc/arm-none-eabi/${GCC_VERSION}/interwork";"${TCINSTALL}/arm-none-eabi/lib/interwork";
|
||||
eclipse.preferences.version=1
|
||||
@ -0,0 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project>
|
||||
<configuration id="com.renesas.cdt.rz.hardwaredebug.win32.configuration.Id.137003302" name="HardwareDebug">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider class="com.renesas.cdt.common.build.spec.RZGCCBuiltinSpecsDetector" console="false" env-hash="-432948836777516605" id="RZGCCBuiltinSpecsDetector" keep-relative-paths="false" name="Renesas GNUARM-NONE GCCBuildinCompilerSettings" options-hash="857384749" parameter="arm-none-eabi-gcc -E -P -v -dD ${INPUTS}" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
</extension>
|
||||
</configuration>
|
||||
</project>
|
||||
@ -0,0 +1,35 @@
|
||||
[BREAKPOINTS]
|
||||
ForceImpTypeAny = 0
|
||||
ShowInfoWin = 1
|
||||
EnableFlashBP = 2
|
||||
BPDuringExecution = 0
|
||||
[CFI]
|
||||
CFISize = 0x00
|
||||
CFIAddr = 0x00
|
||||
[CPU]
|
||||
OverrideMemMap = 0
|
||||
AllowSimulation = 1
|
||||
ScriptFile=""
|
||||
[FLASH]
|
||||
CacheExcludeSize = 0x00
|
||||
CacheExcludeAddr = 0x00
|
||||
MinNumBytesFlashDL = 0
|
||||
SkipProgOnCRCMatch = 1
|
||||
VerifyDownload = 1
|
||||
AllowCaching = 1
|
||||
EnableFlashDL = 2
|
||||
Override = 0
|
||||
Device="UNSPECIFIED"
|
||||
[GENERAL]
|
||||
WorkRAMSize = 0x00
|
||||
WorkRAMAddr = 0x00
|
||||
RAMUsageLimit = 0x00
|
||||
[SWO]
|
||||
SWOLogFile=""
|
||||
[MEM]
|
||||
RdOverrideOrMask = 0x00
|
||||
RdOverrideAndMask = 0xFFFFFFFF
|
||||
RdOverrideAddr = 0xFFFFFFFF
|
||||
WrOverrideOrMask = 0x00
|
||||
WrOverrideAndMask = 0xFFFFFFFF
|
||||
WrOverrideAddr = 0xFFFFFFFF
|
||||
@ -0,0 +1,215 @@
|
||||
/****************************************************************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
****************************************************************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* File Name : GNU_LINKER_ATCM.ld
|
||||
* Device(s) : RZ/T1 (R7S910018)
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* H/W Platform : RSK+RZT1 CPU Board
|
||||
* Description : Linker file for projects that require to load and run from RAM (ATCM)
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00
|
||||
***********************************************************************************************************************/
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(start)
|
||||
|
||||
/* Base Address RAM Memory Table 1 Mbyte on-chip RAM */
|
||||
MEMORY
|
||||
{
|
||||
/* Internal RAM address range H'2000_0000 to H'2001_FFFF is configured as data retention RAM */
|
||||
/* Write access to this address range has to be enabled by writing to registers SYSCR1 and SYSCR2 */
|
||||
ATCM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 /* (512KB) H'00000000 to H'0007FFFF */
|
||||
BTCM (rwx) : ORIGIN = 0x00800000, LENGTH = 0x00800000 /* (32KB) H'00800000 to H'00807FFF */
|
||||
BUFFER_RAM (rwx) : ORIGIN = 0x20200000, LENGTH = 0x00100000 /* (1024KB) H'08000000 to H'0FFFFFFF */
|
||||
DATA_RAM0 (rwx) : ORIGIN = 0x24000000, LENGTH = 0x00080000 /* (512KB) H'22000000 to H'2207FFFF */
|
||||
DATA_RAM1 (rwx) : ORIGIN = 0x22000000, LENGTH = 0x00080000 /* (512KB) H'24000000 to H'2407FFFF */
|
||||
|
||||
SPIBSC (rw) : ORIGIN = 0x30000000, LENGTH = 0x04000000 /* attached to H'30000000 to H'33FFFFFF */
|
||||
CS0 (rw) : ORIGIN = 0x40000000, LENGTH = 0x04000000 /* attached to H'40000000 to H'43FFFFFF */
|
||||
CS1 (rw) : ORIGIN = 0x44000000, LENGTH = 0x04000000 /* attached to H'44000000 to H'47FFFFFF */
|
||||
CS2 (rw) : ORIGIN = 0x48000000, LENGTH = 0x04000000 /* attached to H'40000000 to H'4CFFFFFF */
|
||||
CS3 (rw) : ORIGIN = 0x4C000000, LENGTH = 0x04000000 /* attached to H'4C000000 to H'4FFFFFFF */
|
||||
CS4 (rw) : ORIGIN = 0x50000000, LENGTH = 0x04000000 /* attached to H'50000000 to H'53FFFFFF */
|
||||
CS5 (rw) : ORIGIN = 0x54000000, LENGTH = 0x04000000 /* attached to H'54000000 to H'57FFFFFF */
|
||||
|
||||
/* Mapped memory type */
|
||||
SPI_ROM (rw) : ORIGIN = 0x30000000, LENGTH = 0x04000000
|
||||
CS0_ROM (rw) : ORIGIN = 0x40000000, LENGTH = 0x04000000
|
||||
CS1_ROM (rw) : ORIGIN = 0x44000000, LENGTH = 0x04000000
|
||||
SDRAM0_EXT (rw) : ORIGIN = 0x48000000, LENGTH = 0x04000000
|
||||
SDRAM1_EXT (rw) : ORIGIN = 0x4C000000, LENGTH = 0x04000000
|
||||
}
|
||||
|
||||
SYS_STACK_SIZE = 0x200; /* Application stack size */
|
||||
SVC_STACK_SIZE = 0x200; /* SVC mode stack */
|
||||
IRQ_STACK_SIZE = 0x200; /* IRQ mode stack */
|
||||
FIQ_STACK_SIZE = 0x200; /* FRQ mode stack */
|
||||
UND_STACK_SIZE = 0x200; /* SVC mode stack */
|
||||
ABT_STACK_SIZE = 0x200; /* ABT mode stack */
|
||||
HEAP_STACK_SIZE = 0x1000; /* Heap stack size */
|
||||
|
||||
ATCM_BASE = 0x00000000; /* User application located here */
|
||||
BTCM_BASE = 0x00800000; /* BTCM base address */
|
||||
|
||||
USER_EXEC_BASE = 0x00000000; /* Application loads and runs from here */
|
||||
|
||||
USER_RAM = 0x20000000; /* Application's RAM base */
|
||||
|
||||
STACK_BASE = 0x00807800; /* Stacks located in BTCM */
|
||||
|
||||
SDRAM0_BASE = 0x48000000; /* SDRAM1 is attached to CS2 space */
|
||||
SDRAM1_BASE = 0x4C000000; /* SDRAM1 is attached to CS3 space */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.reset USER_EXEC_BASE :
|
||||
{
|
||||
reset_start = .;
|
||||
execute = .;
|
||||
_intvec_start = .;
|
||||
*start.o (.text);
|
||||
. = ALIGN(0x4);
|
||||
_intvec_end = .;
|
||||
end_reset = .;
|
||||
} > ATCM
|
||||
|
||||
.text :
|
||||
{
|
||||
text_start = .;
|
||||
*(.text)
|
||||
*(.text.startup)
|
||||
text_end = .;
|
||||
} > ATCM
|
||||
|
||||
.rodata :
|
||||
{
|
||||
_rodata_start = .;
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
. = ALIGN(0x8);
|
||||
_start_data_ROM = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
_end_data_ROM = .;
|
||||
*(.got.plt)
|
||||
*(.got)
|
||||
. = ALIGN(0x8);
|
||||
_rodata_end = .;
|
||||
PROVIDE(end = .);
|
||||
} > ATCM
|
||||
|
||||
_ram_data_size = (_end_data_ROM - _start_data_ROM);
|
||||
|
||||
.data USER_RAM :
|
||||
{
|
||||
_data_start = .;
|
||||
_start_data_RAM = .;
|
||||
. += _ram_data_size;
|
||||
_data_end = .;
|
||||
}
|
||||
|
||||
.bss _data_end :
|
||||
{
|
||||
_bss = .;
|
||||
PROVIDE(__bss_start__ = .);
|
||||
*(.bss)
|
||||
*(.bss.**)
|
||||
*(COMMON)
|
||||
. = ALIGN(0x4);
|
||||
PROVIDE(__bss_end__ = .);
|
||||
_ebss = .;
|
||||
_end = .;
|
||||
PROVIDE(end = .);
|
||||
}
|
||||
|
||||
.heap :
|
||||
{
|
||||
heap_start = .;
|
||||
. = ALIGN(0x8);
|
||||
*(.heap_stack)
|
||||
. += HEAP_STACK_SIZE;
|
||||
heap_end = .;
|
||||
} > ATCM
|
||||
|
||||
.sys_stack STACK_BASE :
|
||||
{
|
||||
sys_stack_start = .;
|
||||
. = ALIGN(0x8);
|
||||
*(.sys_stack)
|
||||
. += SYS_STACK_SIZE;
|
||||
sys_stack_end = .;
|
||||
} > BTCM
|
||||
|
||||
.svc_stack sys_stack_end :
|
||||
{
|
||||
svc_stack_start = .;
|
||||
. = ALIGN(0x8);
|
||||
*(.svc_stack)
|
||||
. += SVC_STACK_SIZE;
|
||||
svc_stack_end = .;
|
||||
} > BTCM
|
||||
|
||||
.irq_stack svc_stack_end :
|
||||
{
|
||||
irq_stack_start = .;
|
||||
. = ALIGN(0x8);
|
||||
*(.irq_stack)
|
||||
. += IRQ_STACK_SIZE;
|
||||
irq_stack_end = .;
|
||||
} > BTCM
|
||||
|
||||
.fiq_stack irq_stack_end :
|
||||
{
|
||||
fiq_stack_start = .;
|
||||
. = ALIGN(0x8);
|
||||
*(.fiq_stack)
|
||||
. += FIQ_STACK_SIZE;
|
||||
fiq_stack_end = .;
|
||||
} > BTCM
|
||||
|
||||
.und_stack fiq_stack_end :
|
||||
{
|
||||
und_stack_start = .;
|
||||
. = ALIGN(0x8);
|
||||
*(.und_stack)
|
||||
. += UND_STACK_SIZE;
|
||||
und_stack_end = .;
|
||||
} > BTCM
|
||||
|
||||
.abt_stack und_stack_end :
|
||||
{
|
||||
abt_stack_start = .;
|
||||
. = ALIGN(0x8);
|
||||
*(.abt_stack)
|
||||
. += ABT_STACK_SIZE;
|
||||
abt_stack_end = .;
|
||||
} > BTCM
|
||||
|
||||
/* NOLOAD directs linker NOT to fill VRAMx_SECTION with 0. */
|
||||
/* Usage of NOLOAD increases speed of linker and download to target */
|
||||
.sdram0_section SDRAM0_BASE (NOLOAD) : {} > SDRAM0_EXT
|
||||
.sdram1_section SDRAM1_BASE (NOLOAD) : {} > SDRAM1_EXT
|
||||
}
|
||||
@ -0,0 +1,351 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : loader_init.asm
|
||||
* Version : 0.1
|
||||
* Device : R7S910018
|
||||
* Abstract : Loader program 1
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1
|
||||
* Description : System low level configuration.
|
||||
* Limitation : none
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.04.2015 1.00 First Release
|
||||
***********************************************************************************************************************/
|
||||
|
||||
.text
|
||||
.code 32
|
||||
|
||||
.global reset_handler
|
||||
.global loader_init1
|
||||
.global set_low_vec
|
||||
.global cache_init
|
||||
.global mpu_init
|
||||
.global loader_init2
|
||||
.global r_icu_nmi_interrupt
|
||||
|
||||
|
||||
reset_handler:
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : loader_init1
|
||||
* Description : Initialize system by loader program
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
loader_init1:
|
||||
|
||||
/* ========================================================================= */
|
||||
/* Multi-core startup (future proofing boot code) */
|
||||
/* Check core, if not core 0 put to sleep. */
|
||||
/* ========================================================================= */
|
||||
mrc p15, 0, r0, c0, c0, 5 /* Read MPIDR */
|
||||
ands r0, r0, #3
|
||||
goToSleep:
|
||||
wfine
|
||||
bne goToSleep
|
||||
|
||||
mrs r0, cpsr /* Disalbe FIQ and IRQ */
|
||||
orr r0, r0, #0x000000C0
|
||||
msr cpsr, r0
|
||||
isb
|
||||
|
||||
stack_init:
|
||||
/* Stack setting */
|
||||
cps #17 /* FIQ mode */
|
||||
ldr sp, =fiq_stack_end
|
||||
cps #18 /* IRQ mode */
|
||||
ldr sp, =irq_stack_end
|
||||
cps #23 /* Abort mode */
|
||||
ldr sp, =abt_stack_end
|
||||
cps #27 /* Undef mode */
|
||||
ldr sp, =und_stack_end
|
||||
cps #31 /* System mode */
|
||||
ldr sp, =sys_stack_end
|
||||
cps #19 /* SVC mode */
|
||||
ldr sp, =svc_stack_end
|
||||
|
||||
vfp_init:
|
||||
/* Initialize VFP setting */
|
||||
mrc p15, #0, r0, c1, c0, #2 /* Enables cp10 and cp11 accessing */
|
||||
orr r0, r0, #0xF00000
|
||||
mcr p15, #0, r0, c1, c0, #2
|
||||
isb /* Ensuring Context-changing */
|
||||
|
||||
mov r0, #0x40000000 /* Enables VFP operation */
|
||||
vmsr fpexc, r0
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 0 /* Set SCTLR.VE bit to 1 (Use VIC) */
|
||||
orr r0, r0, #0x01000000
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
isb /* Ensuring Context-changing */
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 1 /* Enalbe ECC */
|
||||
orr r0, r0, #0x06000000
|
||||
mcr p15, 0, r0, c1, c0, 1
|
||||
isb /* Ensuring Context-changing */
|
||||
|
||||
mrs r0, cpsr /* Re-enalbe FIQ */
|
||||
and r0, r0, #0xFFFFFFBF
|
||||
msr cpsr, r0
|
||||
isb
|
||||
|
||||
/* Jump to loader_init2 */
|
||||
jump_loader_init2:
|
||||
ldr r0, =loader_init2
|
||||
bx r0
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : cache_init
|
||||
* Description : Initialize I1, D1 cache and MPU settings
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
.equ SCTLR_BR, 0x00020000
|
||||
.equ SCTLR_M, 0x00000001
|
||||
.equ SCTLR_I_C, 0x00001004
|
||||
|
||||
.equ DRBAR_REGION_0, 0x04000000 /*Base address = 0400_0000h */
|
||||
.equ DRACR_REGION_0, 0x0000030C /*R/W(full), Normal, Non-cache, share */
|
||||
.equ DRSR_REGION_0, 0x00000025 /*Size 512KB, MPU enable */
|
||||
|
||||
.equ DRBAR_REGION_1, 0x10000000 /*Base address = 1000_0000h */
|
||||
.equ DRACR_REGION_1, 0x0000030C /*R/W(full), Normal, Non-cache, share */
|
||||
.equ DRSR_REGION_1, 0x00000033 /*Size 64MB, MPU enable */
|
||||
|
||||
.equ DRBAR_REGION_2, 0x20000000 /*Base address = 2000_0000h */
|
||||
.equ DRACR_REGION_2, 0x0000030C /*R/W(full), Normal, Non-cache, share */
|
||||
.equ DRSR_REGION_2, 0x00000025 /*Size 512KB, MPU enable */
|
||||
|
||||
.equ DRBAR_REGION_3, 0x22000000 /*Base address = 2200_0000h */
|
||||
.equ DRACR_REGION_3, 0x00000307 /*R/W(full), Normal, Write-back no allocate, share */
|
||||
.equ DRSR_REGION_3, 0x00000033 /*Size 64MB, MPU enable */
|
||||
|
||||
.equ DRBAR_REGION_4, 0x30000000 /*Base address = 3000_0000h */
|
||||
.equ DRACR_REGION_4, 0x00000307 /*R/W(full), Normal, Write-back no allocate, share */
|
||||
.equ DRSR_REGION_4, 0x00000033 /*Size 64MB, MPU enable */
|
||||
|
||||
.equ DRBAR_REGION_5, 0x40000000 /*Base address = 4000_0000h */
|
||||
.equ DRACR_REGION_5, 0x00000307 /*R/W(full), Normal, Write-back no allocate, share */
|
||||
.equ DRSR_REGION_5, 0x00000035 /*Size 128MB, MPU enable */
|
||||
|
||||
.equ DRBAR_REGION_6, 0x48000000 /*Base address = 4800_0000h */
|
||||
.equ DRACR_REGION_6, 0x00000307 /*R/W(full), Normal, Write-back no allocate, share */
|
||||
.equ DRSR_REGION_6, 0x00000035 /*Size 128MB, MPU enable */
|
||||
|
||||
.equ DRBAR_REGION_7, 0x50000000 /*Base address = 5000_0000h */
|
||||
.equ DRACR_REGION_7, 0x00001305 /*R/W(full), XN, Device, share */
|
||||
.equ DRSR_REGION_7, 0x00000035 /*Size 128MB, MPU enable */
|
||||
|
||||
.equ DRBAR_REGION_8, 0x60000000 /*Base address = 6000_0000h */
|
||||
.equ DRACR_REGION_8, 0x0000030C /*R/W(full), Normal, Non-cache, share */
|
||||
.equ DRSR_REGION_8, 0x00000035 /*Size 128MB, MPU enable */
|
||||
|
||||
.equ DRBAR_REGION_9, 0x68000000 /*Base address = 6800_0000h */
|
||||
.equ DRACR_REGION_9, 0x0000030C /*R/W(full), Normal, Non-cache, share */
|
||||
.equ DRSR_REGION_9, 0x00000035 /*Size 128MB, MPU enable */
|
||||
|
||||
.equ DRBAR_REGION_10, 0x70000000 /*Base address = 7000_0000h */
|
||||
.equ DRACR_REGION_10, 0x00001305 /*R/W(full), XN, Device, share */
|
||||
.equ DRSR_REGION_10, 0x00000035 /*Size 128MB, MPU enable */
|
||||
|
||||
.equ DRBAR_REGION_11, 0x80000000 /*Base address = 8000_0000h */
|
||||
.equ DRACR_REGION_11, 0x00001305 /*R/W(full), XN, Device, share */
|
||||
.equ DRSR_REGION_11, 0x0000003D /*Size 2GB, MPU enable */
|
||||
|
||||
cache_init:
|
||||
push {lr}
|
||||
|
||||
cache_invalidate:
|
||||
/*Invalidate the I1, D1 cache */
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c7, c5, #0 /*Invalidate all Instruction Caches (Write-value is Ignored) */
|
||||
isb /*Ensuring Context-changing */
|
||||
mcr p15, #0, r0, c15, c5, #0 /*Invalidate all Data Caches (Write-value is Ignored) */
|
||||
isb /*Ensuring Context-changing */
|
||||
|
||||
/*Adopt default memory map as background map. */
|
||||
ldr r0, =SCTLR_BR /*Set SCTLR.BR bit to 1 */
|
||||
mrc p15, 0, r1, c1, c0, 0
|
||||
orr r1, r1, r0
|
||||
dsb
|
||||
mcr p15, 0, r1, c1, c0, 0
|
||||
isb /*Ensuring Context-changing */
|
||||
|
||||
/*Initialize MPU settings (region 0 to 11) */
|
||||
/*Define region 0 */
|
||||
mov r0, #0
|
||||
ldr r1, =DRBAR_REGION_0
|
||||
ldr r2, =DRACR_REGION_0
|
||||
ldr r3, =DRSR_REGION_0
|
||||
bl mpu_init
|
||||
|
||||
/*Define region 1 */
|
||||
mov r0, #1
|
||||
ldr r1, =DRBAR_REGION_1
|
||||
ldr r2, =DRACR_REGION_1
|
||||
ldr r3, =DRSR_REGION_1
|
||||
bl mpu_init
|
||||
|
||||
/*Define region 2 */
|
||||
mov r0, #2
|
||||
ldr r1, =DRBAR_REGION_2
|
||||
ldr r2, =DRACR_REGION_2
|
||||
ldr r3, =DRSR_REGION_2
|
||||
bl mpu_init
|
||||
|
||||
/*Define region 3 */
|
||||
mov r0, #3
|
||||
ldr r1, =DRBAR_REGION_3
|
||||
ldr r2, =DRACR_REGION_3
|
||||
ldr r3, =DRSR_REGION_3
|
||||
bl mpu_init
|
||||
|
||||
/*Define region 4 */
|
||||
mov r0, #4
|
||||
ldr r1, =DRBAR_REGION_4
|
||||
ldr r2, =DRACR_REGION_4
|
||||
ldr r3, =DRSR_REGION_4
|
||||
bl mpu_init
|
||||
|
||||
/*Define region 5 */
|
||||
mov r0, #5
|
||||
ldr r1, =DRBAR_REGION_5
|
||||
ldr r2, =DRACR_REGION_5
|
||||
ldr r3, =DRSR_REGION_5
|
||||
bl mpu_init
|
||||
|
||||
/*Define region 6 */
|
||||
mov r0, #6
|
||||
ldr r1, =DRBAR_REGION_6
|
||||
ldr r2, =DRACR_REGION_6
|
||||
ldr r3, =DRSR_REGION_6
|
||||
bl mpu_init
|
||||
|
||||
/*Define region 7 */
|
||||
mov r0, #7
|
||||
ldr r1, =DRBAR_REGION_7
|
||||
ldr r2, =DRACR_REGION_7
|
||||
ldr r3, =DRSR_REGION_7
|
||||
bl mpu_init
|
||||
|
||||
/*Define region 8 */
|
||||
mov r0, #8
|
||||
ldr r1, =DRBAR_REGION_8
|
||||
ldr r2, =DRACR_REGION_8
|
||||
ldr r3, =DRSR_REGION_8
|
||||
bl mpu_init
|
||||
|
||||
/*Define region 9
|
||||
mov r0, #9 */
|
||||
ldr r1, =DRBAR_REGION_9
|
||||
ldr r2, =DRACR_REGION_9
|
||||
ldr r3, =DRSR_REGION_9
|
||||
bl mpu_init
|
||||
|
||||
/*Define region 10 */
|
||||
mov r0, #10
|
||||
ldr r1, =DRBAR_REGION_10
|
||||
ldr r2, =DRACR_REGION_10
|
||||
ldr r3, =DRSR_REGION_10
|
||||
bl mpu_init
|
||||
|
||||
/*Define region 11 */
|
||||
mov r0, #11
|
||||
ldr r1, =DRBAR_REGION_11
|
||||
ldr r2, =DRACR_REGION_11
|
||||
ldr r3, =DRSR_REGION_11
|
||||
bl mpu_init
|
||||
|
||||
/*Enables MPU operation */
|
||||
ldr r0, =SCTLR_M /*Set SCTLR.M bit to 1 */
|
||||
mrc p15, 0, r1, c1, c0, 0
|
||||
orr r1, r1, r0
|
||||
dsb
|
||||
mcr p15, 0, r1, c1, c0, 0
|
||||
isb /*Ensuring Context-changing */
|
||||
|
||||
/*Enables I1,D1 cache operation */
|
||||
ldr r0, =SCTLR_I_C /*Set SCTLR.I and C bit to 1 */
|
||||
mrc p15, 0, r1, c1, c0, 0
|
||||
orr r1, r1, r0
|
||||
dsb
|
||||
mcr p15, 0, r1, c1, c0, 0
|
||||
isb /*Ensuring Context-changing */
|
||||
|
||||
pop {pc}
|
||||
bx lr
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : mpu_init
|
||||
* Description : Initialize MPU settings
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
mpu_init:
|
||||
/*RGNR(MPU Memory Region Number Register) */
|
||||
mcr p15, #0, r0, c6, c2, #0
|
||||
isb /*Ensuring Context-changing */
|
||||
|
||||
/*DRBAR(Data Region Base Address Register) */
|
||||
mcr p15, #0, r1, c6, c1, #0
|
||||
isb /*Ensuring Context-changing */
|
||||
|
||||
/*DRACR(Data Region Access Control Register) */
|
||||
mcr p15, #0, r2, c6, c1, #4
|
||||
isb /*Ensuring Context-changing */
|
||||
|
||||
/*DRSR(Data Region Size and Enable Register) */
|
||||
mcr p15, #0, r3, c6, c1, #2
|
||||
isb /*Ensuring Context-changing */
|
||||
|
||||
bx lr
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : set_low_vec
|
||||
* Description : Initialize sysytem by loader program
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
set_low_vec:
|
||||
mrc p15, 0, r0, c1, c0, 0 /*Set SCTLR.V bit to 1 (low-vector)*/
|
||||
and r0, r0, #0xFFFFDFFF
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
isb /*Ensuring Context-changing*/
|
||||
|
||||
bx lr
|
||||
|
||||
.end
|
||||
|
||||
/*End of File */
|
||||
@ -0,0 +1,70 @@
|
||||
/************************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
************************************************************************************************************************/
|
||||
/************************************************************************************************************************
|
||||
* File Name : start.asm
|
||||
* Device(s) : RZ/T1 (R7S910018)
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* H/W Platform : RSK+T1 CPU Board
|
||||
* Description : This is the code to be executed on the target
|
||||
The copyright string signifies the end of the Vector table
|
||||
* Note boot strap sequence is as follows:
|
||||
*
|
||||
* start->reset_handler->main()
|
||||
*
|
||||
* start - first code to be executed on the target
|
||||
start jumps to reset_handler the asm startup routine
|
||||
* reset_handler jumps to loader_init1() C entry point
|
||||
* loader_init2() calls main() C User code entry point
|
||||
************************************************************************************************************************/
|
||||
/************************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00
|
||||
************************************************************************************************************************/
|
||||
|
||||
.text
|
||||
.code 32
|
||||
|
||||
.extern FreeRTOS_SVC_Handler
|
||||
.global start
|
||||
.func start
|
||||
|
||||
start:
|
||||
LDR pc, =reset_handler /* Reset Vector */
|
||||
LDR pc, =undefined_handler
|
||||
LDR pc, =FreeRTOS_SVC_Handler
|
||||
LDR pc, =prefetch_handler
|
||||
LDR pc, =abort_handler
|
||||
LDR pc, =reserved_handler
|
||||
LDR pc, =irq_handler
|
||||
LDR pc, =fiq_handler
|
||||
code_start:
|
||||
.word start /* pointer to the user application start address */
|
||||
/* Used by NOR and SPI (System_Boot_Loader_xxxx) */
|
||||
code_end:
|
||||
.word end
|
||||
code_execute:
|
||||
.word execute /* execute address of first instruction */
|
||||
.string ".BootLoad_ValidProgramTest." /* bootloader validation signature */
|
||||
.align 4
|
||||
.end
|
||||
@ -0,0 +1,77 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
System Name : RZ/T1 Init program
|
||||
File Name : vector.asm
|
||||
Version : 0.1
|
||||
Device : R7S910018
|
||||
Abstract : vector address (in low vector)
|
||||
Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
OS : not use
|
||||
H/W Platform : Renesas Starter Kit for RZ/T1
|
||||
Description : vector address for RZ/T1 (in low vector)
|
||||
Limitation : none
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00 First Release
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/* This program is allocated to section "intvec" */
|
||||
|
||||
.text
|
||||
.code 32
|
||||
|
||||
.global undefined_handler
|
||||
.global FreeRTOS_SVC_Handler
|
||||
.global prefetch_handler
|
||||
.global abort_handler
|
||||
.global reserved_handler
|
||||
.global irq_handler
|
||||
.global fiq_handler
|
||||
|
||||
|
||||
undefined_handler:
|
||||
b undefined_handler
|
||||
|
||||
svc_handler:
|
||||
b svc_handler
|
||||
|
||||
prefetch_handler:
|
||||
b prefetch_handler
|
||||
|
||||
abort_handler:
|
||||
b abort_handler
|
||||
|
||||
reserved_handler:
|
||||
b reserved_handler
|
||||
|
||||
irq_handler:
|
||||
b irq_handler
|
||||
|
||||
fiq_handler:
|
||||
b fiq_handler
|
||||
|
||||
.end
|
||||
|
||||
@ -0,0 +1,65 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
************************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* File Name : compiler_settings.h
|
||||
* Device(s) : RZ/A1H (R7S910018)
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* H/W Platform : RSK+T1 CPU Board
|
||||
* Description : Any compiler specific settings are stored here.
|
||||
* : Variants of this file must be created for each compiler
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
***********************************************************************************************************************/
|
||||
/* Compiler specific UART i/O support header */
|
||||
#include "../../GCC/inc/gnu_io.h"
|
||||
|
||||
#ifndef COMPILER_SETTINGS_H
|
||||
#define COMPILER_SETTINGS_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
/* Definitions of SDRAM sections from the linker */
|
||||
#define BSS_SDRAM0_SECTION __attribute__ ((section (".sdram0_section")))
|
||||
#define BSS_SDRAM1_SECTION __attribute__ ((section (".sdram1_section")))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Variable External definitions and Function External definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Functions Prototypes
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/* COMPILER_SETTINGS_H */
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
@ -0,0 +1,68 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/******************************************************************************
|
||||
* File Name : gnu_io.h
|
||||
* Device(s) : RZ/A1H (R7S910018)
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* H/W Platform : RSK+T1 CPU Board
|
||||
* Description : GCC support for serial I/O header file
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef GNU_IO_H
|
||||
#define GNU_IO_H
|
||||
|
||||
/******************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Typedef definitions
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Macro definitions
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Variable Externs
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
Functions Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
extern void put_string(char *pString);
|
||||
extern void get_string(char *pString);
|
||||
|
||||
|
||||
#endif /* GNU_IO_H */
|
||||
|
||||
/* End of File */
|
||||
|
||||
@ -0,0 +1,104 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
****************************************************************************************************************************************************************/
|
||||
/****************************************************************************************************************************************************************
|
||||
* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
|
||||
****************************************************************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* File Name : gnu_io.c
|
||||
* Device(s) : RZ/A1H RSK+T1
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* H/W Platform : RSK+T1 CPU Board
|
||||
* Description : Sample Program - GCC support for serial I/O
|
||||
* : Variants of this file can be created for each compiler
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
***********************************************************************************************************************/
|
||||
/* Standard IO header */
|
||||
#include <stdio.h>
|
||||
/* Default type definition header */
|
||||
#include "r_typedefs.h"
|
||||
/* Character I/O header */
|
||||
#include "siochar.h"
|
||||
/* I/O Register root header */
|
||||
#include "iodefine.h"
|
||||
/* Compiler specific UART i/O support header */
|
||||
#include "gnu_io.h"
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: put_string
|
||||
* Description : GNU interface to low-level I/O putchar replacement
|
||||
* Arguments : char * pString
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void put_string (char *pString)
|
||||
{
|
||||
while(0 != (*pString))
|
||||
{
|
||||
io_put_char(*pString++);
|
||||
}
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function put_string
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: get_string
|
||||
* Description : GNU interface to low-level I/O getchar replacement
|
||||
* Arguments : char * pString
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void get_string (char * pString)
|
||||
{
|
||||
char * ptr = pString;
|
||||
|
||||
do
|
||||
{
|
||||
(*ptr) = io_get_char();
|
||||
|
||||
io_put_char(*ptr);
|
||||
|
||||
if('\r' == (*ptr))
|
||||
{
|
||||
(*ptr) = 0;
|
||||
|
||||
/* This is intentional since no more input is expected */
|
||||
break;
|
||||
}
|
||||
}
|
||||
while('\0' != (*ptr++));
|
||||
io_put_char('\r');
|
||||
io_put_char('\n');
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function get_string
|
||||
***********************************************************************************************************************/
|
||||
|
||||
@ -0,0 +1,243 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : loader_init2.c
|
||||
* Version : 0.1
|
||||
* Device : R7S910018
|
||||
* Abstract : Loader program 2
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : Initialise the peripheral settings of RZ/T1
|
||||
* Limitation : none
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00 First Release
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
***********************************************************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "iodefine.h"
|
||||
#include "r_cg_cgc.h"
|
||||
#include "r_cg_mpc.h"
|
||||
#include "r_system.h"
|
||||
#include "r_reset.h"
|
||||
#include "r_atcm_init.h"
|
||||
#include "r_typedefs.h"
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Private variables and functions
|
||||
***********************************************************************************************************************/
|
||||
static void reset_check (void);
|
||||
static void cpg_init (void);
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
***********************************************************************************************************************/
|
||||
extern void main(void);
|
||||
extern void set_low_vec(void);
|
||||
extern void cache_init(void);
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
***********************************************************************************************************************/
|
||||
void loader_init2 (void);
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : loader_init2
|
||||
* Description : Initialise system by loader program 2
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void loader_init2 (void)
|
||||
{
|
||||
/* Check the reset source */
|
||||
reset_check();
|
||||
|
||||
/* Set CPU clock and LOCO clock */
|
||||
cpg_init();
|
||||
|
||||
/* Set ATCM access wait to 1-wait with optimisation */
|
||||
/* Caution: ATCM_WAIT_0 is permitted if CPUCLK = 150MHz or 300MHz.
|
||||
ATCM_WAIT_1_OPT is permitted if CPUCLK = 450MHz or 600MHz.*/
|
||||
R_ATCM_WaitSet(ATCM_WAIT_1_OPT);
|
||||
|
||||
/* Initialise I1, D1 Cache and MPU setting */
|
||||
#warning Cache not enabled.
|
||||
// cache_init();
|
||||
|
||||
/* Set RZ/T1 to Low-vector (SCTLR.V = 0) */
|
||||
set_low_vec();
|
||||
|
||||
/* Jump to _main() */
|
||||
main();
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function loader_init2
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : reset_check
|
||||
* Description : Check the reset source and execute the each sequence.
|
||||
* When error source number 35 is generated, set P77 pin to High.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
static void reset_check(void)
|
||||
{
|
||||
volatile uint8_t result;
|
||||
volatile uint32_t dummy;
|
||||
|
||||
UNUSED_VARIABLE(result);
|
||||
UNUSED_VARIABLE(dummy);
|
||||
|
||||
/* Check the reset status flag and execute the each sequence */
|
||||
if (RST_SOURCE_ECM == SYSTEM.RSTSR0.LONG)
|
||||
{
|
||||
/* Enable writing to the RSTSR0 register */
|
||||
r_rst_write_enable();
|
||||
|
||||
/* Clear reset factor flag */
|
||||
SYSTEM.RSTSR0.LONG = 0x00000000;
|
||||
|
||||
/* Disable writing to the RSTSR0 register */
|
||||
r_rst_write_disable();
|
||||
|
||||
/* Please coding the User program */
|
||||
|
||||
}
|
||||
|
||||
/* Software reset 1 is generated */
|
||||
else if (RST_SOURCE_SWR1 == SYSTEM.RSTSR0.LONG)
|
||||
{
|
||||
/* Clear reset status flag */
|
||||
/* Enable writing to the RSTSR0 register */
|
||||
r_rst_write_enable();
|
||||
|
||||
/* Clear reset factor flag */
|
||||
SYSTEM.RSTSR0.LONG = 0x00000000;
|
||||
|
||||
/* Disable writing to the RSTSR0 register */
|
||||
r_rst_write_disable();
|
||||
|
||||
/* Please coding the User program */
|
||||
|
||||
}
|
||||
else if (RST_SOURCE_RES == SYSTEM.RSTSR0.LONG) // RES# pin reset is generated
|
||||
{
|
||||
/* Clear reset status flag */
|
||||
|
||||
/* Enable writing to the RSTSR0 register */
|
||||
r_rst_write_enable();
|
||||
|
||||
/* Clear reset factor flag */
|
||||
SYSTEM.RSTSR0.LONG = 0x00000000;
|
||||
|
||||
/* Disable writing to the RSTSR0 register */
|
||||
r_rst_write_disable();
|
||||
|
||||
/* Please add user code */
|
||||
|
||||
}
|
||||
|
||||
/* Any reset is not generated */
|
||||
else
|
||||
{
|
||||
/* Please add user code */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function reset_check
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : cpg_init
|
||||
* Description : Set CPU clock and LOCO clock by CPG function
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
static void cpg_init(void)
|
||||
{
|
||||
volatile uint32_t dummy;
|
||||
|
||||
UNUSED_VARIABLE(dummy);
|
||||
|
||||
/* Enables writing to the registers related to CPG function */
|
||||
R_CPG_WriteEnable();
|
||||
|
||||
/* Enables LOCO clock operation */
|
||||
SYSTEM.LOCOCR.BIT.LCSTP = CPG_LOCO_ENABLE;
|
||||
|
||||
/* Set CPUCLK to 450MHz, and dummy read at three times */
|
||||
SYSTEM.PLL1CR.LONG = CPG_CPUCLK_450_MHz;
|
||||
dummy = SYSTEM.PLL1CR.LONG;
|
||||
dummy = SYSTEM.PLL1CR.LONG;
|
||||
dummy = SYSTEM.PLL1CR.LONG;
|
||||
|
||||
/* Enables PLL1 operation */
|
||||
SYSTEM.PLL1CR2.LONG = CPG_PLL1_ON;
|
||||
|
||||
/* Disables writing to the registers related to CPG function */
|
||||
R_CPG_WriteDisable();
|
||||
|
||||
/* Wait about 100us for PLL1 (and LOCO) stabilisation */
|
||||
R_CPG_PLLWait();
|
||||
|
||||
/* Enables writing to the registers related to CPG function */
|
||||
R_CPG_WriteEnable();
|
||||
|
||||
/* Selects the PLL1 as clock source */
|
||||
SYSTEM.SCKCR2.LONG = CPG_SELECT_PLL1;
|
||||
|
||||
/* Disables writing to the registers related to CPG function */
|
||||
R_CPG_WriteDisable();
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function cpg_init
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/* End of File */
|
||||
|
||||
|
||||
@ -0,0 +1,717 @@
|
||||
/* Support files for GNU libc. Files in the system namespace go here.
|
||||
Files in the C namespace (ie those that do not start with an
|
||||
underscore) go in .c. */
|
||||
|
||||
#include <_ansi.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <sys/fcntl.h>
|
||||
#include <stdio.h>
|
||||
#include <time.h>
|
||||
#include <sys/time.h>
|
||||
#include <sys/times.h>
|
||||
#include <errno.h>
|
||||
#include <reent.h>
|
||||
#include <signal.h>
|
||||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/wait.h>
|
||||
#include "r_typedefs.h"
|
||||
#include "siochar.h"
|
||||
#include "swi.h"
|
||||
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL (0)
|
||||
#endif
|
||||
|
||||
/* Forward prototypes. */
|
||||
int _system _PARAMS ((const char *));
|
||||
int _rename _PARAMS ((const char *, const char *));
|
||||
int _isatty _PARAMS ((int));
|
||||
clock_t _times _PARAMS ((struct tms *));
|
||||
int _gettimeofday _PARAMS ((struct timeval *, void *));
|
||||
void _raise _PARAMS ((void));
|
||||
int _unlink _PARAMS ((const char *));
|
||||
int _link _PARAMS ((void));
|
||||
int _stat _PARAMS ((const char *, struct stat *));
|
||||
int _fstat _PARAMS ((int, struct stat *));
|
||||
caddr_t _sbrk _PARAMS ((int));
|
||||
int _getpid _PARAMS ((int));
|
||||
int _kill _PARAMS ((int, int));
|
||||
void _exit _PARAMS ((int));
|
||||
int _close _PARAMS ((int));
|
||||
int _swiclose _PARAMS ((int));
|
||||
int _open _PARAMS ((const char *, int, ...));
|
||||
int _swiopen _PARAMS ((const char *, int));
|
||||
int _write _PARAMS ((int, const char *, unsigned int));
|
||||
|
||||
int _swiwrite _PARAMS ((int, char *, int));
|
||||
int _lseek _PARAMS ((int, int, int));
|
||||
int _swilseek _PARAMS ((int, int, int));
|
||||
int _read _PARAMS ((int, char *, unsigned int));
|
||||
|
||||
int _swiread _PARAMS ((int, char *, int));
|
||||
void initialise_monitor_handles _PARAMS ((void));
|
||||
|
||||
static int wrap _PARAMS ((int));
|
||||
static int error _PARAMS ((int));
|
||||
static int get_errno _PARAMS ((void));
|
||||
static int remap_handle _PARAMS ((int));
|
||||
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
static int do_AngelSWI _PARAMS ((int, void *));
|
||||
#endif
|
||||
|
||||
static int findslot _PARAMS ((int));
|
||||
|
||||
/* Register name faking - works in collusion with the linker. */
|
||||
register char * stack_ptr __asm ("sp");
|
||||
|
||||
|
||||
/* following is copied from libc/stdio/local.h to check std streams */
|
||||
extern void _EXFUN(__sinit,(struct _reent *));
|
||||
#define CHECK_INIT(ptr) \
|
||||
do \
|
||||
{ \
|
||||
if ((ptr) && !(ptr)->__sdidinit) \
|
||||
__sinit (ptr); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
/* Adjust our internal handles to stay away from std* handles. */
|
||||
#define FILE_HANDLE_OFFSET (0x20)
|
||||
|
||||
static int monitor_stdin;
|
||||
static int monitor_stdout;
|
||||
static int monitor_stderr;
|
||||
|
||||
/* Struct used to keep track of the file position, just so we
|
||||
can implement fseek(fh,x,SEEK_CUR). */
|
||||
typedef struct
|
||||
{
|
||||
int handle;
|
||||
int pos;
|
||||
}
|
||||
poslog;
|
||||
|
||||
#define MAX_OPEN_FILES (20)
|
||||
static poslog openfiles [MAX_OPEN_FILES];
|
||||
|
||||
static int
|
||||
findslot (int fh)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < MAX_OPEN_FILES; i ++)
|
||||
if (openfiles[i].handle == fh)
|
||||
{
|
||||
break;
|
||||
}
|
||||
return (i);
|
||||
}
|
||||
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
|
||||
static inline int
|
||||
do_AngelSWI (int reason, void * arg)
|
||||
{
|
||||
int value;
|
||||
asm volatile ("mov r0, %1; mov r1, %2; " AngelSWIInsn " %a3; mov %0, r0"
|
||||
: "=r" (value) /* Outputs */
|
||||
: "r" (reason), "r" (arg), "i" (AngelSWI) /* Inputs */
|
||||
: "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"
|
||||
/* Clobbers r0 and r1, and lr if in supervisor mode */);
|
||||
/* Accordingly to page 13-77 of ARM DUI 0040D other registers
|
||||
can also be clobbered. Some memory positions may also be
|
||||
changed by a system call, so they should not be kept in
|
||||
registers. Note: we are assuming the manual is right and
|
||||
Angel is respecting the APCS. */
|
||||
return value;
|
||||
}
|
||||
#endif /* ARM_RDI_MONITOR */
|
||||
|
||||
/* Function to convert std(in|out|err) handles to internal versions. */
|
||||
static int
|
||||
remap_handle (int fh)
|
||||
{
|
||||
CHECK_INIT(_REENT);
|
||||
|
||||
if (STDIN_FILENO == fh)
|
||||
{
|
||||
return (monitor_stdin);
|
||||
}
|
||||
if (STDOUT_FILENO == fh)
|
||||
{
|
||||
return (monitor_stdout);
|
||||
}
|
||||
if (STDERR_FILENO == fh)
|
||||
{
|
||||
return (monitor_stderr);
|
||||
}
|
||||
|
||||
return (fh - FILE_HANDLE_OFFSET);
|
||||
}
|
||||
|
||||
void
|
||||
initialise_monitor_handles (void)
|
||||
{
|
||||
int i;
|
||||
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
int volatile block[3];
|
||||
|
||||
block[0] = (int) ":tt";
|
||||
block[2] = 3; /* length of filename */
|
||||
block[1] = 0; /* mode "r" */
|
||||
monitor_stdin = do_AngelSWI (AngelSWI_Reason_Open, (void *) block);
|
||||
|
||||
block[0] = (int) ":tt";
|
||||
block[2] = 3; /* length of filename */
|
||||
block[1] = 4; /* mode "w" */
|
||||
monitor_stdout = monitor_stderr = do_AngelSWI (AngelSWI_Reason_Open, (void *) block);
|
||||
#else
|
||||
int fh;
|
||||
const char * pname;
|
||||
|
||||
pname = ":tt";
|
||||
__asm ("mov r0,%2; mov r1, #0; swi %a1; mov %0, r0"
|
||||
: "=r"(fh)
|
||||
: "i" (SWI_Open),"r"(pname)
|
||||
: "r0","r1");
|
||||
monitor_stdin = fh;
|
||||
|
||||
pname = ":tt";
|
||||
__asm ("mov r0,%2; mov r1, #4; swi %a1; mov %0, r0"
|
||||
: "=r"(fh)
|
||||
: "i" (SWI_Open),"r"(pname)
|
||||
: "r0","r1");
|
||||
monitor_stdout = (monitor_stderr = fh);
|
||||
#endif
|
||||
|
||||
for (i = 0; i < MAX_OPEN_FILES; i ++)
|
||||
{
|
||||
openfiles[i].handle = (-1);
|
||||
}
|
||||
|
||||
openfiles[0].handle = monitor_stdin;
|
||||
openfiles[0].pos = 0;
|
||||
openfiles[1].handle = monitor_stdout;
|
||||
openfiles[1].pos = 0;
|
||||
}
|
||||
|
||||
static int
|
||||
get_errno (void)
|
||||
{
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
return do_AngelSWI (AngelSWI_Reason_Errno, NULL);
|
||||
#else
|
||||
__asm ("swi %a0" :: "i" (SWI_GetErrno));
|
||||
return (0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static int
|
||||
error (int result)
|
||||
{
|
||||
errno = get_errno ();
|
||||
return (result);
|
||||
}
|
||||
|
||||
static int
|
||||
wrap (int result)
|
||||
{
|
||||
if ((-1) == result)
|
||||
{
|
||||
return (error(-1));
|
||||
}
|
||||
return (result);
|
||||
}
|
||||
|
||||
/* Returns # chars not! written. */
|
||||
int
|
||||
_swiread (int file,
|
||||
char * ptr,
|
||||
int len)
|
||||
{
|
||||
int fh = remap_handle (file);
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
int block[3];
|
||||
|
||||
block[0] = fh;
|
||||
block[1] = (int) ptr;
|
||||
block[2] = len;
|
||||
|
||||
return do_AngelSWI (AngelSWI_Reason_Read, block);
|
||||
#else
|
||||
__asm ("mov r0, %1; mov r1, %2;mov r2, %3; swi %a0"
|
||||
: /* No outputs */
|
||||
: "i"(SWI_Read), "r"(fh), "r"(ptr), "r"(len)
|
||||
: "r0","r1","r2");
|
||||
return (0);
|
||||
#endif
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function Name: _read
|
||||
* Description : GNU interface to low-level I/O read
|
||||
* Arguments : int file_no
|
||||
* : const char *buffer
|
||||
* : unsigned int n
|
||||
* Return Value : none
|
||||
******************************************************************************/
|
||||
int _read(int file_no , char *buffer , unsigned int n)
|
||||
{
|
||||
return (sio_read(file_no , buffer , n));
|
||||
}
|
||||
|
||||
int
|
||||
_swilseek (int file,
|
||||
int ptr,
|
||||
int dir)
|
||||
{
|
||||
int res;
|
||||
int fh = remap_handle (file);
|
||||
int slot = findslot (fh);
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
int block[2];
|
||||
#endif
|
||||
|
||||
if (SEEK_CUR == dir)
|
||||
{
|
||||
if (MAX_OPEN_FILES == slot)
|
||||
{
|
||||
return (-1);
|
||||
}
|
||||
ptr = (openfiles[slot].pos + ptr);
|
||||
dir = SEEK_SET;
|
||||
}
|
||||
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
if (dir == SEEK_END)
|
||||
{
|
||||
block[0] = fh;
|
||||
ptr += do_AngelSWI (AngelSWI_Reason_FLen, block);
|
||||
}
|
||||
|
||||
/* This code only does absolute seeks. */
|
||||
block[0] = remap_handle (file);
|
||||
block[1] = ptr;
|
||||
res = do_AngelSWI (AngelSWI_Reason_Seek, block);
|
||||
#else
|
||||
if (SEEK_END == dir)
|
||||
{
|
||||
__asm ("mov r0, %2; swi %a1; mov %0, r0"
|
||||
: "=r" (res)
|
||||
: "i" (SWI_Flen), "r" (fh)
|
||||
: "r0");
|
||||
ptr += res;
|
||||
}
|
||||
|
||||
/* This code only does absolute seeks. */
|
||||
__asm ("mov r0, %2; mov r1, %3; swi %a1; mov %0, r0"
|
||||
: "=r" (res)
|
||||
: "i" (SWI_Seek), "r" (fh), "r" (ptr)
|
||||
: "r0", "r1");
|
||||
#endif
|
||||
|
||||
if ((MAX_OPEN_FILES != slot) && (0 == res))
|
||||
{
|
||||
openfiles[slot].pos = ptr;
|
||||
}
|
||||
|
||||
/* This is expected to return the position in the file. */
|
||||
return ((0 == res) ? ptr : (-1));
|
||||
}
|
||||
|
||||
int
|
||||
_lseek (int file,
|
||||
int ptr,
|
||||
int dir)
|
||||
{
|
||||
return (wrap (_swilseek (file, ptr, dir)));
|
||||
}
|
||||
|
||||
/* Returns #chars not! written. */
|
||||
int
|
||||
_swiwrite (
|
||||
int file,
|
||||
char * ptr,
|
||||
int len)
|
||||
{
|
||||
int fh = remap_handle (file);
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
int block[3];
|
||||
|
||||
block[0] = fh;
|
||||
block[1] = (int) ptr;
|
||||
block[2] = len;
|
||||
|
||||
return do_AngelSWI (AngelSWI_Reason_Write, block);
|
||||
#else
|
||||
__asm ("mov r0, %1; mov r1, %2;mov r2, %3; swi %a0"
|
||||
: /* No outputs */
|
||||
: "i"(SWI_Write), "r"(fh), "r"(ptr), "r"(len)
|
||||
: "r0","r1","r2");
|
||||
return (0);
|
||||
#endif
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function Name: _write
|
||||
* Description : GNU interface to low-level I/O write
|
||||
* Arguments : int file_no
|
||||
* : const char *buffer
|
||||
* : unsigned int n
|
||||
* Return Value : none
|
||||
******************************************************************************/
|
||||
int _write(int file_no , const char *buffer , unsigned int n)
|
||||
{
|
||||
return (sio_write(file_no , buffer , n));
|
||||
}
|
||||
|
||||
int
|
||||
_swiopen (const char * path,
|
||||
int flags)
|
||||
{
|
||||
int aflags = 0, fh;
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
int block[3];
|
||||
#endif
|
||||
|
||||
int i = findslot (-1);
|
||||
|
||||
if (MAX_OPEN_FILES == i)
|
||||
{
|
||||
return (-1);
|
||||
}
|
||||
|
||||
/* The flags are Unix-style, so we need to convert them. */
|
||||
#ifdef O_BINARY
|
||||
if (flags & O_BINARY)
|
||||
{
|
||||
aflags |= 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (flags & O_RDWR)
|
||||
{
|
||||
aflags |= 2;
|
||||
}
|
||||
|
||||
if (flags & O_CREAT)
|
||||
{
|
||||
aflags |= 4;
|
||||
}
|
||||
|
||||
if (flags & O_TRUNC)
|
||||
{
|
||||
aflags |= 4;
|
||||
}
|
||||
|
||||
if (flags & O_APPEND)
|
||||
{
|
||||
aflags &= (~4); /* Can't ask for w AND a; means just 'a'. */
|
||||
aflags |= 8;
|
||||
}
|
||||
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
block[0] = (int) path;
|
||||
block[2] = strlen (path);
|
||||
block[1] = aflags;
|
||||
|
||||
fh = do_AngelSWI (AngelSWI_Reason_Open, block);
|
||||
|
||||
#else
|
||||
__asm ("mov r0,%2; mov r1, %3; swi %a1; mov %0, r0"
|
||||
: "=r"(fh)
|
||||
: "i" (SWI_Open),"r"(path),"r"(aflags)
|
||||
: "r0","r1");
|
||||
#endif
|
||||
|
||||
if (fh >= 0)
|
||||
{
|
||||
openfiles[i].handle = fh;
|
||||
openfiles[i].pos = 0;
|
||||
}
|
||||
|
||||
return ((fh >= 0) ? (fh + FILE_HANDLE_OFFSET) : error (fh));
|
||||
}
|
||||
|
||||
int
|
||||
_open (const char * path,
|
||||
int flags,
|
||||
...)
|
||||
{
|
||||
return (wrap (_swiopen (path, flags)));
|
||||
}
|
||||
|
||||
int
|
||||
_swiclose (int file)
|
||||
{
|
||||
int myhan = remap_handle (file);
|
||||
int slot = findslot (myhan);
|
||||
|
||||
if (MAX_OPEN_FILES != slot)
|
||||
{
|
||||
openfiles[slot].handle = (-1);
|
||||
}
|
||||
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
return do_AngelSWI (AngelSWI_Reason_Close, & myhan);
|
||||
#else
|
||||
__asm ("mov r0, %1; swi %a0" :: "i" (SWI_Close),"r"(myhan):"r0");
|
||||
return (0);
|
||||
#endif
|
||||
}
|
||||
|
||||
int
|
||||
_close (int file)
|
||||
{
|
||||
return (wrap (_swiclose (file)));
|
||||
}
|
||||
|
||||
int
|
||||
_kill (int pid, int sig)
|
||||
{
|
||||
(void)pid; (void)sig;
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
/* Note: The pid argument is thrown away. */
|
||||
switch (sig) {
|
||||
case SIGABRT:
|
||||
return do_AngelSWI (AngelSWI_Reason_ReportException,
|
||||
(void *) ADP_Stopped_RunTimeError);
|
||||
default:
|
||||
return do_AngelSWI (AngelSWI_Reason_ReportException,
|
||||
(void *) ADP_Stopped_ApplicationExit);
|
||||
}
|
||||
#else
|
||||
__asm ("swi %a0" :: "i" (SWI_Exit));
|
||||
return (0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
_exit (int status)
|
||||
{
|
||||
/* There is only one SWI for both _exit and _kill. For _exit, call
|
||||
the SWI with the second argument set to -1, an invalid value for
|
||||
signum, so that the SWI handler can distinguish the two calls.
|
||||
Note: The RDI implementation of _kill throws away both its
|
||||
arguments. */
|
||||
_kill(status, -1);
|
||||
while(1)
|
||||
{
|
||||
/* exit occurred */
|
||||
};
|
||||
}
|
||||
|
||||
int
|
||||
_getpid (int n)
|
||||
{
|
||||
(void)(n);
|
||||
return (1);
|
||||
}
|
||||
|
||||
caddr_t
|
||||
_sbrk (int incr)
|
||||
{
|
||||
extern char end __asm ("end"); /* Defined by the linker. */
|
||||
static char * pheap_end;
|
||||
char * prev_heap_end;
|
||||
|
||||
if (NULL == pheap_end)
|
||||
{
|
||||
pheap_end = (&end);
|
||||
}
|
||||
|
||||
prev_heap_end = pheap_end;
|
||||
|
||||
if ((pheap_end + incr) > stack_ptr)
|
||||
{
|
||||
/* Some of the libstdc++-v3 tests rely upon detecting
|
||||
out of memory errors, so do not abort here. */
|
||||
#if 0
|
||||
extern void abort (void);
|
||||
|
||||
_write (1, "_sbrk: Heap and stack collision\n", 32);
|
||||
|
||||
abort ();
|
||||
#else
|
||||
errno = ENOMEM;
|
||||
return ((caddr_t) (-1));
|
||||
#endif
|
||||
}
|
||||
|
||||
pheap_end += incr;
|
||||
|
||||
return ((caddr_t) prev_heap_end);
|
||||
}
|
||||
|
||||
int
|
||||
_fstat (int file, struct stat * st)
|
||||
{
|
||||
(void)file;
|
||||
memset (st, 0, sizeof (* st));
|
||||
st->st_mode = S_IFCHR;
|
||||
st->st_blksize = 1024;
|
||||
return (0);
|
||||
}
|
||||
|
||||
int _stat (const char *fname, struct stat *st)
|
||||
{
|
||||
int file;
|
||||
|
||||
/* The best we can do is try to open the file read-only. If it exists,
|
||||
then we can guess a few things about it. */
|
||||
if ((file = _open (fname, O_RDONLY)) < 0)
|
||||
{
|
||||
return (-1);
|
||||
}
|
||||
|
||||
memset (st, 0, sizeof (* st));
|
||||
st->st_mode = (S_IFREG | S_IREAD);
|
||||
st->st_blksize = 1024;
|
||||
_swiclose (file); /* Not interested in the error. */
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
_link (void)
|
||||
{
|
||||
return (-1);
|
||||
}
|
||||
|
||||
int
|
||||
_unlink (const char *path)
|
||||
{
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
int block[2];
|
||||
block[0] = path;
|
||||
block[1] = strlen(path);
|
||||
return wrap (do_AngelSWI (AngelSWI_Reason_Remove, block)) ? -1 : 0;
|
||||
#else
|
||||
return -1;
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
_raise (void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
int
|
||||
_gettimeofday (struct timeval * tp, void * tzvp)
|
||||
{
|
||||
struct timezone * ptzp = tzvp;
|
||||
if (tp)
|
||||
{
|
||||
/* Ask the host for the seconds since the Unix epoch. */
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
tp->tv_sec = do_AngelSWI (AngelSWI_Reason_Time,NULL);
|
||||
#else
|
||||
{
|
||||
int value;
|
||||
__asm ("swi %a1; mov %0, r0" : "=r" (value): "i" (SWI_Time) : "r0");
|
||||
tp->tv_sec = value;
|
||||
}
|
||||
#endif
|
||||
tp->tv_usec = 0;
|
||||
}
|
||||
|
||||
/* Return fixed data for the time-zone. */
|
||||
if (ptzp)
|
||||
{
|
||||
ptzp->tz_minuteswest = 0;
|
||||
ptzp->tz_dsttime = 0;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* Return a clock that ticks at 100Hz. */
|
||||
clock_t
|
||||
_times (struct tms * tp)
|
||||
{
|
||||
clock_t timeval;
|
||||
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
timeval = do_AngelSWI (AngelSWI_Reason_Clock,NULL);
|
||||
#else
|
||||
__asm ("swi %a1; mov %0, r0" : "=r" (timeval): "i" (SWI_Clock) : "r0");
|
||||
#endif
|
||||
|
||||
if (tp)
|
||||
{
|
||||
tp->tms_utime = timeval; /* user time */
|
||||
tp->tms_stime = 0; /* system time */
|
||||
tp->tms_cutime = 0; /* user time, children */
|
||||
tp->tms_cstime = 0; /* system time, children */
|
||||
}
|
||||
|
||||
return (timeval);
|
||||
};
|
||||
|
||||
|
||||
int
|
||||
_isatty (int fd)
|
||||
{
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
int fh = remap_handle (fd);
|
||||
return wrap (do_AngelSWI (AngelSWI_Reason_IsTTY, &fh));
|
||||
#else
|
||||
return ((fd <= 2) ? 1 : 0); /* one of stdin, stdout, stderr */
|
||||
#endif
|
||||
}
|
||||
|
||||
int
|
||||
_system (const char *s)
|
||||
{
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
int block[2];
|
||||
int e;
|
||||
|
||||
/* Hmmm. The ARM debug interface specification doesn't say whether
|
||||
SYS_SYSTEM does the right thing with a null argument, or assign any
|
||||
meaning to its return value. Try to do something reasonable.... */
|
||||
if (!s)
|
||||
return 1; /* maybe there is a shell available? we can hope. :-P */
|
||||
block[0] = s;
|
||||
block[1] = strlen (s);
|
||||
e = wrap (do_AngelSWI (AngelSWI_Reason_System, block));
|
||||
if ((e >= 0) && (e < 256))
|
||||
{
|
||||
/* We have to convert e, an exit status to the encoded status of
|
||||
the command. To avoid hard coding the exit status, we simply
|
||||
loop until we find the right position. */
|
||||
int exit_code;
|
||||
|
||||
for (exit_code = e; e && WEXITSTATUS (e) != exit_code; e <<= 1)
|
||||
continue;
|
||||
}
|
||||
return e;
|
||||
#else
|
||||
if (NULL == s)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
errno = ENOSYS;
|
||||
return (-1);
|
||||
#endif
|
||||
}
|
||||
|
||||
int
|
||||
_rename (const char * oldpath, const char * newpath)
|
||||
{
|
||||
#ifdef ARM_RDI_MONITOR
|
||||
int block[4];
|
||||
block[0] = oldpath;
|
||||
block[1] = strlen(oldpath);
|
||||
block[2] = newpath;
|
||||
block[3] = strlen(newpath);
|
||||
return wrap (do_AngelSWI (AngelSWI_Reason_Rename, block)) ? -1 : 0;
|
||||
#else
|
||||
errno = ENOSYS;
|
||||
return (-1);
|
||||
#endif
|
||||
}
|
||||
111
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/r_atcm_init.c
Normal file
111
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/r_atcm_init.c
Normal file
@ -0,0 +1,111 @@
|
||||
/*******************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_atcm_init.c
|
||||
* Version : 0.1
|
||||
* Device : R7S910018
|
||||
* Abstract : API for ATCM function
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : ATCM access wait setting API of RZ/T1
|
||||
* Limitation : This wait setting could not be executed in ATCM program area.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00 First Release
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
***********************************************************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "iodefine.h"
|
||||
#include "r_system.h"
|
||||
#include "r_atcm_init.h"
|
||||
#include "r_typedefs.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#define ATCM_WRITE_ENABLE (0x0000A508)
|
||||
#define ATCM_WRITE_DISABLE (0x0000A500)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Private variables and functions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : R_ATCM_WaitSet
|
||||
* Description : Sets ATCM access wait.
|
||||
* Arguments : atcm_wait
|
||||
* Wait settings for ATCM access
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void R_ATCM_WaitSet(uint32_t atcm_wait)
|
||||
{
|
||||
volatile uint32_t dummy;
|
||||
|
||||
UNUSED_VARIABLE(dummy);
|
||||
|
||||
/* Enables writing to the ATCM register */
|
||||
SYSTEM.PRCR.LONG = ATCM_WRITE_ENABLE;
|
||||
dummy = SYSTEM.PRCR.LONG;
|
||||
|
||||
/* Sets ATCM access wait to atcm_wait value */
|
||||
SYSTEM.SYTATCMWAIT.LONG = atcm_wait;
|
||||
|
||||
/* Disables writing to the ATCM register */
|
||||
SYSTEM.PRCR.LONG = ATCM_WRITE_DISABLE;
|
||||
dummy = SYSTEM.PRCR.LONG;
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function R_ATCM_WaitSet
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/* End of File */
|
||||
|
||||
|
||||
153
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/r_ram_init.c
Normal file
153
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/r_ram_init.c
Normal file
@ -0,0 +1,153 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_ram_init.c
|
||||
* Version : 0.1
|
||||
* Device : R7S910018
|
||||
* Abstract : API for internal extended RAM function
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : internal extended RAM setting API of RZ/T1
|
||||
* Limitation : none
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00 First Release
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
***********************************************************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "iodefine.h"
|
||||
#include "r_system.h"
|
||||
#include "r_ram_init.h"
|
||||
#include "r_typedefs.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#define RAM_ECC_ENABLE (0x00000001)
|
||||
#define RAM_ECC_DISABLE (0x00000000)
|
||||
#define RAM_PROTECT (0x00000000)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Private variables and functions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : R_RAM_ECCEnable
|
||||
* Description : Enable ECC function for internal extended RAM.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void R_RAM_ECCEnable(void)
|
||||
{
|
||||
/* Enables writing to the protected registers related to RAM function */
|
||||
R_RAM_WriteEnable();
|
||||
|
||||
/* Enable ECC function */
|
||||
ECCRAM.RAMEDC.LONG = RAM_ECC_ENABLE;
|
||||
|
||||
/* Disables writing to the protected registers related to RAM function */
|
||||
R_RAM_WriteDisable();
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function R_RAM_ECCEnable
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : R_RAM_WriteEnable
|
||||
* Description : Enable writing to the protected registers related to RAM.
|
||||
* And dummy read the register in order to fix the register value.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void R_RAM_WriteEnable(void)
|
||||
{
|
||||
volatile uint32_t dummy;
|
||||
|
||||
UNUSED_VARIABLE(dummy);
|
||||
|
||||
/* Special sequence for protect release */
|
||||
ECCRAM.RAMPCMD.LONG = 0x000000A5; // Write fixed value 0x000000A5
|
||||
ECCRAM.RAMPCMD.LONG = 0x00000001; // Write expected value
|
||||
ECCRAM.RAMPCMD.LONG = 0x0000FFFE; // Write inverted value of the expected value
|
||||
ECCRAM.RAMPCMD.LONG = 0x00000001; // Write expected value again
|
||||
dummy = ECCRAM.RAMPCMD.LONG;
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function R_RAM_WriteEnable
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : R_RAM_WriteDisable
|
||||
* Description : Disable writing to the protected registers related to RAM.
|
||||
* And dummy read the register in order to fix the register value.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void R_RAM_WriteDisable(void)
|
||||
{
|
||||
volatile uint32_t dummy;
|
||||
|
||||
UNUSED_VARIABLE(dummy);
|
||||
|
||||
/* Clear RAMPCMD register to zero */
|
||||
ECCRAM.RAMPCMD.LONG = RAM_PROTECT;
|
||||
dummy = ECCRAM.RAMPCMD.LONG;
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function R_RAM_WriteDisable
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/* End of File */
|
||||
|
||||
|
||||
128
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/r_reset.c
Normal file
128
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/r_reset.c
Normal file
@ -0,0 +1,128 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_reset.c
|
||||
* Version : 0.1
|
||||
* Device : R7S910018
|
||||
* Abstract : API for RESET and Low-Power function
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : RESET and Low-Power API of RZ/T1
|
||||
* Limitation : none
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00 First Release
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
***********************************************************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "iodefine.h"
|
||||
#include "r_system.h"
|
||||
#include "r_reset.h"
|
||||
#include "r_typedefs.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#define RST_WRITE_ENABLE (0x0000A502)
|
||||
#define RST_WRITE_DISABLE (0x0000A500)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Private variables and functions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : r_rst_write_enable
|
||||
* Description : Enables writing to the registers related to RESET and Low-
|
||||
* Power function. And dummy read the register in order to fix
|
||||
* the register value.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void r_rst_write_enable(void)
|
||||
{
|
||||
volatile uint32_t dummy;
|
||||
|
||||
UNUSED_VARIABLE(dummy);
|
||||
|
||||
/* Enables writing to the Reset and Low-Power register */
|
||||
SYSTEM.PRCR.LONG = RST_WRITE_ENABLE;
|
||||
dummy = SYSTEM.PRCR.LONG;
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function r_rst_write_enable
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : r_rst_write_disable
|
||||
* Description : Disables writing to the registers related to RESET and Low-
|
||||
* Power function. And dummy read the register in order to fix
|
||||
* the register value.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void r_rst_write_disable(void)
|
||||
{
|
||||
volatile uint32_t dummy;
|
||||
|
||||
UNUSED_VARIABLE(dummy);
|
||||
|
||||
/* Disables writing to the Reset and Low-Power register */
|
||||
SYSTEM.PRCR.LONG = RST_WRITE_DISABLE;
|
||||
dummy = SYSTEM.PRCR.LONG;
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function r_rst_write_disable
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/* End of File */
|
||||
|
||||
|
||||
196
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/siochar.c
Normal file
196
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/siochar.c
Normal file
@ -0,0 +1,196 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* System Name : RZ/T1 SCIF program
|
||||
* File Name : siochar.c
|
||||
* Version : 0.1
|
||||
* Device : R7S910018
|
||||
* Abstract : Serial I/O settings controlling the character
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : Control the character with serial I/O
|
||||
* Limitation : none
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00 First Release
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_userdefine.h"
|
||||
#include "r_cg_scifa.h"
|
||||
#include "siochar.h"
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Private global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: io_init_scifa2
|
||||
* Description : This function initialises SCIFA channel 2 as UART mode.
|
||||
* : The transmit and the receive of SCIFA channel 2 are enabled.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void io_init_scifa2 (void)
|
||||
{
|
||||
/* === Initialisation of SCIFA2 if not already initialised ==== */
|
||||
if (1 == MSTP_SCIFA2)
|
||||
{
|
||||
R_SCIFA2_Create();
|
||||
}
|
||||
|
||||
/* Ensure receive FIFO trigger is set to 1 */
|
||||
SCIFA2.FCR.BIT.RTRG = 0U;
|
||||
|
||||
/* Reception triggered by one data */
|
||||
SCIFA2.FTCR.BIT.RFTC = 1u;
|
||||
|
||||
/* Enable reception and receive interrupts */
|
||||
SCIFA2.SCR.BIT.RE = 1U;
|
||||
SCIFA2.SCR.BIT.RIE = 1U;
|
||||
SCIFA2.SCR.BIT.REIE = 1U;
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function io_init_scifa2
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: io_get_char
|
||||
* Description : One character is received from SCIFA2, and it's data is returned.
|
||||
* : This function keeps waiting until it can obtain the receiving data.
|
||||
* Arguments : none
|
||||
* Return Value : Character to receive (Byte).
|
||||
***********************************************************************************************************************/
|
||||
char io_get_char (void)
|
||||
{
|
||||
char data;
|
||||
|
||||
/* Confirming receive error (ER,BRK,FER,PER) */
|
||||
if (SCIFA2.FSR.WORD & 0x09Cu)
|
||||
{
|
||||
/* ---- Detect receive error ---- */
|
||||
|
||||
/* Disable reception */
|
||||
SCIFA2.SCR.BIT.RE = 0U;
|
||||
|
||||
/* Reset receiving FIFO */
|
||||
SCIFA2.FCR.BIT.RFRST = 1U;
|
||||
|
||||
/* Clearing FIFO reception reset */
|
||||
SCIFA2.FCR.BIT.RFRST = 0U;
|
||||
|
||||
/* Error bit clear */
|
||||
SCIFA2.FSR.BIT.DR = 0U;
|
||||
SCIFA2.FSR.BIT.RDF = 0U;
|
||||
|
||||
/* Enable reception */
|
||||
SCIFA2.SCR.BIT.RE = 1U;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* Is there receive FIFO data? */
|
||||
while (0 == SCIFA2.FSR.BIT.RDF)
|
||||
{
|
||||
/* Wait */
|
||||
}
|
||||
|
||||
/* Read receive data */
|
||||
data = SCIFA2.FRDR;
|
||||
|
||||
/* Clear RDF */
|
||||
SCIFA2.FSR.BIT.RDF = 0U;
|
||||
|
||||
/* Is it overflowed? */
|
||||
if (1 == SCIFA2.LSR.BIT.ORER)
|
||||
{
|
||||
/* ORER clear */
|
||||
SCIFA2.LSR.BIT.ORER = 0U;
|
||||
}
|
||||
|
||||
return (data);
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function io_get_char
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: io_put_char
|
||||
* Description : Character "buffer" is output to SCIFA2.
|
||||
* : This function keeps waiting until it becomes the transmission
|
||||
* : enabled state.
|
||||
* Arguments : char buffer : character to output
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void io_put_char (char buffer)
|
||||
{
|
||||
/* Check if it is possible to transmit (TDFE flag) */
|
||||
while (0 == SCIFA2.FSR.BIT.TDFE)
|
||||
{
|
||||
/* Wait */
|
||||
}
|
||||
|
||||
/* Send the character via the terminal output */
|
||||
R_SCIFA2_Serial_Send((uint8_t *)&buffer, 1);
|
||||
|
||||
/* Clear TEND flag */
|
||||
SCIFA2.FSR.BIT.TEND = 0u;
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* End of function io_put_char
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/* End of File */
|
||||
|
||||
226
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/siorw.c
Normal file
226
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/siorw.c
Normal file
@ -0,0 +1,226 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* System Name : RZ/T1 SCIF program
|
||||
* File Name : siorw.c
|
||||
* Version : 0.1
|
||||
* Device : R7S910018
|
||||
* Abstract : Serial I/O settings controlling the read and write command
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : Control the read/write command with serial I/O
|
||||
* Limitation : none
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00 First Release
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
***********************************************************************************************************************/
|
||||
#include <stdio.h>
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_userdefine.h"
|
||||
#include "r_cg_scifa.h"
|
||||
#include "siochar.h"
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
/* File descriptor */
|
||||
#define STDIN (0)
|
||||
#define STDOUT (1)
|
||||
#define STDERR (2)
|
||||
|
||||
#define SIORW_SUCCESS (0)
|
||||
#define SIORW_ERROR (-1)
|
||||
#define SIORW_FLAG_OFF (0)
|
||||
#define SIORW_FLAG_ON (1)
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Imported global variables and functions (from other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Private global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: sio_write
|
||||
* Description : The character strings specified with buffer is output for n
|
||||
* : bytes from serial port. The output is determined by file number fileno.
|
||||
* : The effective outputs in this version are STDOUT and STDERR, and
|
||||
* : it is output to the same serial port.
|
||||
* : The line-feed code '\n'(LF) is converted in '\r'(CR)+'\n'(LF) to output.
|
||||
* Arguments : int32_t file_no ; I : File number to be the target of writing
|
||||
* : int_t * buffer ; O : Pointer to the area in which writing data is stored
|
||||
* : uint32_t writing_b; I : Writing bytes
|
||||
* Return Value : >=0 : Number of transmitting characters
|
||||
* : -1 : File number error
|
||||
***********************************************************************************************************************/
|
||||
int32_t sio_write (int32_t file_no, const char * buffer, uint32_t writing_b)
|
||||
{
|
||||
uint32_t offset;
|
||||
|
||||
if ((STDOUT == file_no) || (STDERR == file_no))
|
||||
{
|
||||
for (offset = 0; offset < writing_b; offset++)
|
||||
|
||||
{
|
||||
/* Writing in buffer converting line-feed code */
|
||||
if ('\n' == (*(buffer + offset)))
|
||||
{
|
||||
if (0 == offset)
|
||||
{
|
||||
io_put_char('\r');
|
||||
}
|
||||
else
|
||||
{
|
||||
if ('\r' != (*((buffer + offset) - 1)))
|
||||
{
|
||||
io_put_char('\r');
|
||||
}
|
||||
}
|
||||
io_put_char('\n');
|
||||
}
|
||||
else
|
||||
{
|
||||
io_put_char(*(buffer + offset));
|
||||
}
|
||||
}
|
||||
return ((int32_t)offset);
|
||||
}
|
||||
|
||||
/* File number error */
|
||||
return SIORW_ERROR;
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* End of function sio_write
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: sio_read
|
||||
* Description : The character strings specified with buffer is input for
|
||||
* : n bytes from serial port.The input is determined by file number fileno.
|
||||
* : The effective input in this version is STDIN.
|
||||
* Arguments : int32_t file_no ; I : File number to be the target of reading
|
||||
* : int_t * buffer ; O : Pointer to the area in which reading data is stored
|
||||
* : uint32_t reading_b; I : Reading bytes
|
||||
* Return Value : >0 : Number of receiving characters
|
||||
* : -1 : File number, receiving data error
|
||||
***********************************************************************************************************************/
|
||||
int32_t sio_read (int32_t file_no, char * buffer, uint32_t reading_b)
|
||||
{
|
||||
int32_t char_mem;
|
||||
int32_t sp_char;
|
||||
uint32_t offset;
|
||||
static int32_t sjis_flg = SIORW_FLAG_OFF;
|
||||
|
||||
if (STDIN == file_no)
|
||||
{
|
||||
for (offset = 0; offset < reading_b; )
|
||||
{
|
||||
/* Reading receiving data */
|
||||
char_mem = io_get_char();
|
||||
|
||||
/* -1 is returned when it is receiving data error */
|
||||
if ((-1) == char_mem)
|
||||
{
|
||||
return SIORW_ERROR;
|
||||
}
|
||||
|
||||
if (SIORW_FLAG_ON == sjis_flg)
|
||||
{
|
||||
sjis_flg = SIORW_FLAG_OFF;
|
||||
sio_write(STDOUT, (char *)&char_mem, 1);
|
||||
|
||||
(*(buffer + offset)) = (char)char_mem;
|
||||
offset++;
|
||||
}
|
||||
if ((0x20 <= char_mem) && (char_mem <= 0x7E))
|
||||
{
|
||||
/* Data possible to display */
|
||||
sio_write(STDOUT, (char *)&char_mem, 1);
|
||||
(*(buffer + offset)) = (char)char_mem;
|
||||
offset++;
|
||||
}
|
||||
|
||||
/* BS process */
|
||||
if (('\b' == char_mem) && (offset > 0))
|
||||
{ sp_char = 0x20;
|
||||
sio_write(STDOUT, (char *)&char_mem, 1);
|
||||
sio_write(STDOUT, (char *)&sp_char, 1);
|
||||
sio_write(STDOUT, (char *)&char_mem, 1);
|
||||
offset--;
|
||||
}
|
||||
|
||||
/* CR process */
|
||||
if ('\r' == char_mem)
|
||||
{
|
||||
(*(buffer + offset)) = '\n';
|
||||
sio_write(STDOUT, buffer + offset, 1);
|
||||
offset++;
|
||||
}
|
||||
|
||||
/* Japanese SJIS ? */
|
||||
if (((char_mem >= 0x80) && (char_mem < 0xA0)) || ((char_mem >= 0xE0) && (char_mem < 0xFE)))
|
||||
{
|
||||
/* Data possible to display */
|
||||
sio_write(STDOUT, (char *)&char_mem, 1);
|
||||
(*(buffer + offset)) = (char)char_mem;
|
||||
offset++;
|
||||
sjis_flg = SIORW_FLAG_ON;
|
||||
}
|
||||
}
|
||||
return ((int32_t)offset);
|
||||
}
|
||||
|
||||
/* File number error */
|
||||
return SIORW_ERROR;
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function sio_read
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/* End of File */
|
||||
|
||||
49
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/ascii.h
Normal file
49
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/ascii.h
Normal file
@ -0,0 +1,49 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
************************************************************************************************************************/
|
||||
/************************************************************************************************************************
|
||||
* File Name : ascii.h
|
||||
* Device(s) : RZ/T1 (R7S910018)
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* H/W Platform : RSK+RZT1 CPU Board
|
||||
* Description : This Header file contains the Macro Definitions & prototypes
|
||||
* for the functions used in lcd.c
|
||||
************************************************************************************************************************/
|
||||
/************************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.04.2015 1.00
|
||||
************************************************************************************************************************/
|
||||
|
||||
/* Multiple inclusion prevention macro */
|
||||
#ifndef ASCII_H
|
||||
#define ASCII_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro Definitions
|
||||
***********************************************************************************************************************/
|
||||
extern const char g_ascii_table[][6];
|
||||
|
||||
/* ASCII_H */
|
||||
#endif
|
||||
|
||||
|
||||
45398
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/iodefine.h
Normal file
45398
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/iodefine.h
Normal file
File diff suppressed because it is too large
Load Diff
227
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/lcd_pmod.h
Normal file
227
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/lcd_pmod.h
Normal file
@ -0,0 +1,227 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* File Name : lcd_pmod.h
|
||||
* Device(s) : RZ/T1 (R7S910017)
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* H/W Platform : RSK+RZT1 CPU Board
|
||||
*
|
||||
* Description : This Header file contains the Macro Definitions & prototypes
|
||||
* for the functions used in lcd.c
|
||||
*
|
||||
* This function is created to drive the Okaya LCD display with
|
||||
* either ST7735 or ST7715 driver device. The commands for both
|
||||
* the devices are the same.
|
||||
*
|
||||
* The display is controlled using the SPI bus. In this example,
|
||||
* the SCI5 is used. This can be modified to the SCI connected to
|
||||
* the PMOD interface. The SCI driver file will also be required.
|
||||
*
|
||||
* The display memory has an offset with respect to the actual
|
||||
* pixel. This is not documented but realised from driving the
|
||||
* display. The offset is set as LEFT MARGIN and TOP MARGIN.
|
||||
* This offset is catered for internally, so as far as the user
|
||||
* is concerned, cursor position 0,0 is the top left pixel.
|
||||
*
|
||||
* The simplest procedure to run the display is as follows:
|
||||
* Init_LCD(); Initialise the serial port and set up the display.
|
||||
*
|
||||
* Clear the display.
|
||||
* The font colour is set to white and background colour to black.
|
||||
*
|
||||
* DisplaySetFontColour(COL_YELLOW);
|
||||
* set the font colour to desired colour
|
||||
* DisplaySetBackColour(COL_BLUE);
|
||||
* set the background colour to desired value
|
||||
* DisplayCenter(1,"Renesas");
|
||||
* write a title on line 1 of the display.
|
||||
*
|
||||
* Note: Line 0 is the top line.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.04.2015 1.00
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
User Includes (Project Level Includes)
|
||||
***********************************************************************************************************************/
|
||||
/* Defines standard variable types used in this file */
|
||||
#include <stdint.h>
|
||||
#include "iodefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro Definitions
|
||||
***********************************************************************************************************************/
|
||||
/* Multiple inclusion prevention macro */
|
||||
#ifndef LCD_PMOD_H
|
||||
#define LCD_PMOD_H
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro Definitions for Okaya display on PMOD connector
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* SCREEN
|
||||
*
|
||||
* The screen size is 128 x 128 pixels, with coordinate 0,0 at the top left.
|
||||
* The display controller is ST7735 or ST7715.
|
||||
*
|
||||
***********************************************************************************************************************/
|
||||
/* 16 lines @ 8 bits = 128. */
|
||||
#define SCREEN_HEIGHT (128)
|
||||
#define SCREEN_WIDTH (128)
|
||||
|
||||
#ifndef USE_PMOD2
|
||||
/* DATA/COMMAND select pin */
|
||||
#define DATA_CMD_PIN (PORT7.PODR.BIT.B6)
|
||||
/* Backlight enable pin */
|
||||
#define BL_ENABLE_PIN (PORT7.PODR.BIT.B4)
|
||||
/* Reset pin */
|
||||
#define RESET_PIN (PORT6.PODR.BIT.B7)
|
||||
#else
|
||||
/* DATA/COMMAND select pin */
|
||||
#define DATA_CMD_PIN (PORTM.PODR.BIT.B2)
|
||||
/* Backlight enable pin */
|
||||
#define BL_ENABLE_PIN (PORTM.PODR.BIT.B3)
|
||||
/* Reset pin */
|
||||
#define RESET_PIN (PORT5.PODR.BIT.B1)
|
||||
#endif
|
||||
|
||||
/* Automatic calculation of parameters */
|
||||
|
||||
/* including a space */
|
||||
#define FONT_WIDTH (6u)
|
||||
/* including 1 pixel space */
|
||||
#define FONT_HEIGHT (8u)
|
||||
#define MAX_LINES (SCREEN_HEIGHT / FONT_HEIGHT)
|
||||
#define CHAR_PER_LINE (SCREEN_WIDTH / FONT_WIDTH)
|
||||
|
||||
/* Allow 2 pixel margin on the left and the top */
|
||||
#define LEFT_MARGIN (2u)
|
||||
#define TOP_MARGIN (3u)
|
||||
#define CR (0x0d)
|
||||
#define LF (0x0a)
|
||||
#define BS (0x08)
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* DISPLAY COLOUR DEFINITIONS (16 bits) R5G6B5 format
|
||||
*
|
||||
* Only Primary & secondary colours are defined here. Other colours can be
|
||||
* created using RGB values.
|
||||
***********************************************************************************************************************/
|
||||
#define COL_BLACK (0x0000)
|
||||
#define COL_RED (0xF800)
|
||||
#define COL_GREEN (0x07E0)
|
||||
#define COL_BLUE (0x001F)
|
||||
#define COL_YELLOW (0xFFE0)
|
||||
#define COL_CYAN (0x07FF)
|
||||
#define COL_MAGENTA (0xF81F)
|
||||
#define COL_WHITE (0xFFFF)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
|
||||
DISPLAY COMMAND SET ST7735
|
||||
|
||||
***********************************************************************************************************************/
|
||||
#define ST7735_NOP (0x0)
|
||||
#define ST7735_SWRESET (0x01)
|
||||
#define ST7735_SLPIN (0x10)
|
||||
#define ST7735_SLPOUT (0x11)
|
||||
#define ST7735_PTLON (0x12)
|
||||
#define ST7735_NORON (0x13)
|
||||
#define ST7735_INVOFF (0x20)
|
||||
#define ST7735_INVON (0x21)
|
||||
#define ST7735_DISPOFF (0x28)
|
||||
#define ST7735_DISPON (0x29)
|
||||
#define ST7735_CASET (0x2A)
|
||||
#define ST7735_RASET (0x2B)
|
||||
#define ST7735_RAMWR (0x2C)
|
||||
#define ST7735_COLMOD (0x3A)
|
||||
#define ST7735_MADCTL (0x36)
|
||||
#define ST7735_FRMCTR1 (0xB1)
|
||||
#define ST7735_INVCTR (0xB4)
|
||||
#define ST7735_DISSET5 (0xB6)
|
||||
#define ST7735_PWCTR1 (0xC0)
|
||||
#define ST7735_PWCTR2 (0xC1)
|
||||
#define ST7735_PWCTR3 (0xC2)
|
||||
#define ST7735_VMCTR1 (0xC5)
|
||||
#define ST7735_PWCTR6 (0xFC)
|
||||
#define ST7735_GMCTRP1 (0xE0)
|
||||
#define ST7735_GMCTRN1 (0xE1)
|
||||
|
||||
/* delay for delay counter */
|
||||
#define DELAY_TIMING (0x08)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Prototypes
|
||||
***********************************************************************************************************************/
|
||||
/* Initialises the debug LCD */
|
||||
void lcd_init (void);
|
||||
|
||||
/* Display string at specific line of display */
|
||||
void display_lcd (uint8_t const line, uint8_t const column, uint8_t const * string);
|
||||
|
||||
/* Display the string at current cursor position */
|
||||
void display_str (uint8_t const * str);
|
||||
|
||||
/* Display the sting at the centre of the specified line */
|
||||
void display_center (uint8_t const line_num, uint8_t * const str);
|
||||
|
||||
/* Clears the display */
|
||||
void clear_display (uint16_t colour);
|
||||
|
||||
/* Clear a specified line */
|
||||
void display_clear_line(uint8_t line_num);
|
||||
|
||||
/* Set the current cursor position */
|
||||
void display_set_cursor (uint8_t const x, uint8_t const y);
|
||||
|
||||
/* Delay function */
|
||||
void display_delay_us (uint32_t time_us);
|
||||
void display_delay_ms (uint32_t time_ms);
|
||||
|
||||
/* Set Font colour */
|
||||
void display_set_font_colour (uint16_t const col);
|
||||
|
||||
/* Set Background colour */
|
||||
void display_set_back_colour (uint16_t const col);
|
||||
|
||||
/* Simple image blit */
|
||||
void display_image (uint8_t *image, uint8_t image_width,
|
||||
uint8_t image_height, uint8_t loc_x, uint8_t loc_y);
|
||||
|
||||
/* Enable display */
|
||||
void display_on (void);
|
||||
|
||||
/* Disable display */
|
||||
void display_off (void);
|
||||
|
||||
|
||||
/* LCD_PMOD_H */
|
||||
#endif
|
||||
|
||||
44
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/logo_data.h
Normal file
44
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/logo_data.h
Normal file
@ -0,0 +1,44 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/******************************************************************************
|
||||
* File Name : logo_data.h
|
||||
* Device(s) : RZ/A1H (R7S910018)
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* H/W Platform : RSK+T1 CPU Board
|
||||
* Description : Renesas Logo 128*24 pixels
|
||||
******************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.10.2014 1.00
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/* Multiple inclusion prevention macro */
|
||||
#ifndef LOGO_DATA_H
|
||||
#define LOGO_DATA_H
|
||||
|
||||
/* Declare the image data section */
|
||||
extern const uint8_t g_rgb888_logo[];
|
||||
|
||||
/* LOGO_DATA_H */
|
||||
#endif
|
||||
64
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_atcm_init.h
Normal file
64
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_atcm_init.h
Normal file
@ -0,0 +1,64 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_atcm.h
|
||||
* Version : 0.1
|
||||
* Device : R7S910018
|
||||
* Abstract : API for ATCM function
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : ATCM access wait setting API of RZ/T1
|
||||
* Limitation : none
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00 First Release
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#ifndef _R_ATCM_HEADER_
|
||||
#define _R_ATCM_HEADER_
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#define ATCM_WAIT_1_OPT (0)
|
||||
#define ATCM_WAIT_1 (1)
|
||||
#define ATCM_WAIT_0 (2)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
***********************************************************************************************************************/
|
||||
void R_ATCM_WaitSet(uint32_t atcm_wait);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
186
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_bsc.h
Normal file
186
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_bsc.h
Normal file
@ -0,0 +1,186 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_bsc.h
|
||||
* Version : 0.1
|
||||
* Device : R7S910018
|
||||
* Abstract : Definitions for BSC functions
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : BSC setting API of RZ/T1
|
||||
* Limitation : none
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00 First Release
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#ifndef _R_BSC_HEADER_
|
||||
#define _R_BSC_HEADER_
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#define BSC_IDLE_CYCLE_0 (0)
|
||||
#define BSC_IDLE_CYCLE_1 (1)
|
||||
#define BSC_IDLE_CYCLE_2 (2)
|
||||
#define BSC_IDLE_CYCLE_4 (3)
|
||||
#define BSC_IDLE_CYCLE_6 (4)
|
||||
#define BSC_IDLE_CYCLE_8 (5)
|
||||
#define BSC_IDLE_CYCLE_10 (6)
|
||||
#define BSC_IDLE_CYCLE_12 (7)
|
||||
|
||||
#define BSC_TYPE_NORMAL (0)
|
||||
#define BSC_TYPE_BURST_ROM_ASYNC (1)
|
||||
#define BSC_TYPE_MPX_IO (2)
|
||||
#define BSC_TYPE_SRAM_BYTE (3)
|
||||
#define BSC_TYPE_SDRAM (4)
|
||||
#define BSC_TYPE_BURST_ROM_SYNC (7)
|
||||
|
||||
#define BSC_WIDTH_8_BIT (1)
|
||||
#define BSC_WIDTH_16_BIT (2)
|
||||
#define BSC_WIDTH_32_BIT (3)
|
||||
|
||||
#define BSC_DELAY_STATE_CYCLE_0_5 (0)
|
||||
#define BSC_DELAY_STATE_CYCLE_1_5 (1)
|
||||
#define BSC_DELAY_STATE_CYCLE_2_5 (2)
|
||||
#define BSC_DELAY_STATE_CYCLE_3_5 (3)
|
||||
|
||||
#define BSC_EXT_WAIT_VALID (0)
|
||||
#define BSC_EXT_WAIT_IGNORED (1)
|
||||
|
||||
#define BSC_ACCESS_WAIT_0 (0)
|
||||
#define BSC_ACCESS_WAIT_1 (1)
|
||||
#define BSC_ACCESS_WAIT_2 (2)
|
||||
#define BSC_ACCESS_WAIT_3 (3)
|
||||
#define BSC_ACCESS_WAIT_4 (4)
|
||||
#define BSC_ACCESS_WAIT_5 (5)
|
||||
#define BSC_ACCESS_WAIT_6 (6)
|
||||
#define BSC_ACCESS_WAIT_8 (7)
|
||||
#define BSC_ACCESS_WAIT_10 (8)
|
||||
#define BSC_ACCESS_WAIT_12 (9)
|
||||
#define BSC_ACCESS_WAIT_14 (10)
|
||||
#define BSC_ACCESS_WAIT_18 (11)
|
||||
#define BSC_ACCESS_WAIT_24 (12)
|
||||
|
||||
#define BSC_WRITE_ACCESS_WAIT_SAME (0)
|
||||
#define BSC_WRITE_ACCESS_WAIT_0 (1)
|
||||
#define BSC_WRITE_ACCESS_WAIT_1 (2)
|
||||
#define BSC_WRITE_ACCESS_WAIT_2 (3)
|
||||
#define BSC_WRITE_ACCESS_WAIT_3 (4)
|
||||
#define BSC_WRITE_ACCESS_WAIT_4 (5)
|
||||
#define BSC_WRITE_ACCESS_WAIT_5 (6)
|
||||
#define BSC_WRITE_ACCESS_WAIT_6 (7)
|
||||
|
||||
#define BSC_BYTE_ENABLE_RD_WR (0)
|
||||
#define BSC_BYTE_ENABLE_WE (1)
|
||||
|
||||
#define BSC_CAS_LATENCY_1 (0)
|
||||
#define BSC_CAS_LATENCY_2 (1)
|
||||
#define BSC_CAS_LATENCY_3 (2)
|
||||
#define BSC_CAS_LATENCY_4 (3)
|
||||
|
||||
#define BSC_WTRC_IDLE_2 (0)
|
||||
#define BSC_WTRC_IDLE_3 (1)
|
||||
#define BSC_WTRC_IDLE_5 (2)
|
||||
#define BSC_WTRC_IDLE_8 (3)
|
||||
|
||||
#define BSC_TRWL_CYCLE_0 (0)
|
||||
#define BSC_TRWL_CYCLE_1 (1)
|
||||
#define BSC_TRWL_CYCLE_2 (2)
|
||||
#define BSC_TRWL_CYCLE_3 (3)
|
||||
|
||||
#define BSC_PRECHARGE_0 (0x00000000)
|
||||
#define BSC_PRECHARGE_1 (0x00000008)
|
||||
#define BSC_PRECHARGE_2 (0x00000010)
|
||||
#define BSC_PRECHARGE_3 (0x00000018)
|
||||
|
||||
#define BSC_WTRCD_WAIT_0 (0)
|
||||
#define BSC_WTRCD_WAIT_1 (1)
|
||||
#define BSC_WTRCD_WAIT_2 (2)
|
||||
#define BSC_WTRCD_WAIT_3 (3)
|
||||
|
||||
#define BSC_WTRP_WAIT_0 (0)
|
||||
#define BSC_WTRP_WAIT_1 (1)
|
||||
#define BSC_WTRP_WAIT_2 (2)
|
||||
#define BSC_WTRP_WAIT_3 (3)
|
||||
|
||||
#define BSC_ROW_11_BIT (0)
|
||||
#define BSC_ROW_12_BIT (1)
|
||||
#define BSC_ROW_13_BIT (2)
|
||||
|
||||
#define BSC_COL_8_BIT (0)
|
||||
#define BSC_COL_9_BIT (1)
|
||||
#define BSC_COL_10_BIT (2)
|
||||
|
||||
#define BSC_BACTV_AUTO (0)
|
||||
#define BSC_BACTV_BANK (1)
|
||||
|
||||
#define BSC_PDOWN_INVALID (0)
|
||||
#define BSC_PDOWN_VALID (1)
|
||||
|
||||
#define BSC_RMODE_AUTO (0)
|
||||
#define BSC_RMODE_SELF (1)
|
||||
|
||||
#define BSC_RFSH_NONE (0)
|
||||
#define BSC_RFSH_DONE (1)
|
||||
|
||||
#define BSC_DEEP_SELF (0)
|
||||
#define BSC_DEEP_DEEP (1)
|
||||
|
||||
#define BSC_PROTECT_KEY (0xA55A0000)
|
||||
|
||||
#define BSC_RFSH_TIME_1 (0)
|
||||
#define BSC_RFSH_TIME_2 (1)
|
||||
#define BSC_RFSH_TIME_4 (2)
|
||||
#define BSC_RFSH_TIME_6 (3)
|
||||
#define BSC_RFSH_TIME_8 (4)
|
||||
|
||||
#define BSC_CKS_DIV_STOP (0x00000000)
|
||||
#define BSC_CKS_DIV_4 (0x00000008)
|
||||
#define BSC_CKS_DIV_16 (0x00000010)
|
||||
#define BSC_CKS_DIV_64 (0x00000018)
|
||||
#define BSC_CKS_DIV_256 (0x00000020)
|
||||
#define BSC_CKS_DIV_1024 (0x00000028)
|
||||
#define BSC_CKS_DIV_2048 (0x00000030)
|
||||
#define BSC_CKS_DIV_4096 (0x00000038)
|
||||
|
||||
#define BSC_CMIE_DISABLE (0x00000000)
|
||||
#define BSC_CMIE_ENABLE (0x00000040)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
64
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_ram_init.h
Normal file
64
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_ram_init.h
Normal file
@ -0,0 +1,64 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_ram.h
|
||||
* Version : 0.1
|
||||
* Device : R7S910018
|
||||
* Abstract : API for internal extended RAM function
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : Internal extended RAM setting API of RZ/T1
|
||||
* Limitation : none
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00 First Release
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#ifndef _R_RAM_HEADER_
|
||||
#define _R_RAM_HEADER_
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
***********************************************************************************************************************/
|
||||
void R_RAM_Init(void);
|
||||
void R_RAM_ECCEnable(void);
|
||||
void R_RAM_WriteEnable(void);
|
||||
void R_RAM_WriteDisable(void);
|
||||
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
62
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_reset.h
Normal file
62
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_reset.h
Normal file
@ -0,0 +1,62 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_reset.h
|
||||
* Version : 0.1
|
||||
* Device : R7S910018
|
||||
* Abstract : API for reset function
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : Reset function API of RZ/T1
|
||||
* Limitation : none
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00 First Release
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#ifndef _R_RESET_HEADER_
|
||||
#define _R_RESET_HEADER_
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#define RST_SOURCE_RES (0x00000002)
|
||||
#define RST_SOURCE_ECM (0x00000004)
|
||||
#define RST_SOURCE_SWR1 (0x00000008)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/* RESET and Low-Power function registers access control */
|
||||
void r_rst_write_enable(void);
|
||||
void r_rst_write_disable(void);
|
||||
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
116
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_system.h
Normal file
116
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_system.h
Normal file
@ -0,0 +1,116 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* System Name : RZ/T1 Init program
|
||||
* File Name : r_system.h
|
||||
* Version : 0.1
|
||||
* Device : R7S910018
|
||||
* Abstract : Definitions for System
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* OS : not use
|
||||
* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary)
|
||||
* Description : Define the system settings ans value.
|
||||
* Limitation : none
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.05.2015 1.00 First Release
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#ifndef _R_SYSTEM_HEADER_
|
||||
#define _R_SYSTEM_HEADER_
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPCRA0
|
||||
#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPCRA1
|
||||
#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPCRA2
|
||||
#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPCRA3
|
||||
#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPCRA4
|
||||
#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPCRA5
|
||||
#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPCRA6
|
||||
#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPCRA7
|
||||
#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPCRA8
|
||||
#define MSTP_GPTA SYSTEM.MSTPCRA.BIT.MSTPCRA9
|
||||
#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPCRA11
|
||||
|
||||
#define MSTP_RSCAN SYSTEM.MSTPCRB.BIT.MSTPCRB1
|
||||
#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPCRB2
|
||||
#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPCRB3
|
||||
#define MSTP_SCIFA4 SYSTEM.MSTPCRB.BIT.MSTPCRB5
|
||||
#define MSTP_SCIFA3 SYSTEM.MSTPCRB.BIT.MSTPCRB6
|
||||
#define MSTP_SCIFA2 SYSTEM.MSTPCRB.BIT.MSTPCRB7
|
||||
#define MSTP_SCIFA1 SYSTEM.MSTPCRB.BIT.MSTPCRB8
|
||||
#define MSTP_SCIFA0 SYSTEM.MSTPCRB.BIT.MSTPCRB9
|
||||
#define MSTP_RSPI3 SYSTEM.MSTPCRB.BIT.MSTPCRB10
|
||||
#define MSTP_RSPI2 SYSTEM.MSTPCRB.BIT.MSTPCRB11
|
||||
#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPCRB12
|
||||
#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPCRB13
|
||||
#define MSTP_ETHERSW SYSTEM.MSTPCRB.BIT.MSTPCRB14
|
||||
#define MSTP_ECATC SYSTEM.MSTPCRB.BIT.MSTPCRB15
|
||||
#define MSTP_EMDIO SYSTEM.MSTPCRB.BIT.MSTPCRB16
|
||||
#define MSTP_ERMII SYSTEM.MSTPCRB.BIT.MSTPCRB17
|
||||
#define MSTP_HWRTOS SYSTEM.MSTPCRB.BIT.MSTPCRB18
|
||||
#define MSTP_CLKOUT25M SYSTEM.MSTPCRB.BIT.MSTPCRB19
|
||||
|
||||
#define MSTP_USB SYSTEM.MSTPCRC.BIT.MSTPCRC1
|
||||
#define MSTP_DSMIF SYSTEM.MSTPCRC.BIT.MSTPCRC2
|
||||
#define MSTP_TEMPS SYSTEM.MSTPCRC.BIT.MSTPCRC3
|
||||
#define MSTP_S12ADC1 SYSTEM.MSTPCRC.BIT.MSTPCRC4
|
||||
#define MSTP_S12ADC0 SYSTEM.MSTPCRC.BIT.MSTPCRC5
|
||||
#define MSTP_ELC SYSTEM.MSTPCRC.BIT.MSTPCRC6
|
||||
#define MSTP_BSC SYSTEM.MSTPCRC.BIT.MSTPCRC7
|
||||
#define MSTP_CKIO SYSTEM.MSTPCRC.BIT.MSTPCRC8
|
||||
#define MSTP_SPIBSC SYSTEM.MSTPCRC.BIT.MSTPCRC9
|
||||
#define MSTP_DOC SYSTEM.MSTPCRC.BIT.MSTPCRC10
|
||||
#define MSTP_CRC SYSTEM.MSTPCRC.BIT.MSTPCRC11
|
||||
#define MSTP_CLMA2 SYSTEM.MSTPCRC.BIT.MSTPCRC12
|
||||
#define MSTP_CLMA1 SYSTEM.MSTPCRC.BIT.MSTPCRC13
|
||||
#define MSTP_CLMA0 SYSTEM.MSTPCRC.BIT.MSTPCRC14
|
||||
|
||||
#define MSTP_SSI SYSTEM.MSTPCRD.BIT.MSTPCRD2
|
||||
|
||||
#define MSTP_DMAC1 SYSTEM.MSTPCRE.BIT.MSTPCRE4
|
||||
#define MSTP_DMAC0 SYSTEM.MSTPCRE.BIT.MSTPCRE5
|
||||
|
||||
#define MSTP_CORESIGHT SYSTEM.MSTPCRF.BIT.MSTPCRF0
|
||||
|
||||
#define __MSTP( x ) MSTP ## x
|
||||
#define _MSTP( x ) __MSTP( x )
|
||||
#define MSTP( x ) _MSTP( _ ## x )
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Exported global variables and functions (to be accessed by other files)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/* End _R_SYSTEM_HEADER_ */
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
87
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_typedefs.h
Normal file
87
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/r_typedefs.h
Normal file
@ -0,0 +1,87 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_typedefs.h
|
||||
* Device(s) : RZ/A1H (R7S910018)
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* H/W Platform : RSK+T1 CPU Board
|
||||
* Description : basic type definition
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.10.2014 1.00
|
||||
***********************************************************************************************************************/
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
***********************************************************************************************************************/
|
||||
#include <stdint.h>
|
||||
/* Multiple inclusion prevention macro */
|
||||
#ifndef R_TYPEDEFS_H
|
||||
#define R_TYPEDEFS_H
|
||||
|
||||
|
||||
/* in case <stdio.h> has defined it. */
|
||||
#ifndef NULL
|
||||
#define NULL (0)
|
||||
#endif
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#if !defined(__bool_true_false_are_defined) && !defined(__cplusplus)
|
||||
|
||||
#define FALSE (0)
|
||||
#define TRUE (1)
|
||||
|
||||
#endif
|
||||
|
||||
/* These two macros are used to suppress warnings generated by unused variables.
|
||||
Writing to some registers require a read instruction following the write.
|
||||
A dummy variable is declared and used to read the register written to. */
|
||||
#define UNUSED_PARAM(param) ((void)(param))
|
||||
#define UNUSED_VARIABLE(param) ((void)(param))
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
typedef char char_t;
|
||||
typedef unsigned int bool_t;
|
||||
typedef int int_t;
|
||||
typedef signed char int8_t;
|
||||
typedef signed short int16_t;
|
||||
typedef signed long int32_t;
|
||||
typedef signed long long int64_t;
|
||||
typedef unsigned char uint8_t;
|
||||
typedef unsigned short uint16_t;
|
||||
typedef unsigned long uint32_t;
|
||||
typedef unsigned long long uint64_t;
|
||||
typedef float float32_t;
|
||||
typedef double float64_t;
|
||||
typedef long double float128_t;
|
||||
|
||||
/* R_TYPEDEFS_H */
|
||||
#endif
|
||||
|
||||
57
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/siochar.h
Normal file
57
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/inc/siochar.h
Normal file
@ -0,0 +1,57 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only
|
||||
* intended for use with Renesas products. No other uses are authorized. This
|
||||
* software is owned by Renesas Electronics Corporation and is protected under
|
||||
* all applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
||||
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
||||
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
||||
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
||||
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
||||
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software
|
||||
* and to discontinue the availability of this software. By using this software,
|
||||
* you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* File Name : siochar.h
|
||||
* Device(s) : RZ/A1H (R7S910018)
|
||||
* Tool-Chain : GNUARM-NONEv14.02-EABI
|
||||
* H/W Platform : RSK+T1 CPU Board
|
||||
* Description : Sample Program - Terminal I/O header file
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* History : DD.MM.YYYY Version Description
|
||||
* : 21.10.2014 1.00
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/* Multiple inclusion prevention macro */
|
||||
#ifndef SIO_CHAR_H
|
||||
#define SIO_CHAR_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes <System Includes> , "Project Includes"
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Functions Prototypes
|
||||
***********************************************************************************************************************/
|
||||
int32_t sio_write (int32_t file_no, const char * buffer, uint32_t writing_b);
|
||||
int32_t sio_read (int32_t file_no, char * buffer, uint32_t reading_b);
|
||||
|
||||
void io_init_scifa2 (void);
|
||||
char io_get_char (void);
|
||||
void io_put_char (char buffer);
|
||||
|
||||
/* SIO_CHAR_H */
|
||||
#endif
|
||||
|
||||
/* End of File */
|
||||
5
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/makefile.init
Normal file
5
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/makefile.init
Normal file
@ -0,0 +1,5 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
PATH := $(PATH):C:\PROGRA~2\KPIT\GNUARM~1.02-\ARM-NO~1\ARM-NO~1\bin;C:\PROGRA~2\KPIT\GNUARM~1.02-\ARM-NO~1\ARM-NO~1\libexec\gcc\arm-none-eabi\4.9-GNUARM-NONE_v14.02
|
||||
212
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc.c
Normal file
212
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc.c
Normal file
@ -0,0 +1,212 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_cgc.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for CGC module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_cgc.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
#include "r_reset.h"
|
||||
#include "r_system.h"
|
||||
#include "r_typedefs.h"
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
|
||||
#define CPG_WRITE_ENABLE (0x0000A501)
|
||||
#define CPG_WRITE_DISABLE (0x0000A500)
|
||||
|
||||
#define CPG_CMT0_CLOCK_PCLKD_32 (1)
|
||||
#define CPG_CMT0_CMI0_ENABLE (1)
|
||||
#define CPG_CMT0_CONST_100_US (0xEA)
|
||||
#define CPG_CMT0_START (1)
|
||||
#define CPG_CMT0_STOP (0)
|
||||
|
||||
#define CPG_CMT_REG_CLEAR (0x0000)
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_CGC_Create
|
||||
* Description : This function initializes the clock generator.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_CGC_Create(void)
|
||||
{
|
||||
uint16_t w_count;
|
||||
|
||||
/* LOCO circuit disable */
|
||||
SYSTEM.LOCOCR.BIT.LCSTP = 1U;
|
||||
|
||||
/* Systen clock control register setting */
|
||||
SYSTEM.SCKCR.LONG = _CGC_CKIO_0 | _CGC_TCLK_0 | _CGC_PCLKE_0 | _CGC_PCLKF_0 | _CGC_PCLKG_0 | _CGC_SERICLK_0 |
|
||||
_CGC_ETCKE_0 | _CGC_ETCKD_0;
|
||||
|
||||
/* Set the CPU frequency for PLL1 */
|
||||
SYSTEM.PLL1CR.BIT.CPUCKSEL = _CGC_PLL1_CPUCKSEL_600;
|
||||
|
||||
/* PLL1 circuit enable */
|
||||
SYSTEM.PLL1CR2.BIT.PLL1EN = 1U;
|
||||
|
||||
/* Wait 100us for PLL1 stabilization */
|
||||
for (w_count = 0U; w_count < _CGC_PLL_WAIT_CYCLE; w_count++)
|
||||
{
|
||||
nop();
|
||||
}
|
||||
|
||||
/* Set system clock register 2 to PLL1 */
|
||||
SYSTEM.SCKCR2.BIT.CKSEL0 = 1U;
|
||||
|
||||
/* Delta-sigma interface operation setting, DSCLK0 and DSCLK1 both in master mode */
|
||||
SYSTEM.DSCR.LONG = _CGC_DSSEL0_MASTER | _CGC_DSCLK0_0 | _CGC_DSSEL1_MASTER | _CGC_DSCLK1_0;
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : R_CPG_WriteEnable
|
||||
* Description : Enables writing to the registers related to CPG function.
|
||||
* And dummy read the register in order to fix the register value.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void R_CPG_WriteEnable(void)
|
||||
{
|
||||
volatile uint32_t dummy = 0;
|
||||
|
||||
UNUSED_VARIABLE(dummy);
|
||||
|
||||
/* Enables writing to the CPG register */
|
||||
SYSTEM.PRCR.LONG = CPG_WRITE_ENABLE;
|
||||
dummy = SYSTEM.PRCR.LONG;
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function R_CPG_WriteEnable
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : R_CPG_WriteDisable
|
||||
* Description : Disables writing to the registers related to CPG function.
|
||||
* And dummy read the register in order to fix the register value.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void R_CPG_WriteDisable(void)
|
||||
{
|
||||
volatile uint32_t dummy = 0;
|
||||
|
||||
UNUSED_VARIABLE(dummy);
|
||||
|
||||
/* Disables writing to the CPG register */
|
||||
SYSTEM.PRCR.LONG = CPG_WRITE_DISABLE;
|
||||
dummy = SYSTEM.PRCR.LONG;
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function R_CPG_WriteDisable
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : R_CPG_PLLWait
|
||||
* Description : Wait about 100us for PLL stabilisation by using CMT0
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void R_CPG_PLLWait(void)
|
||||
{
|
||||
|
||||
/* Enables writing to the registers related to Reset and Low-Power function */
|
||||
r_rst_write_enable();
|
||||
|
||||
/* Release from the CMT0 module-stop state */
|
||||
MSTP(CMT0) = 0;
|
||||
|
||||
/* Disables writing to the registers related to Reset and Low-Power function */
|
||||
r_rst_write_disable();
|
||||
|
||||
/* Set CMT0 to 100us interval operation */
|
||||
CMT0.CMCR.BIT.CKS = CPG_CMT0_CLOCK_PCLKD_32;
|
||||
CMT0.CMCR.BIT.CMIE = CPG_CMT0_CMI0_ENABLE;
|
||||
CMT0.CMCNT = CPG_CMT_REG_CLEAR;
|
||||
CMT0.CMCOR = CPG_CMT0_CONST_100_US;
|
||||
|
||||
/* Set IRQ21(CMI0) for polling sequence */
|
||||
VIC.IEC0.BIT.IEC21 = 1U;
|
||||
VIC.PLS0.BIT.PLS21 = 1U;
|
||||
VIC.PIC0.BIT.PIC21 = 1U;
|
||||
|
||||
/* Start CMT0 count */
|
||||
CMT.CMSTR0.BIT.STR0 = CPG_CMT0_START;
|
||||
|
||||
/* Wait for 100us (IRQ21 is generated) */
|
||||
while ( !(VIC.RAIS0.BIT.RAI21) )
|
||||
{
|
||||
/* Wait */
|
||||
}
|
||||
|
||||
/* Stop CMT0 count */
|
||||
CMT.CMSTR0.BIT.STR0 = CPG_CMT0_STOP;
|
||||
|
||||
/* Initialise CMT0 settings and clear interrupt detection edge */
|
||||
CMT0.CMCR.WORD = CPG_CMT_REG_CLEAR;
|
||||
CMT0.CMCNT = CPG_CMT_REG_CLEAR;
|
||||
CMT0.CMCOR = CPG_CMT_REG_CLEAR;
|
||||
CMT.CMSTR0.WORD = CPG_CMT_REG_CLEAR;
|
||||
|
||||
VIC.PIC0.BIT.PIC21 = 1U;
|
||||
|
||||
/* Enables writing to the registers related to Reset and Low-Power function */
|
||||
r_rst_write_enable();
|
||||
|
||||
/* Set CMT0 to module-stop state */
|
||||
MSTP(CMT0) = 1;
|
||||
|
||||
/* Disables writing to the registers related to Reset and Low-Power function */
|
||||
r_rst_write_disable();
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function R_CPG_PLLWait
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
203
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc.h
Normal file
203
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc.h
Normal file
@ -0,0 +1,203 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_cgc.h
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for CGC module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
#ifndef CGC_H
|
||||
#define CGC_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
/*
|
||||
System Clock Control Register (SCKCR)
|
||||
*/
|
||||
/* Peripheral Module Clock G (PCLKG) */
|
||||
#define _CGC_PCLKG_0 (0x00000000UL) /* 60 MHz */
|
||||
#define _CGC_PCLKG_1 (0x00000001UL) /* 30 MHz */
|
||||
#define _CGC_PCLKG_2 (0x00000002UL) /* 15 MHz */
|
||||
#define _CGC_PCLKG_3 (0x00000003UL) /* 7.5 MHz */
|
||||
/* Peripheral Module Clock F (PCLKF) */
|
||||
#define _CGC_PCLKF_0 (0x00000000UL) /* 60 MHz */
|
||||
#define _CGC_PCLKF_1 (0x00000004UL) /* 30 MHz */
|
||||
#define _CGC_PCLKF_2 (0x00000008UL) /* 15 MHz */
|
||||
#define _CGC_PCLKF_3 (0x0000000CUL) /* 7.5 MHz */
|
||||
/* Peripheral Module Clock E (PCLKE) */
|
||||
#define _CGC_PCLKE_0 (0x00000000UL) /* 75 MHz */
|
||||
#define _CGC_PCLKE_1 (0x00000010UL) /* 37.5 MHz */
|
||||
#define _CGC_PCLKE_2 (0x00000020UL) /* 18.75 MHz */
|
||||
/* External Bus Clock (CKIO) */
|
||||
#define _CGC_CKIO_0 (0x00000000UL) /* 75 MHz */
|
||||
#define _CGC_CKIO_1 (0x00000100UL) /* 50 MHz */
|
||||
#define _CGC_CKIO_2 (0x00000200UL) /* 37.5 MHz */
|
||||
#define _CGC_CKIO_3 (0x00000300UL) /* 30 MHz */
|
||||
#define _CGC_CKIO_4 (0x00000400UL) /* 25 MHz */
|
||||
#define _CGC_CKIO_5 (0x00000500UL) /* 21.43 MHz */
|
||||
#define _CGC_CKIO_6 (0x00000600UL) /* 18.75 MHz */
|
||||
/* Ether Clock E (ETCLKE) */
|
||||
#define _CGC_ETCKE_0 (0x00000000UL) /* 25 MHz */
|
||||
#define _CGC_ETCKE_1 (0x00001000UL) /* 50 MHz */
|
||||
#define _CGC_ETCKE_2 (0x00003000UL) /* 25 MHz */
|
||||
/* Ether Clock D (ETCLKD) */
|
||||
#define _CGC_ETCKD_0 (0x00000000UL) /* 12.5 MHz */
|
||||
#define _CGC_ETCKD_1 (0x00004000UL) /* 6.25 MHz */
|
||||
#define _CGC_ETCKD_2 (0x00008000UL) /* 3.125 MHz */
|
||||
#define _CGC_ETCKD_3 (0x0000C000UL) /* 1.563 MHz */
|
||||
/* High-Speed Serial Clock (SERICLK) */
|
||||
#define _CGC_SERICLK_0 (0x00000000UL) /* 150 MHz */
|
||||
#define _CGC_SERICLK_1 (0x00010000UL) /* 120 MHz */
|
||||
/* USB Clock (USBMCLK) */
|
||||
#define _CGC_UCK_0 (0x00000000UL) /* 50 MHz */
|
||||
#define _CGC_UCK_1 (0x00020000UL) /* 24 MHz */
|
||||
/* Trace Interface Clock (TCLK) */
|
||||
#define _CGC_TCLK_0 (0x00000000UL) /* 150 MHz */
|
||||
#define _CGC_TCLK_1 (0x00100000UL) /* 75 MHz */
|
||||
|
||||
/*
|
||||
System Clock Control Register 2 (SCKCR2)
|
||||
*/
|
||||
#define _CGC_SKSEL0_PLL0 (0x00000000UL) /* PLL0 */
|
||||
#define _CGC_SKSEL0_PLL1 (0x00000001UL) /* PLL1 */
|
||||
|
||||
/*
|
||||
Delta-Sigma Interface Clock Control Register (DSCR)
|
||||
*/
|
||||
#define _CGC_DSSEL0_SLAVE (0x00000000UL) /* Supplied from outside the LSI (slave operation) */
|
||||
#define _CGC_DSSEL0_MASTER (0x00000001UL) /* Supplied from CGC (master operation) */
|
||||
#define _CGC_DSCLK0_0 (0x00000000UL) /* 25 MHz */
|
||||
#define _CGC_DSCLK0_1 (0x00000002UL) /* 18.75 MHz */
|
||||
#define _CGC_DSCLK0_2 (0x00000004UL) /* 12.5 MHz */
|
||||
#define _CGC_DSCLK0_3 (0x00000006UL) /* 9.375 MHz */
|
||||
#define _CGC_DSCLK0_4 (0x00000008UL) /* 6.25 MHz */
|
||||
#define _CGC_DSCLK0_POL_NORMAL (0x00000000UL) /* Polarity not inverted (master and slave operation) */
|
||||
#define _CGC_DSCLK0_POL_INVERT (0x00000010UL) /* Polarity inverted (master and slave operation) */
|
||||
#define _CGC_DSCLK0_SLAVE_MCLK0_2 (0x00000000UL) /* Clock input to MCLK0,MCLK1,MCLK2 pins are used */
|
||||
#define _CGC_DSCLK0_SLAVE_MCLK0 (0x00000020UL) /* Clock input to MCLK0 pin is used */
|
||||
#define _CGC_DSSEL1_SLAVE (0x00000000UL) /* Supplied from outside the LSI (slave operation) */
|
||||
#define _CGC_DSSEL1_MASTER (0x00010000UL) /* Supplied from CGC (master operation) */
|
||||
#define _CGC_DSCLK1_0 (0x00000000UL) /* 25 MHz */
|
||||
#define _CGC_DSCLK1_1 (0x00020000UL) /* 18.75 MHz */
|
||||
#define _CGC_DSCLK1_2 (0x00040000UL) /* 12.5 MHz */
|
||||
#define _CGC_DSCLK1_3 (0x00060000UL) /* 9.375 MHz */
|
||||
#define _CGC_DSCLK1_4 (0x00080000UL) /* 6.25 MHz */
|
||||
#define _CGC_DSCLK1_POL_NORMAL (0x00000000UL) /* Polarity not inverted (master and slave operation) */
|
||||
#define _CGC_DSCLK1_POL_INVERT (0x00100000UL) /* Polarity inverted (master and slave operation) */
|
||||
|
||||
/*
|
||||
PLL1 Control Register (PLL1CR)
|
||||
*/
|
||||
#define _CGC_PLL1_CPUCKSEL_150 (0x00U) /* 150 MHz */
|
||||
#define _CGC_PLL1_CPUCKSEL_300 (0x01U) /* 300 MHz */
|
||||
#define _CGC_PLL1_CPUCKSEL_450 (0x02U) /* 450 MHz */
|
||||
#define _CGC_PLL1_CPUCKSEL_600 (0x03U) /* 600 MHz */
|
||||
|
||||
/*
|
||||
PLL1 Control Register 2 (PLL1CR2)
|
||||
*/
|
||||
#define _CGC_PLL1_DISABLE (0x00000000UL) /* PLL1 stops */
|
||||
#define _CGC_PLL1_ENABLE (0x00000001UL) /* PLL1 runs */
|
||||
|
||||
/*
|
||||
Low-Speed On-Chip Oscillator Control Register (LOCOCR)
|
||||
*/
|
||||
#define _CGC_LOCO_RUN (0x00000000UL) /* LOCO Run */
|
||||
#define _CGC_LOCO_STOP (0x00000001UL) /* LOCO Stop */
|
||||
|
||||
/*
|
||||
Oscillation Stop Detection Control Register (OSTDCR)
|
||||
*/
|
||||
/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */
|
||||
#define _CGC_OSC_STOP_DET_INT_DISABLE (0x00000000UL) /* Stop detection interrupt is disabled */
|
||||
#define _CGC_OSC_STOP_DET_INT_ENABLE (0x00000001UL) /* Stop detection interrupt is enabled */
|
||||
/* Oscillation Stop Detection Function Enable (OSTDE) */
|
||||
#define _CGC_OSC_STOP_DET_DISABLE (0x00000000UL) /* Oscillation stop detection function is disabled */
|
||||
#define _CGC_OSC_STOP_DET_ENABLE (0x00000080UL) /* Oscillation stop detection function is enabled */
|
||||
|
||||
/*
|
||||
ECM Non-maskable Interrupt Configuration Register 0 (ECMNMICFG0)
|
||||
*/
|
||||
#define _ECM_NMI_OSC_STOP_DISABLE (0x00000000UL) /* Stop detection NMI interrupt is disabled */
|
||||
#define _ECM_NMI_OSC_STOP_ENABLE (0x00080000UL) /* Stop detection NMI interrupt is enabled */
|
||||
|
||||
/*
|
||||
ECM Maskable Interrupt Configuration Register 0 (ECMMICFG0)
|
||||
*/
|
||||
#define _ECM_MI_OSC_STOP_DISABLE (0x00000000UL) /* Stop detection Maskable interrupt is disabled */
|
||||
#define _ECM_MI_OSC_STOP_ENABLE (0x00080000UL) /* Stop detection Maskable interrupt is enabled */
|
||||
|
||||
/*
|
||||
Debugging Interface Control Register (DBGIFCNT)
|
||||
*/
|
||||
#define _SWV_SEL_NOOUTPUT (0x00000000UL) /* SWV output is not output */
|
||||
#define _SWV_SEL_TDO (0x00000001UL) /* SWV output is output from the TDO pin */
|
||||
#define _SWV_SEL_TRACEDATA0 (0x00000002UL) /* SWV output is output from the TRACEDATA0 pin */
|
||||
#define _SWV_SEL_TRACECTL (0x00000003UL) /* SWV output is output from the TRACECTL pin */
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#define _CGC_PLL_WAIT_CYCLE (0x1D4CU) /* Wait 100us when switch clock source in PLL0 and PLL1 */
|
||||
#define _CGC_LOCO_WAIT_CYCLE (0x0BB8U) /* Wait 40us for LOCO oscillation stabilization */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_CGC_Create(void);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
|
||||
void R_CPG_PLLWait(void);
|
||||
void R_CPG_WriteEnable(void);
|
||||
void R_CPG_WriteDisable(void);
|
||||
|
||||
#define CPG_CPUCLK_150_MHz (0)
|
||||
#define CPG_CPUCLK_300_MHz (1)
|
||||
#define CPG_CPUCLK_450_MHz (2)
|
||||
#define CPG_CPUCLK_600_MHz (3)
|
||||
|
||||
#define CPG_PLL1_OFF (0)
|
||||
#define CPG_PLL1_ON (1)
|
||||
|
||||
#define CPG_SELECT_PLL0 (0)
|
||||
#define CPG_SELECT_PLL1 (1)
|
||||
|
||||
#define CPG_CKIO_75_MHz (0)
|
||||
#define CPG_CKIO_50_MHz (1)
|
||||
#define CPG_CKIO_37_5_MHz (2)
|
||||
#define CPG_CKIO_30_MHz (3)
|
||||
#define CPG_CKIO_25_MHz (4)
|
||||
#define CPG_CKIO_21_43_MHz (5)
|
||||
#define CPG_CKIO_18_75_MHz (6)
|
||||
|
||||
#define CPG_LOCO_ENABLE (0x00000000)
|
||||
#define CPG_LOCO_DISABLE (0x00000001)
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
@ -0,0 +1,52 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_cgc_user.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for CGC module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_cgc.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
162
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt.c
Normal file
162
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt.c
Normal file
@ -0,0 +1,162 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_cmt.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for CMT module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_cmt.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_CMT4_Create
|
||||
* Description : This function initializes the CMT4 channel.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_CMT4_Create(void)
|
||||
{
|
||||
/* Disable CMI4 interrupt */
|
||||
VIC.IEC9.LONG = 0x00000800UL;
|
||||
|
||||
/* Cancel CMT stop state in LPC */
|
||||
MSTP(CMT2) = 0U;
|
||||
|
||||
/* Set control registers */
|
||||
CMT4.CMCR.WORD = _CMT_CMCR_CKS_PCLK8 | _CMT_CMCR_CMIE_ENABLE;
|
||||
CMT4.CMCOR = _CMT4_CMCOR_VALUE;
|
||||
|
||||
/* Set CMI4 edge detection type */
|
||||
VIC.PLS9.LONG |= 0x00000800UL;
|
||||
|
||||
/* Set CMI4 priority level */
|
||||
VIC.PRL299.LONG = _CMT_PRIORITY_LEVEL16;
|
||||
|
||||
/* Set CMI4 interrupt address */
|
||||
VIC.VAD299.LONG = (uint32_t)r_cmt_cmi4_interrupt;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_CMT4_Start
|
||||
* Description : This function starts the CMT4 channel counter.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_CMT4_Start(void)
|
||||
{
|
||||
/* Enable CMI4 interrupt in ICU */
|
||||
VIC.IEN9.LONG |= 0x00000800UL;
|
||||
|
||||
/* Start CMT4 count */
|
||||
CMT.CMSTR2.BIT.STR4 = 1U;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_CMT4_Stop
|
||||
* Description : This function stops the CMT4 channel counter.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_CMT4_Stop(void)
|
||||
{
|
||||
/* Disable CMI4 interrupt in ICU */
|
||||
VIC.IEC9.LONG = 0x00000800UL;
|
||||
|
||||
/* Stop CMT4 count */
|
||||
CMT.CMSTR2.BIT.STR4 = 0U;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_CMT5_Create
|
||||
* Description : This function initializes the CMT5 channel.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_CMT5_Create(void)
|
||||
{
|
||||
/* Disable CMI5 interrupt */
|
||||
VIC.IEC9.LONG = 0x00001000UL;
|
||||
|
||||
/* Cancel CMT stop state in LPC */
|
||||
MSTP(CMT2) = 0U;
|
||||
|
||||
/* Set control registers */
|
||||
CMT5.CMCR.WORD = _CMT_CMCR_CKS_PCLK8 | _CMT_CMCR_CMIE_ENABLE;
|
||||
CMT5.CMCOR = _CMT5_CMCOR_VALUE;
|
||||
|
||||
/* Set CMI5 edge detection type */
|
||||
VIC.PLS9.LONG |= 0x00001000UL;
|
||||
|
||||
/* Set CMI5 priority level */
|
||||
VIC.PRL300.LONG = _CMT_PRIORITY_LEVEL17;
|
||||
|
||||
/* Set CMI5 interrupt address */
|
||||
VIC.VAD300.LONG = (uint32_t)r_cmt_cmi5_interrupt;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_CMT5_Start
|
||||
* Description : This function starts the CMT5 channel counter.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_CMT5_Start(void)
|
||||
{
|
||||
/* Enable CMI5 interrupt in ICU */
|
||||
VIC.IEN9.LONG |= 0x00001000UL;
|
||||
|
||||
/* Start CMT5 count */
|
||||
CMT.CMSTR2.BIT.STR5 = 1U;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_CMT5_Stop
|
||||
* Description : This function stops the CMT5 channel counter.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_CMT5_Stop(void)
|
||||
{
|
||||
/* Disable CMI5 interrupt in ICU */
|
||||
VIC.IEC9.LONG = 0x00001000UL;
|
||||
|
||||
/* Stop CMT5 count */
|
||||
CMT.CMSTR2.BIT.STR5 = 0U;
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
112
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt.h
Normal file
112
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt.h
Normal file
@ -0,0 +1,112 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_cmt.h
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for CMT module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
#ifndef CMT_H
|
||||
#define CMT_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
/*
|
||||
Compare Match Timer Control Register (CMCR)
|
||||
*/
|
||||
/* Clock Select (CKS[1:0]) */
|
||||
#define _CMT_CMCR_CKS_PCLK8 (0x0000U) /* PCLK/8 */
|
||||
#define _CMT_CMCR_CKS_PCLK32 (0x0001U) /* PCLK/32 */
|
||||
#define _CMT_CMCR_CKS_PCLK128 (0x0002U) /* PCLK/128 */
|
||||
#define _CMT_CMCR_CKS_PCLK512 (0x0003U) /* PCLK/512 */
|
||||
/* Compare Match Interrupt Enable (CMIE) */
|
||||
#define _CMT_CMCR_CMIE_DISABLE (0x0000U) /* Compare match interrupt (CMIn) disabled */
|
||||
#define _CMT_CMCR_CMIE_ENABLE (0x0040U) /* Compare match interrupt (CMIn) enabled */
|
||||
|
||||
/*
|
||||
Interrupt Priority Level Store Register n (PRLn)
|
||||
*/
|
||||
/* Interrupt Priority Level Store (PRL[3:0]) */
|
||||
#define _CMT_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */
|
||||
#define _CMT_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */
|
||||
#define _CMT_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */
|
||||
#define _CMT_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */
|
||||
#define _CMT_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */
|
||||
#define _CMT_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */
|
||||
#define _CMT_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */
|
||||
#define _CMT_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */
|
||||
#define _CMT_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */
|
||||
#define _CMT_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */
|
||||
#define _CMT_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */
|
||||
#define _CMT_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */
|
||||
#define _CMT_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */
|
||||
#define _CMT_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */
|
||||
#define _CMT_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */
|
||||
#define _CMT_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */
|
||||
#define _CMT_PRIORITY_LEVEL16 (0x00000000UL) /* Level 16 */
|
||||
#define _CMT_PRIORITY_LEVEL17 (0x00000001UL) /* Level 17 */
|
||||
#define _CMT_PRIORITY_LEVEL18 (0x00000002UL) /* Level 18 */
|
||||
#define _CMT_PRIORITY_LEVEL19 (0x00000003UL) /* Level 19 */
|
||||
#define _CMT_PRIORITY_LEVEL20 (0x00000004UL) /* Level 20 */
|
||||
#define _CMT_PRIORITY_LEVEL21 (0x00000005UL) /* Level 21 */
|
||||
#define _CMT_PRIORITY_LEVEL22 (0x00000006UL) /* Level 22 */
|
||||
#define _CMT_PRIORITY_LEVEL23 (0x00000007UL) /* Level 23 */
|
||||
#define _CMT_PRIORITY_LEVEL24 (0x00000008UL) /* Level 24 */
|
||||
#define _CMT_PRIORITY_LEVEL25 (0x00000009UL) /* Level 25 */
|
||||
#define _CMT_PRIORITY_LEVEL26 (0x0000000AUL) /* Level 26 */
|
||||
#define _CMT_PRIORITY_LEVEL27 (0x0000000BUL) /* Level 27 */
|
||||
#define _CMT_PRIORITY_LEVEL28 (0x0000000CUL) /* Level 28 */
|
||||
#define _CMT_PRIORITY_LEVEL29 (0x0000000DUL) /* Level 29 */
|
||||
#define _CMT_PRIORITY_LEVEL30 (0x0000000EUL) /* Level 30 */
|
||||
#define _CMT_PRIORITY_LEVEL31 (0x0000000FUL) /* Level 31 (lowest) */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
/* Compare Match Timer Constant Register (CMCOR) */
|
||||
#define _CMT4_CMCOR_VALUE (0x0008U)
|
||||
/* Compare Match Timer Constant Register (CMCOR) */
|
||||
#define _CMT5_CMCOR_VALUE (0x249EU)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_CMT4_Create(void);
|
||||
void R_CMT4_Start(void);
|
||||
void R_CMT4_Stop(void);
|
||||
void R_CMT5_Create(void);
|
||||
void R_CMT5_Start(void);
|
||||
void R_CMT5_Stop(void);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
|
||||
/* Counters used to generate user's delay period */
|
||||
extern volatile uint32_t g_time_ms_count;
|
||||
extern volatile uint32_t g_time_us_count;
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
@ -0,0 +1,99 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_cmt_user.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for CMT module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_cmt.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
|
||||
/* Counters used to generate user's delay period */
|
||||
volatile uint32_t g_time_ms_count;
|
||||
volatile uint32_t g_time_us_count;
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_cmt_cmi4_interrupt
|
||||
* Description : This function is CMI4 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_cmt_cmi4_interrupt(void)
|
||||
{
|
||||
/* Clear the interrupt source CMI4 */
|
||||
VIC.PIC9.LONG = 0x00000800UL;
|
||||
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
|
||||
/* Decrement the count value */
|
||||
g_time_us_count--;
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/* Dummy write */
|
||||
VIC.HVA0.LONG = 0x00000000UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_cmt_cmi5_interrupt
|
||||
* Description : This function is CMI5 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_cmt_cmi5_interrupt(void)
|
||||
{
|
||||
/* Clear the interrupt source CMI5 */
|
||||
VIC.PIC9.LONG = 0x00001000UL;
|
||||
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
|
||||
/* Decrement the count value */
|
||||
g_time_ms_count--;
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/* Dummy write */
|
||||
VIC.HVA0.LONG = 0x00000000UL;
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
102
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.c
Normal file
102
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.c
Normal file
@ -0,0 +1,102 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_icu.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for ICU module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_icu.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_ICU_Create
|
||||
* Description : This function initializes ICU module.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_ICU_Create(void)
|
||||
{
|
||||
|
||||
/* Disable IRQ12 interrupt */
|
||||
VIC.IEC0.LONG = 0x00010000UL;
|
||||
|
||||
/* Set IRQ12 edge detection type */
|
||||
VIC.PLS0.LONG |= 0x00010000UL;
|
||||
ICU.IRQCR12.BIT.IRQMD = (uint8_t)_ICU_IRQ_EDGE_FALLING;
|
||||
|
||||
/* Enable IRQ12 digital filter */
|
||||
ICU.IRQFLTE.BIT.FLTEN12 = 1U;
|
||||
|
||||
/* Set IRQ12 digital filter clock */
|
||||
ICU.IRQFLTC.BIT.FCLKSEL12 = _ICU_IRQ12_FILTER_PCLKB_64;
|
||||
|
||||
/* Set IRQ12 Priority */
|
||||
VIC.PRL16.LONG = _ICU_PRIORITY_LEVEL3;
|
||||
|
||||
/* Set IRQ12 interupt address */
|
||||
VIC.VAD16.LONG = (uint32_t)r_icu_irq12_interrupt;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_ICU_IRQ12_Start
|
||||
* Description : This function enables IRQ12 interrupt.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_ICU_IRQ12_Start(void)
|
||||
{
|
||||
/* Enable IRQ12 interrupt */
|
||||
VIC.IEN0.LONG |= 0x00010000UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_ICU_IRQ12_Stop
|
||||
* Description : This function disables IRQ12 interrupt.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_ICU_IRQ12_Stop(void)
|
||||
{
|
||||
/* Disable IRQ12 interrupt */
|
||||
VIC.IEC0.LONG = 0x00010000UL;
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
326
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.h
Normal file
326
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.h
Normal file
@ -0,0 +1,326 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_icu.h
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for ICU module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
#ifndef ICU_H
|
||||
#define ICU_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/*
|
||||
DMAC Software Activation Register (DMASTG)
|
||||
*/
|
||||
/* DMA Unit 0 Software Activation (DMREQ0) */
|
||||
#define _DMA_UNIT0_SOFTWARE_ACTIVATION_DISABLE (0x00U) /* DMA transfer is not requested for DMA Unit 0*/
|
||||
#define _DMA_UNIT0_SOFTWARE_ACTIVATION_ENABLE (0x01U) /* DMA transfer is requested for DMA Unit 0 */
|
||||
/* DMA Unit 1 Software Activation (DMREQ1) */
|
||||
#define _DMA_UNIT1_SOFTWARE_ACTIVATION_DISABLE (0x00U) /* DMA transfer is not requested for DMA Unit 1*/
|
||||
#define _DMA_UNIT1_SOFTWARE_ACTIVATION_ENABLE (0x02U) /* DMA transfer is requested for DMA Unit 1*/
|
||||
|
||||
/*
|
||||
IRQ Control Register i (IRQCRi) (i = 0 to 15)
|
||||
*/
|
||||
/* IRQ Detection Sense Select (IRQMD[1:0]) */
|
||||
#define _ICU_IRQ_EDGE_LOW_LEVEL (0x00U) /* Low level */
|
||||
#define _ICU_IRQ_EDGE_FALLING (0x01U) /* Falling edge */
|
||||
#define _ICU_IRQ_EDGE_RISING (0x02U) /* Rising edge */
|
||||
#define _ICU_IRQ_EDGE_BOTH (0x03U) /* Rising and falling edge */
|
||||
|
||||
/*
|
||||
IRQ Pin Digital Noise Filter Enable Register 0 (IRQFLTE)
|
||||
*/
|
||||
/* IRQn Digital Noise Filter Enable (FLTEN0n) */
|
||||
#define _ICU_IRQn_FILTER_DISABLE (0x00000000UL) /* IRQn digital noise filter is disabled */
|
||||
#define _ICU_IRQ0_FILTER_ENABLE (0x00000001UL) /* IRQ0 digital noise filter is enabled */
|
||||
#define _ICU_IRQ1_FILTER_ENABLE (0x00000002UL) /* IRQ1 digital noise filter is enabled */
|
||||
#define _ICU_IRQ2_FILTER_ENABLE (0x00000004UL) /* IRQ2 digital noise filter is enabled */
|
||||
#define _ICU_IRQ3_FILTER_ENABLE (0x00000008UL) /* IRQ3 digital noise filter is enabled */
|
||||
#define _ICU_IRQ4_FILTER_ENABLE (0x00000010UL) /* IRQ4 digital noise filter is enabled */
|
||||
#define _ICU_IRQ5_FILTER_ENABLE (0x00000020UL) /* IRQ5 digital noise filter is enabled */
|
||||
#define _ICU_IRQ6_FILTER_ENABLE (0x00000040UL) /* IRQ6 digital noise filter is enabled */
|
||||
#define _ICU_IRQ7_FILTER_ENABLE (0x00000080UL) /* IRQ7 digital noise filter is enabled */
|
||||
#define _ICU_IRQ8_FILTER_ENABLE (0x00000100UL) /* IRQ8 digital noise filter is enabled */
|
||||
#define _ICU_IRQ9_FILTER_ENABLE (0x00000200UL) /* IRQ9 digital noise filter is enabled */
|
||||
#define _ICU_IRQ10_FILTER_ENABLE (0x00000400UL) /* IRQ10 digital noise filter is enabled */
|
||||
#define _ICU_IRQ11_FILTER_ENABLE (0x00000800UL) /* IRQ11 digital noise filter is enabled */
|
||||
#define _ICU_IRQ12_FILTER_ENABLE (0x00001000UL) /* IRQ12 digital noise filter is enabled */
|
||||
#define _ICU_IRQ13_FILTER_ENABLE (0x00002000UL) /* IRQ13 digital noise filter is enabled */
|
||||
#define _ICU_IRQ14_FILTER_ENABLE (0x00004000UL) /* IRQ14 digital noise filter is enabled */
|
||||
#define _ICU_IRQ15_FILTER_ENABLE (0x00008000UL) /* IRQ15 digital noise filter is enabled */
|
||||
|
||||
/*
|
||||
IRQ Pin Digital Filter Setting Register (IRQFLTC)
|
||||
*/
|
||||
/* IRQn Digital Filter Sampling Clock (FCLKSELn[1:0]) */
|
||||
#define _ICU_IRQ0_FILTER_PCLKB (0x00U) /* IRQ0 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ0_FILTER_PCLKB_8 (0x01U) /* IRQ0 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ0_FILTER_PCLKB_32 (0x02U) /* IRQ0 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ0_FILTER_PCLKB_64 (0x03U) /* IRQ0 sample clock run at every PCLKB/64 cycle */
|
||||
#define _ICU_IRQ1_FILTER_PCLKB (0x00U) /* IRQ1 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ1_FILTER_PCLKB_8 (0x01U) /* IRQ1 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ1_FILTER_PCLKB_32 (0x02U) /* IRQ1 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ1_FILTER_PCLKB_64 (0x03U) /* IRQ1 sample clock run at every PCLKB/64 cycle */
|
||||
#define _ICU_IRQ2_FILTER_PCLKB (0x00U) /* IRQ2 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ2_FILTER_PCLKB_8 (0x01U) /* IRQ2 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ2_FILTER_PCLKB_32 (0x02U) /* IRQ2 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ2_FILTER_PCLKB_64 (0x03U) /* IRQ2 sample clock run at every PCLKB/64 cycle */
|
||||
#define _ICU_IRQ3_FILTER_PCLKB (0x00U) /* IRQ3 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ3_FILTER_PCLKB_8 (0x01U) /* IRQ3 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ3_FILTER_PCLKB_32 (0x02U) /* IRQ3 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ3_FILTER_PCLKB_64 (0x03U) /* IRQ3 sample clock run at every PCLKB/64 cycle */
|
||||
#define _ICU_IRQ4_FILTER_PCLKB (0x00U) /* IRQ4 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ4_FILTER_PCLKB_8 (0x01U) /* IRQ4 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ4_FILTER_PCLKB_32 (0x02U) /* IRQ4 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ4_FILTER_PCLKB_64 (0x03U) /* IRQ4 sample clock run at every PCLKB/64 cycle */
|
||||
#define _ICU_IRQ5_FILTER_PCLKB (0x00U) /* IRQ5 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ5_FILTER_PCLKB_8 (0x01U) /* IRQ5 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ5_FILTER_PCLKB_32 (0x02U) /* IRQ5 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ5_FILTER_PCLKB_64 (0x03U) /* IRQ5 sample clock run at every PCLKB/64 cycle */
|
||||
#define _ICU_IRQ6_FILTER_PCLKB (0x00U) /* IRQ6 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ6_FILTER_PCLKB_8 (0x01U) /* IRQ6 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ6_FILTER_PCLKB_32 (0x02U) /* IRQ6 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ6_FILTER_PCLKB_64 (0x03U) /* IRQ6 sample clock run at every PCLKB/64 cycle */
|
||||
#define _ICU_IRQ7_FILTER_PCLKB (0x00U) /* IRQ7 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ7_FILTER_PCLKB_8 (0x01U) /* IRQ7 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ7_FILTER_PCLKB_32 (0x02U) /* IRQ7 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ7_FILTER_PCLKB_64 (0x03U) /* IRQ7 sample clock run at every PCLKB/64 cycle */
|
||||
#define _ICU_IRQ8_FILTER_PCLKB (0x00U) /* IRQ8 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ8_FILTER_PCLKB_8 (0x01U) /* IRQ8 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ8_FILTER_PCLKB_32 (0x02U) /* IRQ8 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ8_FILTER_PCLKB_64 (0x03U) /* IRQ8 sample clock run at every PCLKB/64 cycle */
|
||||
#define _ICU_IRQ9_FILTER_PCLKB (0x00U) /* IRQ9 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ9_FILTER_PCLKB_8 (0x01U) /* IRQ9 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ9_FILTER_PCLKB_32 (0x02U) /* IRQ9 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ9_FILTER_PCLKB_64 (0x03U) /* IRQ9 sample clock run at every PCLKB/64 cycle */
|
||||
#define _ICU_IRQ10_FILTER_PCLKB (0x00U) /* IRQ10 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ10_FILTER_PCLKB_8 (0x01U) /* IRQ10 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ10_FILTER_PCLKB_32 (0x02U) /* IRQ10 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ10_FILTER_PCLKB_64 (0x03U) /* IRQ10 sample clock run at every PCLKB/64 cycle */
|
||||
#define _ICU_IRQ11_FILTER_PCLKB (0x00U) /* IRQ11 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ11_FILTER_PCLKB_8 (0x01U) /* IRQ11 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ11_FILTER_PCLKB_32 (0x02U) /* IRQ11 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ11_FILTER_PCLKB_64 (0x03U) /* IRQ11 sample clock run at every PCLKB/64 cycle */
|
||||
#define _ICU_IRQ12_FILTER_PCLKB (0x00U) /* IRQ12 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ12_FILTER_PCLKB_8 (0x01U) /* IRQ12 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ12_FILTER_PCLKB_32 (0x02U) /* IRQ12 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ12_FILTER_PCLKB_64 (0x03U) /* IRQ12 sample clock run at every PCLKB/64 cycle */
|
||||
#define _ICU_IRQ13_FILTER_PCLKB (0x00U) /* IRQ13 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ13_FILTER_PCLKB_8 (0x01U) /* IRQ13 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ13_FILTER_PCLKB_32 (0x02U) /* IRQ13 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ13_FILTER_PCLKB_64 (0x03U) /* IRQ13 sample clock run at every PCLKB/64 cycle */
|
||||
#define _ICU_IRQ14_FILTER_PCLKB (0x00U) /* IRQ14 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ14_FILTER_PCLKB_8 (0x01U) /* IRQ14 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ14_FILTER_PCLKB_32 (0x02U) /* IRQ14 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ14_FILTER_PCLKB_64 (0x03U) /* IRQ14 sample clock run at every PCLKB/64 cycle */
|
||||
#define _ICU_IRQ15_FILTER_PCLKB (0x00U) /* IRQ15 sample clock run at every PCLKB cycle */
|
||||
#define _ICU_IRQ15_FILTER_PCLKB_8 (0x01U) /* IRQ15 sample clock run at every PCLKB/8 cycle */
|
||||
#define _ICU_IRQ15_FILTER_PCLKB_32 (0x02U) /* IRQ15 sample clock run at every PCLKB/32 cycle */
|
||||
#define _ICU_IRQ15_FILTER_PCLKB_64 (0x03U) /* IRQ15 sample clock run at every PCLKB/64 cycle */
|
||||
|
||||
/*
|
||||
Interrupt Source Priority Register n (IPRn)
|
||||
*/
|
||||
/* Interrupt Priority Level Select (IPR[3:0]) */
|
||||
#define _ICU_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (interrupt disabled) */
|
||||
#define _ICU_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */
|
||||
#define _ICU_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */
|
||||
#define _ICU_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */
|
||||
#define _ICU_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */
|
||||
#define _ICU_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */
|
||||
#define _ICU_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */
|
||||
#define _ICU_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */
|
||||
#define _ICU_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */
|
||||
#define _ICU_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */
|
||||
#define _ICU_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */
|
||||
#define _ICU_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */
|
||||
#define _ICU_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */
|
||||
#define _ICU_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */
|
||||
#define _ICU_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */
|
||||
#define _ICU_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 (highest) */
|
||||
|
||||
/*
|
||||
NMI Pin Interrupt Control Register (NMICR)
|
||||
*/
|
||||
/* NMI Detection Sense Selection (NMIMD) */
|
||||
#define _ICU_NMI_DETECTION_SENSE_FALLING (0x00U) /* Falling edge */
|
||||
#define _ICU_NMI_DETECTION_SENSE_RISING (0x08U) /* Rising edge */
|
||||
|
||||
/*
|
||||
DMA Noise Filter Setting Register (DMAINT)
|
||||
*/
|
||||
/* DMA Digital Noise Filter Sampling Clock (DREQFLTC[1:0]) */
|
||||
#define _ICU_DMAINT0_FILTER_PCLKB (0x00U) /* NMI sample clock is run at every PCLKB cycle */
|
||||
#define _ICU_DMAINT0_FILTER_PCLKB_8 (0x01U) /* NMI sample clock is run at every PCLKB/8 cycle */
|
||||
#define _ICU_DMAINT0_FILTER_PCLKB_32 (0x02U) /* NMI sample clock is run at every PCLKB/32 cycle */
|
||||
#define _ICU_DMAINT0_FILTER_PCLKB_64 (0x03U) /* NMI sample clock is run at every PCLKB/64 cycle */
|
||||
#define _ICU_DMAINT1_FILTER_PCLKB (0x00U) /* NMI sample clock is run at every PCLKB cycle */
|
||||
#define _ICU_DMAINT1_FILTER_PCLKB_8 (0x01U) /* NMI sample clock is run at every PCLKB/8 cycle */
|
||||
#define _ICU_DMAINT1_FILTER_PCLKB_32 (0x02U) /* NMI sample clock is run at every PCLKB/32 cycle */
|
||||
#define _ICU_DMAINT1_FILTER_PCLKB_64 (0x03U) /* NMI sample clock is run at every PCLKB/64 cycle */
|
||||
#define _ICU_DMAINT2_FILTER_PCLKB (0x00U) /* NMI sample clock is run at every PCLKB cycle */
|
||||
#define _ICU_DMAINT2_FILTER_PCLKB_8 (0x01U) /* NMI sample clock is run at every PCLKB/8 cycle */
|
||||
#define _ICU_DMAINT2_FILTER_PCLKB_32 (0x02U) /* NMI sample clock is run at every PCLKB/32 cycle */
|
||||
#define _ICU_DMAINT2_FILTER_PCLKB_64 (0x03U) /* NMI sample clock is run at every PCLKB/64 cycle */
|
||||
|
||||
/*
|
||||
NMI Pin Digital Noise Filter Setting Register (NMIFLTC)
|
||||
*/
|
||||
/* NMI Digital Noise Filter Sampling Clock (NFCLKSEL[1:0]) */
|
||||
#define _ICU_NMI_FILTER_PCLKB (0x00U) /* NMI sample clock is run at every PCLKB cycle */
|
||||
#define _ICU_NMI_FILTER_PCLKB_8 (0x01U) /* NMI sample clock is run at every PCLKB/8 cycle */
|
||||
#define _ICU_NMI_FILTER_PCLKB_32 (0x02U) /* NMI sample clock is run at every PCLKB/32 cycle */
|
||||
#define _ICU_NMI_FILTER_PCLKB_64 (0x03U) /* NMI sample clock is run at every PCLKB/64 cycle */
|
||||
|
||||
/*
|
||||
EtherPHY Control Register i (EPHYCRi) (i = 0 to 2)
|
||||
*/
|
||||
/* EtherPHYn interrupt Detection Setting (EPHYMD[1:0]) */
|
||||
#define _ICU_ETHERPHY0_EDGE_LOW_LEVEL (0x00U) /* Low level */
|
||||
#define _ICU_ETHERPHY0_EDGE_FALLING (0x01U) /* Falling edge */
|
||||
#define _ICU_ETHERPHY0_EDGE_RISING (0x02U) /* Rising edge */
|
||||
#define _ICU_ETHERPHY0_EDGE_BOTH (0x03U) /* Rising and falling edge */
|
||||
#define _ICU_ETHERPHY1_EDGE_LOW_LEVEL (0x00U) /* Low level */
|
||||
#define _ICU_ETHERPHY1_EDGE_FALLING (0x01U) /* Falling edge */
|
||||
#define _ICU_ETHERPHY1_EDGE_RISING (0x02U) /* Rising edge */
|
||||
#define _ICU_ETHERPHY1_EDGE_BOTH (0x03U) /* Rising and falling edge */
|
||||
#define _ICU_ETHERPHY2_EDGE_LOW_LEVEL (0x00U) /* Low level */
|
||||
#define _ICU_ETHERPHY2_EDGE_FALLING (0x01U) /* Falling edge */
|
||||
#define _ICU_ETHERPHY2_EDGE_RISING (0x02U) /* Rising edge */
|
||||
#define _ICU_ETHERPHY2_EDGE_BOTH (0x03U) /* Rising and falling edge */
|
||||
|
||||
/*
|
||||
EtherPHY Interrupt Request Pin Digital Noise Filter Enable Register 0 (EPHYFLTE)
|
||||
*/
|
||||
/* EtherPHYn Interrupt Digital Noise Filter Enable (EFLTENn) */
|
||||
#define _ICU_ETHERPHYn_FILTER_DISABLE (0x00U) /* ETHER PHY0 digital noise filter is disabled */
|
||||
#define _ICU_ETHERPHY0_FILTER_ENABLE (0x01U) /* ETHER PHY0 digital noise filter is enabled */
|
||||
#define _ICU_ETHERPHY1_FILTER_ENABLE (0x01U) /* ETHER PHY1 digital noise filter is enabled */
|
||||
#define _ICU_ETHERPHY2_FILTER_ENABLE (0x01U) /* ETHER PHY2 digital noise filter is enabled */
|
||||
|
||||
/*
|
||||
EtherPHY Interrupt Request Pin Digital Filter Setting Register (EPHYFLTC)
|
||||
*/
|
||||
/* EtherPHYn Interrupts Digital Noise Filter Sampling Clock (EFCLKSELn[1:0]) */
|
||||
#define _ICU_ETHPHYI0_FILTER_PCLKB (0x00U) /* ETHER PHY0 sample clock is run at every PCLKB cycle */
|
||||
#define _ICU_ETHPHYI0_FILTER_PCLKB_8 (0x01U) /* ETHER PHY0 sample clock is run at every PCLKB/8 cycle */
|
||||
#define _ICU_ETHPHYI0_FILTER_PCLKB_32 (0x02U) /* ETHER PHY0 sample clock is run at every PCLKB/32 cycle */
|
||||
#define _ICU_ETHPHYI0_FILTER_PCLKB_64 (0x03U) /* ETHER PHY0 sample clock is run at every PCLKB/64 cycle */
|
||||
#define _ICU_ETHPHYI1_FILTER_PCLKB (0x00U) /* ETHER PHY1 sample clock is run at every PCLKB cycle */
|
||||
#define _ICU_ETHPHYI1_FILTER_PCLKB_8 (0x01U) /* ETHER PHY1 sample clock is run at every PCLKB/8 cycle */
|
||||
#define _ICU_ETHPHYI1_FILTER_PCLKB_32 (0x02U) /* ETHER PHY1 sample clock is run at every PCLKB/32 cycle */
|
||||
#define _ICU_ETHPHYI1_FILTER_PCLKB_64 (0x03U) /* ETHER PHY1 sample clock is run at every PCLKB/64 cycle */
|
||||
#define _ICU_ETHPHYI2_FILTER_PCLKB (0x00U) /* ETHER PHY2 sample clock is run at every PCLKB cycle */
|
||||
#define _ICU_ETHPHYI2_FILTER_PCLKB_8 (0x01U) /* ETHER PHY2 sample clock is run at every PCLKB/8 cycle */
|
||||
#define _ICU_ETHPHYI2_FILTER_PCLKB_32 (0x02U) /* ETHER PHY2 sample clock is run at every PCLKB/32 cycle */
|
||||
#define _ICU_ETHPHYI2_FILTER_PCLKB_64 (0x03U) /* ETHER PHY2 sample clock is run at every PCLKB/64 cycle */
|
||||
|
||||
/*
|
||||
External DMA Request Pin Digital Noise Enable Register (DREQFLTE)
|
||||
*/
|
||||
/* DREQn Digital Noise Filter Enable (DFLTENn) */
|
||||
#define _ICU_DREQn_FILTER_DISABLE (0x00U) /* Digital noise filter is disabled */
|
||||
#define _ICU_DREQ0_FILTER_ENABLE (0x01U) /* DREQ0 Digital noise filter is enabled */
|
||||
#define _ICU_DREQ1_FILTER_ENABLE (0x01U) /* DREQ1 Digital noise filter is enabled */
|
||||
#define _ICU_DREQ2_FILTER_ENABLE (0x01U) /* DREQ2 Digital noise filter is enabled */
|
||||
|
||||
/*
|
||||
External DMA Request Pin Digital Noise Setting Register (DREQFLTC)
|
||||
*/
|
||||
/* DREQn Digital Noise Filter Sampling Clock (DFCLKSELn[1:0]) */
|
||||
#define _ICU_DREQ0_FILTER_PCLKB (0x00U) /* DREQ0 sample clock is run at every PCLKB cycle */
|
||||
#define _ICU_DREQ0_FILTER_PCLKB_8 (0x01U) /* DREQ0 sample clock is run at every PCLKB/8 cycle */
|
||||
#define _ICU_DREQ0_FILTER_PCLKB_32 (0x02U) /* DREQ0 sample clock is run at every PCLKB/32 cycle */
|
||||
#define _ICU_DREQ0_FILTER_PCLKB_64 (0x03U) /* DREQ0 sample clock is run at every PCLKB/64 cycle */
|
||||
#define _ICU_DREQ1_FILTER_PCLKB (0x00U) /* DREQ1 sample clock is run at every PCLKB cycle */
|
||||
#define _ICU_DREQ1_FILTER_PCLKB_8 (0x01U) /* DREQ1 sample clock is run at every PCLKB/8 cycle */
|
||||
#define _ICU_DREQ1_FILTER_PCLKB_32 (0x02U) /* DREQ1 sample clock is run at every PCLKB/32 cycle */
|
||||
#define _ICU_DREQ1_FILTER_PCLKB_64 (0x03U) /* DREQ1 sample clock is run at every PCLKB/64 cycle */
|
||||
#define _ICU_DREQ2_FILTER_PCLKB (0x00U) /* DREQ2 sample clock is run at every PCLKB cycle */
|
||||
#define _ICU_DREQ2_FILTER_PCLKB_8 (0x01U) /* DREQ2 sample clock is run at every PCLKB/8 cycle */
|
||||
#define _ICU_DREQ2_FILTER_PCLKB_32 (0x02U) /* DREQ2 sample clock is run at every PCLKB/32 cycle */
|
||||
#define _ICU_DREQ2_FILTER_PCLKB_64 (0x03U) /* DREQ2 sample clock is run at every PCLKB/64 cycle */
|
||||
|
||||
/*
|
||||
User Mode Enable Register 0 (UEN0)
|
||||
*/
|
||||
/* Interrupt control register access selection (UE) */
|
||||
#define _ICU_UEN0_CTRL_REG_ACCESS_DISABLE (0x00000000UL) /* Disables access in user mode. */
|
||||
#define _ICU_UEN0_CTRL_REG_ACCESS_ENABLE (0x00000001UL) /* Enables access in user mode. */
|
||||
|
||||
/*
|
||||
User Mode Enable Register 1 (UEN1)
|
||||
*/
|
||||
/* Interrupt control register access selection (UE) */
|
||||
#define _ICU_UEN1_CTRL_REG_ACCESS_DISABLE (0x00000000UL) /* Disables access in user mode. */
|
||||
#define _ICU_UEN1_CTRL_REG_ACCESS_ENABLE (0x00000001UL) /* Enables access in user mode. */
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_ICU_Create(void);
|
||||
void R_ICU_IRQ12_Start(void);
|
||||
void R_ICU_IRQ12_Stop(void);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
|
||||
#define SW1_PRESS_FLG (0x01)
|
||||
#define SW2_PRESS_FLG (0x02)
|
||||
#define SW3_PRESS_FLG (0x04)
|
||||
|
||||
#define SW1_HELD_FLG (0x10)
|
||||
#define SW2_HELD_FLG (0x20)
|
||||
#define SW3_HELD_FLG (0x40)
|
||||
|
||||
#define SW1_SET_FLG_MASK (0xEE)
|
||||
#define SW2_SET_FLG_MASK (0xDD)
|
||||
#define SW3_SET_FLG_MASK (0xBB)
|
||||
|
||||
#define SW_ALL_OFF (0xF8)
|
||||
|
||||
#define SW1_INPUT_STATE (PORT3.PIDR.BIT.B5)
|
||||
#define SW2_INPUT_STATE (PORTN.PIDR.BIT.B5)
|
||||
#define SW3_INPUT_STATE (PORT4.PIDR.BIT.B4)
|
||||
|
||||
#define SW1_OUTPUT_PIN (PORT3.PODR.BIT.B5)
|
||||
#define SW2_OUTPUT_PIN (PORTN.PODR.BIT.B5)
|
||||
#define SW3_OUTPUT_PIN (PORT4.PODR.BIT.B4)
|
||||
|
||||
/* Stores switch states detected via interrupts */
|
||||
extern volatile uint8_t g_switch_press_flg;
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
@ -0,0 +1,73 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_icu_user.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for ICU module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_icu.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
|
||||
/* Stores switch states detected via interrupts */
|
||||
volatile uint8_t g_switch_press_flg = 0u;
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_icu_irq12_interrupt
|
||||
* Description : This function handles the irqn pin interrupt.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_icu_irq12_interrupt(void)
|
||||
{
|
||||
VIC.PIC0.LONG = 0x00010000UL;
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
|
||||
/* Set global switch flag to indicate SW3 is pressed */
|
||||
g_switch_press_flg |= SW3_PRESS_FLG;
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
VIC.HVA0.LONG = 0x00000000UL;
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@ -0,0 +1,83 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_interrupthandlers.h
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file declares interrupt handlers.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
#ifndef INTERRUPT_HANDLERS_H
|
||||
#define INTERRUPT_HANDLERS_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
/* FIQ exception handler */
|
||||
void r_fiq_handler(void) __attribute__((interrupt ("FIQ")));
|
||||
|
||||
/* ICU IRQ12 */
|
||||
void r_icu_irq12_interrupt(void) __attribute__((interrupt ("IRQ")));
|
||||
|
||||
/* ADC Unit0 S12ADI0 */
|
||||
void r_s12ad_s12adi0_interrupt(void) __attribute__((interrupt ("IRQ")));
|
||||
|
||||
/* RSPI1 SPTI1 */
|
||||
void r_rspi1_transmit_interrupt(void) __attribute__((interrupt ("IRQ")));
|
||||
|
||||
/* RSPI1 SPEI1 */
|
||||
void r_rspi1_error_interrupt(void) __attribute__((interrupt ("IRQ")));
|
||||
|
||||
/* RSPI1 SPII1 */
|
||||
void r_rspi1_idle_interrupt(void) __attribute__((interrupt ("IRQ")));
|
||||
|
||||
/* SCIFA TXIF2 */
|
||||
void r_scifa2_txif2_interrupt(void) __attribute__((interrupt ("IRQ")));
|
||||
|
||||
/* SCIFA DRIF2 */
|
||||
void r_scifa2_drif2_interrupt(void) __attribute__((interrupt ("IRQ")));
|
||||
|
||||
/* SCIFA RXIF2 */
|
||||
void r_scifa2_rxif2_interrupt(void) __attribute__((interrupt ("IRQ")));
|
||||
|
||||
/* SCIFA BRIF2 */
|
||||
void r_scifa2_brif2_interrupt(void) __attribute__((interrupt ("IRQ")));
|
||||
|
||||
/* CMT CMI4 */
|
||||
void r_cmt_cmi4_interrupt(void) __attribute__((interrupt ("IRQ")));
|
||||
|
||||
/* CMT CMI5 */
|
||||
void r_cmt_cmi5_interrupt(void) __attribute__((interrupt ("IRQ")));
|
||||
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,84 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_intprg.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : Set the non-maskable interrupt.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_set_exception_handler
|
||||
* Description : None
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_set_exception_handler(void)
|
||||
{
|
||||
uint32_t *pointer;
|
||||
|
||||
/* FIQ exception handler address */
|
||||
pointer = (uint32_t *)0x1c;
|
||||
|
||||
/* Branch to next address instruction */
|
||||
*pointer ++ = 0xeaffffff;
|
||||
|
||||
/* LDR PC,[PC, #-0x04], load r_fiq_handler address to PC */
|
||||
*pointer ++ = 0xe51ff004;
|
||||
|
||||
/* DC32 r_fiq_handler, define the r_fiq_handler address */
|
||||
*pointer = (uint32_t)r_fiq_handler;
|
||||
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_fiq_handler
|
||||
* Description : None
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_fiq_handler(void)
|
||||
{
|
||||
while(1);
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@ -0,0 +1,145 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_macrodriver.h
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements general head file.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
#ifndef MODULEID_H
|
||||
#define MODULEID_H
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "iodefine.h"
|
||||
#include "r_cg_interrupthandlers.h"
|
||||
#include "r_cg_mpc.h"
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#ifndef __TYPEDEF__
|
||||
#define DI() asm("cpsid i") /* Disable IRQ interrupt (Set CPSR.I bit to 1) */
|
||||
#define EI() asm("cpsie i") /* Enable IRQ interrupt (Clear CPSR.I bit to 0) */
|
||||
#define nop() asm("nop")
|
||||
|
||||
/* Status list definition */
|
||||
#define MD_STATUSBASE (0x00U)
|
||||
#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */
|
||||
#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */
|
||||
#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */
|
||||
#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */
|
||||
#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */
|
||||
|
||||
/* Error list definition */
|
||||
#define MD_ERRORBASE (0x80U)
|
||||
#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */
|
||||
#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */
|
||||
#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */
|
||||
#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */
|
||||
#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */
|
||||
#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */
|
||||
#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */
|
||||
|
||||
/* MSTP macro definition */
|
||||
#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPCRA0
|
||||
#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPCRA1
|
||||
#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPCRA2
|
||||
#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPCRA3
|
||||
#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPCRA4
|
||||
#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPCRA5
|
||||
#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPCRA6
|
||||
#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPCRA7
|
||||
#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPCRA8
|
||||
#define MSTP_GPTA SYSTEM.MSTPCRA.BIT.MSTPCRA9
|
||||
#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPCRA11
|
||||
|
||||
#define MSTP_RSCAN SYSTEM.MSTPCRB.BIT.MSTPCRB1
|
||||
#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPCRB2
|
||||
#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPCRB3
|
||||
#define MSTP_SCIFA4 SYSTEM.MSTPCRB.BIT.MSTPCRB5
|
||||
#define MSTP_SCIFA3 SYSTEM.MSTPCRB.BIT.MSTPCRB6
|
||||
#define MSTP_SCIFA2 SYSTEM.MSTPCRB.BIT.MSTPCRB7
|
||||
#define MSTP_SCIFA1 SYSTEM.MSTPCRB.BIT.MSTPCRB8
|
||||
#define MSTP_SCIFA0 SYSTEM.MSTPCRB.BIT.MSTPCRB9
|
||||
#define MSTP_RSPI3 SYSTEM.MSTPCRB.BIT.MSTPCRB10
|
||||
#define MSTP_RSPI2 SYSTEM.MSTPCRB.BIT.MSTPCRB11
|
||||
#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPCRB12
|
||||
#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPCRB13
|
||||
#define MSTP_ETHERSW SYSTEM.MSTPCRB.BIT.MSTPCRB14
|
||||
#define MSTP_ECATC SYSTEM.MSTPCRB.BIT.MSTPCRB15
|
||||
#define MSTP_EMDIO SYSTEM.MSTPCRB.BIT.MSTPCRB16
|
||||
#define MSTP_ERMII SYSTEM.MSTPCRB.BIT.MSTPCRB17
|
||||
#define MSTP_HWRTOS SYSTEM.MSTPCRB.BIT.MSTPCRB18
|
||||
#define MSTP_CLKOUT25M SYSTEM.MSTPCRB.BIT.MSTPCRB19
|
||||
|
||||
#define MSTP_USB SYSTEM.MSTPCRC.BIT.MSTPCRC1
|
||||
#define MSTP_DSMIF SYSTEM.MSTPCRC.BIT.MSTPCRC2
|
||||
#define MSTP_TEMPS SYSTEM.MSTPCRC.BIT.MSTPCRC3
|
||||
#define MSTP_S12ADC1 SYSTEM.MSTPCRC.BIT.MSTPCRC4
|
||||
#define MSTP_S12ADC0 SYSTEM.MSTPCRC.BIT.MSTPCRC5
|
||||
#define MSTP_ELC SYSTEM.MSTPCRC.BIT.MSTPCRC6
|
||||
#define MSTP_BSC SYSTEM.MSTPCRC.BIT.MSTPCRC7
|
||||
#define MSTP_CKIO SYSTEM.MSTPCRC.BIT.MSTPCRC8
|
||||
#define MSTP_SPIBSC SYSTEM.MSTPCRC.BIT.MSTPCRC9
|
||||
#define MSTP_DOC SYSTEM.MSTPCRC.BIT.MSTPCRC10
|
||||
#define MSTP_CRC SYSTEM.MSTPCRC.BIT.MSTPCRC11
|
||||
#define MSTP_CLMA2 SYSTEM.MSTPCRC.BIT.MSTPCRC12
|
||||
#define MSTP_CLMA1 SYSTEM.MSTPCRC.BIT.MSTPCRC13
|
||||
#define MSTP_CLMA0 SYSTEM.MSTPCRC.BIT.MSTPCRC14
|
||||
|
||||
#define MSTP_SSI SYSTEM.MSTPCRD.BIT.MSTPCRD2
|
||||
|
||||
#define MSTP_DMAC1 SYSTEM.MSTPCRE.BIT.MSTPCRE4
|
||||
#define MSTP_DMAC0 SYSTEM.MSTPCRE.BIT.MSTPCRE5
|
||||
|
||||
#define MSTP_CORESIGHT SYSTEM.MSTPCRF.BIT.MSTPCRF0
|
||||
|
||||
#define __MSTP( x ) MSTP ## x
|
||||
#define _MSTP( x ) __MSTP( x )
|
||||
#define MSTP( x ) _MSTP( _ ## x )
|
||||
#endif
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
#ifndef __TYPEDEF__
|
||||
typedef signed char int8_t;
|
||||
typedef unsigned char uint8_t;
|
||||
typedef signed short int16_t;
|
||||
typedef unsigned short uint16_t;
|
||||
typedef signed long int32_t;
|
||||
typedef unsigned long uint32_t;
|
||||
typedef unsigned short MD_STATUS;
|
||||
#define __TYPEDEF__
|
||||
#endif
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#endif
|
||||
155
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_mpc.c
Normal file
155
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_mpc.c
Normal file
@ -0,0 +1,155 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_mpc.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : Setting of port and mpc registers.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
#include "r_typedefs.h"
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_mpc.h"
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_MPC_Create
|
||||
* Description : This function initializes the Port I/O.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_MPC_Create(void)
|
||||
{
|
||||
/* Set RSPCK1 pin */
|
||||
MPC.PN3PFS.BYTE |= 0x0EU;
|
||||
PORTN.PMR.BYTE |= 0x08U;
|
||||
/* Set MOSI1 pin */
|
||||
MPC.PN2PFS.BYTE |= 0x0EU;
|
||||
PORTN.PMR.BYTE |= 0x04U;
|
||||
/* Set MISO1 pin */
|
||||
MPC.PN1PFS.BYTE |= 0x0EU;
|
||||
PORTN.PMR.BYTE |= 0x02U;
|
||||
/* Set SSL10 pin */
|
||||
MPC.PN0PFS.BYTE |= 0x0EU;
|
||||
PORTN.PMR.BYTE |= 0x01U;
|
||||
/* Set SSL11 pin */
|
||||
MPC.PN4PFS.BYTE |= 0x0EU;
|
||||
PORTN.PMR.BYTE |= 0x10U;
|
||||
/* Set TXD2 pin */
|
||||
MPC.P91PFS.BYTE |= 0x0BU;
|
||||
PORT9.PMR.BYTE |= 0x02U;
|
||||
/* Set RXD2 pin */
|
||||
MPC.P92PFS.BYTE |= 0x0BU;
|
||||
PORT9.PMR.BYTE |= 0x04U;
|
||||
/* Set IRQ12 pin */
|
||||
MPC.P44PFS.BYTE |= 0x40U;
|
||||
PORT4.PMR.BYTE &= 0xEFU;
|
||||
PORT4.PDR.WORD &= 0xFEFFU;
|
||||
PORT4.PDR.WORD |= 0x0200U;
|
||||
/* Set TIOCB9 pin */
|
||||
MPC.PL0PFS.BYTE |= 0x03U;
|
||||
PORTL.PMR.BYTE |= 0x01U;
|
||||
/* Set TIOCC9 pin */
|
||||
MPC.PU4PFS.BYTE |= 0x03U;
|
||||
PORTU.PMR.BYTE |= 0x10U;
|
||||
/* Set TIOCD9 pin */
|
||||
MPC.PN5PFS.BYTE |= 0x03U;
|
||||
PORTN.PMR.BYTE |= 0x20U;
|
||||
|
||||
R_MPC_Create_UserInit();
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_MPC_Create_UserInit
|
||||
* Description : This function adds user code after initializing modules pin setting.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_MPC_Create_UserInit(void)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : R_MPC_WriteEnable
|
||||
* Description : Enables writing to the PmnPFS register (m = 0-9, A-U, n = 0-7).
|
||||
And dummy read the register in order to fix the register value.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void R_MPC_WriteEnable(void)
|
||||
{
|
||||
volatile uint8_t dummy;
|
||||
|
||||
UNUSED_VARIABLE(dummy);
|
||||
|
||||
/* Enables writing to the PmnPFS register */
|
||||
MPC.PWPR.BYTE = MPC_PFSWE_WRITE_ENABLE;
|
||||
dummy = MPC.PWPR.BYTE;
|
||||
MPC.PWPR.BYTE = MPC_PFS_WRITE_ENABLE;
|
||||
dummy = MPC.PWPR.BYTE;
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function R_MPC_WriteEnable
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name : R_MPC_WriteDisable
|
||||
* Description : Disables writing to the PmnPFS register (m = 0-9, A-U, n = 0-7).
|
||||
And dummy read the register in order to fix the register value.
|
||||
* Arguments : none
|
||||
* Return Value : none
|
||||
***********************************************************************************************************************/
|
||||
void R_MPC_WriteDisable(void)
|
||||
{
|
||||
volatile uint8_t dummy;
|
||||
|
||||
UNUSED_PARAM(dummy);
|
||||
|
||||
/* Disables writing to the PmnPFS register */
|
||||
MPC.PWPR.BYTE = MPC_PFS_WRITE_DISABLE;
|
||||
dummy = MPC.PWPR.BYTE;
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
End of function R_MPC_WriteDisable
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@ -0,0 +1,49 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_mpc.h
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : Header file of mpc file.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
#ifndef _MPC_H
|
||||
#define _MPC_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_MPC_Create(void);
|
||||
void R_MPC_Create_UserInit(void);
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,69 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_port.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for Port module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_port.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_PORT_Create
|
||||
* Description : This function initializes the Port I/O.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_PORT_Create(void)
|
||||
{
|
||||
PORT5.PODR.BYTE = _Pm1_OUTPUT_1;
|
||||
PORT6.PODR.BYTE = _Pm7_OUTPUT_1;
|
||||
PORT5.PDR.WORD = _Pm1_MODE_OUTPUT | _Pm6_MODE_OUTPUT;
|
||||
PORT6.PDR.WORD = _Pm7_MODE_OUTPUT;
|
||||
PORT7.PDR.WORD = _Pm4_MODE_OUTPUT | _Pm6_MODE_OUTPUT | _Pm7_MODE_OUTPUT;
|
||||
PORTA.PDR.WORD = _Pm0_MODE_OUTPUT;
|
||||
PORTF.PDR.WORD = _Pm7_MODE_OUTPUT;
|
||||
PORTM.PDR.WORD = _Pm2_MODE_OUTPUT | _Pm3_MODE_OUTPUT;
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
135
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port.h
Normal file
135
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port.h
Normal file
@ -0,0 +1,135 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_port.h
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for Port module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
#ifndef PORT_H
|
||||
#define PORT_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
/*
|
||||
Port Direction Register (PDR)
|
||||
*/
|
||||
/* Pmn Direction Control (B0 - B15) */
|
||||
#define _Pm0_MODE_NOT_USED (0x0000U) /* Pm0 not used (Hi-z input protection) */
|
||||
#define _Pm0_MODE_INPUT (0x0002U) /* Pm0 as input */
|
||||
#define _Pm0_MODE_OUTPUT (0x0003U) /* Pm0 as output */
|
||||
#define _Pm1_MODE_NOT_USED (0x0000U) /* Pm1 not used (Hi-z input protection) */
|
||||
#define _Pm1_MODE_INPUT (0x0008U) /* Pm1 as input */
|
||||
#define _Pm1_MODE_OUTPUT (0x000CU) /* Pm1 as output */
|
||||
#define _Pm2_MODE_NOT_USED (0x0000U) /* Pm2 not used (Hi-z input protection) */
|
||||
#define _Pm2_MODE_INPUT (0x0020U) /* Pm2 as input */
|
||||
#define _Pm2_MODE_OUTPUT (0x0030U) /* Pm2 as output */
|
||||
#define _Pm3_MODE_NOT_USED (0x0000U) /* Pm3 not used (Hi-z input protection) */
|
||||
#define _Pm3_MODE_INPUT (0x0080U) /* Pm3 as input */
|
||||
#define _Pm3_MODE_OUTPUT (0x00C0U) /* Pm3 as output */
|
||||
#define _Pm4_MODE_NOT_USED (0x0000U) /* Pm4 not used (Hi-z input protection) */
|
||||
#define _Pm4_MODE_INPUT (0x0200U) /* Pm4 as input */
|
||||
#define _Pm4_MODE_OUTPUT (0x0300U) /* Pm4 as output */
|
||||
#define _Pm5_MODE_NOT_USED (0x0000U) /* Pm5 not used (Hi-z input protection) */
|
||||
#define _Pm5_MODE_INPUT (0x0800U) /* Pm5 as input */
|
||||
#define _Pm5_MODE_OUTPUT (0x0C00U) /* Pm5 as output */
|
||||
#define _Pm6_MODE_NOT_USED (0x0000U) /* Pm6 not used (Hi-z input protection) */
|
||||
#define _Pm6_MODE_INPUT (0x2000U) /* Pm6 as input */
|
||||
#define _Pm6_MODE_OUTPUT (0x3000U) /* Pm6 as output */
|
||||
#define _Pm7_MODE_NOT_USED (0x0000U) /* Pm7 not used (Hi-z input protection) */
|
||||
#define _Pm7_MODE_INPUT (0x8000U) /* Pm7 as input */
|
||||
#define _Pm7_MODE_OUTPUT (0xC000U) /* Pm7 as output */
|
||||
|
||||
/*
|
||||
Port Output Data Register (PODR)
|
||||
*/
|
||||
/* Pmn Output Data Store (B0 - B7) */
|
||||
#define _Pm0_OUTPUT_0 (0x00U) /* Output low at B0 */
|
||||
#define _Pm0_OUTPUT_1 (0x01U) /* Output high at B0 */
|
||||
#define _Pm1_OUTPUT_0 (0x00U) /* Output low at B1 */
|
||||
#define _Pm1_OUTPUT_1 (0x02U) /* Output high at B1 */
|
||||
#define _Pm2_OUTPUT_0 (0x00U) /* Output low at B2 */
|
||||
#define _Pm2_OUTPUT_1 (0x04U) /* Output high at B2 */
|
||||
#define _Pm3_OUTPUT_0 (0x00U) /* Output low at B3 */
|
||||
#define _Pm3_OUTPUT_1 (0x08U) /* Output high at B3 */
|
||||
#define _Pm4_OUTPUT_0 (0x00U) /* Output low at B4 */
|
||||
#define _Pm4_OUTPUT_1 (0x10U) /* Output high at B4 */
|
||||
#define _Pm5_OUTPUT_0 (0x00U) /* Output low at B5 */
|
||||
#define _Pm5_OUTPUT_1 (0x20U) /* Output high at B5 */
|
||||
#define _Pm6_OUTPUT_0 (0x00U) /* Output low at B6 */
|
||||
#define _Pm6_OUTPUT_1 (0x40U) /* Output high at B6 */
|
||||
#define _Pm7_OUTPUT_0 (0x00U) /* Output low at B7 */
|
||||
#define _Pm7_OUTPUT_1 (0x80U) /* Output high at B7 */
|
||||
|
||||
/*
|
||||
Pull-Up/Pull-Down Control Register (PCR)
|
||||
*/
|
||||
/* Pmn Input Pull-Up Resistor Control (B0 - B15) */
|
||||
#define _Pm0_PULLUPDOWN_DISABLE (0x0000U) /* Pm0 pull-up resistor and pull-down resistor not connected */
|
||||
#define _Pm0_PULLUPDOWN_PULLDOWN_ON (0x0001U) /* Pm0 pull-down resistor connected */
|
||||
#define _Pm0_PULLUPDOWN_PULLUP_ON (0x0002U) /* Pm0 pull-up resistor connected */
|
||||
#define _Pm1_PULLUPDOWN_DISABLE (0x0000U) /* Pm1 pull-up resistor and pull-down resistor not connected */
|
||||
#define _Pm1_PULLUPDOWN_PULLDOWN_ON (0x0004U) /* Pm1 pull-down resistor connected */
|
||||
#define _Pm1_PULLUPDOWN_PULLUP_ON (0x0008U) /* Pm1 pull-up resistor connected */
|
||||
#define _Pm2_PULLUPDOWN_DISABLE (0x0000U) /* Pm2 pull-up resistor and pull-down resistor not connected */
|
||||
#define _Pm2_PULLUPDOWN_PULLDOWN_ON (0x0010U) /* Pm2 pull-down resistor connected */
|
||||
#define _Pm2_PULLUPDOWN_PULLUP_ON (0x0020U) /* Pm2 pull-up resistor connected */
|
||||
#define _Pm3_PULLUPDOWN_DISABLE (0x0000U) /* Pm3 pull-up resistor and pull-down resistor not connected */
|
||||
#define _Pm3_PULLUPDOWN_PULLDOWN_ON (0x0040U) /* Pm3 pull-down resistor connected */
|
||||
#define _Pm3_PULLUPDOWN_PULLUP_ON (0x0080U) /* Pm3 pull-up resistor connected */
|
||||
#define _Pm4_PULLUPDOWN_DISABLE (0x0000U) /* Pm4 pull-up resistor and pull-down resistor not connected */
|
||||
#define _Pm4_PULLUPDOWN_PULLDOWN_ON (0x0100U) /* Pm4 pull-down resistor connected */
|
||||
#define _Pm4_PULLUPDOWN_PULLUP_ON (0x0200U) /* Pm4 pull-up resistor connected */
|
||||
#define _Pm5_PULLUPDOWN_DISABLE (0x0000U) /* Pm5 pull-up resistor and pull-down resistor not connected */
|
||||
#define _Pm5_PULLUPDOWN_PULLDOWN_ON (0x0400U) /* Pm5 pull-down resistor connected */
|
||||
#define _Pm5_PULLUPDOWN_PULLUP_ON (0x0800U) /* Pm5 pull-up resistor connected */
|
||||
#define _Pm6_PULLUPDOWN_DISABLE (0x0000U) /* Pm6 pull-up resistor and pull-down resistor not connected */
|
||||
#define _Pm6_PULLUPDOWN_PULLDOWN_ON (0x1000U) /* Pm6 pull-down resistor connected */
|
||||
#define _Pm6_PULLUPDOWN_PULLUP_ON (0x2000U) /* Pm6 pull-up resistor connected */
|
||||
#define _Pm7_PULLUPDOWN_DISABLE (0x0000U) /* Pm7 pull-up resistor and pull-down resistor not connected */
|
||||
#define _Pm7_PULLUPDOWN_PULLDOWN_ON (0x4000U) /* Pm7 pull-down resistor connected */
|
||||
#define _Pm7_PULLUPDOWN_PULLUP_ON (0x8000U) /* Pm7 pull-up resistor connected */
|
||||
|
||||
/*
|
||||
Drive Capacity Control Register (DSCR)
|
||||
*/
|
||||
/* P10 Drive Capacity Control (B0) */
|
||||
#define _Pm0_HIDRV_OFF (0x0000U) /* P10 Normal drive output */
|
||||
#define _Pm0_HIDRV_ON (0x0001U) /* P10 High-drive output */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_PORT_Create(void);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
@ -0,0 +1,52 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_port_user.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for Port module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_port.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
196
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi.c
Normal file
196
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi.c
Normal file
@ -0,0 +1,196 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_rspi.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for RSPI module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_rspi.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
const uint32_t * gp_rspi1_tx_address; /* RSPI1 transmit buffer address */
|
||||
uint16_t g_rspi1_tx_count; /* RSPI1 transmit data number */
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_RSPI1_Create
|
||||
* Description : This function initializes the RSPI1 module.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_RSPI1_Create(void)
|
||||
{
|
||||
/* Disable RSPI interrupts */
|
||||
VIC.IEC2.LONG = 0x00200000UL; /* Disable SPTI1 interrupt */
|
||||
VIC.IEC2.LONG = 0x00400000UL; /* Disable SPEI1 interrupt */
|
||||
VIC.IEC2.LONG = 0x00800000UL; /* Disable SPII1 interrupt */
|
||||
|
||||
/* Set interrupt detection type */
|
||||
VIC.PLS2.LONG |= 0x00200000UL; /* Set SPTI1 edge detection interrupt */
|
||||
|
||||
/* Cancel RSPI module stop state */
|
||||
MSTP(RSPI1) = 0U;
|
||||
|
||||
/* Disable RSPI function */
|
||||
RSPI1.SPCR.BIT.SPE = 0U;
|
||||
|
||||
/* Set control registers */
|
||||
RSPI1.SPPCR.BYTE = _RSPI_MOSI_LEVEL_HIGH | _RSPI_MOSI_FIXING_MOIFV_BIT | _RSPI_OUTPUT_PIN_CMOS | _RSPI_LOOPBACK_DISABLED | _RSPI_LOOPBACK2_DISABLED;
|
||||
RSPI1.SPBR = _RSPI1_DIVISOR;
|
||||
RSPI1.SPDCR.BYTE = _RSPI_ACCESS_LONGWORD | _RSPI_FRAMES_1;
|
||||
RSPI1.SPSCR.BYTE = _RSPI_SEQUENCE_LENGTH_1;
|
||||
RSPI1.SSLP.BYTE = _RSPI_SSL0_POLARITY_LOW | _RSPI_SSL1_POLARITY_LOW;
|
||||
RSPI1.SPCKD.BYTE = _RSPI_RSPCK_DELAY_1;
|
||||
RSPI1.SSLND.BYTE = _RSPI_SSL_NEGATION_DELAY_1;
|
||||
RSPI1.SPND.BYTE = _RSPI_NEXT_ACCESS_DELAY_1;
|
||||
RSPI1.SPCR2.BYTE = _RSPI_PARITY_DISABLE;
|
||||
RSPI1.SPCMD0.WORD = _RSPI_RSPCK_SAMPLING_EVEN | _RSPI_RSPCK_POLARITY_HIGH | _RSPI_BASE_BITRATE_1 |
|
||||
_RSPI_SIGNAL_ASSERT_SSL0 | _RSPI_SSL_KEEP_DISABLE | _RSPI_DATA_LENGTH_BITS_8 |
|
||||
_RSPI_MSB_FIRST | _RSPI_NEXT_ACCESS_DELAY_DISABLE | _RSPI_NEGATION_DELAY_DISABLE |
|
||||
_RSPI_RSPCK_DELAY_DISABLE;
|
||||
|
||||
/* Set SPTI1 priority level */
|
||||
VIC.PRL85.LONG = _RSPI_PRIORITY_LEVEL6;
|
||||
|
||||
/* Set SPEI1 priority level */
|
||||
VIC.PRL86.LONG = _RSPI_PRIORITY_LEVEL5;
|
||||
|
||||
/* Set SPII1 priority level */
|
||||
VIC.PRL87.LONG = _RSPI_PRIORITY_LEVEL7;
|
||||
|
||||
/* Set SPTI1 interrupt address */
|
||||
VIC.VAD85.LONG = (uint32_t)r_rspi1_transmit_interrupt;
|
||||
|
||||
/* Set SPEI1 interrupt address */
|
||||
VIC.VAD86.LONG = (uint32_t)r_rspi1_error_interrupt;
|
||||
|
||||
/* Set SPII1 interrupt address */
|
||||
VIC.VAD87.LONG = (uint32_t)r_rspi1_idle_interrupt;
|
||||
|
||||
RSPI1.SPCR.BYTE = _RSPI_MODE_SPI | _RSPI_TRANSMIT_ONLY | _RSPI_MASTER_MODE;
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_RSPI1_Start
|
||||
* Description : This function starts the RSPI1 module operation.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_RSPI1_Start(void)
|
||||
{
|
||||
volatile uint8_t dummy;
|
||||
|
||||
/* Enable RSPI interrupts */
|
||||
VIC.IEN2.LONG |= 0x00200000UL; /* Enable SPTI1 interrupt */
|
||||
VIC.IEN2.LONG |= 0x00400000UL; /* Enable SPEI1 interrupt */
|
||||
VIC.IEN2.LONG |= 0x00800000UL; /* Enable SPII1 interrupt */
|
||||
|
||||
/* Clear error sources */
|
||||
dummy = RSPI1.SPSR.BYTE;
|
||||
( void ) dummy;
|
||||
RSPI1.SPSR.BYTE = 0x00U;
|
||||
|
||||
/* Disable idle interrupt */
|
||||
RSPI1.SPCR2.BIT.SPIIE = 0U;
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_RSPI1_Stop
|
||||
* Description : This function stops the RSPI1 module operation.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_RSPI1_Stop(void)
|
||||
{
|
||||
/* Disable RSPI interrupts */
|
||||
VIC.IEC2.LONG = 0x00200000UL; /* Disable SPTI1 interrupt */
|
||||
VIC.IEC2.LONG = 0x00400000UL; /* Disable SPEI1 interrupt */
|
||||
VIC.IEC2.LONG = 0x00800000UL; /* Disable SPII1 interrupt */
|
||||
|
||||
/* Disable RSPI function */
|
||||
RSPI1.SPCR.BIT.SPE = 0U;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_RSPI1_Send
|
||||
* Description : This function sends RSPI1 data.
|
||||
* Arguments : tx_buf -
|
||||
* transfer buffer pointer (not used when data is handled by DMAC)
|
||||
* tx_num -
|
||||
* buffer size
|
||||
* Return Value : status -
|
||||
* MD_OK or MD_ARGERROR
|
||||
***********************************************************************************************************************/
|
||||
MD_STATUS R_RSPI1_Send(const uint32_t * tx_buf, uint16_t tx_num)
|
||||
{
|
||||
MD_STATUS status = MD_OK;
|
||||
|
||||
if (tx_num < 1U)
|
||||
{
|
||||
status = MD_ARGERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
gp_rspi1_tx_address = tx_buf;
|
||||
g_rspi1_tx_count = tx_num;
|
||||
|
||||
/* Enable transmit interrupt */
|
||||
RSPI1.SPCR.BIT.SPTIE = 1U;
|
||||
|
||||
/* Enable error interrupt */
|
||||
RSPI1.SPCR.BIT.SPEIE = 1U;
|
||||
|
||||
/* Enable idle interrupt */
|
||||
RSPI1.SPCR2.BIT.SPIIE = 1U;
|
||||
|
||||
/* Enable RSPI function */
|
||||
RSPI1.SPCR.BIT.SPE = 1U;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
274
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi.h
Normal file
274
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi.h
Normal file
@ -0,0 +1,274 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_rspi.h
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for RSPI module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
#ifndef RSPI_H
|
||||
#define RSPI_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
/*
|
||||
RSPI Control Register (SPCR)
|
||||
*/
|
||||
/* RSPI Mode Select (SPMS) */
|
||||
#define _RSPI_MODE_SPI (0x00U) /* SPI operation (four-wire method) */
|
||||
#define _RSPI_MODE_CLOCK_SYNCHRONOUS (0x01U) /* Clock synchronous operation (three-wire method) */
|
||||
/* Communications Operating Mode Select (TXMD) */
|
||||
#define _RSPI_FULL_DUPLEX_SYNCHRONOUS (0x00U) /* Full-duplex synchronous serial communications */
|
||||
#define _RSPI_TRANSMIT_ONLY (0x02U) /* Serial communications with transmit only operations */
|
||||
/* Mode Fault Error Detection Enable (MODFEN) */
|
||||
#define _RSPI_MODE_FAULT_DETECT_DISABLED (0x00U) /* Disables the detection of mode fault error */
|
||||
#define _RSPI_MODE_FAULT_DETECT_ENABLED (0x04U) /* Enables the detection of mode fault error */
|
||||
/* RSPI Master/Slave Mode Select (MSTR) */
|
||||
#define _RSPI_SLAVE_MODE (0x00U) /* Slave mode */
|
||||
#define _RSPI_MASTER_MODE (0x08U) /* Master mode */
|
||||
/* RSPI Error Interrupt Enable (SPEIE) */
|
||||
#define _RSPI_ERROR_INTERRUPT_DISABLED (0x00U) /* Disables the generation of RSPI error interrupt */
|
||||
#define _RSPI_ERROR_INTERRUPT_ENABLED (0x10U) /* Enables the generation of RSPI error interrupt */
|
||||
/* RSPI Transmit Interrupt Enable (SPTIE) */
|
||||
#define _RSPI_TRANSMIT_INTERRUPT_DISABLED (0x00U) /* Disables the generation of RSPI transmit interrupt */
|
||||
#define _RSPI_TRANSMIT_INTERRUPT_ENABLED (0x20U) /* Enables the generation of RSPI transmit interrupt */
|
||||
/* RSPI Function Enable (SPE) */
|
||||
#define _RSPI_FUNCTION_DISABLED (0x00U) /* Disables the RSPI function */
|
||||
#define _RSPI_FUNCTION_ENABLED (0x40U) /* Enables the RSPI function */
|
||||
/* RSPI Receive Interrupt Enable (SPRIE) */
|
||||
#define _RSPI_RECEIVE_INTERRUPT_DISABLED (0x00U) /* Disables the generation of RSPI receive interrupt */
|
||||
#define _RSPI_RECEIVE_INTERRUPT_ENABLED (0x80U) /* Enables the generation of RSPI receive interrupt */
|
||||
|
||||
/*
|
||||
RSPI Slave Select Polarity Register (SSLP)
|
||||
*/
|
||||
/* SSL0 Signal Polarity Setting (SSL0P) */
|
||||
#define _RSPI_SSL0_POLARITY_LOW (0x00U) /* SSL0 signal is active low */
|
||||
#define _RSPI_SSL0_POLARITY_HIGH (0x01U) /* SSL0 signal is active high */
|
||||
/* SSL1 Signal Polarity Setting (SSL1P) */
|
||||
#define _RSPI_SSL1_POLARITY_LOW (0x00U) /* SSL1 signal is active low */
|
||||
#define _RSPI_SSL1_POLARITY_HIGH (0x02U) /* SSL1 signal is active high */
|
||||
/* SSL2 Signal Polarity Setting (SSL2P) */
|
||||
#define _RSPI_SSL2_POLARITY_LOW (0x00U) /* SSL2 signal is active low */
|
||||
#define _RSPI_SSL2_POLARITY_HIGH (0x04U) /* SSL2 signal is active high */
|
||||
/* SSL3 Signal Polarity Setting (SSL3P) */
|
||||
#define _RSPI_SSL3_POLARITY_LOW (0x00U) /* SSL3 signal is active low */
|
||||
#define _RSPI_SSL3_POLARITY_HIGH (0x08U) /* SSL3 signal is active high */
|
||||
|
||||
/*
|
||||
RSPI Pin Control Register (SPPCR)
|
||||
*/
|
||||
/* RSPI Loopback (SPLP) */
|
||||
#define _RSPI_LOOPBACK_DISABLED (0x00U) /* Normal mode */
|
||||
#define _RSPI_LOOPBACK_ENABLED (0x01U) /* Loopback mode (reversed transmit data = receive data) */
|
||||
/* RSPI Loopback 2 (SPLP2) */
|
||||
#define _RSPI_LOOPBACK2_DISABLED (0x00U) /* Normal mode */
|
||||
#define _RSPI_LOOPBACK2_ENABLED (0x02U) /* Loopback mode (transmit data = receive data) */
|
||||
/* Output pin mode (SPOM) */
|
||||
#define _RSPI_OUTPUT_PIN_CMOS (0x00U) /* CMOS output */
|
||||
#define _RSPI_OUTPUT_PIN_OPEN_DRAIN (0x04U) /* Open-drain output */
|
||||
/* MOSI Idle Fixed Value (MOIFV) */
|
||||
#define _RSPI_MOSI_LEVEL_LOW (0x00U) /* Level output on MOSIA during idling corresponds to low */
|
||||
#define _RSPI_MOSI_LEVEL_HIGH (0x10U) /* Level output on MOSIA during idling corresponds to high */
|
||||
/* MOSI Idle Value Fixing Enable (MOIFE) */
|
||||
#define _RSPI_MOSI_FIXING_PREV_TRANSFER (0x00U) /* MOSI output value equals final data from previous transfer */
|
||||
#define _RSPI_MOSI_FIXING_MOIFV_BIT (0x20U) /* MOSI output value equals the value set in the MOIFV bit */
|
||||
|
||||
/*
|
||||
RSPI Sequence Control Register (SPSCR)
|
||||
*/
|
||||
/* RSPI Sequence Length Specification (SPSLN[2:0]) */
|
||||
#define _RSPI_SEQUENCE_LENGTH_1 (0x00U) /* 0 -> 0... */
|
||||
#define _RSPI_SEQUENCE_LENGTH_2 (0x01U) /* 0 -> 1 -> 0... */
|
||||
#define _RSPI_SEQUENCE_LENGTH_3 (0x02U) /* 0 -> 1 -> 2 -> 0... */
|
||||
#define _RSPI_SEQUENCE_LENGTH_4 (0x03U) /* 0 -> 1 -> 2 -> 3 -> 0... */
|
||||
#define _RSPI_SEQUENCE_LENGTH_5 (0x04U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 0... */
|
||||
#define _RSPI_SEQUENCE_LENGTH_6 (0x05U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 0... */
|
||||
#define _RSPI_SEQUENCE_LENGTH_7 (0x06U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 6 -> 0... */
|
||||
#define _RSPI_SEQUENCE_LENGTH_8 (0x07U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 6 -> 7 -> 0... */
|
||||
|
||||
/*
|
||||
RSPI Data Control Register (SPDCR)
|
||||
*/
|
||||
/* Number of Frames Specification (SPFC[1:0]) */
|
||||
#define _RSPI_FRAMES_1 (0x00U) /* 1 frame */
|
||||
#define _RSPI_FRAMES_2 (0x01U) /* 2 frames */
|
||||
#define _RSPI_FRAMES_3 (0x02U) /* 3 frames */
|
||||
#define _RSPI_FRAMES_4 (0x03U) /* 4 frames */
|
||||
/* RSPI Receive/Transmit Data Selection (SPRDTD) */
|
||||
#define _RSPI_READ_SPDR_RX_BUFFER (0x00U) /* read SPDR values from receive buffer */
|
||||
#define _RSPI_READ_SPDR_TX_BUFFER (0x10U) /* read SPDR values from transmit buffer (transmit buffer empty) */
|
||||
/* RSPI Longword Access/Word Access Specification (SPLW) */
|
||||
#define _RSPI_ACCESS_WORD (0x00U) /* SPDR is accessed in words */
|
||||
#define _RSPI_ACCESS_LONGWORD (0x20U) /* SPDR is accessed in longwords */
|
||||
|
||||
/*
|
||||
RSPI Clock Delay Register (SPCKD)
|
||||
*/
|
||||
/* RSPCK Delay Setting (SCKDL[2:0]) */
|
||||
#define _RSPI_RSPCK_DELAY_1 (0x00U) /* 1 RSPCK */
|
||||
#define _RSPI_RSPCK_DELAY_2 (0x01U) /* 2 RSPCK */
|
||||
#define _RSPI_RSPCK_DELAY_3 (0x02U) /* 3 RSPCK */
|
||||
#define _RSPI_RSPCK_DELAY_4 (0x03U) /* 4 RSPCK */
|
||||
#define _RSPI_RSPCK_DELAY_5 (0x04U) /* 5 RSPCK */
|
||||
#define _RSPI_RSPCK_DELAY_6 (0x05U) /* 6 RSPCK */
|
||||
#define _RSPI_RSPCK_DELAY_7 (0x06U) /* 7 RSPCK */
|
||||
#define _RSPI_RSPCK_DELAY_8 (0x07U) /* 8 RSPCK */
|
||||
|
||||
/*
|
||||
RSPI Slave Select Negation Delay Register (SSLND)
|
||||
*/
|
||||
/* SSL Negation Delay Setting (SLNDL[2:0]) */
|
||||
#define _RSPI_SSL_NEGATION_DELAY_1 (0x00U) /* 1 RSPCK */
|
||||
#define _RSPI_SSL_NEGATION_DELAY_2 (0x01U) /* 2 RSPCK */
|
||||
#define _RSPI_SSL_NEGATION_DELAY_3 (0x02U) /* 3 RSPCK */
|
||||
#define _RSPI_SSL_NEGATION_DELAY_4 (0x03U) /* 4 RSPCK */
|
||||
#define _RSPI_SSL_NEGATION_DELAY_5 (0x04U) /* 5 RSPCK */
|
||||
#define _RSPI_SSL_NEGATION_DELAY_6 (0x05U) /* 6 RSPCK */
|
||||
#define _RSPI_SSL_NEGATION_DELAY_7 (0x06U) /* 7 RSPCK */
|
||||
#define _RSPI_SSL_NEGATION_DELAY_8 (0x07U) /* 8 RSPCK */
|
||||
|
||||
/*
|
||||
RSPI Next-Access Delay Register (SPND)
|
||||
*/
|
||||
/* RSPI Next-Access Delay Setting (SPNDL[2:0]) */
|
||||
#define _RSPI_NEXT_ACCESS_DELAY_1 (0x00U) /* 1 RSPCK + 2 SERICLK */
|
||||
#define _RSPI_NEXT_ACCESS_DELAY_2 (0x01U) /* 2 RSPCK + 2 SERICLK */
|
||||
#define _RSPI_NEXT_ACCESS_DELAY_3 (0x02U) /* 3 RSPCK + 2 SERICLK */
|
||||
#define _RSPI_NEXT_ACCESS_DELAY_4 (0x03U) /* 4 RSPCK + 2 SERICLK */
|
||||
#define _RSPI_NEXT_ACCESS_DELAY_5 (0x04U) /* 5 RSPCK + 2 SERICLK */
|
||||
#define _RSPI_NEXT_ACCESS_DELAY_6 (0x05U) /* 6 RSPCK + 2 SERICLK */
|
||||
#define _RSPI_NEXT_ACCESS_DELAY_7 (0x06U) /* 7 RSPCK + 2 SERICLK */
|
||||
#define _RSPI_NEXT_ACCESS_DELAY_8 (0x07U) /* 8 RSPCK + 2 SERICLK */
|
||||
|
||||
/*
|
||||
RSPI Control Register 2 (SPCR2)
|
||||
*/
|
||||
/* Parity Enable (SPPE) */
|
||||
#define _RSPI_PARITY_DISABLE (0x00U) /* Does not add parity bit to transmit data */
|
||||
#define _RSPI_PARITY_ENABLE (0x01U) /* Adds the parity bit to transmit data */
|
||||
/* Parity Mode (SPOE) */
|
||||
#define _RSPI_PARITY_EVEN (0x00U) /* Selects even parity for use in transmission and reception */
|
||||
#define _RSPI_PARITY_ODD (0x02U) /* Selects odd parity for use in transmission and reception */
|
||||
/* RSPI Idle Interrupt Enable (SPIIE) */
|
||||
#define _RSPI_IDLE_INTERRUPT_DISABLED (0x00U) /* Disables the generation of RSPI idle interrupt */
|
||||
#define _RSPI_IDLE_INTERRUPT_ENABLED (0x04U) /* Enables the generation of RSPI idle interrupt */
|
||||
/* Parity Self-Testing (PTE) */
|
||||
#define _RSPI_SELF_TEST_DISABLED (0x00U) /* Disables the self-diagnosis function of the parity circuit */
|
||||
#define _RSPI_SELF_TEST_ENABLED (0x08U) /* Enables the self-diagnosis function of the parity circuit */
|
||||
/* RSPCK Auto-Stop Function Enable (SCKASE) */
|
||||
#define _RSPI_AUTO_STOP_DISABLED (0x00U) /* Disables the RSPCK auto-stop function */
|
||||
#define _RSPI_AUTO_STOP_ENABLED (0x10U) /* Enables the RSPCK auto-stop function */
|
||||
|
||||
/*
|
||||
RSPI Command Registers 0 to 7 (SPCMD0 to SPCMD7)
|
||||
*/
|
||||
/* RSPCK Phase Setting (CPHA) */
|
||||
#define _RSPI_RSPCK_SAMPLING_ODD (0x0000U) /* Data sampling on odd edge, data variation on even edge */
|
||||
#define _RSPI_RSPCK_SAMPLING_EVEN (0x0001U) /* Data variation on odd edge, data sampling on even edge */
|
||||
/* RSPCK Polarity Setting (CPOL) */
|
||||
#define _RSPI_RSPCK_POLARITY_LOW (0x0000U) /* RSPCK is low when idle */
|
||||
#define _RSPI_RSPCK_POLARITY_HIGH (0x0002U) /* RSPCK is high when idle */
|
||||
/* Bit Rate Division Setting (BRDV[1:0]) */
|
||||
#define _RSPI_BASE_BITRATE_1 (0x0000U) /* These bits select the base bit rate */
|
||||
#define _RSPI_BASE_BITRATE_2 (0x0004U) /* These bits select the base bit rate divided by 2 */
|
||||
#define _RSPI_BASE_BITRATE_4 (0x0008U) /* These bits select the base bit rate divided by 4 */
|
||||
#define _RSPI_BASE_BITRATE_8 (0x000CU) /* These bits select the base bit rate divided by 8 */
|
||||
/* SSL Signal Assertion Setting (SSLA[2:0]) */
|
||||
#define _RSPI_SIGNAL_ASSERT_SSL0 (0x0000U) /* SSL0 */
|
||||
#define _RSPI_SIGNAL_ASSERT_SSL1 (0x0010U) /* SSL1 */
|
||||
#define _RSPI_SIGNAL_ASSERT_SSL2 (0x0020U) /* SSL2 */
|
||||
#define _RSPI_SIGNAL_ASSERT_SSL3 (0x0030U) /* SSL3 */
|
||||
/* SSL Signal Level Keeping (SSLKP) */
|
||||
#define _RSPI_SSL_KEEP_DISABLE (0x0000U) /* Negates all SSL signals upon completion of transfer */
|
||||
#define _RSPI_SSL_KEEP_ENABLE (0x0080U) /* Keep SSL level from end of transfer till next access */
|
||||
/* RSPI Data Length Setting (SPB[3:0]) */
|
||||
#define _RSPI_DATA_LENGTH_BITS_8 (0x0400U) /* 8 bits */
|
||||
#define _RSPI_DATA_LENGTH_BITS_9 (0x0800U) /* 9 bits */
|
||||
#define _RSPI_DATA_LENGTH_BITS_10 (0x0900U) /* 10 bits */
|
||||
#define _RSPI_DATA_LENGTH_BITS_11 (0x0A00U) /* 11 bits */
|
||||
#define _RSPI_DATA_LENGTH_BITS_12 (0x0B00U) /* 12 bits */
|
||||
#define _RSPI_DATA_LENGTH_BITS_13 (0x0C00U) /* 13 bits */
|
||||
#define _RSPI_DATA_LENGTH_BITS_14 (0x0D00U) /* 14 bits */
|
||||
#define _RSPI_DATA_LENGTH_BITS_15 (0x0E00U) /* 15 bits */
|
||||
#define _RSPI_DATA_LENGTH_BITS_16 (0x0F00U) /* 16 bits */
|
||||
#define _RSPI_DATA_LENGTH_BITS_20 (0x0000U) /* 20 bits */
|
||||
#define _RSPI_DATA_LENGTH_BITS_24 (0x0100U) /* 24 bits */
|
||||
#define _RSPI_DATA_LENGTH_BITS_32 (0x0200U) /* 32 bits */
|
||||
/* RSPI LSB First (LSBF) */
|
||||
#define _RSPI_MSB_FIRST (0x0000U) /* MSB first */
|
||||
#define _RSPI_LSB_FIRST (0x1000U) /* LSB first */
|
||||
/* RSPI Next-Access Delay Enable (SPNDEN) */
|
||||
#define _RSPI_NEXT_ACCESS_DELAY_DISABLE (0x0000U) /* Next-access delay of 1 RSPCK + 2 SERICLK */
|
||||
#define _RSPI_NEXT_ACCESS_DELAY_ENABLE (0x2000U) /* Next-access delay equal to setting of SPND register */
|
||||
/* SSL Negation Delay Setting Enable (SLNDEN) */
|
||||
#define _RSPI_NEGATION_DELAY_DISABLE (0x0000U) /* SSL negation delay of 1 RSPCK */
|
||||
#define _RSPI_NEGATION_DELAY_ENABLE (0x4000U) /* SSL negation delay equal to setting of SSLND register */
|
||||
/* RSPCK Delay Setting Enable (SCKDEN) */
|
||||
#define _RSPI_RSPCK_DELAY_DISABLE (0x0000U) /* RSPCK delay of 1 RSPCK */
|
||||
#define _RSPI_RSPCK_DELAY_ENABLE (0x8000U) /* RSPCK delay equal to setting of the SPCKD register */
|
||||
|
||||
/*
|
||||
Interrupt Priority Level Store Register n (PRLn)
|
||||
*/
|
||||
/* Interrupt Priority Level Store (PRL[3:0]) */
|
||||
#define _RSPI_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */
|
||||
#define _RSPI_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */
|
||||
#define _RSPI_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */
|
||||
#define _RSPI_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */
|
||||
#define _RSPI_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */
|
||||
#define _RSPI_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */
|
||||
#define _RSPI_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */
|
||||
#define _RSPI_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */
|
||||
#define _RSPI_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */
|
||||
#define _RSPI_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */
|
||||
#define _RSPI_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */
|
||||
#define _RSPI_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */
|
||||
#define _RSPI_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */
|
||||
#define _RSPI_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */
|
||||
#define _RSPI_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */
|
||||
#define _RSPI_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#define _RSPI1_DIVISOR (0x4AU)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_RSPI1_Create(void);
|
||||
void R_RSPI1_Start(void);
|
||||
void R_RSPI1_Stop(void);
|
||||
MD_STATUS R_RSPI1_Send(const uint32_t * tx_buf, uint16_t tx_num);
|
||||
void r_rspi1_callback_transmitend(void);
|
||||
void r_rspi1_callback_error(uint8_t err_type);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
@ -0,0 +1,188 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_rspi_user.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for RSPI module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_rspi.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
#include "r_typedefs.h"
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
extern const uint32_t * gp_rspi1_tx_address; /* RSPI1 transmit buffer address */
|
||||
extern uint16_t g_rspi1_tx_count; /* RSPI1 transmit data number */
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_rspi1_transmit_interrupt
|
||||
* Description : This function is SPTI1 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_rspi1_transmit_interrupt(void)
|
||||
{
|
||||
uint16_t frame_cnt;
|
||||
|
||||
/* Clear the interrupt source */
|
||||
VIC.PIC2.LONG = 0x00200000UL;
|
||||
|
||||
for (frame_cnt = 0U; frame_cnt < (_RSPI_FRAMES_1 + 1U); frame_cnt++)
|
||||
{
|
||||
if (g_rspi1_tx_count > 0U)
|
||||
{
|
||||
/* Write data for transmission */
|
||||
RSPI1.SPDR.LONG = (*(uint32_t*)gp_rspi1_tx_address);
|
||||
gp_rspi1_tx_address++;
|
||||
g_rspi1_tx_count--;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable transmit interrupt */
|
||||
RSPI1.SPCR.BIT.SPTIE = 0U;
|
||||
|
||||
/* Enable idle interrupt */
|
||||
RSPI1.SPCR2.BIT.SPIIE = 1U;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Dummy write */
|
||||
VIC.HVA0.LONG = 0x00000000UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_rspi1_error_interrupt
|
||||
* Description : This function is SPEI1 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_rspi1_error_interrupt(void)
|
||||
{
|
||||
uint8_t err_type;
|
||||
|
||||
/* Disable RSPI function */
|
||||
RSPI1.SPCR.BIT.SPE = 0U;
|
||||
|
||||
/* Disable transmit interrupt */
|
||||
RSPI1.SPCR.BIT.SPTIE = 0U;
|
||||
|
||||
/* Disable error interrupt */
|
||||
RSPI1.SPCR.BIT.SPEIE = 0U;
|
||||
|
||||
/* Disable idle interrupt */
|
||||
RSPI1.SPCR2.BIT.SPIIE = 0U;
|
||||
|
||||
/* Clear error sources */
|
||||
err_type = RSPI1.SPSR.BYTE;
|
||||
RSPI1.SPSR.BYTE = 0xA0U;
|
||||
|
||||
if (err_type != 0U)
|
||||
{
|
||||
r_rspi1_callback_error(err_type);
|
||||
}
|
||||
/* Wait the interrupt signal is disabled */
|
||||
while (0U != (VIC.IRQS2.LONG & 0x00400000UL))
|
||||
{
|
||||
VIC.IEC2.LONG = 0x00400000UL;
|
||||
}
|
||||
|
||||
VIC.IEN2.LONG |= 0x00400000UL;
|
||||
|
||||
/* Dummy write */
|
||||
VIC.HVA0.LONG = 0x00000000UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_rspi1_idle_interrupt
|
||||
* Description : This function is SPII1 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_rspi1_idle_interrupt(void)
|
||||
{
|
||||
/* Disable RSPI function */
|
||||
RSPI1.SPCR.BIT.SPE = 0U;
|
||||
|
||||
/* Disable idle interrupt */
|
||||
RSPI1.SPCR2.BIT.SPIIE = 0U;
|
||||
|
||||
r_rspi1_callback_transmitend();
|
||||
|
||||
/* Wait the interrupt signal is disabled */
|
||||
while (0U != (VIC.IRQS2.LONG & 0x00800000UL))
|
||||
{
|
||||
VIC.IEC2.LONG = 0x00800000UL;
|
||||
}
|
||||
|
||||
VIC.IEN2.LONG |= 0x00800000UL;
|
||||
|
||||
/* Dummy write */
|
||||
VIC.HVA0.LONG = 0x00000000UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_rspi1_callback_transmitend
|
||||
* Description : This function is a callback function when RSPI1 finishes transmission.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_rspi1_callback_transmitend(void)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_rspi1_callback_error
|
||||
* Description : This function is a callback function when RSPI1 error occurs.
|
||||
* Arguments : err_type -
|
||||
* error type value
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_rspi1_callback_error(uint8_t err_type)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
|
||||
/* Used to suppress the warning message generated for unused variables */
|
||||
UNUSED_VARIABLE(err_type);
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@ -0,0 +1,200 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_s12ad.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for S12AD module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_s12ad.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_S12AD0_Create
|
||||
* Description : This function initializes the AD0 converter.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_S12AD0_Create(void)
|
||||
{
|
||||
/* Cancel S12ADC0 module stop state */
|
||||
MSTP(S12ADC0) = 0U;
|
||||
|
||||
/* Disable and clear S12ADI0, S12GBADI0, S12CMPI0 interrupt flags */
|
||||
S12ADC0.ADCSR.BIT.ADIE = 0U;
|
||||
S12ADC0.ADCSR.BIT.GBADIE = 0U;
|
||||
S12ADC0.ADCMPCR.BIT.CMPIE = 0U;
|
||||
VIC.IEC1.LONG = 0x00000008UL;
|
||||
|
||||
/* Set S12AD0 control registers */
|
||||
S12ADC0.ADDISCR.BYTE = _AD0_DISCONECT_SETTING;
|
||||
S12ADC0.ADCSR.WORD = _AD_DBLTRIGGER_DISABLE | _AD_SCAN_END_INTERRUPT_ENABLE | _AD_SINGLE_SCAN_MODE;
|
||||
S12ADC0.ADCER.WORD = _AD_AUTO_CLEARING_DISABLE | _AD_RIGHT_ALIGNMENT | _AD_RESOLUTION_12BIT;
|
||||
S12ADC0.ADADC.BYTE = _AD_1_TIME_CONVERSION | _AD_ADDITION_MODE;
|
||||
|
||||
/* Set channels and sampling time */
|
||||
S12ADC0.ADANSA.WORD = _AD0_CHANNEL_SELECT_A;
|
||||
S12ADC0.ADADS.WORD = _AD0_ADDAVG_CHANNEL_SELECT;
|
||||
S12ADC0.ADSSTR7.BYTE = _AD0_SAMPLING_STATE_7;
|
||||
|
||||
/* Set compare control register */
|
||||
S12ADC0.ADCMPCR.BYTE = _AD_WINDOWFUNCTION_DISABLE;
|
||||
S12ADC0.ADCMPANSR.WORD = _AD0_COMPARECHANNEL_SELECT;
|
||||
S12ADC0.ADCMPLR.WORD = _AD0_COMPARELEVEL_SELECT;
|
||||
S12ADC0.ADCMPDR0 = 0x0000U;
|
||||
|
||||
/* Set S12ADI0 edge detection type */
|
||||
VIC.PLS1.LONG |= 0x00000008UL;
|
||||
|
||||
/* Set S12ADI0 interrupt priority level */
|
||||
VIC.PRL35.LONG = _AD_PRIORITY_LEVEL0;
|
||||
|
||||
/* Set S12ADI0 interrupt address */
|
||||
VIC.VAD35.LONG = (uint32_t)r_s12ad_s12adi0_interrupt;
|
||||
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_S12AD0_Start
|
||||
* Description : This function starts the AD0 converter.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_S12AD0_Start(void)
|
||||
{
|
||||
/* Enable S12ADI0 interrupt in ICU */
|
||||
VIC.IEN1.LONG |= 0x00000008UL;
|
||||
|
||||
S12ADC0.ADCSR.BIT.ADST = 1U;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_S12AD0_Stop
|
||||
* Description : This function stops the AD0 converter.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_S12AD0_Stop(void)
|
||||
{
|
||||
S12ADC0.ADCSR.BIT.ADST = 0U;
|
||||
|
||||
/* Disable S12ADI0 interrupt in ICU */
|
||||
VIC.IEC1.LONG = 0x00000008UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_S12AD0_Get_ValueResult
|
||||
* Description : This function gets result from the AD0 converter.
|
||||
* Arguments : channel -
|
||||
* channel of data register to be read
|
||||
* buffer -
|
||||
* buffer pointer
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_S12AD0_Get_ValueResult(ad_channel_t channel, uint16_t * const buffer)
|
||||
{
|
||||
if (channel == ADSELFDIAGNOSIS)
|
||||
{
|
||||
*buffer = (uint16_t)(S12ADC0.ADRD);
|
||||
}
|
||||
else if (channel == ADCHANNEL0)
|
||||
{
|
||||
*buffer = (uint16_t)(S12ADC0.ADDR0);
|
||||
}
|
||||
else if (channel == ADCHANNEL1)
|
||||
{
|
||||
*buffer = (uint16_t)(S12ADC0.ADDR1);
|
||||
}
|
||||
else if (channel == ADCHANNEL2)
|
||||
{
|
||||
*buffer = (uint16_t)(S12ADC0.ADDR2);
|
||||
}
|
||||
else if (channel == ADCHANNEL3)
|
||||
{
|
||||
*buffer = (uint16_t)(S12ADC0.ADDR3);
|
||||
}
|
||||
else if (channel == ADCHANNEL4)
|
||||
{
|
||||
*buffer = (uint16_t)(S12ADC0.ADDR4);
|
||||
}
|
||||
else if (channel == ADCHANNEL5)
|
||||
{
|
||||
*buffer = (uint16_t)(S12ADC0.ADDR5);
|
||||
}
|
||||
else if (channel == ADCHANNEL6)
|
||||
{
|
||||
*buffer = (uint16_t)(S12ADC0.ADDR6);
|
||||
}
|
||||
else if (channel == ADCHANNEL7)
|
||||
{
|
||||
*buffer = (uint16_t)(S12ADC0.ADDR7);
|
||||
}
|
||||
else if (channel == ADTEMPSENSOR)
|
||||
{
|
||||
*buffer = (uint16_t)(S12ADC0.ADTSDR);
|
||||
}
|
||||
else if (channel == ADDATADUPLICATION)
|
||||
{
|
||||
*buffer = (uint16_t)(S12ADC0.ADDBLDR);
|
||||
}
|
||||
else if (channel == ADDATADUPLICATIONA)
|
||||
{
|
||||
*buffer = (uint16_t)(S12ADC0.ADDBLDRA);
|
||||
}
|
||||
else if (channel == ADDATADUPLICATIONB)
|
||||
{
|
||||
*buffer = (uint16_t)(S12ADC0.ADDBLDRB);
|
||||
}
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_S12AD0_Set_CompareValue
|
||||
* Description : This function sets reference data for AD0 comparison.
|
||||
* Arguments : reg_value0 -
|
||||
* reference data 0 for comparison
|
||||
* reg_value1 -
|
||||
* reference data 1 for comparison
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_S12AD0_Set_CompareValue(uint16_t reg_value0, uint16_t reg_value1 )
|
||||
{
|
||||
S12ADC0.ADCMPDR0 = reg_value0;
|
||||
S12ADC0.ADCMPDR1 = reg_value1;
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@ -0,0 +1,347 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_s12ad.h
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for S12AD module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
#ifndef S12AD_H
|
||||
#define S12AD_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/*
|
||||
A/D control register (ADCSR)
|
||||
*/
|
||||
/* Group B scan end interrupt enable (GBADIE) */
|
||||
#define _AD_GBADI_DISABLE (0x0000U) /* Disables S12GBADI interrupt generation upon group B scan
|
||||
completion */
|
||||
#define _AD_GBADI_ENABLE (0x0040U) /* Enables S12GBADI interrupt generation upon group B scan
|
||||
completion */
|
||||
/* Double trigger mode select (DBLE) */
|
||||
#define _AD_DBLTRIGGER_DISABLE (0x0000U) /* Disable double trigger mode */
|
||||
#define _AD_DBLTRIGGER_ENABLE (0x0080U) /* Enable double trigger mode */
|
||||
/* Trigger select (EXTRG) */
|
||||
#define _AD_SYNC_TRIGGER (0x0000U) /* A/D conversion started by snychronous trigger */
|
||||
#define _AD_ASYNC_TRIGGER (0x0100U) /* A/D conversion started by asynchronous trigger */
|
||||
/* Trigger start enable (TRGE) */
|
||||
#define _AD_SYNCASYNCTRG_DISABLE (0x0000U) /* A/D conversion synchronous or asynchronous trigger disable */
|
||||
#define _AD_SYNCASYNCTRG_ENABLE (0x0200U) /* A/D conversion synchronous or asynchronous trigger enable */
|
||||
/* Scan end interrupt enable (ADIE) */
|
||||
#define _AD_SCAN_END_INTERRUPT_DISABLE (0x0000U) /* Disable S12ADI0 interrupt generation upon scan completion */
|
||||
#define _AD_SCAN_END_INTERRUPT_ENABLE (0x1000U) /* Enable S12ADI0 interrupt generation upon scan completion */
|
||||
/* Scan mode select (ADCS) */
|
||||
#define _AD_SINGLE_SCAN_MODE (0x0000U) /* Single scan mode */
|
||||
#define _AD_GROUP_SCAN_MODE (0x2000U) /* Group scan mode */
|
||||
#define _AD_CONTINUOUS_SCAN_MODE (0x4000U) /* Continuous scan mode */
|
||||
/* A/D conversion start (ADST) */
|
||||
#define _AD_CONVERSION_STOP (0x0000U) /* Stop A/D conversion */
|
||||
#define _AD_CONVERSION_START (0x8000U) /* Start A/D conversion */
|
||||
|
||||
/*
|
||||
A/D converted value addition count select register (ADADC)
|
||||
*/
|
||||
/* Addition Count Select (ADC[1:0]) */
|
||||
#define _AD_1_TIME_CONVERSION (0x00U) /* 1-time conversion */
|
||||
#define _AD_2_TIME_CONVERSION (0x01U) /* 2-time conversion */
|
||||
#define _AD_3_TIME_CONVERSION (0x02U) /* 3-time conversion */
|
||||
#define _AD_4_TIME_CONVERSION (0x03U) /* 4-time conversion */
|
||||
/* Average Mode Enable bit (AVEE) */
|
||||
#define _AD_ADDITION_MODE (0x00U) /* Addition mode */
|
||||
#define _AD_AVERAGE_MODE (0x80U) /* Average mode */
|
||||
|
||||
/*
|
||||
A/D control extended register (ADCER)
|
||||
*/
|
||||
/* A/D Conversion Accuracy Specify (ADPRC) */
|
||||
#define _AD_RESOLUTION_12BIT (0x0000U) /* 12 bit resolution */
|
||||
#define _AD_RESOLUTION_10BIT (0x0002U) /* 10 bit resolution */
|
||||
#define _AD_RESOLUTION_8BIT (0x0004U) /* 8 bit resolution */
|
||||
/* Automatic clearing enable (ACE) */
|
||||
#define _AD_AUTO_CLEARING_DISABLE (0x0000U) /* Disable auto clearing */
|
||||
#define _AD_AUTO_CLEARING_ENABLE (0x0020U) /* Enable auto clearing */
|
||||
/* A/D Self-diagnosis selection (DIAGVAL) */
|
||||
#define _AD_SELFTDIAGST_DISABLE (0x0000U) /* Disable self-diagnosis */
|
||||
#define _AD_SELFTDIAGST_VREFH0_0 (0x0100U) /* Self-diagnosis using a voltage of 0V */
|
||||
#define _AD_SELFTDIAGST_VREFH0_HALF (0x0200U) /* Self-diagnosis using a voltage of VREFH0_1/2*/
|
||||
#define _AD_SELFTDIAGST_VREFH0 (0x0300U) /* Self-diagnosis using a voltage of VREFH0_1*/
|
||||
#define _AD_SELFTDIAGST_VREFH1_0 (0x0100U) /* Self-diagnosis using a voltage of 0V */
|
||||
#define _AD_SELFTDIAGST_VREFH1_HALF (0x0200U) /* Self-diagnosis using a voltage of VREFH1_1/2*/
|
||||
#define _AD_SELFTDIAGST_VREFH1 (0x0300U) /* Self-diagnosis using a voltage of VREFH1_1*/
|
||||
/* A/D Self-diagnostic mode selection (DIAGLD) */
|
||||
#define _AD_SELFTDIAGST_ROTATION (0x0000U) /* Rotation mode for self-diagnosis voltage */
|
||||
#define _AD_SELFTDIAGST_FIX (0x0400U) /* Fixed mode for self-diagnosis voltage */
|
||||
/* A/D Self-diagnostic enable (DIAGM) */
|
||||
#define _AD_SELFTDIAGST_DISABLE (0x0000U) /* 12bit self-diagnosis disable */
|
||||
#define _AD_SELFTDIAGST_ENABLE (0x0800U) /* 12bit self-diagnosis enable */
|
||||
/* A/D data register format selection (ADRFMT) */
|
||||
#define _AD_RIGHT_ALIGNMENT (0x0000U) /* Right-alignment for data register format */
|
||||
#define _AD_LEFT_ALIGNMENT (0x8000U) /* Left-alignment for data register format */
|
||||
|
||||
/*
|
||||
A/D start trigger select register (ADSTRGR)
|
||||
*/
|
||||
/* A/D conversion start trigger select for group B (TRSB) */
|
||||
#define _AD_TRSB_TRGA0N (0x0001U) /* Compare match with or input capture to MTU0.TGRA */
|
||||
#define _AD_TRSB_TRGA1N (0x0002U) /* Compare match with or input capture to MTU1.TGRA */
|
||||
#define _AD_TRSB_TRGA2N (0x0003U) /* Compare match with or input capture to MTU2.TGRA */
|
||||
#define _AD_TRSB_TRGA3N (0x0004U) /* Compare match with or input capture to MTU3.TGRA */
|
||||
#define _AD_TRSB_TRGA4N (0x0005U) /* Compare match with or input capture to MTU4.TGRA,or an
|
||||
underflow of MTU4.TCNT (in the trough) in complementary
|
||||
PWM mode */
|
||||
#define _AD_TRSB_TRGA6N (0x0006U) /* Compare match with or input capture to MTU6.TGRA */
|
||||
#define _AD_TRSB_TRGA7N (0x0007U) /* Compare match with or input capture to MTU7.TGRA,or an
|
||||
underflow of MTU7.TCNT (in the trough) in complementary
|
||||
PWM mode */
|
||||
#define _AD_TRSB_TRG0N (0x0008U) /* Compare match with MTU0.TGRE */
|
||||
#define _AD_TRSB_TRG4AN (0x0009U) /* Compare match between MTU4.TADCORA and MTU4.TCNT */
|
||||
#define _AD_TRSB_TRG4BN (0x000AU) /* Compare match between MTU4.TADCORB and MTU4.TCNT */
|
||||
#define _AD_TRSB_TRG4BN_TRG4AN (0x000BU) /* Compare match between MTU4.TADCORA and MTU4.TCNT, or
|
||||
between MTU4.TADCORB and MTU4.TCNT */
|
||||
#define _AD_TRSB_TRG4ABN (0x000CU) /* Compare match between MTU4.TADCORA and MTU4.TCNT, and
|
||||
between MTU4.TADCORB and MTU4.TCNT (when interrupt skipping
|
||||
function 2 is in use) */
|
||||
#define _AD_TRSB_TRG7AN (0x000DU) /* Compare match between MTU7.TADCORA and MTU7.TCNT */
|
||||
#define _AD_TRSB_TRG7BN (0x000EU) /* Compare match between MTU7.TADCORB and MTU7.TCNT */
|
||||
#define _AD_TRSB_TRG7AN_TRG7BN (0x000FU) /* Compare match between MTU7.TADCORA and MTU7.TCNT, or between
|
||||
MTU7.TADCORB and MTU7.TCNT */
|
||||
#define _AD_TRSB_TRG7ABN (0x0010U) /* Compare match between MTU7.TADCORA and MTU7.TCNT, and between
|
||||
MTU7.TADCORB and MTU7.TCNT (when interrupt skipping function
|
||||
2 is in use) */
|
||||
#define _AD_TRSB_GTADTRA0N (0x0011U) /* Compare match with GPT0.GTADTRA */
|
||||
#define _AD_TRSB_GTADTRB0N (0x0012U) /* Compare match with GPT0.GTADTRB */
|
||||
#define _AD_TRSB_GTADTRA1N (0x0013U) /* Compare match with GPT1.GTADTRA */
|
||||
#define _AD_TRSB_GTADTRB1N (0x0014U) /* Compare match with GPT1.GTADTRB */
|
||||
#define _AD_TRSB_GTADTRA2N (0x0015U) /* Compare match with GPT2.GTADTRA */
|
||||
#define _AD_TRSB_GTADTRB2N (0x0016U) /* Compare match with GPT2.GTADTRB */
|
||||
#define _AD_TRSB_GTADTRA3N (0x0017U) /* Compare match with GPT3.GTADTRA */
|
||||
#define _AD_TRSB_GTADTRB3N (0x0018U) /* Compare match with GPT3.GTADTRB */
|
||||
#define _AD_TRSB_GTADTRA0N_GTADTRB0N (0x0019U) /* Compare match with GPT0.GTADTRA or with GPT0.GTADTRB */
|
||||
#define _AD_TRSB_GTADTRA1N_GTADTRB1N (0x001AU) /* Compare match with GPT1.GTADTRA or with GPT1.GTADTRB */
|
||||
#define _AD_TRSB_GTADTRA2N_GTADTRB2N (0x001BU) /* Compare match with GPT2.GTADTRA or with GPT2.GTADTRB*/
|
||||
#define _AD_TRSB_GTADTRA3N_GTADTRB3N (0x001CU) /* Compare match with GPT3.GTADTRA or with GPT3.GTADTRB */
|
||||
#define _AD_TRSB_TPTRGAN_0 (0x001FU) /* Compare match with or input capture to TPUn.TGRA(n = 0 to 5) */
|
||||
#define _AD_TRSB_TPTRG0AN_0 (0x0020U) /* Compare match with or input capture to TPU0.TGRA */
|
||||
#define _AD_TRSB_TPTRGAN_1 (0x0021U) /* Compare match with or input capture to TPUn.TGRA(n = 6 to 11) */
|
||||
#define _AD_TRSB_TPTRG6AN_1 (0x0022U) /* Compare match with or input capture to TPU6.TGRA */
|
||||
#define _AD_TRSB_ELCTRG0N_ELCTRG1N (0x0030U) /* Trigger from ELC */
|
||||
|
||||
/* A/D conversion start trigger select for group A (TRSA) */
|
||||
#define _AD_TRSA_ADTRG (0x0000U) /* Input pin for the trigger */
|
||||
#define _AD_TRSA_TRGA0N (0x0100U) /* Compare match with or input capture to MTU0.TGRA */
|
||||
#define _AD_TRSA_TRGA1N (0x0200U) /* Compare match with or input capture to MTU1.TGRA */
|
||||
#define _AD_TRSA_TRGA2N (0x0300U) /* Compare match with or input capture to MTU2.TGRA */
|
||||
#define _AD_TRSA_TRGA3N (0x0400U) /* Compare match with or input capture to MTU3.TGRA */
|
||||
#define _AD_TRSA_TRGA4N (0x0500U) /* Compare match with or input capture to MTU4.TGRA or, in
|
||||
complementary PWM mode,an underflow of MTU4.TCNT
|
||||
(in the trough)*/
|
||||
#define _AD_TRSA_TRGA6N (0x0600U) /* Compare match with or input capture to MTU6.TGRA */
|
||||
#define _AD_TRSA_TRGA7N (0x0700U) /* Compare match with or input capture to MTU7.TGRA or, in
|
||||
complementary PWM mode,an underflow of MTU7.TCNT
|
||||
(in the trough)*/
|
||||
#define _AD_TRSA_TRG0N (0x0800U) /* Compare match with MTU0.TGRE */
|
||||
#define _AD_TRSA_TRG4AN (0x0900U) /* Compare match between MTU4.TADCORA and MTU4.TCNT */
|
||||
#define _AD_TRSA_TRG4BN (0x0A00U) /* Compare match between MTU4.TADCORB and MTU4.TCNT */
|
||||
#define _AD_TRSA_TRG4BN_TRG4AN (0x0B00U) /* Compare match between MTU4.TADCORA and MTU4.TCNT, or between
|
||||
MTU4.TADCORB and MTU4.TCNT */
|
||||
#define _AD_TRSA_TRG4ABN (0x0C00U) /* Compare match between MTU4.TADCORA and MTU4.TCNT, and between
|
||||
MTU4.TADCORB and MTU4.TCNT (when interrupt skipping function
|
||||
2 is in use) */
|
||||
#define _AD_TRSA_TRG7AN (0x0D00U) /* Compare match between MTU7.TADCORA and MTU7.TCNT */
|
||||
#define _AD_TRSA_TRG7BN (0x0E00U) /* Compare match between MTU7.TADCORB and MTU7.TCNT */
|
||||
#define _AD_TRSA_TRG7AN_TRG7BN (0x0F00U) /* Compare match between MTU7.TADCORA and MTU7.TCNT, or between
|
||||
MTU7.TADCORB and MTU7.TCNT */
|
||||
#define _AD_TRSA_TRG7ABN (0x1000U) /* Compare match between MTU7.TADCORA and MTU7.TCNT, and between
|
||||
MTU7.TADCORB and MTU7.TCNT (when interrupt skipping function
|
||||
2 is in use) */
|
||||
#define _AD_TRSA_GTADTRA0N (0x1100U) /* Compare match with GPT0.GTADTRA */
|
||||
#define _AD_TRSA_GTADTRB0N (0x1200U) /* Compare match with GPT0.GTADTRB */
|
||||
#define _AD_TRSA_GTADTRA1N (0x1300U) /* Compare match with GPT1.GTADTRA */
|
||||
#define _AD_TRSA_GTADTRB1N (0x1400U) /* Compare match with GPT1.GTADTRB */
|
||||
#define _AD_TRSA_GTADTRA2N (0x1500U) /* Compare match with GPT2.GTADTRA */
|
||||
#define _AD_TRSA_GTADTRB2N (0x1600U) /* Compare match with GPT2.GTADTRB */
|
||||
#define _AD_TRSA_GTADTRA3N (0x1700U) /* Compare match with GPT3.GTADTRA */
|
||||
#define _AD_TRSA_GTADTRB3N (0x1800U) /* Compare match with GPT3.GTADTRB */
|
||||
#define _AD_TRSA_GTADTRA0N_GTADTRB0N (0x1900U) /* Compare match with GPT0.GTADTRA or with GPT0.GTADTRB */
|
||||
#define _AD_TRSA_GTADTRA1N_GTADTRB1N (0x1A00U) /* Compare match with GPT1.GTADTRA or with GPT1.GTADTRB */
|
||||
#define _AD_TRSA_GTADTRA2N_GTADTRB2N (0x1B00U) /* Compare match with GPT2.GTADTRA or with GPT2.GTADTRB */
|
||||
#define _AD_TRSA_GTADTRA3N_GTADTRB3N (0x1C00U) /* Compare match with GPT3.GTADTRA or with GPT3.GTADTRB */
|
||||
#define _AD_TRSA_TPTRGAN_0 (0x1F00U) /* Compare match with or input capture to TPUn.TGRA(n= 0 to 5) */
|
||||
#define _AD_TRSA_TPTRG0AN_0 (0x2000U) /* Compare match with or input capture to TPU0.TGRA */
|
||||
#define _AD_TRSA_TPTRGAN_1 (0x2100U) /* Compare match with or input capture to TPUn.TGRA(n= 6 to 11) */
|
||||
#define _AD_TRSA_TPTRG6AN_1 (0x2200U) /* Compare match with or input capture to TPU6.TGRA */
|
||||
#define _AD_TRSA_ELCTRG0N_ELCTRG1N (0x3000U) /* Trigger from ELC */
|
||||
|
||||
/*
|
||||
A/D converted extended input control register (ADEXICR)
|
||||
*/
|
||||
/* Temperature sensor output A/D conversion value addition mode selection (TSSAD) */
|
||||
#define _AD_TEMP_ADDITION_DISABLE (0x0000U) /* Temperature sensor output A/D converted value addition/average
|
||||
mode disabled */
|
||||
#define _AD_TEMP_ADDITION_ENABLE (0x0001U) /* Temperature sensor output A/D converted value addition/average
|
||||
mode enabled */
|
||||
/* Temperature sensor output A/D conversion select (TSSA) */
|
||||
#define _AD_TEMP_GROUPA_DISABLE (0x0000U) /* A/D conversion of temperature sensor output is disabled in
|
||||
group A */
|
||||
#define _AD_TEMP_GROUPA_ENABLE (0x0100U) /* A/D conversion of temperature sensor output is enabled in
|
||||
group A */
|
||||
/* Temperature sensor output A/D conversion select (TSSB) */
|
||||
#define _AD_TEMP_GROUPB_DISABLE (0x0000U) /* A/D conversion of temperature sensor output is disabled in
|
||||
group B */
|
||||
#define _AD_TEMP_GROUPB_ENABLE (0x0400U) /* A/D conversion of temperature sensor output is enabled in
|
||||
group B */
|
||||
/* Extended analog input selection (EXSEL) */
|
||||
#define _AD_EXTNANEX1_IN_DISABLE (0x0000U) /* Extended analog input disable */
|
||||
#define _AD_EXTNANEX1_IN_ENABLE (0x2000U) /* Extended analog input enable */
|
||||
/* Extended analog output control (EXOEN) */
|
||||
#define _AD_EXTNANEX0_OUT_DISABLE (0x0000U) /* Extended analog output disable */
|
||||
#define _AD_EXTNANEX0_IN_ENABLE (0x8000U) /* Extended analog output enable */
|
||||
|
||||
/*
|
||||
A/D Group Scan Priority Control Register (ADGSPCR)
|
||||
*/
|
||||
/* Group-A Priority Control Setting (PGS) */
|
||||
#define _AD_GPAPRIORITY_DISABLE (0x0000U) /* Operation is without group A priority control */
|
||||
#define _AD_GPAPRIORITY_ENABLE (0x0001U) /* Operation is with group A priority control */
|
||||
/* Group B Restart Setting (GBRSCN) */
|
||||
#define _AD_GPBRESTART_DISABLE (0x0000U) /* Group B not restart after discontinued due to Group A
|
||||
priority */
|
||||
#define _AD_GPBRESTART_ENABLE (0x0002U) /* Group B restart after discontinued due to Group A priority */
|
||||
/* Group B Single Cycle Scan Continuous Start (GBRP) */
|
||||
#define _AD_GPBSCSCS_DISABLE (0x0000U) /* Single cycle scan for group B not continuously activated */
|
||||
#define _AD_GPBSCSCS_ENABLE (0x8000U) /* Single cycle scan for group B is continuously activated */
|
||||
|
||||
/*
|
||||
A/D Compare Control Register (ADCMPCR)
|
||||
*/
|
||||
/* Window Function Setting (WCMPE) */
|
||||
#define _AD_WINDOWFUNCTION_DISABLE (0x00U) /* Window function disabled */
|
||||
#define _AD_WINDOWFUNCTION_ENABLE (0x40U) /* Window function enabled */
|
||||
/* Compare Interrupt Enable (CMPIE) */
|
||||
#define _AD_COMPARISON_INTERRUPT_DISABLE (0x00U) /* S12CMPI interrupt is disabled */
|
||||
#define _AD_COMPARISON_INTERRUPT_ENABLE (0x80U) /* S12CMPI interrupt is enabled */
|
||||
|
||||
/*
|
||||
A/D Compare Channel Select Extended Register (ADCMPANSER)
|
||||
*/
|
||||
/* Temperature Sensor Output Compare Select(CMPSTS) */
|
||||
#define _AD_TEMP_COMPARE_DISABLE (0x00U) /* Temperature sensor output is not a target for comparison. */
|
||||
#define _AD_TEMP_COMPARE_ENABLE (0x01U) /* Temperature sensor output is a target for comparison. */
|
||||
|
||||
/*
|
||||
A/D Compare Level Extended Register (ADCMPLER)
|
||||
*/
|
||||
/* Temperature Sensor Output Compare Level Select(CMPLTS) */
|
||||
#define _AD_TEMP0_COMPARELEVEL (0x00U) /* AD-converted value < ADCMPDR0 register value or A/D-converted
|
||||
value > ADCMPDR1 register value */
|
||||
#define _AD_TEMP1_COMPARELEVEL (0x01U) /* ADCMPDR0 register value < A/D-converted value < ADCMPDR1
|
||||
register value */
|
||||
|
||||
/*
|
||||
A/D Pin-Level Self-Diagnosis Control Register (ADTDCR)
|
||||
*/
|
||||
/* Pin-level Self-diagnosis Level Select (TDLV[1:0]) */
|
||||
#define _AD_EVEN_AVSS0 (0x00U) /* Input channels with even numbers are discharged to AVSS,
|
||||
and input channels with odd numbers are charged to AVCC. */
|
||||
#define _AD_EVEN_AVCC0 (0x01U) /* Input channels with even numbers are charged to AVCC,
|
||||
and input channels with odd numbers are discharged to AVSS. */
|
||||
#define _AD_ODD_AVCC0_HALF (0x02U) /* Input channels with even numbers are discharged to AVSS,
|
||||
and input channels with odd numbers are charged to AVCx1/2. */
|
||||
#define _AD_EVEN_AVCC0_HALF (0x03U) /* Input channels with even numbers are charged to AVCCx1/2,
|
||||
and input channels with odd numbers are discharged to AVSS. */
|
||||
#define _AD_EVEN_AVSS1 (0x00U) /* Input channels with even numbers are discharged to AVSS,
|
||||
and input channels with odd numbers are charged to AVCC. */
|
||||
#define _AD_EVEN_AVCC1 (0x01U) /* Input channels with even numbers are charged to AVCC,
|
||||
and input channels with odd numbers are discharged to AVSS. */
|
||||
#define _AD_ODD_AVCC1_HALF (0x02U) /* Input channels with even numbers are discharged to AVSS,
|
||||
and input channels with odd numbers are charged to AVCx1/2. */
|
||||
#define _AD_EVEN_AVCC1_HALF (0x03U) /* Input channels with even numbers are charged to AVCCx1/2,
|
||||
and input channels with odd numbers are discharged to AVSS. */
|
||||
/* Pin-level Self-diagnosis Enable (TDE) */
|
||||
#define _AD_PINLVL_ENABLE (0x00U) /* Enables pin-level self-diagnosis. */
|
||||
#define _AD_PINLVL_DISABLE (0x80U) /* Disables pin-level self-diagnosis. */
|
||||
|
||||
|
||||
/*
|
||||
A/D Error Control Register (ADERCR)
|
||||
*/
|
||||
/* Overwrite Error Interrupt Enable (OWEIE) */
|
||||
#define _AD_ERROR_INT_REQUEST_DISABLE (0x00U) /* Disables interrupt generation when an overwrite error is detected. */
|
||||
#define _AD_ERROR_INT_REQUEST_ENABLE (0x04U) /* Enables interrupt generation when an overwrite error is detected. */
|
||||
|
||||
/*
|
||||
Interrupt Source Priority Register n (PRLn)
|
||||
*/
|
||||
/* Interrupt Priority Level Select (PRL[3:0]) */
|
||||
#define _AD_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */
|
||||
#define _AD_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */
|
||||
#define _AD_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */
|
||||
#define _AD_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */
|
||||
#define _AD_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */
|
||||
#define _AD_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */
|
||||
#define _AD_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */
|
||||
#define _AD_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */
|
||||
#define _AD_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */
|
||||
#define _AD_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */
|
||||
#define _AD_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */
|
||||
#define _AD_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */
|
||||
#define _AD_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */
|
||||
#define _AD_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */
|
||||
#define _AD_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */
|
||||
#define _AD_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#define _AD0_CHANNEL_SELECT_A (0x0080U)
|
||||
#define _AD0_ADDAVG_CHANNEL_SELECT (0x0000U)
|
||||
#define _AD0_DISCONECT_SETTING (0x00U)
|
||||
#define _AD0_COMPARECHANNEL_SELECT (0x0000U)
|
||||
#define _AD0_COMPARELEVEL_SELECT (0x0000U)
|
||||
#define _AD0_SAMPLING_STATE_7 (0x16U)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
ADCHANNEL0, ADCHANNEL1, ADCHANNEL2, ADCHANNEL3, ADCHANNEL4, ADCHANNEL5, ADCHANNEL6,
|
||||
ADCHANNEL7, ADCHANNEL8, ADCHANNEL9, ADCHANNEL10, ADCHANNEL11, ADCHANNEL12,
|
||||
ADCHANNEL13, ADCHANNEL14, ADCHANNEL15, ADSELFDIAGNOSIS, ADTEMPSENSOR, ADDATADUPLICATION,
|
||||
ADDATADUPLICATIONA, ADDATADUPLICATIONB
|
||||
} ad_channel_t;
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_S12AD0_Create(void);
|
||||
void R_S12AD0_Start(void);
|
||||
void R_S12AD0_Stop(void);
|
||||
void R_S12AD0_Get_ValueResult(ad_channel_t channel, uint16_t * const buffer);
|
||||
void R_S12AD0_Set_CompareValue(uint16_t reg_value0, uint16_t reg_value1);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
@ -0,0 +1,69 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_s12ad_user.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for S12AD module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_s12ad.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_s12ad_s12adi0_interrupt
|
||||
* Description : This function is ADI0 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_s12ad_s12adi0_interrupt(void)
|
||||
{
|
||||
/* Clear the interrupt source S12ADI0 */
|
||||
VIC.PIC1.LONG = 0x00000008UL;
|
||||
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/* Dummy write */
|
||||
VIC.HVA0.LONG = 0x00000000UL;
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@ -0,0 +1,266 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_scifa.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for SCIF module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_scifa.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
const uint8_t * gp_scifa2_tx_address; /* SCIFA2 transmit buffer address */
|
||||
uint16_t g_scifa2_tx_count; /* SCIFA2 transmit data number */
|
||||
uint8_t * gp_scifa2_rx_address; /* SCIFA2 receive buffer address */
|
||||
uint16_t g_scifa2_rx_count; /* SCIFA2 receive data number */
|
||||
uint16_t g_scifa2_rx_length; /* SCIFA2 receive data length */
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_SCIFA2_Create
|
||||
* Description : This function initializes SCIFA2.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_SCIFA2_Create(void)
|
||||
{
|
||||
volatile uint16_t dummy;
|
||||
uint16_t w_count;
|
||||
|
||||
/* Cancel SCIFA2 module stop state */
|
||||
MSTP(SCIFA2) = 0U;
|
||||
|
||||
/* Disable TXIF2 interrupt */
|
||||
VIC.IEC3.LONG = 0x00008000UL;
|
||||
|
||||
/* Disable RXIF2 interrupt */
|
||||
VIC.IEC3.LONG = 0x00004000UL;
|
||||
|
||||
/* Disable BRIF2 interrupt */
|
||||
VIC.IEC3.LONG = 0x00002000UL;
|
||||
|
||||
/* Disable DRIF2 interrupt */
|
||||
VIC.IEC3.LONG = 0x00010000UL;
|
||||
|
||||
/* Clear transmit/receive enable bits */
|
||||
SCIFA2.SCR.BIT.TE = 0U;
|
||||
SCIFA2.SCR.BIT.RE = 0U;
|
||||
|
||||
/* Reset transmit/receive FIFO data register operation */
|
||||
SCIFA2.FCR.BIT.TFRST = 1U;
|
||||
SCIFA2.FCR.BIT.RFRST = 1U;
|
||||
|
||||
/* Read and clear status flags */
|
||||
dummy = SCIFA2.FSR.WORD;
|
||||
( void ) dummy;
|
||||
SCIFA2.FSR.WORD = 0x00U;
|
||||
dummy = (uint16_t) SCIFA2.LSR.BIT.ORER;
|
||||
( void ) dummy;
|
||||
SCIFA2.LSR.BIT.ORER = 0U;
|
||||
|
||||
/* Set clock enable bits */
|
||||
SCIFA2.SCR.WORD = _SCIF_INTERNAL_SCK_UNUSED;
|
||||
|
||||
/* Set transmission/reception format */
|
||||
SCIFA2.SMR.WORD = _SCIF_CLOCK_SERICLK_4 | _SCIF_STOP_1 | _SCIF_PARITY_DISABLE | _SCIF_DATA_LENGTH_8 |
|
||||
_SCIF_ASYNCHRONOUS_MODE;
|
||||
SCIFA2.SEMR.BYTE = _SCIF_16_BASE_CLOCK | _SCIF_NOISE_FILTER_ENABLE | _SCIF_DATA_TRANSFER_LSB_FIRST |
|
||||
_SCIF_BAUDRATE_SINGLE;
|
||||
|
||||
/* Clear modulation duty register select */
|
||||
SCIFA2.SEMR.BIT.MDDRS = 0U;
|
||||
|
||||
/* Set bit rate */
|
||||
SCIFA2.BRR_MDDR.BRR = 0x3CU;
|
||||
|
||||
/* Wait for at least 1-bit interval */
|
||||
for (w_count = 0U; w_count < _SCIF_1BIT_INTERVAL_2; w_count++)
|
||||
{
|
||||
nop();
|
||||
}
|
||||
|
||||
/* Set FIFO trigger conditions */
|
||||
SCIFA2.FTCR.WORD = _SCIF_TX_FIFO_TRIGGER_NUM_0 | _SCIF_TX_TRIGGER_TFTC_VALID | _SCIF_RX_FIFO_TRIGGER_NUM_1 |
|
||||
_SCIF_RX_TRIGGER_RFTC_VALID;
|
||||
SCIFA2.FCR.WORD = _SCIF_LOOPBACK_DISABLE | _SCIF_MODEM_CONTROL_DISABLE;
|
||||
|
||||
/* Disable transmit/receive FIFO data register reset operation */
|
||||
SCIFA2.FCR.BIT.TFRST = 0U;
|
||||
SCIFA2.FCR.BIT.RFRST = 0U;
|
||||
|
||||
/* Set TXIF2 interrupt priority */
|
||||
VIC.PRL111.LONG = _SCIF_PRIORITY_LEVEL2;
|
||||
|
||||
/* Set TXIF2 interrupt address */
|
||||
VIC.VAD111.LONG = (uint32_t)r_scifa2_txif2_interrupt;
|
||||
|
||||
/* Set RXIF2 interrupt priority */
|
||||
VIC.PRL110.LONG = _SCIF_PRIORITY_LEVEL3;
|
||||
|
||||
/* Set RXIF2 interrupt address */
|
||||
VIC.VAD110.LONG = (uint32_t)r_scifa2_rxif2_interrupt;
|
||||
|
||||
/* Set BRIF2 interrupt priority */
|
||||
VIC.PRL109.LONG = _SCIF_PRIORITY_LEVEL5;
|
||||
|
||||
/* Set BRIF2 interrupt address */
|
||||
VIC.VAD109.LONG = (uint32_t)r_scifa2_brif2_interrupt;
|
||||
|
||||
/* Set DRIF2 interrupt priority */
|
||||
VIC.PRL112.LONG = _SCIF_PRIORITY_LEVEL4;
|
||||
|
||||
/* Set DRIF2 interrupt address */
|
||||
VIC.VAD112.LONG = (uint32_t)r_scifa2_drif2_interrupt;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_SCIFA2_Start
|
||||
* Description : This function starts SCIFA2.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_SCIFA2_Start(void)
|
||||
{
|
||||
/* Enable TXIF2 interrupt */
|
||||
VIC.IEN3.LONG |= 0x00008000UL;
|
||||
|
||||
/* Enable RXIF2 interrupt */
|
||||
VIC.IEN3.LONG |= 0x00004000UL;
|
||||
|
||||
/* Enable BRIF2 interrupt */
|
||||
VIC.IEN3.LONG |= 0x00002000UL;
|
||||
|
||||
/* Enable DRIF2 interrupt */
|
||||
VIC.IEN3.LONG |= 0x00010000UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_SCIFA2_Stop
|
||||
* Description : This function stops SCIFA2.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_SCIFA2_Stop(void)
|
||||
{
|
||||
/* Disable serial transmit */
|
||||
SCIFA2.SCR.BIT.TE = 0U;
|
||||
|
||||
/* Disable serial receive */
|
||||
SCIFA2.SCR.BIT.RE = 0U;
|
||||
|
||||
/* Disable TXI interrupt */
|
||||
SCIFA2.SCR.BIT.TIE = 0U;
|
||||
|
||||
/* Disable RXI and ERI interrupt */
|
||||
SCIFA2.SCR.BIT.RIE = 0U;
|
||||
|
||||
/* Disable TXIF2 interrupt */
|
||||
VIC.IEC3.LONG = 0x00008000UL;
|
||||
|
||||
/* Disable RXIF2 interrupt */
|
||||
VIC.IEC3.LONG = 0x00004000UL;
|
||||
|
||||
/* Disable BRIF2 interrupt */
|
||||
VIC.IEC3.LONG = 0x00002000UL;
|
||||
|
||||
/* Disable DRIF2 interrupt */
|
||||
VIC.IEC3.LONG = 0x00010000UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_SCIFA2_Serial_Receive
|
||||
* Description : This function receives SCIFA2 data.
|
||||
* Arguments : rx_buf -
|
||||
* receive buffer pointer (Not used when receive data handled by DMAC)
|
||||
* rx_num -
|
||||
* buffer size (Not used when receive data handled by DMAC)
|
||||
* Return Value : status -
|
||||
* MD_OK or MD_ARGERROR
|
||||
***********************************************************************************************************************/
|
||||
MD_STATUS R_SCIFA2_Serial_Receive(uint8_t * rx_buf, uint16_t rx_num)
|
||||
{
|
||||
MD_STATUS status = MD_OK;
|
||||
|
||||
if (rx_num < 1U)
|
||||
{
|
||||
status = MD_ARGERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
g_scifa2_rx_count = 0U;
|
||||
g_scifa2_rx_length = rx_num;
|
||||
gp_scifa2_rx_address = rx_buf;
|
||||
|
||||
SCIFA2.FTCR.BIT.RFTC = _SCIF_RX_TRIG_NUM_2;
|
||||
|
||||
SCIFA2.SCR.BIT.RE = 1U;
|
||||
SCIFA2.SCR.BIT.RIE = 1U;
|
||||
SCIFA2.SCR.BIT.REIE = 1U;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_SCIFA2_Serial_Send
|
||||
* Description : This function transmits SCIFA2 data.
|
||||
* Arguments : tx_buf -
|
||||
* transfer buffer pointer (Not used when transmit data handled by DMAC)
|
||||
* tx_num -
|
||||
* buffer size (Not used when transmit data handled by DMAC)
|
||||
* Return Value : status -
|
||||
* MD_OK or MD_ARGERROR
|
||||
***********************************************************************************************************************/
|
||||
MD_STATUS R_SCIFA2_Serial_Send(const uint8_t * tx_buf, uint16_t tx_num)
|
||||
{
|
||||
MD_STATUS status = MD_OK;
|
||||
|
||||
if (tx_num < 1U)
|
||||
{
|
||||
status = MD_ARGERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
gp_scifa2_tx_address = tx_buf;
|
||||
g_scifa2_tx_count = tx_num;
|
||||
SCIFA2.SCR.BIT.TE = 1U;
|
||||
SCIFA2.SCR.BIT.TIE = 1U;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@ -0,0 +1,275 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_scifa.h
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for SCIF module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
#ifndef SCIF_H
|
||||
#define SCIF_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/*
|
||||
Serial mode register (SMR)
|
||||
*/
|
||||
/* Clock select (CKS[1:0]) */
|
||||
#define _SCIF_CLOCK_SERICLK (0x0000U) /* SERICLK */
|
||||
#define _SCIF_CLOCK_SERICLK_4 (0x0001U) /* SERICLK/4 */
|
||||
#define _SCIF_CLOCK_SERICLK_16 (0x0002U) /* SERICLK/16 */
|
||||
#define _SCIF_CLOCK_SERICLK_64 (0x0003U) /* SERICLK/64 */
|
||||
/* Stop bit length (STOP) */
|
||||
#define _SCIF_STOP_1 (0x0000U) /* 1 stop bit */
|
||||
#define _SCIF_STOP_2 (0x0008U) /* 2 stop bits */
|
||||
/* Parity mode (PM) */
|
||||
#define _SCIF_PARITY_EVEN (0x0000U) /* Parity even */
|
||||
#define _SCIF_PARITY_ODD (0x0010U) /* Parity odd */
|
||||
/* Parity enable (PE) */
|
||||
#define _SCIF_PARITY_DISABLE (0x0000U) /* Parity disable */
|
||||
#define _SCIF_PARITY_ENABLE (0x0020U) /* Parity enable */
|
||||
/* Character length (CHR) */
|
||||
#define _SCIF_DATA_LENGTH_8 (0x0000U) /* Data length 8 bits */
|
||||
#define _SCIF_DATA_LENGTH_7 (0x0040U) /* Data length 7 bits */
|
||||
/* Communications mode (CM) */
|
||||
#define _SCIF_ASYNCHRONOUS_MODE (0x0000U) /* Asynchronous mode */
|
||||
#define _SCIF_CLOCK_SYNCHRONOUS_MODE (0x0080U) /* Clock synchronous mode */
|
||||
|
||||
/*
|
||||
Serial control register (SCR)
|
||||
*/
|
||||
/* Clock enable (CKE) */
|
||||
#define _SCIF_INTERNAL_SCK_UNUSED (0x0000U) /* Internal clock selected, SCK pin unused */
|
||||
#define _SCIF_INTERNAL_SCK_OUTPUT (0x0001U) /* Internal clock selected, SCK pin as clock output */
|
||||
/* Clock enable (CKE) for clock synchronous mode */
|
||||
#define _SCIF_INTERNAL_SCK_OUTPUT_SYNC (0x0000U) /* Internal clock, SCK pin is used for clock output */
|
||||
#define _SCIF_EXTERNAL_SCK_INPUT_SYNC (0x0002U) /* External clock, SCK pin is used for clock input */
|
||||
/* Transmit end interrupt enable (TEIE) */
|
||||
#define _SCIF_TEI_INTERRUPT_DISABLE (0x0000U) /* TEI interrupt request disable */
|
||||
#define _SCIF_TEI_INTERRUPT_ENABLE (0x0004U) /* TEI interrupt request enable */
|
||||
/* Receive error interrupt enable (REIE) */
|
||||
#define _SCIF_ERI_BRI_INTERRUPT_DISABLE (0x0000U) /* Disable receive-error interrupt and break interrupt */
|
||||
#define _SCIF_ERI_BRI_INTERRUPT_ENABLE (0x0008U) /* Enable receive-error interrupt and break interrupt */
|
||||
/* Receive enable (RE) */
|
||||
#define _SCIF_RECEIVE_DISABLE (0x0000U) /* Disable receive mode */
|
||||
#define _SCIF_RECEIVE_ENABLE (0x0010U) /* Enable receive mode */
|
||||
/* Transmit enable (TE) */
|
||||
#define _SCIF_TRANSMIT_DISABLE (0x0000U) /* Disable transmit mode */
|
||||
#define _SCIF_TRANSMIT_ENABLE (0x0020U) /* Enable transmit mode */
|
||||
/* Receive interrupt enable (RIE) */
|
||||
#define _SCIF_RXI_ERI_DISABLE (0x0000U) /* Disable RXI and ERI interrupt requests */
|
||||
#define _SCIF_RXI_ERI_ENABLE (0x0040U) /* Enable RXI and ERI interrupt requests */
|
||||
/* Transmit interrupt enable (TIE) */
|
||||
#define _SCIF_TXI_DISABLE (0x0000U) /* Disable TXI interrupt requests */
|
||||
#define _SCIF_TXI_ENABLE (0x0080U) /* Enable TXI interrupt requests */
|
||||
|
||||
/*
|
||||
FIFO control register (FCR)
|
||||
*/
|
||||
/* Loop-Back test (LOOP) */
|
||||
#define _SCIF_LOOPBACK_DISABLE (0x0000U) /* Loop back test is disabled */
|
||||
#define _SCIF_LOOPBACK_ENABLE (0x0001U) /* Loop back test is enabled */
|
||||
/* Receive FIFO Data Register Reset (RFRST) */
|
||||
#define _SCIF_RX_FIFO_RESET_DISABLE (0x0000U) /* FRDR reset operation is disabled */
|
||||
#define _SCIF_RX_FIFO_RESET_ENABLE (0x0002U) /* FRDR reset operation is enabled */
|
||||
/* Transmit FIFO Data Register Reset (TFRST) */
|
||||
#define _SCIF_TX_FIFO_RESET_DISABLE (0x0000U) /* FTDR reset operation is disabled */
|
||||
#define _SCIF_TX_FIFO_RESET_ENABLE (0x0004U) /* FTDR reset operation is enabled */
|
||||
/* Modem control enable (MCE) */
|
||||
#define _SCIF_MODEM_CONTROL_DISABLE (0x0000U) /* Model signal is disabled */
|
||||
#define _SCIF_MODEM_CONTROL_ENABLE (0x0008U) /* Model signal is enabled */
|
||||
/* Transmit FIFO Data Trigger Number (TTRG[1:0]) */
|
||||
#define _SCIF_TX_TRIGGER_NUMBER_8 (0x0000U) /* 8 (or 8 when TDFE flag is 1) */
|
||||
#define _SCIF_TX_TRIGGER_NUMBER_4 (0x0010U) /* 4 (or 12 when TDFE flag is 1) */
|
||||
#define _SCIF_TX_TRIGGER_NUMBER_2 (0x0020U) /* 2 (or 14 when TDFE flag is 1) */
|
||||
#define _SCIF_TX_TRIGGER_NUMBER_0 (0x0030U) /* 0 (or 16 when TDFE flag is 1) */
|
||||
/* Receive FIFO Data Trigger Number (RTRG[1:0]) */
|
||||
#define _SCIF_RX_TRIGGER_NUMBER_1 (0x0000U) /* 1 */
|
||||
#define _SCIF_RX_TRIGGER_NUMBER_4 (0x0040U) /* 4 (for asynchronous mode) */
|
||||
#define _SCIF_RX_TRIGGER_NUMBER_2 (0x0040U) /* 2 (for clock synchronous mode */
|
||||
#define _SCIF_RX_TRIGGER_NUMBER_8 (0x0080U) /* 8 */
|
||||
#define _SCIF_RX_TRIGGER_NUMBER_14 (0x00C0U) /* 14 */
|
||||
/* RTS# Output Active Trigger Number Select (RSTRG[2:0]) */
|
||||
#define _SCIF_RTS_TRIGGER_NUMBER_15 (0x0000U) /* 15 */
|
||||
#define _SCIF_RTS_TRIGGER_NUMBER_1 (0x0100U) /* 1 */
|
||||
#define _SCIF_RTS_TRIGGER_NUMBER_4 (0x0200U) /* 4 */
|
||||
#define _SCIF_RTS_TRIGGER_NUMBER_6 (0x0300U) /* 6 */
|
||||
#define _SCIF_RTS_TRIGGER_NUMBER_8 (0x0400U) /* 8 */
|
||||
#define _SCIF_RTS_TRIGGER_NUMBER_10 (0x0500U) /* 10 */
|
||||
#define _SCIF_RTS_TRIGGER_NUMBER_12 (0x0600U) /* 12 */
|
||||
#define _SCIF_RTS_TRIGGER_NUMBER_14 (0x0700U) /* 14 */
|
||||
|
||||
/*
|
||||
Serial port register (SPTR)
|
||||
*/
|
||||
/* Serial Port Break Data (SPB2DT) */
|
||||
#define _SCIF_SERIAL_BREAK_DATA_LOW (0x0000U) /* Input/output data is at low */
|
||||
#define _SCIF_SERIAL_BREAK_DATA_HIGH (0x0001U) /* Input/output data is at high */
|
||||
/* Serial Port Break input/output (SPB2IO) */
|
||||
#define _SCIF_SERIAL_BREAK_TXD_NO_OUTPUT (0x0000U) /* SPB2DT bit value is not output to TXD pin */
|
||||
#define _SCIF_SERIAL_BREAK_TXD_OUTPUT (0x0002U) /* SPB2DT bit value is output to TXD pin */
|
||||
/* SCK Port Data (SCKDT) */
|
||||
#define _SCIF_SCK_DATA_LOW (0x0000U) /* Input/output data is at low */
|
||||
#define _SCIF_SCK_DATA_HIGH (0x0004U) /* Input/output data is at high */
|
||||
/* SCK Port input/output (SCKIO) */
|
||||
#define _SCIF_SCK_PORT_NO_OUTPUT (0x0000U) /* SCKDT bit value is not output to SCK pin */
|
||||
#define _SCIF_SCK_PORT_OUTPUT (0x0008U) /* SCKDT bit value is output to SCK pin */
|
||||
/* CTS# Port Data Select (CTS2DT) */
|
||||
#define _SCIF_CTS_DATA_0 (0x0000U) /* Set b4 to 0. Controls CTS# pin with MCE, CTS2IO bit */
|
||||
#define _SCIF_CTS_DATA_1 (0x0010U) /* Set b4 to 1. Controls CTS# pin with MCE, CTS2IO bit */
|
||||
/* CTS# Port Output Specify (CTS2IO) */
|
||||
#define _SCIF_CTS_OUTPUT_0 (0x0000U) /* Set b5 to 0. Controls CTS# pin with MCE, CTS2IO bit */
|
||||
#define _SCIF_CTS_OUTPUT_1 (0x0020U) /* Set b5 to 1. Controls CTS# pin with MCE, CTS2IO bit */
|
||||
/* RTS# Port Data Select (RTS2DT) */
|
||||
#define _SCIF_RTS_DATA_0 (0x0000U) /* Set b6 to 0. Controls RTS# pin with MCE, RTS2IO bit */
|
||||
#define _SCIF_RTS_DATA_1 (0x0040U) /* Set b6 to 1. Controls RTS# pin with MCE, RTS2IO bit */
|
||||
/* RTS# Port Output Specify (RTS2IO) */
|
||||
#define _SCIF_RTS_OUTPUT_0 (0x0000U) /* Set b7 to 0. Controls RTS# pin with MCE, RTS2IO bit */
|
||||
#define _SCIF_RTS_OUTPUT_1 (0x0080U) /* Set b7 to 1. Controls RTS# pin with MCE, RTS2IO bit */
|
||||
|
||||
/*
|
||||
FIFO Trigger Control Register (FTCR)
|
||||
*/
|
||||
/* Transmit FIFO Data Trigger Number (TFTC[4:0]) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_0 (0x0000U) /* 0 (no transmit data trigger) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_1 (0x0001U) /* 1 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_2 (0x0002U) /* 2 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_3 (0x0003U) /* 3 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_4 (0x0004U) /* 4 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_5 (0x0005U) /* 5 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_6 (0x0006U) /* 6 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_7 (0x0007U) /* 7 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_8 (0x0008U) /* 8 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_9 (0x0009U) /* 9 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_10 (0x000AU) /* 10 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_11 (0x000BU) /* 11 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_12 (0x000CU) /* 12 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_13 (0x000DU) /* 13 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_14 (0x000EU) /* 14 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_15 (0x000FU) /* 15 (transmit data triggers) */
|
||||
/* Transmit Trigger Select (TTRGS) */
|
||||
#define _SCIF_TX_TRIGGER_TTRG_VALID (0x0000U) /* TTRG[1:0] bits in FCR are valid */
|
||||
#define _SCIF_TX_TRIGGER_TFTC_VALID (0x0080U) /* TFTC[4:0] bits in FTCR are valid */
|
||||
/* Receive FIFO Data Trigger Number (RFTC[4:0]) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_1 (0x0100U) /* 1 (no receive data trigger) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_2 (0x0200U) /* 2 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_3 (0x0300U) /* 3 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_4 (0x0400U) /* 4 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_5 (0x0500U) /* 5 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_6 (0x0600U) /* 6 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_7 (0x0700U) /* 7 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_8 (0x0800U) /* 8 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_9 (0x0900U) /* 9 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_10 (0x0A00U) /* 10 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_11 (0x0B00U) /* 11 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_12 (0x0C00U) /* 12 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_13 (0x0D00U) /* 13 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_14 (0x0E00U) /* 14 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_15 (0x0F00U) /* 15 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_16 (0x1000U) /* 16 (receive data triggers) */
|
||||
/* Transmit Trigger Select (RTRGS) */
|
||||
#define _SCIF_RX_TRIGGER_RTRG_VALID (0x0000U) /* RTRG[1:0] bits in FCR are valid */
|
||||
#define _SCIF_RX_TRIGGER_RFTC_VALID (0x8000U) /* RFTC[4:0] bits in FTCR are valid */
|
||||
|
||||
/*
|
||||
Serial extended mode register (SEMR)
|
||||
*/
|
||||
/* Asynchronous base clock select (ABCS0) */
|
||||
#define _SCIF_16_BASE_CLOCK (0x00U) /* Selects 16 base clock cycles for 1 bit period */
|
||||
#define _SCIF_8_BASE_CLOCK (0x01U) /* Selects 8 base clock cycles for 1 bit period */
|
||||
/* Noise Cancellation Enable (NFEN) */
|
||||
#define _SCIF_NOISE_FILTER_DISABLE (0x00U) /* Noise cancellation for the RxD pin input is disabled */
|
||||
#define _SCIF_NOISE_FILTER_ENABLE (0x04U) /* Noise cancellation for the RxD pin input is enabled */
|
||||
/* Data Transfer Direction Select (DIR) */
|
||||
#define _SCIF_DATA_TRANSFER_LSB_FIRST (0x00U) /* Transmits the data in FTDR by the LSB-first method */
|
||||
#define _SCIF_DATA_TRANSFER_MSB_FIRST (0x08U) /* Transmits the data in FTDR by the MSB-first method */
|
||||
/* Modulation Duty Register Select (MDDRS) */
|
||||
#define _SCIF_BRR_USED (0x00U) /* BRR register can be accessed */
|
||||
#define _SCIF_MDDR_USED (0x10U) /* MDDR register can be accessed. */
|
||||
/* Bit Rate Modulation Enable (BRME) */
|
||||
#define _SCIF_BIT_RATE_MODULATION_DISABLE (0x00U) /* Bit rate modulation function is disabled */
|
||||
#define _SCIF_BIT_RATE_MODULATION_ENABLE (0x20U) /* Bit rate modulation function is enabled */
|
||||
/* Baud Rate Generator Double-Speed Mode Select (BGDM) */
|
||||
#define _SCIF_BAUDRATE_SINGLE (0x00U) /* Baud rate generator outputs normal frequency */
|
||||
#define _SCIF_BAUDRATE_DOUBLE (0x80U) /* Baud rate generator doubles output frequency */
|
||||
|
||||
/*
|
||||
Interrupt Source Priority Register n (PRLn)
|
||||
*/
|
||||
/* Interrupt Priority Level Select (PRL[3:0]) */
|
||||
#define _SCIF_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */
|
||||
#define _SCIF_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */
|
||||
#define _SCIF_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */
|
||||
#define _SCIF_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */
|
||||
#define _SCIF_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */
|
||||
#define _SCIF_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */
|
||||
#define _SCIF_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */
|
||||
#define _SCIF_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */
|
||||
#define _SCIF_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */
|
||||
#define _SCIF_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */
|
||||
#define _SCIF_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */
|
||||
#define _SCIF_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */
|
||||
#define _SCIF_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */
|
||||
#define _SCIF_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */
|
||||
#define _SCIF_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */
|
||||
#define _SCIF_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */
|
||||
|
||||
/* FIFO buffer maximum size */
|
||||
#define _SCIF_FIFO_MAX_SIZE (0x10U) /* Size of 16-stage FIFO buffer */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#define _SCIF_1BIT_INTERVAL_2 (0x0619U) /* Wait time for 1-bit interval */
|
||||
#define _SCIF_RX_TRIG_NUM_2 (0x01U) /* Receive FIFO data trigger number */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
OVERRUN_ERROR,
|
||||
BREAK_DETECT,
|
||||
RECEIVE_ERROR
|
||||
} scif_error_type_t;
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_SCIFA2_Create(void);
|
||||
void R_SCIFA2_Start(void);
|
||||
void R_SCIFA2_Stop(void);
|
||||
MD_STATUS R_SCIFA2_Serial_Send(const uint8_t * tx_buf, uint16_t tx_num);
|
||||
MD_STATUS R_SCIFA2_Serial_Receive(uint8_t * rx_buf, uint16_t rx_num);
|
||||
void r_scifa2_callback_transmitend(void);
|
||||
void r_scifa2_callback_receiveend(void);
|
||||
void r_scifa2_callback_error(scif_error_type_t error_type);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
|
||||
/* Contains status of user input from the serial terminal program */
|
||||
extern volatile uint8_t g_terminal_request;
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
@ -0,0 +1,287 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_scifa_user.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for SCIF module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_scifa.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
#include "r_typedefs.h"
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
extern const uint8_t * gp_scifa2_tx_address; /* SCIFA2 send buffer address */
|
||||
extern uint16_t g_scifa2_tx_count; /* SCIFA2 send data number */
|
||||
extern uint8_t * gp_scifa2_rx_address; /* SCIFA2 receive buffer address */
|
||||
extern uint16_t g_scifa2_rx_count; /* SCIFA2 receive data number */
|
||||
extern uint16_t g_scifa2_rx_length; /* SCIFA2 receive data length */
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
|
||||
/* Contains status of user input from the serial terminal program */
|
||||
volatile uint8_t g_terminal_request = 0;
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_scifa2_txif2_interrupt
|
||||
* Description : This function is TXIF2 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_scifa2_txif2_interrupt(void)
|
||||
{
|
||||
uint16_t count = 0;
|
||||
|
||||
/* Get the amount of untransmitted data stored in the FRDR register */
|
||||
uint16_t dummy_fdr = SCIFA2.FDR.BIT.T;
|
||||
|
||||
/* Write data to the transmit FIFO data register */
|
||||
while ((g_scifa2_tx_count > 0U) && (count < _SCIF_FIFO_MAX_SIZE - dummy_fdr))
|
||||
{
|
||||
SCIFA2.FTDR = *gp_scifa2_tx_address;
|
||||
gp_scifa2_tx_address++;
|
||||
g_scifa2_tx_count--;
|
||||
count++;
|
||||
}
|
||||
|
||||
if (SCIFA2.FSR.BIT.TDFE == 1U)
|
||||
{
|
||||
SCIFA2.FSR.BIT.TDFE = 0U;
|
||||
}
|
||||
|
||||
if (g_scifa2_tx_count <= 0U)
|
||||
{
|
||||
SCIFA2.SCR.BIT.TIE = 0U;
|
||||
SCIFA2.SCR.BIT.TEIE = 1U;
|
||||
}
|
||||
|
||||
/* Wait the interrupt signal is disabled */
|
||||
while (0U != (VIC.IRQS3.LONG & 0x00008000UL))
|
||||
{
|
||||
VIC.IEC3.LONG = 0x00008000UL;
|
||||
}
|
||||
|
||||
VIC.IEN3.LONG |= 0x00008000UL;
|
||||
|
||||
/* Dummy write */
|
||||
VIC.HVA0.LONG = 0x00000000UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_scifa2_rxif2_interrupt
|
||||
* Description : This function is RXIF2 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_scifa2_rxif2_interrupt(void)
|
||||
{
|
||||
uint16_t count = 0;
|
||||
|
||||
/* Get the amount of receive data stored in FRDR register */
|
||||
uint16_t dummy_fdr = SCIFA2.FDR.BIT.R;
|
||||
|
||||
/* Read data from the receive FIFO data register */
|
||||
while ((g_scifa2_rx_length > g_scifa2_rx_count) && (count < dummy_fdr))
|
||||
{
|
||||
*gp_scifa2_rx_address = SCIFA2.FRDR;
|
||||
gp_scifa2_rx_address++;
|
||||
g_scifa2_rx_count++;
|
||||
count++;
|
||||
}
|
||||
|
||||
/* If remaining data is less than the receive trigger number, receive interrupt will not occur.
|
||||
In this case, set trigger number to 1 to force receive interrupt for each one byte of data in FRDR */
|
||||
if ((g_scifa2_rx_length - g_scifa2_rx_count < _SCIF_RX_TRIG_NUM_2) && (SCIFA2.FTCR.BIT.RFTC != 1U))
|
||||
{
|
||||
SCIFA2.FTCR.BIT.RFTC = 1U;
|
||||
}
|
||||
|
||||
/* Clear receive FIFO data full flag */
|
||||
if (SCIFA2.FSR.BIT.RDF == 1U)
|
||||
{
|
||||
SCIFA2.FSR.BIT.RDF = 0U;
|
||||
}
|
||||
|
||||
if (g_scifa2_rx_length <= g_scifa2_rx_count)
|
||||
{
|
||||
/* All data received */
|
||||
SCIFA2.SCR.BIT.RE = 0U;
|
||||
r_scifa2_callback_receiveend();
|
||||
}
|
||||
|
||||
/* Wait the interrupt signal is disabled */
|
||||
while (0U != (VIC.IRQS3.LONG & 0x00004000UL))
|
||||
{
|
||||
VIC.IEC3.LONG = 0x00004000UL;
|
||||
}
|
||||
|
||||
VIC.IEN3.LONG |= 0x00004000UL;
|
||||
|
||||
/* Dummy write */
|
||||
VIC.HVA0.LONG = 0x00000000UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_scifa2_drif2_interrupt
|
||||
* Description : This function is TEIF 2 or DRIF2 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_scifa2_drif2_interrupt(void)
|
||||
{
|
||||
if (1U == SCIFA2.FSR.BIT.TEND)
|
||||
{
|
||||
SCIFA2.SPTR.BIT.SPB2DT = 0U;
|
||||
SCIFA2.SPTR.BIT.SPB2IO = 1U;
|
||||
SCIFA2.SCR.BIT.TE = 0U;
|
||||
SCIFA2.SCR.BIT.TEIE = 0U;
|
||||
}
|
||||
r_scifa2_callback_transmitend();
|
||||
|
||||
/* Clear data ready detect flag */
|
||||
if (1U == SCIFA2.FSR.BIT.DR)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
SCIFA2.FSR.BIT.DR = 0U;
|
||||
}
|
||||
|
||||
/* Wait the interrupt signal is disabled */
|
||||
while (0U != (VIC.IRQS3.LONG & 0x00010000UL))
|
||||
{
|
||||
VIC.IEC3.LONG = 0x00010000UL;
|
||||
}
|
||||
|
||||
VIC.IEN3.LONG |= 0x00010000UL;
|
||||
|
||||
/* Dummy write */
|
||||
VIC.HVA0.LONG = 0x00000000UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_scifa2_brif2_interrupt
|
||||
* Description : This function is BRIF2 or ERIF2 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_scifa2_brif2_interrupt(void)
|
||||
{
|
||||
if (1U == SCIFA2.FSR.BIT.BRK)
|
||||
{
|
||||
r_scifa2_callback_error(BREAK_DETECT);
|
||||
/* Clear break detect flag */
|
||||
SCIFA2.FSR.BIT.BRK = 0U;
|
||||
}
|
||||
|
||||
if (1U == SCIFA2.FSR.BIT.ER)
|
||||
{
|
||||
r_scifa2_callback_error(RECEIVE_ERROR);
|
||||
/* Clear receive error flag */
|
||||
SCIFA2.FSR.BIT.ER = 0U;
|
||||
}
|
||||
|
||||
if (1U == SCIFA2.LSR.BIT.ORER)
|
||||
{
|
||||
r_scifa2_callback_error(OVERRUN_ERROR);
|
||||
/* Clear overrun error flag */
|
||||
SCIFA2.LSR.BIT.ORER = 0U;
|
||||
}
|
||||
|
||||
/* Wait the interrupt signal is disabled */
|
||||
while (0U != (VIC.IRQS3.LONG & 0x00002000UL))
|
||||
{
|
||||
VIC.IEC3.LONG = 0x00002000UL;
|
||||
}
|
||||
|
||||
VIC.IEN3.LONG |= 0x00002000UL;
|
||||
|
||||
/* Dummy write */
|
||||
VIC.HVA0.LONG = 0x00000000UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_scifa2_callback_transmitend
|
||||
* Description : This function is a callback function when SCIFA2 finishes transmission.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_scifa2_callback_transmitend(void)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_scifa2_callback_receiveend
|
||||
* Description : This function is a callback function when SCIFA2 finishes reception.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_scifa2_callback_receiveend(void)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
|
||||
/* Read the received data */
|
||||
uint8_t uart_in = SCIFA2.FRDR;
|
||||
|
||||
/* Check if desired character is received */
|
||||
if (('c' != uart_in) || ('C' != uart_in))
|
||||
{
|
||||
/* Set global flag to indicate user requested ADC reading */
|
||||
g_terminal_request = 1U;
|
||||
}
|
||||
|
||||
/* Re-enable receptions */
|
||||
SCIFA2.SCR.BIT.RE = 1U;
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_scifa2_callback_error
|
||||
* Description : This function is a callback function when SCIFA2 reception encounters error.
|
||||
* Arguments : error_type -
|
||||
* reception error type
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_scifa2_callback_error(scif_error_type_t error_type)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
|
||||
/* Used to suppress the warning message generated for unused variables */
|
||||
UNUSED_PARAM(error_type);
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@ -0,0 +1,103 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_systeminit.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements system initializing function.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_cgc.h"
|
||||
#include "r_cg_icu.h"
|
||||
#include "r_cg_port.h"
|
||||
#include "r_cg_tpu.h"
|
||||
#include "r_cg_cmt.h"
|
||||
#include "r_cg_scifa.h"
|
||||
#include "r_cg_rspi.h"
|
||||
#include "r_cg_s12ad.h"
|
||||
#include "r_cg_mpc.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
|
||||
void R_Systeminit(void);
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
extern void r_set_exception_handler(void);
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_Systeminit
|
||||
* Description : This function initializes every macro.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_Systeminit(void)
|
||||
{
|
||||
DI();
|
||||
|
||||
/* Enable writing to registers related to operating modes, LPC, CGC and ATCM */
|
||||
SYSTEM.PRCR.LONG = 0x0000A50BU;
|
||||
|
||||
/* Enable writing to MPC pin function control registers */
|
||||
MPC.PWPR.BIT.B0WI = 0U;
|
||||
MPC.PWPR.BIT.PFSWE = 1U;
|
||||
|
||||
r_set_exception_handler();
|
||||
|
||||
/* Set peripheral settings */
|
||||
R_CGC_Create();
|
||||
R_ICU_Create();
|
||||
R_PORT_Create();
|
||||
R_TPU_Create();
|
||||
R_CMT4_Create();
|
||||
R_CMT5_Create();
|
||||
R_SCIFA2_Create();
|
||||
R_RSPI1_Create();
|
||||
R_S12AD0_Create();
|
||||
R_MPC_Create();
|
||||
|
||||
/* Disable writing to MPC pin function control registers */
|
||||
MPC.PWPR.BIT.PFSWE = 0U;
|
||||
MPC.PWPR.BIT.B0WI = 1U;
|
||||
|
||||
/* Enable protection */
|
||||
SYSTEM.PRCR.LONG = 0x0000A500U;
|
||||
EI();
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@ -0,0 +1,98 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_tpu.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for TPU module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_tpu.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_TPU_Create
|
||||
* Description : This function initializes the TPU Unit0 module.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_TPU_Create(void)
|
||||
{
|
||||
/* Cancel TPU stop state in LPC */
|
||||
MSTP(TPU1) = 0U;
|
||||
|
||||
/* Stop all channels */
|
||||
TPUA.TSTRB.BYTE = 0x00U;
|
||||
|
||||
/* Channel 9 is used as normal mode */
|
||||
TPU9.TCR.BYTE = _TPU_PCLKD_4096 | _TPU_CKEG_IT_R | _TPU_CKCL_DIS;
|
||||
TPU9.TIER.BYTE |= _TPU_TGIEA_DISABLE | _TPU_TGIEB_DISABLE | _TPU_TGIEC_DISABLE | _TPU_TGIED_DISABLE |
|
||||
_TPU_TCIEV_DISABLE | _TPU_TTGE_DISABLE;
|
||||
TPU9.TIORH.BYTE = _TPU_IOB_IR | _TPU_IOA_DISABLE;
|
||||
TPU9.TIORL.BYTE = _TPU_IOD_IR | _TPU_IOC_IR;
|
||||
TPU9.TGRA = _TPU9_TCNTA_VALUE;
|
||||
TPU9.TMDR.BYTE = _TPU_NORMAL | _TPU_BFA_NORMAL | _TPU_BFB_NORMAL | _TPU_ICSELB_BPIN | _TPU_ICSELD_DPIN;
|
||||
|
||||
/* Internal PWM feedback function status */
|
||||
TPUSL.PWMFBSLR.LONG = _TPU_TPU0EN_DISABLE | _TPU_TPU1EN_DISABLE;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_TPU9_Start
|
||||
* Description : This function starts TPU channel 9 counter.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_TPU9_Start(void)
|
||||
{
|
||||
TPUA.TSTRB.BIT.CST3 = 1U;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_TPU9_Stop
|
||||
* Description : This function stops TPU channel 9 counter.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_TPU9_Stop(void)
|
||||
{
|
||||
TPUA.TSTRB.BIT.CST3 = 0U;
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
328
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu.h
Normal file
328
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu.h
Normal file
@ -0,0 +1,328 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_tpu.h
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for TPU module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
#ifndef TPU_H
|
||||
#define TPU_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
/*
|
||||
Timer Control Register (TCR)
|
||||
*/
|
||||
/* Time Prescaler Select (TPSC[2:0]) */
|
||||
#define _TPU_PCLKD_1 (0x00U) /* Internal clock: counts on PCLKD/1 */
|
||||
#define _TPU_PCLKD_4 (0x01U) /* Internal clock: counts on PCLKD/4 */
|
||||
#define _TPU_PCLKD_16 (0x02U) /* Internal clock: counts on PCLKD/16 */
|
||||
#define _TPU_PCLKD_64 (0x03U) /* Internal clock: counts on PCLKD/64 */
|
||||
#define _TPU_PCLKD_256 (0x06U) /* Internal clock: counts on PCLKD/256 */
|
||||
#define _TPU2_PCLKD_1024 (0x07U) /* TPU2 Internal clock: counts on PCLKD/1024 */
|
||||
#define _TPU3_PCLKD_1024 (0x05U) /* TPU3 Internal clock: counts on PCLKD/1024 */
|
||||
#define _TPU4_PCLKD_1024 (0x06U) /* TPU4 Internal clock: counts on PCLKD/1024 */
|
||||
#define _TPU8_PCLKD_1024 (0x07U) /* TPU8 Internal clock: counts on PCLKD/1024 */
|
||||
#define _TPU9_PCLKD_1024 (0x05U) /* TPU9 Internal clock: counts on PCLKD/1024 */
|
||||
#define _TPU10_PCLKD_1024 (0x06U) /* TPU10 Internal clock: counts on PCLKD/1024 */
|
||||
#define _TPU_PCLKD_4096 (0x07U) /* Internal clock: counts on PCLKD/4096 */
|
||||
#define _TPU_TCLKA (0x04U) /* External clock: counts on TCLKA pin input */
|
||||
#define _TPU_TCLKB (0x05U) /* External clock: counts on TCLKB pin input */
|
||||
#define _TPU_TCLKC_06 (0x06U) /* External clock: counts on TCLKC pin input */
|
||||
#define _TPU_TCLKC_05 (0x05U) /* External clock: counts on TCLKC pin input */
|
||||
#define _TPU_TCLKD (0x07U) /* External clock: counts on TCLKD pin input */
|
||||
#define _TPU_TCLKE (0x04U) /* External clock: counts on TCLKE pin input */
|
||||
#define _TPU_TCLKF (0x05U) /* External clock: counts on TCLKF pin input */
|
||||
#define _TPU_TCLKG_06 (0x06U) /* External clock: counts on TCLKG pin input */
|
||||
#define _TPU_TCLKG_05 (0x05U) /* External clock: counts on TCLKG pin input */
|
||||
#define _TPU_TCLKH (0x07U) /* External clock: counts on TCLKH pin input */
|
||||
#define _TPU2_COUNT (0x07U) /* TPU1: Counts on TPU2.TCNT counter overflow/underflow */
|
||||
#define _TPU5_COUNT (0x07U) /* TPU4: Counts on TPU5.TCNT counter overflow/underflow */
|
||||
#define _TPU8_COUNT (0x07U) /* TPU7: Counts on TPU8.TCNT counter overflow/underflow */
|
||||
#define _TPU11_COUNT (0x07U) /* TPU10: Counts on TPU11.TCNT counter overflow/underflow */
|
||||
/* Clock Edge Select (CKEG[1:0]) */
|
||||
#define _TPU_CKEG_IT_F (0x00U) /* Internal Clock: Count at falling edge */
|
||||
#define _TPU_CKEG_EX_R (0x00U) /* External Clock: Count at rising edge */
|
||||
#define _TPU_CKEG_IT_R (0x08U) /* Internal Clock: Count at rising edge */
|
||||
#define _TPU_CKEG_EX_F (0x08U) /* External Clock: Count at falling edge */
|
||||
#define _TPU_CKEG_BOTH (0x10U) /* Count at both edge */
|
||||
/* Counter Clear Select (CCLR[2:0]) */
|
||||
#define _TPU_CKCL_DIS (0x00U) /* TCNT clearing disabled */
|
||||
#define _TPU_CKCL_A (0x20U) /* TCNT cleared by TGRA compare match/input capture */
|
||||
#define _TPU_CKCL_B (0x40U) /* TCNT cleared by TGRB compare match/input capture */
|
||||
#define _TPU_CKCL_SYN (0x60U) /* TCNT cleared by counter clearing in another synchronous channel */
|
||||
#define _TPU_CKCL_C (0xA0U) /* TCNT cleared by TGRC compare match/input capture */
|
||||
#define _TPU_CKCL_D (0xC0U) /* TCNT cleared by TGRD compare match/input capture */
|
||||
|
||||
/*
|
||||
Timer Mode Register (TMDR)
|
||||
*/
|
||||
/* Mode Select (MD[3:0]) */
|
||||
#define _TPU_NORMAL (0x00U) /* Normal mode */
|
||||
#define _TPU_PWM1 (0x02U) /* PWM mode 1 */
|
||||
#define _TPU_PWM2 (0x03U) /* PWM mode 2 */
|
||||
#define _TPU_COT1 (0x04U) /* Phase counting mode 1 */
|
||||
#define _TPU_COT2 (0x05U) /* Phase counting mode 2 */
|
||||
#define _TPU_COT3 (0x06U) /* Phase counting mode 3 */
|
||||
#define _TPU_COT4 (0x07U) /* Phase counting mode 4 */
|
||||
/* Buffer Operation A (BFA) */
|
||||
#define _TPU_BFA_NORMAL (0x00U) /* TPUm.TGRA operates normally (m = 0, 3, 6, 9) */
|
||||
#define _TPU_BFA_BUFFER (0x10U) /* TPUm.TGRA and TPUm.TGRC used together for buffer operation */
|
||||
/* Buffer Operation B (BFB) */
|
||||
#define _TPU_BFB_NORMAL (0x00U) /* TPUm.TGRB operates normally (m = 0, 3, 6, 9) */
|
||||
#define _TPU_BFB_BUFFER (0x20U) /* TPUm.TGRB and TPUm.TGRD used together for buffer operation */
|
||||
/* TGRB Input Capture Input Select (ICSELB) */
|
||||
#define _TPU_ICSELB_BPIN (0x00U) /* Input capture input source is TIOCBn pin */
|
||||
#define _TPU_ICSELB_APIN (0x40U) /* Input capture input source is TIOCAn pin (n = 0 to 11) */
|
||||
/* TGRD Input Capture Input Select (ICSELD) */
|
||||
#define _TPU_ICSELD_DPIN (0x00U) /* Input capture input source is TIOCDn pin */
|
||||
#define _TPU_ICSELD_CPIN (0x80U) /* Input capture input source is TIOCCn pin (n = 0, 3, 6, 9) */
|
||||
|
||||
/*
|
||||
Timer I/O Control Register (TIOR)
|
||||
*/
|
||||
/* I/O Control A (IOA[3:0]) for TPU0.TIORH, TPU1.TIOR, TPU2.TIOR, TPU3.TIORH, TPU4.TIORH, TPU5.TIOR
|
||||
TPU6.TIORH, TPU7.TIOR, TPU8.TIOR, TPU9.TIORH, TPU10.TIOR, TPU11.TIOR*/
|
||||
#define _TPU_IOA_DISABLE (0x00U) /* Output prohibited */
|
||||
#define _TPU_IOA_LL (0x01U) /* Initial output is low. Low output at compare match */
|
||||
#define _TPU_IOA_LH (0x02U) /* Initial output is low. High output at compare match */
|
||||
#define _TPU_IOA_LT (0x03U) /* Initial output is low. Toggle output at compare match */
|
||||
#define _TPU_IOA_HL (0x05U) /* Initial output is high. Low output at compare match */
|
||||
#define _TPU_IOA_HH (0x06U) /* Initial output is high. High output at compare match */
|
||||
#define _TPU_IOA_HT (0x07U) /* Initial output is high. Toggle output at compare match */
|
||||
#define _TPU_IOA_IR (0x08U) /* Input capture at rising edge. */
|
||||
#define _TPU_IOA_IF (0x09U) /* Input capture at falling edge */
|
||||
#define _TPU_IOA_IB (0x0AU) /* Input capture at both edges */
|
||||
#define _TPU_IOA_EX (0x0CU) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count
|
||||
or TPU7.TCNT or TPU10.TCNT up-count/down-count */
|
||||
#define _TPU_IOA_TGRA (0x0DU) /* Input capture at TPU0.TGRA or TPU3.TGRA compare match/input capture
|
||||
or TPU6.TGRA or TPU9.TGRA compare match/input capture */
|
||||
/* I/O Control B (IOB[3:0]) for TPU0.TIORH, TPU1.TIOR, TPU2.TIOR, TPU3.TIORH, TPU4.TIORH, TPU5.TIOR
|
||||
TPU6.TIORH, TPU7.TIOR, TPU8.TIOR, TPU9.TIORH, TPU10.TIOR, TPU11.TIOR*/
|
||||
#define _TPU_IOB_DISABLE (0x00U) /* Output prohibited */
|
||||
#define _TPU_IOB_LL (0x10U) /* Initial output is low. Low output at compare match */
|
||||
#define _TPU_IOB_LH (0x20U) /* Initial output is low. High output at compare match */
|
||||
#define _TPU_IOB_LT (0x30U) /* Initial output is low. Toggle output at compare match */
|
||||
#define _TPU_IOB_HL (0x50U) /* Initial output is high. Low output at compare match */
|
||||
#define _TPU_IOB_HH (0x60U) /* Initial output is high. High output at compare match */
|
||||
#define _TPU_IOB_HT (0x70U) /* Initial output is high. Toggle output at compare match */
|
||||
#define _TPU_IOB_IR (0x80U) /* Input capture at rising edge */
|
||||
#define _TPU_IOB_IF (0x90U) /* Input capture at falling edge */
|
||||
#define _TPU_IOB_IB (0xA0U) /* Input capture at both edges. */
|
||||
#define _TPU_IOB_EX (0xC0U) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count
|
||||
or TPU7.TCNT or TPU10.TCNT up-count/down-count*/
|
||||
#define _TPU_IOB_TGRC (0xD0U) /* Input capture at TPU0.TGRC or TPU3.TGRC compare match/input capture
|
||||
or TPU6.TGRC or TPU9.TGRC compare match/input capture*/
|
||||
/* I/O Control C (IOC[3:0]) for TPU0.TIORL, TPU3.TIORL, TPU6.TIORL, TPU9.TIORL */
|
||||
#define _TPU_IOC_DISABLE (0x00U) /* Output prohibited */
|
||||
#define _TPU_IOC_LL (0x01U) /* Initial output is low. Low output at compare match */
|
||||
#define _TPU_IOC_LH (0x02U) /* Initial output is low. High output at compare match */
|
||||
#define _TPU_IOC_LT (0x03U) /* Initial output is low. Toggle output at compare match */
|
||||
#define _TPU_IOC_HL (0x05U) /* Initial output is high. Low output at compare match. */
|
||||
#define _TPU_IOC_HH (0x06U) /* Initial output is high. High output at compare match. */
|
||||
#define _TPU_IOC_HT (0x07U) /* Initial output is high. Toggle output at compare match. */
|
||||
#define _TPU_IOC_IR (0x08U) /* Input capture at rising edge. */
|
||||
#define _TPU_IOC_IF (0x09U) /* Input capture at falling edge. */
|
||||
#define _TPU_IOC_IB (0x0AU) /* Input capture at both edges. */
|
||||
#define _TPU_IOC_EX (0x0CU) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count
|
||||
or TPU7.TCNT or TPU10.TCNT up-count/down-count. */
|
||||
/* I/O Control D (IOD[3:0]) for TPU0.TIORL, TPU3.TIORL, TPU6.TIORL, TPU9.TIOR */
|
||||
#define _TPU_IOD_DISABLE (0x00U) /* Output prohibited */
|
||||
#define _TPU_IOD_LL (0x10U) /* Initial output is low. Low output at compare match */
|
||||
#define _TPU_IOD_LH (0x20U) /* Initial output is low. High output at compare match */
|
||||
#define _TPU_IOD_LT (0x30U) /* Initial output is low. Toggle output at compare match */
|
||||
#define _TPU_IOD_HL (0x50U) /* Initial output is high. Low output at compare match. */
|
||||
#define _TPU_IOD_HH (0x60U) /* Initial output is high. High output at compare match. */
|
||||
#define _TPU_IOD_HT (0x70U) /* Initial output is high. Toggle output at compare match. */
|
||||
#define _TPU_IOD_IR (0x80U) /* Input capture at rising edge. */
|
||||
#define _TPU_IOD_IF (0x90U) /* Input capture at falling edge. */
|
||||
#define _TPU_IOD_IB (0xA0U) /* Input capture at both edges. */
|
||||
#define _TPU_IOD_EX (0xC0U) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count
|
||||
or TPU7.TCNT or TPU10.TCNT up-count/down-count. */
|
||||
|
||||
/*
|
||||
Timer Start Registers (TSTRA)
|
||||
*/
|
||||
/* Counter Start 0 (CST0) */
|
||||
#define _TPU_CST0_OFF (0x00U) /* TPU0.TCNT performs count stop */
|
||||
#define _TPU_CST0_ON (0x01U) /* TPU0.TCNT performs count operation */
|
||||
/* Counter Start 1 (CST1) */
|
||||
#define _TPU_CST1_OFF (0x00U) /* TPU1.TCNT performs count stop */
|
||||
#define _TPU_CST1_ON (0x02U) /* TPU1.TCNT performs count operation */
|
||||
/* Counter Start 2 (CST2) */
|
||||
#define _TPU_CST2_OFF (0x00U) /* TPU3.TCNT performs count stop */
|
||||
#define _TPU_CST2_ON (0x04U) /* TPU3.TCNT performs count operation */
|
||||
/* Counter Start 3 (CST3) */
|
||||
#define _TPU_CST3_OFF (0x00U) /* TPU3.TCNT performs count stop */
|
||||
#define _TPU_CST3_ON (0x08U) /* TPU3.TCNT performs count operation */
|
||||
/* Counter Start 4 (CST4) */
|
||||
#define _TPU_CST4_OFF (0x00U) /* TPU4.TCNT performs count stop */
|
||||
#define _TPU_CST4_ON (0x10U) /* TPU4.TCNT performs count operation */
|
||||
/* Counter Start 5 (CST5) */
|
||||
#define _TPU_CST5_OFF (0x00U) /* TPU5.TCNT performs count stop */
|
||||
#define _TPU_CST5_ON (0x20U) /* TPU5.TCNT performs count operation */
|
||||
|
||||
/*
|
||||
Timer Start Registers (TSTRB)
|
||||
*/
|
||||
/* Counter Start 6 (CST0) */
|
||||
#define _TPU_CST6_OFF (0x00U) /* TPU6.TCNT performs count stop */
|
||||
#define _TPU_CST6_ON (0x01U) /* TPU6.TCNT performs count operation */
|
||||
/* Counter Start 7 (CST1) */
|
||||
#define _TPU_CST7_OFF (0x00U) /* TPU7.TCNT performs count stop */
|
||||
#define _TPU_CST7_ON (0x02U) /* TPU7.TCNT performs count operation */
|
||||
/* Counter Start 8 (CST2) */
|
||||
#define _TPU_CST8_OFF (0x00U) /* TPU8.TCNT performs count stop */
|
||||
#define _TPU_CST8_ON (0x04U) /* TPU8.TCNT performs count operation */
|
||||
/* Counter Start 9 (CST3) */
|
||||
#define _TPU_CST9_OFF (0x00U) /* TPU9.TCNT performs count stop */
|
||||
#define _TPU_CST9_ON (0x08U) /* TPU9.TCNT performs count operation */
|
||||
/* Counter Start 10 (CST4) */
|
||||
#define _TPU_CST10_OFF (0x00U) /* TPU10.TCNT performs count stop */
|
||||
#define _TPU_CST10_ON (0x10U) /* TPU10.TCNT performs count operation */
|
||||
/* Counter Start 11 (CST5) */
|
||||
#define _TPU_CST11_OFF (0x00U) /* TPU11.TCNT performs count stop */
|
||||
#define _TPU_CST11_ON (0x20U) /* TPU11.TCNT performs count operation */
|
||||
|
||||
/*
|
||||
Noise Filter Control Register (NFCR)
|
||||
*/
|
||||
/* Noise Filter A Enable Bit (NFAEN) */
|
||||
#define _TPU_NFAEN_DISABLE (0x00U) /* The noise filter for the TIOCAm pin is disabled */
|
||||
#define _TPU_NFAEN_ENABLE (0x01U) /* The noise filter for the TIOCAm pin is enabled */
|
||||
/* Noise Filter B Enable Bit (NFBEN) */
|
||||
#define _TPU_NFBEN_DISABLE (0x00U) /* The noise filter for the TIOCBm pin is disabled */
|
||||
#define _TPU_NFBEN_ENABLE (0x02U) /* The noise filter for the TIOCBm pin is enabled */
|
||||
/* Noise Filter C Enable Bit (NFCEN) */
|
||||
#define _TPU_NFCEN_DISABLE (0x00U) /* The noise filter for the TIOCCm pin is disabled */
|
||||
#define _TPU_NFCEN_ENABLE (0x04U) /* The noise filter for the TIOCCm pin is enabled */
|
||||
/* Noise Filter D Enable Bit (NFDEN) */
|
||||
#define _TPU_NFDEN_DISABLE (0x00U) /* The noise filter for the TIOCDm pin is disabled */
|
||||
#define _TPU_NFDEN_ENABLE (0x08U) /* The noise filter for the TIOCDm pin is enabled */
|
||||
/* Noise Filter Clock Select (NFCS[1:0]) */
|
||||
#define _TPU_NFCS_PCLKD_1 (0x00U) /* PCLKD/1 */
|
||||
#define _TPU_NFCS_PCLKD_8 (0x10U) /* PCLKD/8 */
|
||||
#define _TPU_NFCS_PCLKD_32 (0x20U) /* PCLKD/32 */
|
||||
#define _TPU_NFCS_EXCLK (0x30U) /* The clock source for counting is the external clock */
|
||||
|
||||
/*
|
||||
PWM Feedback Select Register (PWMFBSLR)
|
||||
*/
|
||||
/* TPU (Unit 0) Internal PWM Feedback Enable (TPU0EN)*/
|
||||
#define _TPU_TPU0EN_DISABLE (0x00000000UL) /* Internal PWM feedback input function unit 0 is disabled */
|
||||
#define _TPU_TPU0EN_ENABLE (0x00000001UL) /* Internal PWM feedback input function unit 0 is enabled */
|
||||
/* Internal PWM Feedback Input Source Select 0 (FBSL0[2:0]) */
|
||||
#define _TPU0_PWM_SIG_MTU34 (0x00000010UL) /* PWM output signals of MTU3 and MTU4 */
|
||||
#define _TPU0_PWM_SIG_MTU67 (0x00000014UL) /* PWM output signals of MTU6 and MTU7 */
|
||||
#define _TPU0_PWM_SIG_GPT02 (0x00000018UL) /* PWM output signals of GPT0 to GPT2 */
|
||||
/* TPU (Unit 1) Internal PWM Feedback Enable (TPU1EN)*/
|
||||
#define _TPU_TPU1EN_DISABLE (0x00000000UL) /* Internal PWM feedback input function unit 1 is disabled */
|
||||
#define _TPU_TPU1EN_ENABLE (0x00000100UL) /* Internal PWM feedback input function unit 1 is enabled */
|
||||
/* Internal PWM Feedback Input Source Select 1 (FBSL1[2:0]) */
|
||||
#define _TPU1_PWM_SIG_MTU34 (0x00001000UL) /* PWM output signals of MTU3 and MTU4 */
|
||||
#define _TPU1_PWM_SIG_MTU67 (0x00001400UL) /* PWM output signals of MTU6 and MTU7 */
|
||||
#define _TPU1_PWM_SIG_GPT02 (0x00001800UL) /* PWM output signals of GPT0 to GPT2 */
|
||||
/*
|
||||
Timer Interrupt Enable Register (TIER)
|
||||
*/
|
||||
/* TGR Interrupt Enable A (TGIEA) */
|
||||
#define _TPU_TGIEA_DISABLE (0x00U) /* Interrupt requests TGIA disabled */
|
||||
#define _TPU_TGIEA_ENABLE (0x01U) /* Interrupt requests TGIA enabled */
|
||||
/* TGR Interrupt Enable B (TGIEB) */
|
||||
#define _TPU_TGIEB_DISABLE (0x00U) /* Interrupt requests TGIB disabled */
|
||||
#define _TPU_TGIEB_ENABLE (0x02U) /* Interrupt requests TGIB enabled */
|
||||
/* TGR Interrupt Enable C (TGIEC) */
|
||||
#define _TPU_TGIEC_DISABLE (0x00U) /* Interrupt requests TGIC disabled */
|
||||
#define _TPU_TGIEC_ENABLE (0x04U) /* Interrupt requests TGIC enabled */
|
||||
/* TGR Interrupt Enable D (TGIED) */
|
||||
#define _TPU_TGIED_DISABLE (0x00U) /* Interrupt requests TGID disabled */
|
||||
#define _TPU_TGIED_ENABLE (0x08U) /* Interrupt requests TGID enabled */
|
||||
/* Overflow Interrupt Enable (TCIEV) */
|
||||
#define _TPU_TCIEV_DISABLE (0x00U) /* Interrupt requests TCIV disabled */
|
||||
#define _TPU_TCIEV_ENABLE (0x10U) /* Interrupt requests TCIV enabled */
|
||||
/* Underflow Interrupt Enable (TCIEU) */
|
||||
#define _TPU_TCIEU_DISABLE (0x00U) /* Interrupt requests TCIU disabled */
|
||||
#define _TPU_TCIEU_ENABLE (0x20U) /* Interrupt requests TCIU enabled */
|
||||
/* A/D Converter Start Request Enable (TTGE) */
|
||||
#define _TPU_TTGE_DISABLE (0x00U) /* A/D converter start request generation disabled */
|
||||
#define _TPU_TTGE_ENABLE (0x80U) /* A/D converter start request generation enabled */
|
||||
|
||||
/*
|
||||
Interrupt Source Priority Register n (PRLn)
|
||||
*/
|
||||
/* Interrupt Priority Level Select (PRL[3:0]) */
|
||||
#define _TPU_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */
|
||||
#define _TPU_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */
|
||||
#define _TPU_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */
|
||||
#define _TPU_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */
|
||||
#define _TPU_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */
|
||||
#define _TPU_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */
|
||||
#define _TPU_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */
|
||||
#define _TPU_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */
|
||||
#define _TPU_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */
|
||||
#define _TPU_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */
|
||||
#define _TPU_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */
|
||||
#define _TPU_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */
|
||||
#define _TPU_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */
|
||||
#define _TPU_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */
|
||||
#define _TPU_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */
|
||||
#define _TPU_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */
|
||||
#define _TPU_PRIORITY_LEVEL16 (0x00000000UL) /* Level 16 */
|
||||
#define _TPU_PRIORITY_LEVEL17 (0x00000001UL) /* Level 17 */
|
||||
#define _TPU_PRIORITY_LEVEL18 (0x00000002UL) /* Level 18 */
|
||||
#define _TPU_PRIORITY_LEVEL19 (0x00000003UL) /* Level 19 */
|
||||
#define _TPU_PRIORITY_LEVEL20 (0x00000004UL) /* Level 20 */
|
||||
#define _TPU_PRIORITY_LEVEL21 (0x00000005UL) /* Level 21 */
|
||||
#define _TPU_PRIORITY_LEVEL22 (0x00000006UL) /* Level 22 */
|
||||
#define _TPU_PRIORITY_LEVEL23 (0x00000007UL) /* Level 23 */
|
||||
#define _TPU_PRIORITY_LEVEL24 (0x00000008UL) /* Level 24 */
|
||||
#define _TPU_PRIORITY_LEVEL25 (0x00000009UL) /* Level 25 */
|
||||
#define _TPU_PRIORITY_LEVEL26 (0x0000000AUL) /* Level 26 */
|
||||
#define _TPU_PRIORITY_LEVEL27 (0x0000000BUL) /* Level 27 */
|
||||
#define _TPU_PRIORITY_LEVEL28 (0x0000000CUL) /* Level 28 */
|
||||
#define _TPU_PRIORITY_LEVEL29 (0x0000000DUL) /* Level 29 */
|
||||
#define _TPU_PRIORITY_LEVEL30 (0x0000000EUL) /* Level 30 */
|
||||
#define _TPU_PRIORITY_LEVEL31 (0x0000000FUL) /* Level 31 (lowest) */
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
/* TGRA value channel 9 */
|
||||
#define _TPU9_TCNTA_VALUE (0x0726U)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_TPU_Create(void);
|
||||
void R_TPU9_Start(void);
|
||||
void R_TPU9_Stop(void);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
@ -0,0 +1,52 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_tpu_user.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for TPU module.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_tpu.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@ -0,0 +1,72 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_userdefine.h
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file includes user definition.
|
||||
* Creation Date: 22/04/2015
|
||||
***********************************************************************************************************************/
|
||||
#ifndef _USER_DEF_H
|
||||
#define _USER_DEF_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
User definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
|
||||
#define MPC_PFSWE_WRITE_ENABLE (0x00)
|
||||
#define MPC_PFS_WRITE_ENABLE (0x40)
|
||||
#define MPC_PFS_WRITE_DISABLE (0x80)
|
||||
|
||||
#define MPC_IRQ_DISABLE (0)
|
||||
#define MPC_IRQ_ENABLE (1)
|
||||
|
||||
/* Define LED states */
|
||||
#define LED_ON (1U)
|
||||
#define LED_OFF (0U)
|
||||
|
||||
/* Define user LEDs mode register pins */
|
||||
#define LED0_MODE (PORTF.PMR.BIT.B7)
|
||||
#define LED1_MODE (PORT5.PMR.BIT.B6)
|
||||
#define LED2_MODE (PORT7.PMR.BIT.B7)
|
||||
#define LED3_MODE (PORTA.PMR.BIT.B0)
|
||||
|
||||
/* Define user LEDs direction's pins */
|
||||
#define LED0_DIR (PORTF.PDR.BIT.B7)
|
||||
#define LED1_DIR (PORT5.PDR.BIT.B6)
|
||||
#define LED2_DIR (PORT7.PDR.BIT.B7)
|
||||
#define LED3_DIR (PORTA.PDR.BIT.B0)
|
||||
|
||||
/* Define user LEDs */
|
||||
#define LED0 (PORTF.PODR.BIT.B7)
|
||||
#define LED1 (PORT5.PODR.BIT.B6)
|
||||
#define LED2 (PORT7.PODR.BIT.B7)
|
||||
#define LED3 (PORTA.PODR.BIT.B0)
|
||||
|
||||
void R_MPC_WriteEnable (void);
|
||||
void R_MPC_WriteDisable (void);
|
||||
|
||||
extern void r_set_exception_handler(void);
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
539
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/main.c
Normal file
539
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/main.c
Normal file
@ -0,0 +1,539 @@
|
||||
#if 1
|
||||
/*
|
||||
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* This project provides two demo applications. A simple blinky style project,
|
||||
* and a more comprehensive test and demo application. The
|
||||
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
|
||||
* select between the two. The simply blinky demo is implemented and described
|
||||
* in main_blinky.c. The more comprehensive test and demo application is
|
||||
* implemented and described in main_full.c.
|
||||
*
|
||||
* This file implements the code that is not demo specific, including the
|
||||
* hardware setup, standard FreeRTOS hook functions, and the ISR hander called
|
||||
* by the RTOS after interrupt entry (including nesting) has been taken care of.
|
||||
*
|
||||
* ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON
|
||||
* THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO
|
||||
* APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!
|
||||
*
|
||||
*/
|
||||
|
||||
/* Standard includes. */
|
||||
#include "string.h"
|
||||
|
||||
/* Scheduler include files. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "semphr.h"
|
||||
|
||||
/* Renesas includes. */
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_icu.h"
|
||||
#include "r_cg_scifa.h"
|
||||
#include "r_cg_rspi.h"
|
||||
#include "r_system.h"
|
||||
#include "r_reset.h"
|
||||
#include "siochar.h"
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
|
||||
or 0 to run the more comprehensive test and demo application. */
|
||||
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvClearBSS( void );
|
||||
|
||||
/*
|
||||
* Configure the hardware as necessary to run this demo.
|
||||
*/
|
||||
static void prvSetupHardware( void );
|
||||
|
||||
/*
|
||||
* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
|
||||
* main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
|
||||
*/
|
||||
#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )
|
||||
extern void main_blinky( void );
|
||||
#else
|
||||
extern void main_full( void );
|
||||
#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */
|
||||
|
||||
/* Prototypes for the standard FreeRTOS callback/hook functions implemented
|
||||
within this file. */
|
||||
void vApplicationMallocFailedHook( void );
|
||||
void vApplicationIdleHook( void );
|
||||
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
|
||||
void vApplicationTickHook( void );
|
||||
|
||||
/* Prototype for the IRQ handler called by the generic Cortex-A5 RTOS port
|
||||
layer. */
|
||||
void vApplicationIRQHandler( void );
|
||||
|
||||
/* Library initialisation. */
|
||||
extern void R_Systeminit( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
volatile uint32_t ultest = 0, ultest2 = 9999;
|
||||
|
||||
int main( void )
|
||||
{
|
||||
prvClearBSS();
|
||||
|
||||
configASSERT( ultest == 0 );
|
||||
configASSERT( ultest2 == 9999 );
|
||||
|
||||
/* Configure the hardware ready to run the demo. */
|
||||
prvSetupHardware();
|
||||
|
||||
/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
|
||||
of this file. */
|
||||
#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )
|
||||
{
|
||||
main_blinky();
|
||||
}
|
||||
#else
|
||||
{
|
||||
main_full();
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvSetupHardware( void )
|
||||
{
|
||||
R_Systeminit();
|
||||
|
||||
/* Enable RSPI1 (serial peripheral interface). */
|
||||
R_RSPI1_Start();
|
||||
|
||||
/* Configure the UART channel for communication with a host PC via on-board
|
||||
RL78/G1C device. */
|
||||
io_init_scifa2();
|
||||
|
||||
/* Enable SCIFA2 (serial communications interface with FIFO). */
|
||||
R_SCIFA2_Start();
|
||||
|
||||
/* SW3 interrupts. */
|
||||
R_ICU_IRQ12_Start();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationMallocFailedHook( void )
|
||||
{
|
||||
/* Called if a call to pvPortMalloc() fails because there is insufficient
|
||||
free memory available in the FreeRTOS heap. pvPortMalloc() is called
|
||||
internally by FreeRTOS API functions that create tasks, queues, software
|
||||
timers, and semaphores. The size of the FreeRTOS heap is set by the
|
||||
configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */
|
||||
|
||||
/* Force an assert. */
|
||||
configASSERT( ( volatile void * ) NULL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
|
||||
{
|
||||
( void ) pcTaskName;
|
||||
( void ) pxTask;
|
||||
|
||||
/* Run time stack overflow checking is performed if
|
||||
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
|
||||
function is called if a stack overflow is detected. */
|
||||
|
||||
/* Force an assert. */
|
||||
configASSERT( ( volatile void * ) NULL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationIdleHook( void )
|
||||
{
|
||||
volatile size_t xFreeHeapSpace;
|
||||
|
||||
/* This is just a trivial example of an idle hook. It is called on each
|
||||
cycle of the idle task. It must *NOT* attempt to block. In this case the
|
||||
idle task just queries the amount of FreeRTOS heap that remains. See the
|
||||
memory management section on the http://www.FreeRTOS.org web site for memory
|
||||
management options. If there is a lot of heap memory free then the
|
||||
configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up
|
||||
RAM. */
|
||||
// xFreeHeapSpace = xPortGetFreeHeapSize();
|
||||
|
||||
/* Remove compiler warning about xFreeHeapSpace being set but never used. */
|
||||
( void ) xFreeHeapSpace;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationTickHook( void )
|
||||
{
|
||||
#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0
|
||||
{
|
||||
extern void vFullDemoTickHook( void );
|
||||
|
||||
vFullDemoTickHook();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The function called by the RTOS port layer after it has managed interrupt
|
||||
entry. */
|
||||
void vApplicationIRQHandler( void )
|
||||
{
|
||||
#if 1
|
||||
extern void FreeRTOS_Tick_Handler( void );
|
||||
|
||||
/* Clear the interrupt source CMI5. */
|
||||
VIC.PIC9.LONG = 0x00001000UL;
|
||||
|
||||
FreeRTOS_Tick_Handler();
|
||||
|
||||
/* Dummy write */
|
||||
portDISABLE_INTERRUPTS();
|
||||
// Done in the epilogue code VIC.HVA0.LONG = 0x00000000UL;
|
||||
|
||||
#else
|
||||
typedef void (*ISRFunction_t)( void );
|
||||
ISRFunction_t pxISRFunction;
|
||||
volatile uint32_t * pulAIC_IVR = ( uint32_t * ) configINTERRUPT_VECTOR_ADDRESS;
|
||||
|
||||
/* Obtain the address of the interrupt handler from the AIR. */
|
||||
pxISRFunction = ( ISRFunction_t ) *pulAIC_IVR;
|
||||
|
||||
/* Write back to the SAMA5's interrupt controller's IVR register in case the
|
||||
CPU is in protect mode. If the interrupt controller is not in protect mode
|
||||
then this write is not necessary. */
|
||||
*pulAIC_IVR = ( uint32_t ) pxISRFunction;
|
||||
|
||||
/* Ensure the write takes before re-enabling interrupts. */
|
||||
__DSB();
|
||||
__ISB();
|
||||
__enable_irq();
|
||||
|
||||
/* Call the installed ISR. */
|
||||
pxISRFunction();
|
||||
#endif
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvClearBSS( void )
|
||||
{
|
||||
extern uint32_t __bss_start__[];
|
||||
extern uint32_t __bss_end__[];
|
||||
size_t xSize;
|
||||
|
||||
/* Zero out bss. */
|
||||
xSize = ( ( size_t ) __bss_end__ ) - ( ( size_t ) __bss_start__ );
|
||||
memset( ( void * ) __bss_start__, 0x00, xSize );
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#else
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_cgc.h"
|
||||
#include "r_cg_icu.h"
|
||||
#include "r_cg_port.h"
|
||||
#include "r_cg_tpu.h"
|
||||
#include "r_cg_cmt.h"
|
||||
#include "r_cg_scifa.h"
|
||||
#include "r_cg_rspi.h"
|
||||
#include "r_cg_s12ad.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
#include "r_cg_mpc.h"
|
||||
#include "r_system.h"
|
||||
#include "r_reset.h"
|
||||
#include "lcd_pmod.h"
|
||||
#include "logo_data.h"
|
||||
#include "stdio.h"
|
||||
#include "siochar.h"
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
|
||||
#define LZ_ENABLE (1)
|
||||
#define LZ_DISABLE (0)
|
||||
|
||||
/* Welcome banner - displayed on serial port at startup*/
|
||||
static uint8_t welcome_banner[] = "\n\n\rRSK+RZT1 \n\n\r- Tutorial - Press 'c' or SW3 for ADC Conversion\r\n\0";
|
||||
|
||||
/* Used as a Data Transmit counter */
|
||||
static uint8_t uart_buffer[] = " ADC count: x. Value: xxxxx\r\n";
|
||||
|
||||
/* Used as a Data Transmit counter */
|
||||
static uint8_t lcd_buffer[] = " ADC = xxxx ";
|
||||
|
||||
/* Function prototype for displaying the 2 bit binary counter using LEDs */
|
||||
static void led_display_count (const uint8_t count);
|
||||
|
||||
extern void R_Systeminit(void);
|
||||
void R_MAIN_UserInit(void);
|
||||
|
||||
/* Prototypes for the standard FreeRTOS callback/hook functions implemented
|
||||
within this file. */
|
||||
void vApplicationMallocFailedHook( void );
|
||||
void vApplicationIdleHook( void );
|
||||
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
|
||||
void vApplicationTickHook( void );
|
||||
|
||||
|
||||
/* Prototype for the IRQ handler called by the generic Cortex-A5 RTOS port
|
||||
layer. */
|
||||
void vApplicationIRQHandler( void );
|
||||
|
||||
void main(void)
|
||||
{
|
||||
uint32_t adc_count = 0;
|
||||
|
||||
R_Systeminit();
|
||||
|
||||
R_MAIN_UserInit();
|
||||
|
||||
/* SW3 interrupts */
|
||||
R_ICU_IRQ12_Start();
|
||||
|
||||
/* Clear flags */
|
||||
g_switch_press_flg = 0;
|
||||
g_terminal_request = 0;
|
||||
|
||||
/* Display the welcome banner on the serial terminal */
|
||||
R_SCIFA2_Serial_Send((uint8_t *)&welcome_banner, sizeof(welcome_banner));
|
||||
|
||||
/* Data transmission and reception done in the infinite loop */
|
||||
while (1U)
|
||||
{
|
||||
/* Check for a valid request from the switch or serial terminal */
|
||||
if ((g_terminal_request) || (g_switch_press_flg & SW3_PRESS_FLG))
|
||||
{
|
||||
/* Update the binary count using LED2 and LED3 */
|
||||
led_display_count(adc_count);
|
||||
|
||||
while(0u == SCIFA2.FSR.BIT.TDFE)
|
||||
{
|
||||
/* Wait for previous transmission to complete */
|
||||
}
|
||||
|
||||
/* Write send data */
|
||||
R_SCIFA2_Serial_Send((uint8_t *)&uart_buffer, sizeof(uart_buffer));
|
||||
|
||||
/* Clear TDFE */
|
||||
SCIFA2.FSR.BIT.TDFE = 0U;
|
||||
|
||||
if (g_terminal_request)
|
||||
{
|
||||
/* Clear the request */
|
||||
g_terminal_request = 0U;
|
||||
}
|
||||
|
||||
if (g_switch_press_flg & SW3_PRESS_FLG)
|
||||
{
|
||||
/* Clear the request */
|
||||
g_switch_press_flg &= ((uint8_t)~SW3_PRESS_FLG);
|
||||
}
|
||||
|
||||
adc_count++;
|
||||
}
|
||||
}
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_MAIN_UserInit
|
||||
* Description : This function adds user code before implementing main function.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_MAIN_UserInit(void)
|
||||
{
|
||||
/* Enable RSPI1 operations */
|
||||
R_RSPI1_Start();
|
||||
|
||||
/* Configure UART channel for communication with host PC via RL78/G1C device */
|
||||
io_init_scifa2();
|
||||
|
||||
/* Enable SCIFA2 operations */
|
||||
R_SCIFA2_Start();
|
||||
}
|
||||
|
||||
static void led_display_count (const uint8_t count)
|
||||
{
|
||||
/* Set LEDs according to lower nibble of count parameter */
|
||||
LED2 = (uint8_t) ((count & 0x01) ? LED_ON : LED_OFF);
|
||||
LED3 = (uint8_t) ((count & 0x02) ? LED_ON : LED_OFF);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationMallocFailedHook( void )
|
||||
{
|
||||
/* Called if a call to pvPortMalloc() fails because there is insufficient
|
||||
free memory available in the FreeRTOS heap. pvPortMalloc() is called
|
||||
internally by FreeRTOS API functions that create tasks, queues, software
|
||||
timers, and semaphores. The size of the FreeRTOS heap is set by the
|
||||
configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */
|
||||
|
||||
/* Force an assert. */
|
||||
configASSERT( ( volatile void * ) NULL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
|
||||
{
|
||||
( void ) pcTaskName;
|
||||
( void ) pxTask;
|
||||
|
||||
/* Run time stack overflow checking is performed if
|
||||
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
|
||||
function is called if a stack overflow is detected. */
|
||||
|
||||
/* Force an assert. */
|
||||
configASSERT( ( volatile void * ) NULL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationIdleHook( void )
|
||||
{
|
||||
volatile size_t xFreeHeapSpace;
|
||||
|
||||
/* This is just a trivial example of an idle hook. It is called on each
|
||||
cycle of the idle task. It must *NOT* attempt to block. In this case the
|
||||
idle task just queries the amount of FreeRTOS heap that remains. See the
|
||||
memory management section on the http://www.FreeRTOS.org web site for memory
|
||||
management options. If there is a lot of heap memory free then the
|
||||
configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up
|
||||
RAM. */
|
||||
xFreeHeapSpace = xPortGetFreeHeapSize();
|
||||
|
||||
/* Remove compiler warning about xFreeHeapSpace being set but never used. */
|
||||
( void ) xFreeHeapSpace;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationTickHook( void )
|
||||
{
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationIRQHandler( void )
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@ -147,7 +147,7 @@
|
||||
\
|
||||
\
|
||||
/* Has the extremity of the task stack ever been written over? */ \
|
||||
if( memcmp( ( void * ) pxCurrentTCB->pxStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \
|
||||
if( memcmp( ( const void * ) pxCurrentTCB->pxStack, ( const void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \
|
||||
{ \
|
||||
vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
|
||||
} \
|
||||
|
||||
358
FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c
Normal file
358
FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c
Normal file
@ -0,0 +1,358 @@
|
||||
/*
|
||||
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/* Standard includes. */
|
||||
#include <stdlib.h>
|
||||
|
||||
/* Scheduler includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
/* Check the configuration. */
|
||||
#if( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||
|
||||
#ifndef configSETUP_TICK_INTERRUPT
|
||||
#error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.
|
||||
#endif
|
||||
|
||||
#ifndef configCLEAR_TICK_INTERRUPT
|
||||
#error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
|
||||
#endif
|
||||
|
||||
/* A critical section is exited when the critical section nesting count reaches
|
||||
this value. */
|
||||
#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
|
||||
|
||||
/* Tasks are not created with a floating point context, but can be given a
|
||||
floating point context after they have been created. A variable is stored as
|
||||
part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
|
||||
does not have an FPU context, or any other value if the task does have an FPU
|
||||
context. */
|
||||
#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
|
||||
|
||||
/* Constants required to setup the initial task context. */
|
||||
#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
|
||||
#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
|
||||
#define portTHUMB_MODE_ADDRESS ( 0x01UL )
|
||||
|
||||
/* Masks all bits in the APSR other than the mode bits. */
|
||||
#define portAPSR_MODE_BITS_MASK ( 0x1F )
|
||||
|
||||
/* The value of the mode bits in the APSR when the CPU is executing in user
|
||||
mode. */
|
||||
#define portAPSR_USER_MODE ( 0x10 )
|
||||
|
||||
/* Let the user override the pre-loading of the initial LR with the address of
|
||||
prvTaskExitError() in case is messes up unwinding of the stack in the
|
||||
debugger. */
|
||||
#ifdef configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#else
|
||||
#define portTASK_RETURN_ADDRESS prvTaskExitError
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Starts the first task executing. This function is necessarily written in
|
||||
* assembly code so is implemented in portASM.s.
|
||||
*/
|
||||
extern void vPortRestoreTaskContext( void );
|
||||
|
||||
/*
|
||||
* Used to catch tasks that attempt to return from their implementing function.
|
||||
*/
|
||||
static void prvTaskExitError( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* A variable is used to keep track of the critical section nesting. This
|
||||
variable has to be stored as part of the task context and must be initialised to
|
||||
a non zero value to ensure interrupts don't inadvertently become unmasked before
|
||||
the scheduler starts. As it is stored as part of the task context it will
|
||||
automatically be set to 0 when the first task is started. */
|
||||
volatile uint32_t ulCriticalNesting = 9999UL;
|
||||
|
||||
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
|
||||
a floating point context must be saved and restored for the task. */
|
||||
volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
|
||||
|
||||
/* Set to 1 to pend a context switch from an ISR. */
|
||||
volatile uint32_t ulPortYieldRequired = pdFALSE;
|
||||
|
||||
/* Counts the interrupt nesting depth. A context switch is only performed if
|
||||
if the nesting depth is 0. */
|
||||
volatile uint32_t ulPortInterruptNesting = 0UL;
|
||||
|
||||
/* Used in the asm file to clear an interrupt. */
|
||||
__attribute__(( used )) const uint32_t ulICCEOIR = configEOI_ADDRESS;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
||||
{
|
||||
/* Setup the initial stack of the task. The stack is set exactly as
|
||||
expected by the portRESTORE_CONTEXT() macro.
|
||||
|
||||
The fist real value on the stack is the status register, which is set for
|
||||
system mode, with interrupts enabled. A few NULLs are added first to ensure
|
||||
GDB does not try decoding a non-existent return address. */
|
||||
*pxTopOfStack = ( StackType_t ) NULL;
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) NULL;
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) NULL;
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
|
||||
|
||||
if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
|
||||
{
|
||||
/* The task will start in THUMB mode. */
|
||||
*pxTopOfStack |= portTHUMB_MODE_BIT;
|
||||
}
|
||||
|
||||
pxTopOfStack--;
|
||||
|
||||
/* Next the return address, which in this case is the start of the task. */
|
||||
*pxTopOfStack = ( StackType_t ) pxCode;
|
||||
pxTopOfStack--;
|
||||
|
||||
/* Next all the registers other than the stack pointer. */
|
||||
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
|
||||
pxTopOfStack--;
|
||||
|
||||
/* The task will start with a critical nesting count of 0 as interrupts are
|
||||
enabled. */
|
||||
*pxTopOfStack = portNO_CRITICAL_NESTING;
|
||||
pxTopOfStack--;
|
||||
|
||||
/* The task will start without a floating point context. A task that uses
|
||||
the floating point hardware must call vPortTaskUsesFPU() before executing
|
||||
any floating point instructions. */
|
||||
*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
|
||||
|
||||
return pxTopOfStack;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvTaskExitError( void )
|
||||
{
|
||||
/* A function that implements a task must not exit or attempt to return to
|
||||
its caller as there is nothing to return to. If a task wants to exit it
|
||||
should instead call vTaskDelete( NULL ).
|
||||
|
||||
Artificially force an assert() to be triggered if configASSERT() is
|
||||
defined, then stop here so application writers can catch the error. */
|
||||
configASSERT( ulPortInterruptNesting == ~0UL );
|
||||
portDISABLE_INTERRUPTS();
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
uint32_t ulAPSR;
|
||||
|
||||
/* Only continue if the CPU is not in User mode. The CPU must be in a
|
||||
Privileged mode for the scheduler to start. */
|
||||
__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
|
||||
ulAPSR &= portAPSR_MODE_BITS_MASK;
|
||||
configASSERT( ulAPSR != portAPSR_USER_MODE );
|
||||
|
||||
if( ulAPSR != portAPSR_USER_MODE )
|
||||
{
|
||||
/* Start the timer that generates the tick ISR. */
|
||||
portDISABLE_INTERRUPTS();
|
||||
configSETUP_TICK_INTERRUPT();
|
||||
|
||||
/* Start the first task executing. */
|
||||
vPortRestoreTaskContext();
|
||||
}
|
||||
|
||||
/* Will only get here if xTaskStartScheduler() was called with the CPU in
|
||||
a non-privileged mode or the binary point register was not set to its lowest
|
||||
possible value. prvTaskExitError() is referenced to prevent a compiler
|
||||
warning about it being defined but not referenced in the case that the user
|
||||
defines their own exit address. */
|
||||
( void ) prvTaskExitError;
|
||||
return 0;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEndScheduler( void )
|
||||
{
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
Artificially force an assert. */
|
||||
configASSERT( ulCriticalNesting == 1000UL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEnterCritical( void )
|
||||
{
|
||||
portDISABLE_INTERRUPTS();
|
||||
|
||||
/* Now interrupts are disabled ulCriticalNesting can be accessed
|
||||
directly. Increment ulCriticalNesting to keep a count of how many times
|
||||
portENTER_CRITICAL() has been called. */
|
||||
ulCriticalNesting++;
|
||||
|
||||
/* This is not the interrupt safe version of the enter critical function so
|
||||
assert() if it is being called from an interrupt context. Only API
|
||||
functions that end in "FromISR" can be used in an interrupt. Only assert if
|
||||
the critical nesting count is 1 to protect against recursive calls if the
|
||||
assert function also uses a critical section. */
|
||||
if( ulCriticalNesting == 1 )
|
||||
{
|
||||
configASSERT( ulPortInterruptNesting == 0 );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortExitCritical( void )
|
||||
{
|
||||
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
|
||||
{
|
||||
/* Decrement the nesting count as the critical section is being
|
||||
exited. */
|
||||
ulCriticalNesting--;
|
||||
|
||||
/* If the nesting level has reached zero then all interrupt
|
||||
priorities must be re-enabled. */
|
||||
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
|
||||
{
|
||||
/* Critical nesting has reached zero so all interrupt priorities
|
||||
should be unmasked. */
|
||||
portENABLE_INTERRUPTS();
|
||||
}
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void FreeRTOS_Tick_Handler( void )
|
||||
{
|
||||
portDISABLE_INTERRUPTS();
|
||||
|
||||
/* Increment the RTOS tick. */
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
ulPortYieldRequired = pdTRUE;
|
||||
}
|
||||
|
||||
portENABLE_INTERRUPTS();
|
||||
configCLEAR_TICK_INTERRUPT();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortTaskUsesFPU( void )
|
||||
{
|
||||
uint32_t ulInitialFPSCR = 0;
|
||||
|
||||
/* A task is registering the fact that it needs an FPU context. Set the
|
||||
FPU flag (which is saved as part of the task context). */
|
||||
ulPortTaskHasFPUContext = pdTRUE;
|
||||
|
||||
/* Initialise the floating point status register. */
|
||||
__asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
291
FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S
Normal file
291
FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S
Normal file
@ -0,0 +1,291 @@
|
||||
/*
|
||||
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
>>>NOTE<<< The modification to the GPL is included to allow you to
|
||||
distribute a combined work that includes FreeRTOS without being obliged to
|
||||
provide the source code for proprietary components outside of the FreeRTOS
|
||||
kernel. FreeRTOS is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
||||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
.text
|
||||
.arm
|
||||
|
||||
.set SYS_MODE, 0x1f
|
||||
.set SVC_MODE, 0x13
|
||||
.set IRQ_MODE, 0x12
|
||||
|
||||
/* Variables and functions. */
|
||||
.extern ulMaxAPIPriorityMask
|
||||
.extern _freertos_vector_table
|
||||
.extern pxCurrentTCB
|
||||
.extern vTaskSwitchContext
|
||||
.extern vApplicationIRQHandler
|
||||
.extern ulPortInterruptNesting
|
||||
.extern ulPortTaskHasFPUContext
|
||||
.extern ulICCEOIR
|
||||
|
||||
.global FreeRTOS_IRQ_Handler
|
||||
.global FreeRTOS_SVC_Handler
|
||||
.global vPortRestoreTaskContext
|
||||
|
||||
|
||||
|
||||
|
||||
.macro portSAVE_CONTEXT
|
||||
|
||||
/* Save the LR and SPSR onto the system mode stack before switching to
|
||||
system mode to save the remaining system mode registers. */
|
||||
SRSDB sp!, #SYS_MODE
|
||||
CPS #SYS_MODE
|
||||
PUSH {R0-R12, R14}
|
||||
|
||||
/* Push the critical nesting count. */
|
||||
LDR R2, ulCriticalNestingConst
|
||||
LDR R1, [R2]
|
||||
PUSH {R1}
|
||||
|
||||
/* Does the task have a floating point context that needs saving? If
|
||||
ulPortTaskHasFPUContext is 0 then no. */
|
||||
LDR R2, ulPortTaskHasFPUContextConst
|
||||
LDR R3, [R2]
|
||||
CMP R3, #0
|
||||
|
||||
/* Save the floating point context, if any. */
|
||||
FMRXNE R1, FPSCR
|
||||
VPUSHNE {D0-D15}
|
||||
#if configFPU_D32 == 1
|
||||
VPUSHNE {D16-D31}
|
||||
#endif /* configFPU_D32 */
|
||||
PUSHNE {R1}
|
||||
|
||||
/* Save ulPortTaskHasFPUContext itself. */
|
||||
PUSH {R3}
|
||||
|
||||
/* Save the stack pointer in the TCB. */
|
||||
LDR R0, pxCurrentTCBConst
|
||||
LDR R1, [R0]
|
||||
STR SP, [R1]
|
||||
|
||||
.endm
|
||||
|
||||
; /**********************************************************************/
|
||||
|
||||
.macro portRESTORE_CONTEXT
|
||||
|
||||
/* Set the SP to point to the stack of the task being restored. */
|
||||
LDR R0, pxCurrentTCBConst
|
||||
LDR R1, [R0]
|
||||
LDR SP, [R1]
|
||||
|
||||
/* Is there a floating point context to restore? If the restored
|
||||
ulPortTaskHasFPUContext is zero then no. */
|
||||
LDR R0, ulPortTaskHasFPUContextConst
|
||||
POP {R1}
|
||||
STR R1, [R0]
|
||||
CMP R1, #0
|
||||
|
||||
/* Restore the floating point context, if any. */
|
||||
POPNE {R0}
|
||||
#if configFPU_D32 == 1
|
||||
VPOPNE {D16-D31}
|
||||
#endif /* configFPU_D32 */
|
||||
VPOPNE {D0-D15}
|
||||
VMSRNE FPSCR, R0
|
||||
|
||||
/* Restore the critical section nesting depth. */
|
||||
LDR R0, ulCriticalNestingConst
|
||||
POP {R1}
|
||||
STR R1, [R0]
|
||||
|
||||
/* Restore all system mode registers other than the SP (which is already
|
||||
being used). */
|
||||
POP {R0-R12, R14}
|
||||
|
||||
/* Return to the task code, loading CPSR on the way. */
|
||||
RFEIA sp!
|
||||
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* SVC handler is used to start the scheduler.
|
||||
*****************************************************************************/
|
||||
.align 4
|
||||
.type FreeRTOS_SVC_Handler, %function
|
||||
FreeRTOS_SVC_Handler:
|
||||
/* Save the context of the current task and select a new task to run. */
|
||||
portSAVE_CONTEXT
|
||||
LDR R0, vTaskSwitchContextConst
|
||||
BLX R0
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* vPortRestoreTaskContext is used to start the scheduler.
|
||||
*****************************************************************************/
|
||||
.align 4
|
||||
.type vPortRestoreTaskContext, %function
|
||||
vPortRestoreTaskContext:
|
||||
/* Switch to system mode. */
|
||||
CPS #SYS_MODE
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
.align 4
|
||||
.type FreeRTOS_IRQ_Handler, %function
|
||||
FreeRTOS_IRQ_Handler:
|
||||
/* Return to the interrupted instruction. */
|
||||
SUB lr, lr, #4
|
||||
|
||||
/* Push the return address and SPSR. */
|
||||
PUSH {lr}
|
||||
MRS lr, SPSR
|
||||
PUSH {lr}
|
||||
|
||||
/* Change to supervisor mode to allow reentry. */
|
||||
CPS #SVC_MODE
|
||||
|
||||
/* Push used registers. */
|
||||
PUSH {r0-r4, r12}
|
||||
|
||||
/* Increment nesting count. r3 holds the address of ulPortInterruptNesting
|
||||
for future use. r1 holds the original ulPortInterruptNesting value for
|
||||
future use. */
|
||||
LDR r3, ulPortInterruptNestingConst
|
||||
LDR r1, [r3]
|
||||
ADD r4, r1, #1
|
||||
STR r4, [r3]
|
||||
|
||||
/* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
|
||||
future use. */
|
||||
MOV r2, sp
|
||||
AND r2, r2, #4
|
||||
SUB sp, sp, r2
|
||||
|
||||
/* Call the interrupt handler. */
|
||||
PUSH {r0-r3, lr}
|
||||
LDR r1, vApplicationIRQHandlerConst
|
||||
BLX r1
|
||||
POP {r0-r3, lr}
|
||||
ADD sp, sp, r2
|
||||
|
||||
CPSID i
|
||||
DSB
|
||||
ISB
|
||||
|
||||
/* Write to the EOI register. */
|
||||
LDR r4, ulICCEOIRConst
|
||||
LDR r4, [r4]
|
||||
STR r0, [r4]
|
||||
|
||||
/* Restore the old nesting count. */
|
||||
STR r1, [r3]
|
||||
|
||||
/* A context switch is never performed if the nesting count is not 0. */
|
||||
CMP r1, #0
|
||||
BNE exit_without_switch
|
||||
|
||||
/* Did the interrupt request a context switch? r1 holds the address of
|
||||
ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
|
||||
use. */
|
||||
LDR r1, =ulPortYieldRequired
|
||||
LDR r0, [r1]
|
||||
CMP r0, #0
|
||||
BNE switch_before_exit
|
||||
|
||||
exit_without_switch:
|
||||
/* No context switch. Restore used registers, LR_irq and SPSR before
|
||||
returning. */
|
||||
POP {r0-r4, r12}
|
||||
CPS #IRQ_MODE
|
||||
POP {LR}
|
||||
MSR SPSR_cxsf, LR
|
||||
POP {LR}
|
||||
MOVS PC, LR
|
||||
|
||||
switch_before_exit:
|
||||
/* A context swtich is to be performed. Clear the context switch pending
|
||||
flag. */
|
||||
MOV r0, #0
|
||||
STR r0, [r1]
|
||||
|
||||
/* Restore used registers, LR-irq and SPSR before saving the context
|
||||
to the task stack. */
|
||||
POP {r0-r4, r12}
|
||||
CPS #IRQ_MODE
|
||||
POP {LR}
|
||||
MSR SPSR_cxsf, LR
|
||||
POP {LR}
|
||||
portSAVE_CONTEXT
|
||||
|
||||
/* Call the function that selects the new task to execute.
|
||||
vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
|
||||
instructions, or 8 byte aligned stack allocated data. LR does not need
|
||||
saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
|
||||
LDR R0, vTaskSwitchContextConst
|
||||
BLX R0
|
||||
|
||||
/* Restore the context of, and branch to, the task selected to execute
|
||||
next. */
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
ulICCEOIRConst: .word ulICCEOIR
|
||||
pxCurrentTCBConst: .word pxCurrentTCB
|
||||
ulCriticalNestingConst: .word ulCriticalNesting
|
||||
ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
|
||||
vTaskSwitchContextConst: .word vTaskSwitchContext
|
||||
vApplicationIRQHandlerConst: .word vApplicationIRQHandler
|
||||
ulPortInterruptNestingConst: .word ulPortInterruptNesting
|
||||
|
||||
.end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
214
FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
Normal file
214
FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
Normal file
@ -0,0 +1,214 @@
|
||||
/*
|
||||
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
*
|
||||
* The settings in this file configure FreeRTOS correctly for the given hardware
|
||||
* and compiler.
|
||||
*
|
||||
* These settings should not be altered.
|
||||
*-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
not need to be guarded with a critical section. */
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task utilities. */
|
||||
|
||||
/* Called at the end of an ISR that can cause a context switch. */
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired )\
|
||||
{ \
|
||||
extern uint32_t ulPortYieldRequired; \
|
||||
\
|
||||
if( xSwitchRequired != pdFALSE ) \
|
||||
{ \
|
||||
ulPortYieldRequired = pdTRUE; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
|
||||
#define portYIELD() __asm volatile ( "SWI 0 \n" \
|
||||
"ISB " );
|
||||
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Critical section control
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
extern void vPortEnterCritical( void );
|
||||
extern void vPortExitCritical( void );
|
||||
extern uint32_t ulPortSetInterruptMask( void );
|
||||
extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
|
||||
extern void vPortInstallFreeRTOSVectorTable( void );
|
||||
|
||||
/* The I bit within the CPSR. */
|
||||
#define portINTERRUPT_ENABLE_BIT ( 1 << 7 )
|
||||
|
||||
/* In the absence of a priority mask register, these functions and macros
|
||||
globally enable and disable interrupts. */
|
||||
#define portENTER_CRITICAL() vPortEnterCritical();
|
||||
#define portEXIT_CRITICAL() vPortExitCritical();
|
||||
#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" );
|
||||
#define portDISABLE_INTERRUPTS() __asm volatile ( "CPSID i \n" \
|
||||
"DSB \n" \
|
||||
"ISB " );
|
||||
|
||||
__attribute__( ( always_inline ) ) static __inline uint32_t portSET_INTERRUPT_MASK_FROM_ISR( void )
|
||||
{
|
||||
volatile uint32_t ulCPSR;
|
||||
|
||||
__asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) );
|
||||
ulCPSR &= portINTERRUPT_ENABLE_BIT;
|
||||
portDISABLE_INTERRUPTS();
|
||||
return ulCPSR;
|
||||
}
|
||||
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) if( x != 0 ) portENABLE_INTERRUPTS()
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. These are
|
||||
not required for this port but included in case common demo code that uses these
|
||||
macros is used. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
|
||||
/* Prototype of the FreeRTOS tick handler. This must be installed as the
|
||||
handler for whichever peripheral is used to generate the RTOS tick. */
|
||||
void FreeRTOS_Tick_Handler( void );
|
||||
|
||||
/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
|
||||
before any floating point instructions are executed. */
|
||||
void vPortTaskUsesFPU( void );
|
||||
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
|
||||
|
||||
#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
|
||||
#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
|
||||
|
||||
/* Architecture specific optimisations. */
|
||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#endif
|
||||
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) )
|
||||
|
||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||
|
||||
#define portNOP() __asm volatile( "NOP" )
|
||||
#define portINLINE __inline
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* extern C */
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
||||
@ -247,7 +247,7 @@ PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks = ( UBaseType_t ) 0
|
||||
PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE;
|
||||
PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0;
|
||||
PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U;
|
||||
PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY; before the scheduler starts. */
|
||||
PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
|
||||
|
||||
/* Context switches are held pending while the scheduler is suspended. Also,
|
||||
interrupts must not manipulate the xGenericListItem of a TCB, or any of the
|
||||
@ -3629,14 +3629,14 @@ TCB_t *pxTCB;
|
||||
|
||||
static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
|
||||
{
|
||||
BaseType_t x;
|
||||
size_t x;
|
||||
|
||||
/* Start by copying the entire string. */
|
||||
strcpy( pcBuffer, pcTaskName );
|
||||
|
||||
/* Pad the end of the string with spaces to ensure columns line up when
|
||||
printed out. */
|
||||
for( x = strlen( pcBuffer ); x < ( configMAX_TASK_NAME_LEN - 1 ); x++ )
|
||||
for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
|
||||
{
|
||||
pcBuffer[ x ] = ' ';
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user