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Update the Xilinx UltraScale+ demo project to use the BSP and hardware platform generated by the 2016.1 version of the SDK.

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Richard Barry 2016-04-28 12:49:19 +00:00
parent 11fe9de0f0
commit 0cb71ee9ce
12 changed files with 146 additions and 231 deletions
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164
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject
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@ -1,8 +1,8 @@
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108
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.project
View File

@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
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<comment>Created by SDK v2015.1. RTOSDemo_A53_bsp - psu_cortexa53_0</comment> <comment>Created by SDK v2016.1. RTOSDemo_A53_bsp - psu_cortexa53_0</comment>
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79
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld
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@ -22,19 +22,12 @@ _EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
MEMORY MEMORY
{ {
psu_bbram_0_S_AXI_BASEADDR : ORIGIN = 0xFFCD0000, LENGTH = 0x10000 psu_bbram_0_S_AXI_BASEADDR : ORIGIN = 0xFFCD0000, LENGTH = 0x10000
psu_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x0, LENGTH = 0x10000000 psu_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x0, LENGTH = 0x80000000
psu_ocm_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFFC0000, LENGTH = 0x30000 psu_ocm_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFFC0000, LENGTH = 0x30000
psu_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x10000 psu_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x10000
psu_ocm_xmpu_cfg_S_AXI_BASEADDR : ORIGIN = 0xFFA70000, LENGTH = 0x10000 psu_ocm_xmpu_cfg_S_AXI_BASEADDR : ORIGIN = 0xFFA70000, LENGTH = 0x10000
psu_pmu_ram_S_AXI_BASEADDR : ORIGIN = 0xFFDC0000, LENGTH = 0x20000 psu_pmu_ram_S_AXI_BASEADDR : ORIGIN = 0xFFDC0000, LENGTH = 0x20000
psu_qspi_linear_0_S_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x20000000 psu_qspi_linear_0_S_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x20000000
psu_r5_0_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE00000, LENGTH = 0x10000
psu_r5_0_atcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE10000, LENGTH = 0x10000
psu_r5_0_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFE20000, LENGTH = 0x10000
psu_r5_0_btcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE30000, LENGTH = 0x10000
psu_r5_1_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE90000, LENGTH = 0x10000
psu_r5_1_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFEB0000, LENGTH = 0x10000
psu_r5_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x100000, LENGTH = 0x7FF00000
} }
/* Specify the default entry point to the program */ /* Specify the default entry point to the program */
@ -58,23 +51,23 @@ SECTIONS
*(.glue_7t) *(.glue_7t)
*(.ARM.extab) *(.ARM.extab)
*(.gnu.linkonce.armextab.*) *(.gnu.linkonce.armextab.*)
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.init (ALIGN(64)) : { .init (ALIGN(64)) : {
KEEP (*(.init)) KEEP (*(.init))
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.fini (ALIGN(64)) : { .fini (ALIGN(64)) : {
KEEP (*(.fini)) KEEP (*(.fini))
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.interp : { .interp : {
KEEP (*(.interp)) KEEP (*(.interp))
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.note-ABI-tag : { .note-ABI-tag : {
KEEP (*(.note-ABI-tag)) KEEP (*(.note-ABI-tag))
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.rodata : { .rodata : {
. = ALIGN(64); . = ALIGN(64);
@ -83,7 +76,7 @@ SECTIONS
*(.rodata.*) *(.rodata.*)
*(.gnu.linkonce.r.*) *(.gnu.linkonce.r.*)
__rodata_end = .; __rodata_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.rodata1 : { .rodata1 : {
. = ALIGN(64); . = ALIGN(64);
@ -91,7 +84,7 @@ SECTIONS
*(.rodata1) *(.rodata1)
*(.rodata1.*) *(.rodata1.*)
__rodata1_end = .; __rodata1_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.sdata2 : { .sdata2 : {
. = ALIGN(64); . = ALIGN(64);
@ -100,7 +93,7 @@ SECTIONS
*(.sdata2.*) *(.sdata2.*)
*(.gnu.linkonce.s2.*) *(.gnu.linkonce.s2.*)
__sdata2_end = .; __sdata2_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.sbss2 : { .sbss2 : {
. = ALIGN(64); . = ALIGN(64);
@ -109,7 +102,7 @@ SECTIONS
*(.sbss2.*) *(.sbss2.*)
*(.gnu.linkonce.sb2.*) *(.gnu.linkonce.sb2.*)
__sbss2_end = .; __sbss2_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.data : { .data : {
. = ALIGN(64); . = ALIGN(64);
@ -121,7 +114,7 @@ SECTIONS
*(.got) *(.got)
*(.got.plt) *(.got.plt)
__data_end = .; __data_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.data1 : { .data1 : {
. = ALIGN(64); . = ALIGN(64);
@ -129,19 +122,19 @@ SECTIONS
*(.data1) *(.data1)
*(.data1.*) *(.data1.*)
__data1_end = .; __data1_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.got : { .got : {
*(.got) *(.got)
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.got1 : { .got1 : {
*(.got1) *(.got1)
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.got2 : { .got2 : {
*(.got2) *(.got2)
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.ctors : { .ctors : {
. = ALIGN(64); . = ALIGN(64);
@ -153,7 +146,7 @@ SECTIONS
KEEP (*(.ctors)) KEEP (*(.ctors))
__CTOR_END__ = .; __CTOR_END__ = .;
___CTORS_END___ = .; ___CTORS_END___ = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.dtors : { .dtors : {
. = ALIGN(64); . = ALIGN(64);
@ -165,52 +158,52 @@ SECTIONS
KEEP (*(.dtors)) KEEP (*(.dtors))
__DTOR_END__ = .; __DTOR_END__ = .;
___DTORS_END___ = .; ___DTORS_END___ = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.fixup : { .fixup : {
__fixup_start = .; __fixup_start = .;
*(.fixup) *(.fixup)
__fixup_end = .; __fixup_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.eh_frame : { .eh_frame : {
*(.eh_frame) *(.eh_frame)
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.eh_framehdr : { .eh_framehdr : {
__eh_framehdr_start = .; __eh_framehdr_start = .;
*(.eh_framehdr) *(.eh_framehdr)
__eh_framehdr_end = .; __eh_framehdr_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.gcc_except_table : { .gcc_except_table : {
*(.gcc_except_table) *(.gcc_except_table)
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.mmu_tbl0 (ALIGN(4096)) : { .mmu_tbl0 (ALIGN(4096)) : {
__mmu_tbl0_start = .; __mmu_tbl0_start = .;
*(.mmu_tbl0) *(.mmu_tbl0)
__mmu_tbl0_end = .; __mmu_tbl0_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.mmu_tbl1 (ALIGN(4096)) : { .mmu_tbl1 (ALIGN(4096)) : {
__mmu_tbl1_start = .; __mmu_tbl1_start = .;
*(.mmu_tbl1) *(.mmu_tbl1)
__mmu_tbl1_end = .; __mmu_tbl1_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.mmu_tbl2 (ALIGN(4096)) : { .mmu_tbl2 (ALIGN(4096)) : {
__mmu_tbl2_start = .; __mmu_tbl2_start = .;
*(.mmu_tbl2) *(.mmu_tbl2)
__mmu_tbl2_end = .; __mmu_tbl2_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.ARM.exidx : { .ARM.exidx : {
__exidx_start = .; __exidx_start = .;
*(.ARM.exidx*) *(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*) *(.gnu.linkonce.armexidix.*.*)
__exidx_end = .; __exidx_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.preinit_array : { .preinit_array : {
. = ALIGN(64); . = ALIGN(64);
@ -218,7 +211,7 @@ SECTIONS
KEEP (*(SORT(.preinit_array.*))) KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array)) KEEP (*(.preinit_array))
__preinit_array_end = .; __preinit_array_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.init_array : { .init_array : {
. = ALIGN(64); . = ALIGN(64);
@ -226,7 +219,7 @@ SECTIONS
KEEP (*(SORT(.init_array.*))) KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array)) KEEP (*(.init_array))
__init_array_end = .; __init_array_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.fini_array : { .fini_array : {
. = ALIGN(64); . = ALIGN(64);
@ -234,13 +227,13 @@ SECTIONS
KEEP (*(SORT(.fini_array.*))) KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array)) KEEP (*(.fini_array))
__fini_array_end = .; __fini_array_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.ARM.attributes : { .ARM.attributes : {
__ARM.attributes_start = .; __ARM.attributes_start = .;
*(.ARM.attributes) *(.ARM.attributes)
__ARM.attributes_end = .; __ARM.attributes_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.sdata : { .sdata : {
. = ALIGN(64); . = ALIGN(64);
@ -249,7 +242,7 @@ SECTIONS
*(.sdata.*) *(.sdata.*)
*(.gnu.linkonce.s.*) *(.gnu.linkonce.s.*)
__sdata_end = .; __sdata_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.sbss (NOLOAD) : { .sbss (NOLOAD) : {
. = ALIGN(64); . = ALIGN(64);
@ -259,7 +252,7 @@ SECTIONS
*(.gnu.linkonce.sb.*) *(.gnu.linkonce.sb.*)
. = ALIGN(64); . = ALIGN(64);
__sbss_end = .; __sbss_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.tdata : { .tdata : {
. = ALIGN(64); . = ALIGN(64);
@ -268,7 +261,7 @@ SECTIONS
*(.tdata.*) *(.tdata.*)
*(.gnu.linkonce.td.*) *(.gnu.linkonce.td.*)
__tdata_end = .; __tdata_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.tbss : { .tbss : {
. = ALIGN(64); . = ALIGN(64);
@ -277,7 +270,7 @@ SECTIONS
*(.tbss.*) *(.tbss.*)
*(.gnu.linkonce.tb.*) *(.gnu.linkonce.tb.*)
__tbss_end = .; __tbss_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.bss (NOLOAD) : { .bss (NOLOAD) : {
. = ALIGN(64); . = ALIGN(64);
@ -288,7 +281,7 @@ SECTIONS
*(COMMON) *(COMMON)
. = ALIGN(64); . = ALIGN(64);
__bss_end__ = .; __bss_end__ = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
@ -304,7 +297,7 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
. += _HEAP_SIZE; . += _HEAP_SIZE;
_heap_end = .; _heap_end = .;
HeapLimit = .; HeapLimit = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
.stack (NOLOAD) : { .stack (NOLOAD) : {
. = ALIGN(64); . = ALIGN(64);
@ -323,7 +316,7 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
. += _EL0_STACK_SIZE; . += _EL0_STACK_SIZE;
. = ALIGN(64); . = ALIGN(64);
__el0_stack = .; __el0_stack = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR } > psu_ddr_0_S_AXI_BASEADDR
_end = .; _end = .;
} }

22
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/platform.c
View File

@ -1,6 +1,6 @@
/****************************************************************************** /******************************************************************************
* *
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved. * Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a copy * Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal * of this software and associated documentation files (the "Software"), to deal
@ -18,8 +18,8 @@
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE. * SOFTWARE.
@ -36,10 +36,12 @@
#include "platform_config.h" #include "platform_config.h"
/* /*
* Uncomment the following line if ps7 init source files are added in the * Uncomment one of the following two lines, depending on the target,
* source directory for compiling example outside of SDK. * if ps7/psu init source files are added in the source directory for
* compiling example outside of SDK.
*/ */
/*#include "ps7_init.h"*/ /*#include "ps7_init.h"*/
/*#include "psu_init.h"*/
#ifdef STDOUT_IS_16550 #ifdef STDOUT_IS_16550
#include "xuartns550_l.h" #include "xuartns550_l.h"
@ -77,9 +79,7 @@ init_uart()
XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD); XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS); XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
#endif #endif
#ifdef STDOUT_IS_PS7_UART /* Bootrom/BSP configures PS7/PSU UART to 115200 bps */
/* Bootrom/BSP configures PS7 UART to 115200 bps */
#endif
} }
void void
@ -87,11 +87,13 @@ init_platform()
{ {
/* /*
* If you want to run this example outside of SDK, * If you want to run this example outside of SDK,
* uncomment the following line and also #include "ps7_init.h" at the top. * uncomment one of the following two lines and also #include "ps7_init.h"
* Make sure that the ps7_init.c and ps7_init.h files are included * or #include "ps7_init.h" at the top, depending on the target.
* Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included
* along with this example source files for compilation. * along with this example source files for compilation.
*/ */
/* ps7_init();*/ /* ps7_init();*/
/* psu_init();*/
enable_caches(); enable_caches();
init_uart(); init_uart();
} }

4
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/platform.h
View File

@ -18,8 +18,8 @@
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE. * SOFTWARE.

0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/.project → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/.project
View File

0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c
View File

0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h
View File

0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init.tcl → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl
View File

0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init_gpl.c → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c
View File

0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/psu_init_gpl.h → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h
View File

0
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/system.hdf → FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf
View File