311 lines
11 KiB
C
311 lines
11 KiB
C
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/*
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FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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***************************************************************************
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* *
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* FreeRTOS provides completely free yet professionally developed, *
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* robust, strictly quality controlled, supported, and cross *
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* platform software that has become a de facto standard. *
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* *
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* Help yourself get started quickly and support the FreeRTOS *
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* project by purchasing a FreeRTOS tutorial book, reference *
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* manual, or both from: http://www.FreeRTOS.org/Documentation *
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* *
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* Thank you! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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>>! NOTE: The modification to the GPL is included to allow you to distribute
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>>! a combined work that includes FreeRTOS without being obliged to provide
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>>! the source code for proprietary components outside of the FreeRTOS
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>>! kernel.
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. Full license text is available from the following
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link: http://www.freertos.org/a00114.html
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1 tab == 4 spaces!
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***************************************************************************
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* *
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* Having a problem? Start by reading the FAQ "My application does *
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* not run, what could be wrong?" *
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* *
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* http://www.FreeRTOS.org/FAQHelp.html *
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* *
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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license and Real Time Engineers Ltd. contact details.
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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compatible FAT file system, and our tiny thread aware UDP/IP stack.
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http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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licenses offer ticketed support, indemnification and middleware.
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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engineered and independently SIL3 certified version for use in safety and
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mission critical applications that require provable dependability.
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1 tab == 4 spaces!
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the ARM CM0 port.
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Constants required to manipulate the NVIC. */
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#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long *) 0xe000e010 )
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#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long *) 0xe000e014 )
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#define portNVIC_INT_CTRL ( ( volatile unsigned long *) 0xe000ed04 )
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#define portNVIC_SYSPRI2 ( ( volatile unsigned long *) 0xe000ed20 )
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#define portNVIC_SYSTICK_CLK 0x00000004
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#define portNVIC_SYSTICK_INT 0x00000002
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#define portNVIC_SYSTICK_ENABLE 0x00000001
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#define portNVIC_PENDSVSET 0x10000000
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#define portMIN_INTERRUPT_PRIORITY ( 255UL )
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#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
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#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
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/* Constants required to set up the initial stack. */
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#define portINITIAL_XPSR ( 0x01000000 )
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/* Constants used with memory barrier intrinsics. */
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#define portSY_FULL_READ_WRITE ( 15 )
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/* Each task maintains its own interrupt status in the critical nesting
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variable. */
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static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;
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/*
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* Setup the timer to generate the tick interrupts.
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*/
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static void prvSetupTimerInterrupt( void );
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/*
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* Exception handlers.
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*/
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void xPortPendSVHandler( void );
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void xPortSysTickHandler( void );
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void vPortSVCHandler( void );
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/*
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* Start first task is a separate function so it can be tested in isolation.
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*/
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static void vPortStartFirstTask( void );
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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{
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/* Simulate the stack frame as it would be created by a context switch
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interrupt. */
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pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */
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pxTopOfStack -= 6; /* LR, R12, R3..R1 */
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*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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pxTopOfStack -= 8; /* R11..R4. */
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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__asm void vPortSVCHandler( void )
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{
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extern pxCurrentTCB;
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PRESERVE8
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ldr r3, =pxCurrentTCB /* Restore the context. */
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ldr r1, [r3] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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adds r0, #16 /* Move to the high registers. */
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ldmia r0!, {r4-r7} /* Pop the high registers. */
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mov r8, r4
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mov r9, r5
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mov r10, r6
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mov r11, r7
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msr psp, r0 /* Remember the new top of stack for the task. */
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subs r0, #32 /* Go back for the low registers that are not automatically restored. */
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ldmia r0!, {r4-r7} /* Pop low registers. */
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mov r1, r14 /* OR R14 with 0x0d. */
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movs r0, #0x0d
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orrs r1, r0
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bx r1
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nop
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}
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/*-----------------------------------------------------------*/
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__asm void vPortStartFirstTask( void )
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{
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PRESERVE8
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movs r0, #0x00 /* Locate the top of stack. */
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ldr r0, [r0]
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msr msp, r0 /* Set the msp back to the start of the stack. */
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cpsie i /* Globally enable interrupts. */
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svc 0 /* System call to start first task. */
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nop
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}
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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portBASE_TYPE xPortStartScheduler( void )
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{
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/* Make PendSV, CallSV and SysTick the same priroity as the kernel. */
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*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
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*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
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/* Start the timer that generates the tick ISR. Interrupts are disabled
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here already. */
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prvSetupTimerInterrupt();
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/* Initialise the critical nesting count ready for the first task. */
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uxCriticalNesting = 0;
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/* Start the first task. */
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vPortStartFirstTask();
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/* Should not get here! */
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return 0;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* It is unlikely that the CM0 port will require this function as there
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is nothing to return to. */
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}
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/*-----------------------------------------------------------*/
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void vPortYield( void )
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{
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/* Set a PendSV to request a context switch. */
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*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
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/* Barriers are normally not required but do ensure the code is completely
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within the specified behaviour for the architecture. */
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__dsb( portSY_FULL_READ_WRITE );
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__isb( portSY_FULL_READ_WRITE );
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}
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/*-----------------------------------------------------------*/
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void vPortEnterCritical( void )
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{
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portDISABLE_INTERRUPTS();
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uxCriticalNesting++;
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__dsb( portSY_FULL_READ_WRITE );
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__isb( portSY_FULL_READ_WRITE );
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}
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/*-----------------------------------------------------------*/
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void vPortExitCritical( void )
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{
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uxCriticalNesting--;
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if( uxCriticalNesting == 0 )
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{
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portENABLE_INTERRUPTS();
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}
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}
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/*-----------------------------------------------------------*/
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__asm void xPortPendSVHandler( void )
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{
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extern vTaskSwitchContext
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extern pxCurrentTCB
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PRESERVE8
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mrs r0, psp
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ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
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ldr r2, [r3]
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subs r0, #32 /* Make space for the remaining low registers. */
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str r0, [r2] /* Save the new top of stack. */
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stmia r0!, {r4-r7} /* Store the low registers that are not saved automatically. */
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mov r4, r8 /* Store the high registers. */
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mov r5, r9
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mov r6, r10
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mov r7, r11
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stmia r0!, {r4-r7}
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push {r3, r14}
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cpsid i
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bl vTaskSwitchContext
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cpsie i
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pop {r2, r3} /* lr goes in r3. r2 now holds tcb pointer. */
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ldr r1, [r2]
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ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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adds r0, #16 /* Move to the high registers. */
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ldmia r0!, {r4-r7} /* Pop the high registers. */
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mov r8, r4
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mov r9, r5
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mov r10, r6
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mov r11, r7
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msr psp, r0 /* Remember the new top of stack for the task. */
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subs r0, #32 /* Go back for the low registers that are not automatically restored. */
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ldmia r0!, {r4-r7} /* Pop low registers. */
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bx r3
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}
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/*-----------------------------------------------------------*/
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void xPortSysTickHandler( void )
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{
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unsigned long ulDummy;
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ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
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{
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/* Increment the RTOS tick. */
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if( xTaskIncrementTick() != pdFALSE )
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{
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/* Pend a context switch. */
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*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
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}
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}
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portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
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}
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/*-----------------------------------------------------------*/
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/*
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* Setup the systick timer to generate the tick interrupts at the required
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* frequency.
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*/
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void prvSetupTimerInterrupt( void )
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{
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/* Configure SysTick to interrupt at the requested rate. */
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*(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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*(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
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}
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/*-----------------------------------------------------------*/
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