2007-11-26 23:45:21 +08:00
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/*
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2010-01-09 22:48:45 +08:00
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FreeRTOS V6.0.2 - Copyright (C) 2010 Real Time Engineers Ltd.
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2007-11-26 23:45:21 +08:00
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2009-10-13 19:05:41 +08:00
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***************************************************************************
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* *
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* If you are: *
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* *
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* + New to FreeRTOS, *
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* + Wanting to learn FreeRTOS or multitasking in general quickly *
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* + Looking for basic training, *
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* + Wanting to improve your FreeRTOS skills and productivity *
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* *
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* then take a look at the FreeRTOS eBook *
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* *
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* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
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* http://www.FreeRTOS.org/Documentation *
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* *
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* A pdf reference manual is also available. Both are usually delivered *
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* to your inbox within 20 minutes to two hours when purchased between 8am *
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* and 8pm GMT (although please allow up to 24 hours in case of *
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* exceptional circumstances). Thank you for your support! *
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* *
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***************************************************************************
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2009-10-05 19:10:48 +08:00
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This file is part of the FreeRTOS distribution.
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2007-11-26 23:45:21 +08:00
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2009-10-13 19:05:41 +08:00
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FreeRTOS is free software; you can redistribute it and/or modify it under
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2009-10-05 19:10:48 +08:00
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the terms of the GNU General Public License (version 2) as published by the
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2009-10-13 19:05:41 +08:00
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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***NOTE*** The exception to the GPL is included to allow you to distribute
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a combined work that includes FreeRTOS without being obliged to provide the
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2009-10-05 19:10:48 +08:00
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source code for proprietary components outside of the FreeRTOS kernel.
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2009-10-13 19:05:41 +08:00
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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2009-10-05 19:10:48 +08:00
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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2009-10-13 19:05:41 +08:00
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more details. You should have received a copy of the GNU General Public
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License and the FreeRTOS license exception along with FreeRTOS; if not it
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can be viewed here: http://www.freertos.org/a00114.html and also obtained
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by writing to Richard Barry, contact details for whom are available on the
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FreeRTOS WEB site.
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2009-03-15 03:20:12 +08:00
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2009-10-05 19:10:48 +08:00
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1 tab == 4 spaces!
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2007-11-26 23:45:21 +08:00
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2009-10-05 19:10:48 +08:00
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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2008-02-04 03:45:58 +08:00
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2009-10-05 19:10:48 +08:00
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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2008-02-04 03:45:58 +08:00
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2009-10-05 19:10:48 +08:00
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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2007-11-26 23:45:21 +08:00
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*/
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#include <p32xxxx.h>
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#include <sys/asm.h>
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.set nomips16
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.set noreorder
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.global vRegTest1
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.global vRegTest2
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/* .section .FreeRTOS, ax, @progbits */
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.set noreorder
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.set noat
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.ent vRegTest1
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/* Address of $4 ulStatus1 is held in A0, so don't mess with the value of $4 */
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vRegTest1:
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addiu $1, $0, 0x11
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addiu $2, $0, 0x12
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addiu $3, $0, 0x13
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addiu $5, $0, 0x15
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addiu $6, $0, 0x16
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addiu $7, $0, 0x17
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addiu $8, $0, 0x18
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addiu $9, $0, 0x19
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addiu $10, $0, 0x110
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addiu $11, $0, 0x111
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addiu $12, $0, 0x112
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addiu $13, $0, 0x113
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addiu $14, $0, 0x114
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addiu $15, $0, 0x115
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addiu $16, $0, 0x116
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addiu $17, $0, 0x117
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addiu $18, $0, 0x118
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addiu $19, $0, 0x119
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addiu $20, $0, 0x120
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addiu $21, $0, 0x121
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addiu $22, $0, 0x122
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addiu $23, $0, 0x123
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addiu $24, $0, 0x124
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addiu $25, $0, 0x125
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addiu $30, $0, 0x130
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addiu $1, $1, -0x11
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beq $1, $0, .+12
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nop
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sw $0, 0($4)
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addiu $2, $2, -0x12
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beq $2, $0, .+12
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nop
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sw $0, 0($4)
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addiu $3, $3, -0x13
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beq $3, $0, .+12
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nop
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sw $0, 0($4)
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addiu $5, $5, -0x15
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beq $5, $0, .+12
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nop
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sw $0, 0($4)
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addiu $6, $6, -0x16
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beq $6, $0, .+12
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nop
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sw $0, 0($4)
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addiu $7, $7, -0x17
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beq $7, $0, .+12
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nop
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sw $0, 0($4)
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addiu $8, $8, -0x18
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beq $8, $0, .+12
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nop
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sw $0, 0($4)
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addiu $9, $9, -0x19
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beq $9, $0, .+12
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nop
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sw $0, 0($4)
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addiu $10, $10, -0x110
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beq $10, $0, .+12
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nop
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sw $0, 0($4)
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addiu $11, $11, -0x111
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beq $11, $0, .+12
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nop
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sw $0, 0($4)
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addiu $12, $12, -0x112
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beq $12, $0, .+12
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nop
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sw $0, 0($4)
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addiu $13, $13, -0x113
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beq $13, $0, .+12
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nop
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sw $0, 0($4)
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addiu $14, $14, -0x114
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beq $14, $0, .+12
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nop
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sw $0, 0($4)
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addiu $15, $15, -0x115
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beq $15, $0, .+12
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nop
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sw $0, 0($4)
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addiu $16, $16, -0x116
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beq $16, $0, .+12
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nop
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sw $0, 0($4)
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addiu $17, $17, -0x117
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beq $17, $0, .+12
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nop
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sw $0, 0($4)
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addiu $18, $18, -0x118
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beq $18, $0, .+12
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nop
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sw $0, 0($4)
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addiu $19, $19, -0x119
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beq $19, $0, .+12
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nop
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sw $0, 0($4)
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addiu $20, $20, -0x120
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beq $20, $0, .+12
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nop
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sw $0, 0($4)
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addiu $21, $21, -0x121
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beq $21, $0, .+12
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nop
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sw $0, 0($4)
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addiu $22, $22, -0x122
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beq $22, $0, .+12
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nop
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sw $0, 0($4)
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addiu $23, $23, -0x123
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beq $23, $0, .+12
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nop
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sw $0, 0($4)
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addiu $24, $24, -0x124
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beq $24, $0, .+12
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nop
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sw $0, 0($4)
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addiu $25, $25, -0x125
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beq $25, $0, .+12
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nop
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sw $0, 0($4)
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addiu $30, $30, -0x130
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beq $30, $0, .+12
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nop
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sw $0, 0($4)
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jr $31
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nop
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.end vRegTest1
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/* .section .FreeRTOS, ax, @progbits */
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.set noreorder
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.set noat
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.ent vRegTest2
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vRegTest2:
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addiu $1, $0, 0x10
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addiu $2, $0, 0x20
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addiu $3, $0, 0x30
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addiu $5, $0, 0x50
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addiu $6, $0, 0x60
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addiu $7, $0, 0x70
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addiu $8, $0, 0x80
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addiu $9, $0, 0x90
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addiu $10, $0, 0x100
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addiu $11, $0, 0x110
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addiu $12, $0, 0x120
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addiu $13, $0, 0x130
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addiu $14, $0, 0x140
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addiu $15, $0, 0x150
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addiu $16, $0, 0x160
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addiu $17, $0, 0x170
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addiu $18, $0, 0x180
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addiu $19, $0, 0x190
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addiu $20, $0, 0x200
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addiu $21, $0, 0x210
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addiu $22, $0, 0x220
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addiu $23, $0, 0x230
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addiu $24, $0, 0x240
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addiu $25, $0, 0x250
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addiu $30, $0, 0x300
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addiu $1, $1, -0x10
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beq $1, $0, .+12
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nop
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sw $0, 0($4)
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addiu $2, $2, -0x20
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beq $2, $0, .+12
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nop
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sw $0, 0($4)
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addiu $3, $3, -0x30
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beq $3, $0, .+12
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nop
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sw $0, 0($4)
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addiu $5, $5, -0x50
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beq $5, $0, .+12
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nop
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sw $0, 0($4)
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addiu $6, $6, -0x60
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beq $6, $0, .+12
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nop
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sw $0, 0($4)
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addiu $7, $7, -0x70
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beq $7, $0, .+12
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nop
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sw $0, 0($4)
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addiu $8, $8, -0x80
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beq $8, $0, .+12
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nop
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sw $0, 0($4)
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addiu $9, $9, -0x90
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beq $9, $0, .+12
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nop
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sw $0, 0($4)
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addiu $10, $10, -0x100
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beq $10, $0, .+12
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nop
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sw $0, 0($4)
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addiu $11, $11, -0x110
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beq $11, $0, .+12
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nop
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sw $0, 0($4)
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addiu $12, $12, -0x120
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beq $12, $0, .+12
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nop
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sw $0, 0($4)
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addiu $13, $13, -0x130
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beq $13, $0, .+12
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nop
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sw $0, 0($4)
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addiu $14, $14, -0x140
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beq $14, $0, .+12
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nop
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sw $0, 0($4)
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addiu $15, $15, -0x150
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beq $15, $0, .+12
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nop
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sw $0, 0($4)
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addiu $16, $16, -0x160
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beq $16, $0, .+12
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nop
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sw $0, 0($4)
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addiu $17, $17, -0x170
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beq $17, $0, .+12
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nop
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sw $0, 0($4)
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addiu $18, $18, -0x180
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beq $18, $0, .+12
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nop
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sw $0, 0($4)
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addiu $19, $19, -0x190
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beq $19, $0, .+12
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nop
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sw $0, 0($4)
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addiu $20, $20, -0x200
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beq $20, $0, .+12
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nop
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sw $0, 0($4)
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addiu $21, $21, -0x210
|
|
|
|
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beq $21, $0, .+12
|
|
|
|
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nop
|
|
|
|
|
sw $0, 0($4)
|
|
|
|
|
addiu $22, $22, -0x220
|
|
|
|
|
beq $22, $0, .+12
|
|
|
|
|
nop
|
|
|
|
|
sw $0, 0($4)
|
|
|
|
|
addiu $23, $23, -0x230
|
|
|
|
|
beq $23, $0, .+12
|
|
|
|
|
nop
|
|
|
|
|
sw $0, 0($4)
|
|
|
|
|
addiu $24, $24, -0x240
|
|
|
|
|
beq $24, $0, .+12
|
|
|
|
|
nop
|
|
|
|
|
sw $0, 0($4)
|
|
|
|
|
addiu $25, $25, -0x250
|
|
|
|
|
beq $25, $0, .+12
|
|
|
|
|
nop
|
|
|
|
|
sw $0, 0($4)
|
|
|
|
|
addiu $30, $30, -0x300
|
|
|
|
|
beq $30, $0, .+12
|
|
|
|
|
nop
|
|
|
|
|
sw $0, 0($4)
|
|
|
|
|
jr $31
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
.end vRegTest2
|
