380 lines
12 KiB
ArmAsm
380 lines
12 KiB
ArmAsm
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/***********************************************************************/
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/* This file is part of the uVision/ARM development tools */
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/* Copyright KEIL ELEKTRONIK GmbH 2002-2004 */
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/***********************************************************************/
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/* */
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/* STARTUP.S: Startup file for Philips LPC2000 device series */
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/* */
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/***********************************************************************/
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/*
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//*** <<< Use Configuration Wizard in Context Menu >>> ***
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*/
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// *** Startup Code (executed after Reset) ***
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// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
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Mode_USR EQU 0x10
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Mode_FIQ EQU 0x11
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Mode_IRQ EQU 0x12
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Mode_SVC EQU 0x13
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Mode_ABT EQU 0x17
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Mode_UND EQU 0x1B
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Mode_SYS EQU 0x1F
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I_Bit EQU 0x80 /* when I bit is set, IRQ is disabled */
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F_Bit EQU 0x40 /* when F bit is set, FIQ is disabled */
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/*
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// <h> Stack Configuration (Stack Sizes in Bytes)
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// <o0> Undefined Mode <0x0-0xFFFFFFFF>
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// <o1> Supervisor Mode <0x0-0xFFFFFFFF>
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// <o2> Abort Mode <0x0-0xFFFFFFFF>
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// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF>
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// <o4> Interrupt Mode <0x0-0xFFFFFFFF>
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// <o5> User/System Mode <0x0-0xFFFFFFFF>
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// </h>
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*/
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UND_Stack_Size EQU 0x00000004
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SVC_Stack_Size EQU 0x00000100
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ABT_Stack_Size EQU 0x00000004
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FIQ_Stack_Size EQU 0x00000004
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IRQ_Stack_Size EQU 0x00000300
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USR_Stack_Size EQU 0x00000200
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AREA STACK, DATA, READWRITE, ALIGN=2
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DS (USR_Stack_Size+3)&~3 ; Stack for User/System Mode
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DS (IRQ_Stack_Size+3)&~3 ; Stack for Interrupt Mode
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DS (FIQ_Stack_Size+3)&~3 ; Stack for Fast Interrupt Mode
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DS (ABT_Stack_Size+3)&~3 ; Stack for Abort Mode
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DS (SVC_Stack_Size+3)&~3 ; Stack for Supervisor Mode
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DS (UND_Stack_Size+3)&~3 ; Stack for Undefined Mode
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Top_Stack:
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// Phase Locked Loop (PLL) definitions
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PLL_BASE EQU 0xE01FC080 /* PLL Base Address */
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PLLCON_OFS EQU 0x00 /* PLL Control Offset*/
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PLLCFG_OFS EQU 0x04 /* PLL Configuration Offset */
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PLLSTAT_OFS EQU 0x08 /* PLL Status Offset */
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PLLFEED_OFS EQU 0x0C /* PLL Feed Offset */
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PLLCON_PLLE EQU (1<<0) /* PLL Enable */
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PLLCON_PLLC EQU (1<<1) /* PLL Connect */
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PLLCFG_MSEL EQU (0x1F<<0) /* PLL Multiplier */
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PLLCFG_PSEL EQU (0x03<<5) /* PLL Divider */
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PLLSTAT_PLOCK EQU (1<<10) /* PLL Lock Status */
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/*
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// <e> PLL Setup
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// <i> Phase Locked Loop
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// <o1.0..4> MSEL: PLL Multiplier Selection
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// <1-32><#-1>
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// <i> M Value
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// <o1.5..6> PSEL: PLL Divider Selection
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// <0=> 1 <1=> 2 <2=> 4 <3=> 8
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// <i> P Value
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// </e>
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*/
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PLL_SETUP EQU 1
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PLLCFG_Val EQU 0x00000024
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// Memory Accelerator Module (MAM) definitions
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MAM_BASE EQU 0xE01FC000 /* MAM Base Address */
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MAMCR_OFS EQU 0x00 /* MAM Control Offset*/
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MAMTIM_OFS EQU 0x04 /* MAM Timing Offset */
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/*
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// <e> MAM Setup
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// <i> Memory Accelerator Module
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// <o1.0..1> MAM Control
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// <0=> Disabled
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// <1=> Partially Enabled
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// <2=> Fully Enabled
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// <i> Mode
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// <o2.0..2> MAM Timing
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// <0=> Reserved <1=> 1 <2=> 2 <3=> 3
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// <4=> 4 <5=> 5 <6=> 6 <7=> 7
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// <i> Fetch Cycles
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// </e>
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*/
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MAM_SETUP EQU 1
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MAMCR_Val EQU 0x00000002
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MAMTIM_Val EQU 0x00000003
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// External Memory Controller (EMC) definitions
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EMC_BASE EQU 0xFFE00000 /* EMC Base Address */
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BCFG0_OFS EQU 0x00 /* BCFG0 Offset */
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BCFG1_OFS EQU 0x04 /* BCFG1 Offset */
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BCFG2_OFS EQU 0x08 /* BCFG2 Offset */
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BCFG3_OFS EQU 0x0C /* BCFG3 Offset */
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/*
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// <e> External Memory Controller (EMC)
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*/
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EMC_SETUP EQU 0
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/*
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// <e> Bank Configuration 0 (BCFG0)
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// <o1.0..3> IDCY: Idle Cycles <0-15>
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// <o1.5..9> WST1: Wait States 1 <0-31>
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// <o1.11..15> WST2: Wait States 2 <0-31>
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// <o1.10> RBLE: Read Byte Lane Enable
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// <o1.26> WP: Write Protect
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// <o1.27> BM: Burst ROM
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// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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// <2=> 32-bit <3=> Reserved
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// </e>
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*/
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BCFG0_SETUP EQU 0
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BCFG0_Val EQU 0x0000FBEF
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/*
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// <e> Bank Configuration 1 (BCFG1)
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// <o1.0..3> IDCY: Idle Cycles <0-15>
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// <o1.5..9> WST1: Wait States 1 <0-31>
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// <o1.11..15> WST2: Wait States 2 <0-31>
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// <o1.10> RBLE: Read Byte Lane Enable
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// <o1.26> WP: Write Protect
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// <o1.27> BM: Burst ROM
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// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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// <2=> 32-bit <3=> Reserved
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// </e>
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*/
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BCFG1_SETUP EQU 0
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BCFG1_Val EQU 0x0000FBEF
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/*
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// <e> Bank Configuration 0 (BCFG2)
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// <o1.0..3> IDCY: Idle Cycles <0-15>
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// <o1.5..9> WST1: Wait States 1 <0-31>
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// <o1.11..15> WST2: Wait States 2 <0-31>
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// <o1.10> RBLE: Read Byte Lane Enable
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// <o1.26> WP: Write Protect
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// <o1.27> BM: Burst ROM
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// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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// <2=> 32-bit <3=> Reserved
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// </e>
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*/
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BCFG2_SETUP EQU 0
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BCFG2_Val EQU 0x0000FBEF
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/*
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// <e> Bank Configuration 3 (BCFG3)
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// <o1.0..3> IDCY: Idle Cycles <0-15>
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// <o1.5..9> WST1: Wait States 1 <0-31>
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// <o1.11..15> WST2: Wait States 2 <0-31>
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// <o1.10> RBLE: Read Byte Lane Enable
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// <o1.26> WP: Write Protect
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// <o1.27> BM: Burst ROM
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// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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// <2=> 32-bit <3=> Reserved
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// </e>
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*/
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BCFG3_SETUP EQU 0
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BCFG3_Val EQU 0x0000FBEF
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/*
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// </e> End of EMC
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*/
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// External Memory Pins definitions
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PINSEL2 EQU 0xE002C014 /* PINSEL2 Address */
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PINSEL2_Val EQU 0x0E6149E4 /* CS0..3, OE, WE, BLS0..3,
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D0..31, A2..23, JTAG Pins */
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// Starupt Code must be linked first at Address at which it expects to run.
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$IF (EXTERNAL_MODE)
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CODE_BASE EQU 0x80000000
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$ELSE
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CODE_BASE EQU 0x00000000
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$ENDIF
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AREA STARTUPCODE, CODE, AT CODE_BASE // READONLY, ALIGN=4
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PUBLIC __startup
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EXTERN CODE32 (?C?INIT)
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__startup PROC CODE32
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// Pre-defined interrupt handlers that may be directly
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// overwritten by C interrupt functions
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EXTERN CODE32 (Undef_Handler?A)
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EXTERN CODE32 (vPortYieldProcessor?A)
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EXTERN CODE32 (PAbt_Handler?A)
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EXTERN CODE32 (DAbt_Handler?A)
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EXTERN CODE32 (IRQ_Handler?A)
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EXTERN CODE32 (FIQ_Handler?A)
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// Exception Vectors
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// Mapped to Address 0.
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// Absolute addressing mode must be used.
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Vectors: LDR PC,Reset_Addr
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LDR PC,Undef_Addr
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LDR PC,SWI_Addr
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LDR PC,PAbt_Addr
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LDR PC,DAbt_Addr
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NOP /* Reserved Vector */
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; LDR PC,IRQ_Addr
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LDR PC,[PC, #-0x0FF0] /* Vector from VicVectAddr */
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LDR PC,FIQ_Addr
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Reset_Addr: DD Reset_Handler
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Undef_Addr: DD Undef_Handler?A
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SWI_Addr: DD vPortYieldProcessor?A
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PAbt_Addr: DD PAbt_Handler?A
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DAbt_Addr: DD DAbt_Handler?A
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DD 0 /* Reserved Address */
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IRQ_Addr: DD IRQ_Handler?A
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FIQ_Addr: DD FIQ_Handler?A
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// Reset Handler
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Reset_Handler:
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$IF (EXTERNAL_MODE)
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LDR R0, =PINSEL2
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LDR R1, =PINSEL2_Val
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STR R1, [R0]
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$ENDIF
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IF (EMC_SETUP != 0)
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LDR R0, =EMC_BASE
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IF (BCFG0_SETUP != 0)
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LDR R1, =BCFG0_Val
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STR R1, [R0, #BCFG0_OFS]
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ENDIF
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IF (BCFG1_SETUP != 0)
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LDR R1, =BCFG1_Val
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STR R1, [R0, #BCFG1_OFS]
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ENDIF
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IF (BCFG2_SETUP != 0)
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LDR R1, =BCFG2_Val
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STR R1, [R0, #BCFG2_OFS]
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ENDIF
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IF (BCFG3_SETUP != 0)
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LDR R1, =BCFG3_Val
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STR R1, [R0, #BCFG3_OFS]
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ENDIF
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ENDIF
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IF (PLL_SETUP != 0)
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LDR R0, =PLL_BASE
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MOV R1, #0xAA
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MOV R2, #0x55
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// Configure and Enable PLL
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MOV R3, #PLLCFG_Val
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STR R3, [R0, #PLLCFG_OFS]
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MOV R3, #PLLCON_PLLE
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STR R3, [R0, #PLLCON_OFS]
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STR R1, [R0, #PLLFEED_OFS]
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STR R2, [R0, #PLLFEED_OFS]
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// Wait until PLL Locked
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PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS]
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ANDS R3, R3, #PLLSTAT_PLOCK
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BEQ PLL_Loop
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// Switch to PLL Clock
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MOV R3, #(PLLCON_PLLE | PLLCON_PLLC)
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STR R3, [R0, #PLLCON_OFS]
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STR R1, [R0, #PLLFEED_OFS]
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STR R2, [R0, #PLLFEED_OFS]
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ENDIF
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IF (MAM_SETUP != 0)
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LDR R0, =MAM_BASE
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MOV R1, #MAMTIM_Val
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STR R1, [R0, #MAMTIM_OFS]
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MOV R1, #MAMCR_Val
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STR R1, [R0, #MAMCR_OFS]
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ENDIF
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// Memory Mapping (when Interrupt Vectors are in RAM)
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MEMMAP EQU 0xE01FC040 /* Memory Mapping Control */
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$IF (RAM_INTVEC)
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LDR R0, =MEMMAP
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MOV R1, #2
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STR R1, [R0]
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$ENDIF
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// Setup Stack for each mode
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LDR R0, =Top_Stack
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// Enter Undefined Instruction Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_UND|I_Bit|F_Bit
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MOV SP, R0
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SUB R0, R0, #UND_Stack_Size
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// Enter Abort Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit
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MOV SP, R0
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SUB R0, R0, #ABT_Stack_Size
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// Enter FIQ Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit
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MOV SP, R0
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SUB R0, R0, #FIQ_Stack_Size
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// Enter IRQ Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit
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MOV SP, R0
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SUB R0, R0, #IRQ_Stack_Size
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// Enter Supervisor Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
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MOV SP, R0
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SUB R0, R0, #SVC_Stack_Size
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// Enter S Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_SYS
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MOV SP, R0
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// Start in supervisor mode
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MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
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// Enter the C code
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LDR R0,=?C?INIT
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TST R0,#1 ; Bit-0 set: INIT is Thumb
|
||
|
|
LDREQ LR,=exit?A ; ARM Mode
|
||
|
|
LDRNE LR,=exit?T ; Thumb Mode
|
||
|
|
BX R0
|
||
|
|
ENDP
|
||
|
|
|
||
|
|
PUBLIC exit?A
|
||
|
|
exit?A PROC CODE32
|
||
|
|
B exit?A
|
||
|
|
ENDP
|
||
|
|
|
||
|
|
PUBLIC exit?T
|
||
|
|
exit?T PROC CODE16
|
||
|
|
exit: B exit?T
|
||
|
|
ENDP
|
||
|
|
|
||
|
|
|
||
|
|
END
|